Semiconductor package, semiconductor module, electronic component, and method for manufacturing semiconductor package and semiconductor module

Abstract

Semiconductor packages, semiconductor modules, electronic components, and methods for manufacturing semiconductor packages and semiconductor modules are disclosed. In an embodiment, the module includes a first electronic device in a first device region and a second electronic device in a second device region. The first electronic device is operably coupled to the second electronic device to form a circuit. A side of the first electronic device and a side of the second electronic device are embedded in a first epoxy resin layer and in direct contact with the first epoxy resin layer.

Description

Background Art

[0001] In some circuits such as power conversion, the circuit requires two or more semiconductor devices that are electrically coupled together to provide a corresponding circuit or portion of a corresponding circuit. For example, in motor drives, DC-DC converters, and rectifiers, the circuit may require a combination of transistor devices that are used as switches in a half-bridge configuration that includes a low-side switch and a high-side switch. In the half-bridge configuration, the drain of the transistor device that provides the low-side switch is electrically coupled to the source of the transistor that provides the high-side switch.

[0002] In some embodiments, each semiconductor device (e.g., transistor device) is housed within a package, and the packages are electrically coupled together by means of a conductive redistribution structure located outside the package. For example, the packages may be mounted on a circuit board including a conductive redistribution structure that electrically couples the packages to form a circuit or portion of a circuit. However, such an arrangement may occupy an undesirably large lateral area for some applications.

[0003] US 2013 / 0140673 A1 discloses a semiconductor device including one semiconductor die, wherein a first field effect transistor and a second field effect transistor are monolithically integrated and form a half-bridge configuration.

[0004] Semiconductor devices for power conversion circuits that occupy a smaller lateral area and methods for making such semiconductor devices are desirable. Summary of the invention

[0005] In an embodiment, a semiconductor package includes: a first transistor device including a first surface and a second surface opposite to the first surface; a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface; a first metallization structure arranged on the first surface, the first metallization structure including a plurality of external contact pads, the external contact pads including a protective layer of solder, the solder being Ag or Sn; a second metallization structure arranged on the second surface; a conductive connection extending from the first surface to the second surface and electrically connecting the second power electrode to the external contact pads of the first metallization structure; and a first epoxy layer arranged on a side of the transistor device and arranged on the first surface of the transistor device. The first epoxy layer includes an opening defining a lateral size of the external contact pads and the package footprint.

[0006] In an embodiment, a method includes: forming at least one first groove in a first surface of a semiconductor wafer in a device region, wherein the semiconductor wafer includes a separation region arranged between component locations of the semiconductor wafer, the component locations including the device region, and the device region including electronic devices; forming a first metallization structure arranged on the first surface in the component locations, the first metallization structure including a plurality of external contact pads forming package positions; and inserting a conductive material into the first groove; forming at least one second groove in the first surface of the semiconductor wafer in the separation region; applying a first epoxy layer to the first surface of the semiconductor wafer so that the second groove and an edge region of the component location are covered with the first epoxy layer; removing a portion of the second surface of the semiconductor wafer, the second surface being opposite to the first surface; and exposing a portion of the first epoxy layer in the separation region and the conductive material in the first groove and producing a processed second surface; applying a second metallization layer to the processed second surface and operably coupling the second metallization layer to the conductive material and the external contact pads on the first main surface; and cutting through the first epoxy layer in the separation region to form a plurality of separated semiconductor packages.

[0007] In an embodiment, a method includes: forming a first metallization structure on a first surface of a semiconductor wafer, wherein the semiconductor wafer includes a separation region arranged between component locations, the component locations including a device region, the device region including an electronic device, the first metallization structure being arranged on the component locations and including a plurality of external contacts forming a package location; forming at least one second groove in the first surface of the semiconductor wafer in the separation region; applying a first epoxy layer to the first surface of the semiconductor wafer so that the second groove and an edge region of the component location are covered with the first epoxy layer; removing a portion of the second surface of the semiconductor wafer, the second surface being opposite to the first surface; and exposing a portion of the first epoxy layer in the separation region; forming at least one first groove in a processed second surface of the semiconductor wafer in the device region of the component location; inserting a conductive material into the first groove; applying a second metallization layer to the processed second surface and operably coupling the second metallization layer to the conductive material and the external contact pads on the first main surface; and cutting through the first epoxy layer in the separation region to form a plurality of separated semiconductor packages.

[0008] In an embodiment, a module includes a first electronic device in a first device region and a second electronic device in a second device region, wherein the first electronic device is operably coupled to the second electronic device to form a circuit. The module further includes: a first major surface including at least one contact pad; a second major surface including at least one contact pad, the second major surface being opposite to the first major surface; a first epoxy layer disposed on the first major surface, which exposes at least a portion of the first contact pad. Sides of the first electronic device and sides of the second electronic device are embedded in the first epoxy layer and in direct contact with the first epoxy layer. The module further includes a conductive redistribution structure that electrically couples the first electronic device with the second electronic device to form a circuit. The conductive redistribution structure includes: a conductive via extending from the first major surface to the second major surface; and a conductive layer disposed on the conductive via and disposed on at least one of the first device region and the second device region.

[0009] In an embodiment, an electronic assembly includes a module according to any one of the embodiments described herein, a plurality of leads, and a plastic housing component. A first contact pad of the module is coupled to a first lead of the plurality of leads and a second contact pad of the module is coupled to a second lead of the plurality of leads. The plastic housing component covers a first epoxy resin layer.

[0010] In an embodiment, a method for manufacturing a semiconductor module includes: forming at least one groove in a non-device area of ​​a first surface of a semiconductor wafer; and forming at least one groove in a non-circuit area of ​​the first surface of the semiconductor wafer. The non-device area is arranged between component locations and the component locations include at least two semiconductor devices for forming a circuit. The non-circuit area is arranged between a first device area including a first electronic device and a second device area including a second electronic device, and a first metallization layer is arranged on the first surface in the first device area and the second device area. The method further includes: applying a first polymer layer to the first surface of the semiconductor wafer so that the groove, the edge area of ​​the component location, the edge area of ​​the first device area, and the edge area of ​​the second device area are covered with a first polymer layer; removing a portion of the second surface of the semiconductor wafer, the second surface being opposite to the first surface; exposing a portion of the first polymer layer in the non-device area and the non-circuit area and producing a processed second surface. The method further includes: applying a second metallization layer to the processed second surface and operably coupling the first electronic device to the second electronic device to form a circuit; and inserting a separation line through the first polymer layer in the non-device area to form a plurality of separated semiconductor dies including the circuit.

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The elements of the accompanying drawings are not necessarily to scale with respect to each other. The same reference numerals designate corresponding similar parts. The features of the various described embodiments may be combined unless they exclude each other. Exemplary embodiments are depicted in the accompanying drawings and are described in detail in the following description.

[0013] Figure 1 A flow chart illustrating a method for preparing a semiconductor module.

[0014] Figure 2 A schematic cross-sectional view of a semiconductor module is shown.

[0015] Figure 3A The diagram shows a cross-sectional view of a semiconductor module comprising two polymer layers.

[0016] Figure 3B The diagram shows a cross-sectional view of a semiconductor module comprising two polymer layers.

[0017] Figure 4 A cross-sectional view of a semiconductor module is shown.

[0018] Figure 5 Graphics Figure 4 Magnified top view and magnified side view of a conductive via of a semiconductor module.

[0019] Figure 6 A schematic top view of the semiconductor module of FIG. 3 housed within a package is shown.

[0020] Fig. 7A A cross-sectional view of a semiconductor wafer is shown.

[0021] Figure 7B The wafer is shown after forming a first trench and a second trench in the first major surface of the wafer.

[0022] Figure 7C The wafer is shown after application of the first polymer layer.

[0023] Fig.7D The wafer is shown after application of the carrier.

[0024] Fig. 7E The illustration shows a portion of the second major surface of the wafer being removed.

[0025] Figure 7F A second metallization structure is shown being applied to the processed second surface of the wafer.

[0026] Figure 7G The configuration of the second metallization structure is shown.

[0027] Figure 7HThe configuration of the second metallization structure is shown.

[0028] Fig.7I The illustration shows the application of a second polymer layer and the separation of the semiconductor modules.

[0029] Figure 8 A cross-sectional view of a semiconductor module is shown.

[0030] Fig. 9 A cross-sectional view of a semiconductor module is shown.

[0031] FIG. 10 , which includes FIGS. 10 a to 10 f , illustrates a method of manufacturing a semiconductor package according to an embodiment.

[0032] FIG. 11 including FIGS. 11 a to 11 d illustrates a method of preparing a semiconductor package according to an embodiment.

[0033] Fig.12 An enlarged view of a conductive via used in a semiconductor package or semiconductor module is shown.

[0034] FIG. 13 , which includes FIGS. 13 a and 13 b , illustrates two package footprints.

[0035] Fig.14 A flow chart illustrating a method of preparing a semiconductor package according to an embodiment.

[0036] Fig.15 A flow chart illustrating a method of preparing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0037] In the following detailed description, reference is made to the accompanying drawings which form a part of this document, and in the drawings specific embodiments in which the invention may be practiced are shown by way of illustration. In this regard, directional terms such as "top", "bottom", "front", "back", "in front of", "back of", etc. are used with reference to the orientation of the (multiple) figures being described. Because the components of the embodiments can be positioned in many different orientations, the directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description of the invention should not be viewed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0038] A number of exemplary embodiments will be explained below. In this case, identical structural features are identified in the various figures by identical or similar reference symbols. In the context of this description, "lateral" or "lateral direction" should be understood to mean a direction or extent running substantially parallel to the lateral extent of the semiconductor material or semiconductor carrier. The lateral direction thus extends substantially parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction running substantially perpendicular to these surfaces or sides, and therefore running perpendicular to the lateral direction. The vertical direction thus runs in the thickness direction of the semiconductor material or semiconductor carrier.

[0039] As used in this specification, when an element such as a layer, region or substrate is referred to as being "on" or extending "over" another element, it can be directly on or directly extending over the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending directly over" another element, there are no intervening elements present.

[0040] As used in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0041] In power conversion applications, the corresponding circuits usually require a combination of transistors such as field effect transistors (FETs) to form the high side and low side of, for example, a buck converter to be positioned as close as possible. Placing the chips individually requires a minimum spacing distance, which limits the possible shrinking of the package. Wider spacing may also increase stray inductance that affects the performance of the package.

[0042] Some embodiments described herein provide a semiconductor package having a single semiconductor die including a single semiconductor device, particularly a single semiconductor device for power conversion. In some embodiments, the single semiconductor device is a transistor device, such as a vertical MOSFET (metal oxide semiconductor field effect transistor) or a vertical IGBT (insulated gate bipolar transistor). The semiconductor package has a smaller package footprint and occupies a smaller lateral area because the drain external contacts and the source external contacts and the gate external contacts of the package are positioned on the semiconductor die providing the transistor device and within the lateral area of ​​the semiconductor die.

[0043] Some described embodiments provide / include multi-chip or multi-device single-die modules that enable closer spacing of chips within the module and simultaneously allow direct electrical connection between the source and drain of two devices (e.g., vertical transistor devices) by means of through-holes (e.g., through-silicon vias (TSVs)). The modules can be packaged in standard plastic packages or ready for chip embedding, or can be used as a final package without further packaging.

[0044] Figure 1 A flow chart 20 of a method for preparing a semiconductor module including a first electronic device and a second electronic device coupled to form a circuit is illustrated. In frame 21, at least one groove is formed in a separation region of a first surface of a semiconductor wafer. In frame 22, at least one groove is formed in a non-device region of the first surface of the semiconductor wafer. The separation region is arranged between component locations of the semiconductor wafer. Each of the component locations may include at least two electronic devices for forming a circuit and a non-device region arranged between a first device region including a first electronic device and a second device region including a second electronic device. A first metallization structure is arranged on a first surface of the semiconductor wafer in the first device region and the second device region.

[0045] In frame 23, a first polymer layer is applied to the first surface of the semiconductor wafer so that the grooves in both the separation area and the non-device area, the edge area of ​​the component location, the edge area of ​​the first device area, and the edge area of ​​the second device area are covered with the first polymer layer. The polymer layer may include a curable polymer component such as a thermosetting polymer resin, and may include an epoxy resin.

[0046] In block 24 , a portion of a second surface of the semiconductor wafer is removed, the second surface being opposite the first surface and exposing portions of the first polymer layer in the separation region and in the non-device region and producing a processed second surface.

[0047] The thickness of the semiconductor wafer is reduced and the thickness of the semiconductor wafer can be reduced to a predetermined thickness. In these embodiments, the depth of the grooves in the separation area and the non-device area can be selected to be greater than the desired final thickness of the semiconductor wafer so that the portion of the first polymer layer arranged in the grooves formed in the separation area and the non-device area is exposed after the thickness of the semiconductor wafer has been reduced to the predetermined desired thickness.

[0048] A second metallization layer is applied to the processed second surface in block 25. The first electronic device is operably coupled to the second electronic device to form a desired circuit.

[0049] In block 26, a separation line is inserted through the first polymer layer in the separation area to form a plurality of separated semiconductor modules, each semiconductor module including a circuit. Each semiconductor module includes a first electronic device and a second electronic device that are operably coupled to form a circuit. For example, the separation line can be inserted by mechanical sawing or laser cutting.

[0050] The semiconductor module includes two device regions, and the two device regions include semiconductor materials. For example, the semiconductor material can be silicon. Each semiconductor module includes two or more electronic devices, and the two or more electronic devices are separated from each other laterally by the portion of the first polymer layer arranged in the non-device region, and the non-device region is laterally positioned between the first device region including the first electronic device and the second device region including the second electronic device. The sidewalls of the module and the edges formed between the sidewalls and the first surface and the second surface of the device region can be covered and in direct contact with the first polymer layer. The first polymer layer can be used to protect the sides and edges. This arrangement can be used to simplify the handling of the module using automated equipment.

[0051] The module can then be packaged, and the exposed portions of the first and second metallization layers provide contact pads that can be electrically coupled to external contact pads of the package through the internal conductive redistribution structure. In some embodiments, the module can be used in a circuit or application without further packaging.

[0052] As an example, the first electronic device may include a transistor device, such as a field effect transistor device such as a MOSFET or an insulated gate bipolar transistor (IGBT). The second electronic device may also include a transistor device, such as a field effect transistor device such as a MOSFET or an insulated gate bipolar transistor (IGBT), or may include a driver device such as a gate driver device or a portion of a gate driver device such as a pull-down FET (field effect transistor), or may include a passive device such as an inductor, a capacitor or a resistor. If two transistor devices are provided, the module may provide a suitable electrical connection between the two transistor devices for the half-bridge circuit.

[0053] In some embodiments, each component location may include more than two electronic devices used to form a particular circuit. As an example, the circuit may be a half-bridge configuration where both the first electronic device and the second electronic device are transistors, and the component location may further include a driver device or a portion of a driver device such as a pull-down FET coupled to the gates of the two transistor devices.

[0054] The non-device region does not include any device structure and may laterally surround the first device region and the second device region. The separation region located between immediately adjacent component locations typically also does not have a device structure. In some embodiments, the component locations are arranged in a regular array of rows and columns so that the trenches formed in the separation region have the shape of a square or rectangular grid in a plan view.

[0055] The device area in each component position can have different lateral arrangements. In some embodiments, the device area in each electronic component position is arranged to be adjacent to each other laterally so that the grooves formed in the non-device area extend substantially parallel to each other. In some embodiments, the device area in each electronic component position is arranged laterally so that a device area is separated from another device area by two substantially vertical non-device areas and the grooves formed in the non-device area extend substantially perpendicular to each other. For example, a device area can be arranged in the corner of a component position that is square or rectangular in the horizontal direction so that it is defined by two substantially vertical separation areas and by two substantially vertical non-device areas. Another device area can have an L shape. In some embodiments, a device area is laterally surrounded by further device areas on all sides so that the non-device area with a continuous annular shape surrounds the internal device area. For example, the internal device area can be substantially square or rectangular, and is laterally surrounded by a substantially square or rectangular continuous non-device area, which is then laterally surrounded by a further device area of ​​a square or rectangular annular shape. The inner device region and the outer device region may be arranged concentrically or non-concentrically relative to each other.

[0056] In some embodiments, in block 25, a second metallization layer is applied such that it operably couples (e.g., electrically connects) the first electronic device to the second electronic device to form a circuit. In other embodiments, the first electronic device and the second electronic device may be electrically connected via the first metallization structure, and removing a portion of the second surface of the semiconductor wafer causes the semiconductor bodies of the two electronic devices to be electrically isolated from each other. In these embodiments, the second metallization layer may provide a ground plane.

[0057] In some embodiments, the method further includes forming a vertical conductive connection extending between the first surface and the second surface of the wafer. The vertical conductive connection can be used to electrically couple the first electronic device and the second electronic device. For example, if one or more of the electronic devices is a vertical device with a vertical drift path, the vertical conductive connection can be used.

[0058] In some embodiments, the method further includes inserting one or more through holes or vias into the first device region or the second device region, inserting a conductive material into the through hole and electrically coupling the conductive material in the through hole to the first electronic device and the second electronic device. In some embodiments, the through hole can be inserted into both the first device region and the second device region. In some embodiments, two or more through holes can be inserted into at least one of the first device region and the second device region. The number and location of the through holes can be selected depending on the circuit to be formed, the structure of the first electronic device and the second electronic device, and the current carrying capacity required by the through hole structure.

[0059] The through hole can be inserted into the first surface of the semiconductor wafer, and then the first metallization structure and the first polymer layer are applied to the first surface, and then a portion of the second surface of the semiconductor wafer is removed to form a processed second surface. Alternatively, the through hole can be inserted into the first surface of the semiconductor wafer before applying the first metallization structure.

[0060] Insulating material may be inserted into one or more through holes or vias formed in the first device region or the second device region before inserting conductive material into the through holes. The insulating material may line the sidewalls of the through holes or vias and provide insulation to the surrounding device body.

[0061] In some embodiments, a further conductive layer is applied to the first metallization structure, for example to increase the thickness of the area used to provide the contact pad. The conductive material may be inserted into the through hole before applying the further conductive layer so that the further conductive layer electrically couples the conductive material in the through hole to the first metallization structure. Alternatively, the conductive material may be inserted into the through hole and the further conductive layer may be applied to one or both of the main surfaces in the same deposition process.

[0062] In some embodiments, a through hole is inserted into the processed second surface of the semiconductor wafer. In these embodiments, the through hole can be inserted so that the bottom of the through hole is formed by a portion of the first metallization structure or a further conductive layer located on the first surface of the semiconductor wafer. A conductive material is inserted into the through hole so that the through hole contacts and is electrically connected to the first metallization structure. The conductive material can be electrically insulated from the surrounding device body by the insulating material lining the sidewalls of the through hole.

[0063] A second metallization layer can be applied to the processed second surface and the conductive material within the through-hole so as to electrically couple the first electronic device arranged in the first device region to the conductive through-hole and to the second electronic device located in the second device region. The second metallization layer can extend from the first device region to the second device region and to the conductive material located in the through-hole through the non-device region of the first polymer layer exposed in the processed second surface. The second metallization layer can also be constructed so as to form one or more contact areas on the processed second surface of the semiconductor wafer, and the one or more contact areas are electrically separated from further conductive areas (e.g., conductive areas that electrically couple the first electronic device to the conductive through-hole).

[0064] In these embodiments, a vertical portion of a redistribution structure of a module is formed either within the semiconductor material of the semiconductor wafer or within the first device region or within the second device region.

[0065] In other embodiments, the vertical portion of the redistribution structure may be located between the first device region and the second device region and may be located in the non-device region. In some embodiments, the method further includes inserting a conductive material into a trench formed in the non-device region, and electrically coupling the conductive material located in the trench to the first electronic device and the second electronic device. The conductive material in the through hole may be electrically coupled to the first electronic device and the second electronic device through a portion of the first metallization layer disposed on the first surface and through a portion of the second metallization layer disposed on the second surface.

[0066] By applying one or more insulating layers to the sidewalls of the groove, the conductive material arranged in the groove in the non-device area can be electrically insulated from the semiconductor material of the first device area and the second device area. In some embodiments, after inserting the first polymer layer into the groove formed in the non-device area, a through hole is formed in the first polymer layer in the non-device area. The through hole can have a width less than the width of the groove so that the sides of the first device area and the second device area defining the through hole are covered with the first polymer layer. A conductive material is applied to the first polymer layer in the through hole. The first polymer layer is therefore used to electrically insulate the conductive material from the sides of the first device area and the second device area.

[0067] In some embodiments, a portion of the second surface of the wafer is subsequently removed, exposing not only the first polymer layer arranged in the non-device area but also the conductive material arranged in the non-device area in the processed second surface, so that the conductive material extends from the first metallization surface structure arranged on the first surface in the second device area to the processed second surface.

[0068] A second metallization layer may be applied to the conductive material within the through hole disposed in the non-device region to electrically couple the first electronic device to the second electronic device. The second metallization layer may be applied so that it extends from the first device region through the non-device region to the second device region. In the case where the through hole is located in the non-device region, the lateral extension of the second metallization layer to both the first device region and the second device region may be used to assist in the mechanical stability of the structure.

[0069] In some embodiments, a conductive via from a first surface of a semiconductor wafer to a processed second surface of a semiconductor wafer is formed by a conductive portion of a first device region or a second device region. The conductive portion extends from the first surface of the semiconductor wafer to the processed second surface of the semiconductor wafer. The conductive portion can be insulated from the remainder of the semiconductor material of the first device region and the second device region by an insulating layer (e.g., an oxide or nitride) and / or by a first polymer layer. The conductive portion can be coupled to the first electronic device and the second electronic device through a portion of the first metallization layer and the second metallization layer so as to electrically couple the first electronic device and the second electronic device and form a circuit.

[0070] The first polymer layer can be applied to the first surface of the semiconductor wafer so that at least a portion of the first metallization structure is not covered by the first polymer layer. In some embodiments, the first polymer layer can be selectively applied so that it is applied to the edge areas of the grooves, the component locations, and the edge areas of the first device area and the second device area, or can be applied as a closed layer and portions of the first polymer layer are removed to expose at least a portion of the first metallization structure.

[0071] In some embodiments, the first polymer layer is arranged laterally so that the peripheral portion of the first metallization structure is covered by the first polymer layer and defines the exposed portion of the first metallization structure, such as defining and defining one or more contact pads. In these embodiments, the first polymer layer can function to control the lateral extent of the solder applied to the contact pads.

[0072] In some embodiments, the method further includes applying a carrier to a first polymer layer disposed on a first surface, the first polymer layer being configured so that at least a first portion of the first metallization structure is exposed by the first polymer layer. A cavity may be formed between the carrier and the first metallization structure defined by the first polymer layer. A portion of the second surface of the semiconductor wafer is then removed, and portions of the first polymer layer in the separation region and the non-device region are exposed, while the carrier is applied to the first polymer layer. The carrier is not in direct contact with the first metallization structure of the semiconductor wafer.

[0073] The separation lines, for example zigzag lines, may have a width that is smaller than the width of the trenches in the separation region. The separation lines may then be inserted into the separation region such that at least parts of the side surfaces of the plurality of separated semiconductor modules comprise a portion of the first polymer layer.

[0074] In some embodiments, a second polymer layer is applied to the processed second surface in the separation area and the non-device area, and the side of the separated semiconductor module can also include the second polymer layer and a portion of the first polymer layer. The entire side and the edge of the component position can be covered by the first polymer layer and the second polymer layer.

[0075] The second polymer layer may also include, for example, a curable polymer component, such as a thermosetting resin, such as a second epoxy resin layer. The second polymer layer may be applied to the processed second surface so that it at least covers the first polymer layer arranged on the separation area. The second polymer layer may also cover at least part of the second metallization layer. In some embodiments, the second polymer layer covers the peripheral area of ​​the dispersed portion of the second metallization layer and defines one or more contact pads that can be connected to a further conductive surface by solder.

[0076] In some embodiments, the second metallization layer includes a portion extending from the first device region to the second device region and extending through a non-device region that may include a first polymer layer. In some embodiments, the second polymer layer may be adjacent to the device connection portion of the second metallization layer or may cover the peripheral edge region of the portion of the second metallization layer and define a contact pad exposed from the second polymer layer. In other embodiments, the device connection portion of the second metallization layer may be completely covered by the second polymer layer that provides electrical insulation of the portion of the metallization layer. This arrangement may be used if direct electrical contact to the portion of the second metallization layer is not required or in embodiments where electrical insulation of the layer and the portion of the circuit is desired or required.

[0077] In some embodiments, the second metallization layer may be applied by applying a conductive seed layer to the processed second surface; applying a second polymer layer to the seed layer so that at least a portion of the seed layer is exposed from the second polymer layer; and applying a conductive layer to the exposed portion of the seed layer. The seed layer may be applied using a vacuum deposition technique such as sputtering or chemical vapor deposition. The conductive layer may be applied to the seed layer using an electrodeposition technique such as electroless deposition or galvanic deposition.

[0078] A conductive seed layer may be applied to the processed second surface so that the first polymer layer arranged in the separation area and the non-device area and the semiconductor material of the first device area and the second device area are covered by the seed layer. A second epoxy resin layer may be applied to the seed layer so that the separation area is covered by the second polymer layer and the area of ​​the processed second surface including the semiconductor material and the area of ​​the first polymer layer arranged in the non-device area is not covered by the second polymer layer. A conductive layer is then applied to the seed layer in each portion that is not covered by the second polymer layer to form a second metallization layer.

[0079] At least two devices are prepared on a wafer so that the distance between the chips can be reduced and is only limited by the separation process, for example 10 to 50 μm for mechanical half-cut dicing or plasma half-cut dicing. The multi-chip die is encapsulated in epoxy resin and the only corresponding connections are open metal surfaces, such as copper surfaces. With the help of through-holes, direct connection between the front side 1 (source 1) and the back side 2 (drain 2) of the different chips is possible. Due to the encapsulated nature of the multi-chip die, it can be directly picked up and placed in a standard package (such as QFN) or picked up and placed using a chip embedding method.

[0080] Different types of devices can be processed next to each other on a silicon wafer. Once the processing of the front side of the chip has been completed, a half-cut processing step is performed. Here, the individual chips or devices are isolated from each other. At the same time, the lines used for separation between individual multi-chip dies or multi-device modules are also half-cut. After the epoxy resin grinding pre-cutting process, the chips and half-cut lines are covered and filled with epoxy resin (half-cut depth ~ wafer target thickness + 10μm). Then the corresponding epoxy resin properties are used in the photolithography step to open the copper pads on the front side. After the wafer is mounted on a glass carrier, the wafer is thinned to its desired thickness, such as 15-20μm. In the thinning process, the half-cut portion filled with epoxy resin is exposed on the back side. Now deposit the copper back side. This can be achieved by a sputtered Ti / Cu seed layer introduced to the final thickness via copper electrodeposition. Depending on the thickness, it is also possible to perform sputtering only. Afterwards, the copper back side is constructed in a way that the multi-chip dies are connected to form the intended circuit.

[0081] Thus, silicon can be formed from the front side before half-cutting or from the back side before depositing the seed layer. After the copper backside structure is performed, the complete backside is covered with epoxy again and the intended copper pad is opened in the photolithography step utilizing the corresponding epoxy properties. After the epoxy cures, the wafer is framed and the multi-chip die is separated by laser cutting through the epoxy. Now the multi-chip die can be picked up from the dicing foil in a standard manner to be placed in a standard package.

[0082] Alternatively, both the copper front side contact and the copper back side contact and the silicon vias can be formed by using the corresponding front side epoxy and back side epoxy as patterned plating masks on the pre-structured seed layer. This is achieved with the help of electroless plating. In this way, the silicon vias can be integrated in a pre-existing process flow.

[0083] The present concept can be directly and unhinderedly applied to integrate passive components such as capacitors or inductors if they are formed on a portion of the wafer next to the corresponding connection chip. These passive components are treated like additional chips or as part of one of the multi-chip systems. The integration of these passive components in an integrated solution may be of interest because it allows minimizing the contribution of loop inductance and stray passive components. This directly improves the performance of the solution and allows better control of overshoot behavior.

[0084] Figure 2 A schematic cross-sectional view of a semiconductor module 30 is illustrated. The semiconductor module 30 includes a first electronic device 31 in a first device region 32 and a second electronic device 33 in a second device region 34. The first electronic device 31 is operably coupled to the second electronic device 33 to form a circuit. In the illustrated embodiment, the first electronic device 31 is a transistor device, in particular a vertical transistor device, having a gate pad 35 and a source pad 36 on a first surface 37 and a drain pad 38 on a second surface 39 opposite to the first surface 37. The second electronic device 33 is also a transistor device, in particular a vertical transistor device, having a gate pad 40 and a source pad 41 on a first surface 42 and a drain pad 43 on a second surface 44 opposite to the first surface 42. The first surface 42 of the second electronic component 33 is substantially coplanar with the first surface 37 of the first electronic component 31, and the second surface 44 of the second electronic component 33 is substantially coplanar with the second surface 39 of the first electronic component 31.

[0085] The module 30 has a first main surface 45 including at least one contact pad. Figure 2 , the first main surface 45 comprises four contact pads, which are coupled to the source pad 36 and the gate pad 35 of the first electronic device 31 and to the gate pad 40 and the source pad 41 of the second electronic device 33. The semiconductor module 30 further comprises a second main surface 46 opposite to the first main surface 45. The semiconductor module 30 comprises a first polymer layer 47, in particular a first epoxy resin layer, which is arranged on the first main surface 45 and which leaves at least parts of the contact pads 35, 36, 40, 41 exposed.

[0086] The first polymer layer 47 may be arranged on the peripheral area of ​​the contact pads 35, 36, 40, 41. The first polymer layer 47 covers the side surfaces 48 of the first electronic device 31 and the second electronic device 33 so that the first electronic device and the second electronic device 33 may be considered to be embedded in the first polymer layer 47. The semiconductor module 30 further includes a conductive redistribution structure 49 which electrically couples the first electronic device 31 to the second electronic device 33.

[0087] In this embodiment, the conductive redistribution structure 49 includes a conductive via 50 extending from the first main surface 45 of the semiconductor module 30 to the second main surface 46. The conductive via 50 can be positioned in the first device region 32 or in the second device region 34, and can be referred to as a through-silicon via. The conductive via 50 can be electrically insulated from the semiconductor material of the electronic device by an insulating layer 55. The via 50 provides a conductive connection from the first main surface 45 of the module to the second main surface 46 and a conductive connection from the first surface 42 of the second electronic device 33 to the second surface 39 of the first electronic device 32. The redistribution structure 49 further includes a conductive layer 51 extending laterally on the second main surface 46 of the module and arranged on the via 50 formed in the second electronic device 33.

[0088] Conductive layer 51 is arranged on conductive via 50 and on a portion of first polymer layer 47 that forms a portion of second main surface 46. Conductive layer 51 extends from drain pad 38 of first electronic device 31 to conductive via 50, and is located not only on first electronic device 31 and on a portion of first polymer layer 47, but also on a portion of second main surface 44 of second electronic component 33.

[0089] Conductive via 50 may extend between source pad 41 and second surface 44 of second electronic component 33 and be electrically coupled to source pad 41. Conductive layer 51 in combination with conductive via 50 provides a redistribution structure 49 from source pad 41 of second electronic device 33 to drain pad 38 of first electronic device 31. In this particular embodiment, the arrangement may be used to form a half-bridge configuration, wherein first electronic component 31 is a low-side switch of the half-bridge configuration and second electronic device 33 is a high-side switch of the half-bridge configuration.

[0090] The further conductive layer 56 may be arranged on the drain pad 43 of the second electronic device 33 such that outer surfaces of the further conductive layers 51 , 56 are substantially coplanar.

[0091] The conductive layer 51 extending from the second surface 39 of the first electronic device 31 to the second surface 44 of the second electronic device 33 is electrically insulated from further conductive portions (such as contact pads 56) arranged on the second surface 44 of the second electronic device 33, and is insulated from the body of the second electronic device 33 by the insulating layer 55. The insulating layer 55 lines the sidewalls of the via 50 and extends through the second surface 44 of the second electronic device 33 in the area adjacent to the via 50 and is directly arranged on the second surface 44. The insulating layer 55 has a lateral extent so that it is positioned between the second surface 44 and the conductive layer 51, and electrically insulates the conductive layer 51 from the second surface 44 and the second surface 44 of the second electronic device 33 from the second surface 39 of the first electronic device 31.

[0092] Module 30 may be used Figure 1 , whereby the first electronic component 31 is formed from the first device region of the semiconductor wafer and the second electronic component 33 is formed from the second device region of the semiconductor wafer. The region between the adjacent side surfaces 48 of the first electronic component 31 and the second electronic component 33 is a non-device region of the component position of the semiconductor wafer. The outermost surface 53 of the semiconductor module 30 is formed by the following portion of the first polymer layer 47: the portion is formed by inserting the separation line in the separation region of the semiconductor wafer.

[0093] The semiconductor module 30 is formed from a semiconductor wafer by inserting trenches and filling the trenches with a first polymer layer arranged so that at least the sides of the electronic devices 31, 33 are embedded in the first polymer layer 47. The first polymer layer 47 provides a mechanical matrix that holds the electronic devices 31, 33 together. Figure 2 In the embodiment illustrated in , the conductive connection between the electronic devices 31, 33 in a half-bridge configuration) can be formed by depositing a conductive layer on the first main surface 45 and the second main surface 46 of the semiconductor module 30, and in the case of one or more vertical devices, by providing one or more conductive vias 50 extending between the main surface 45 and the main surface 46 of the semiconductor module 30.

[0094] The via 50 may be arranged in the device region. Figure 2 In the embodiment illustrated in FIG. 8 , the through-via 50 is arranged in the second electronic component 33 and extends between the first surface 42 and the second surface 44 of the second electronic component 33 .

[0095] FIG. 3 shows a cross-sectional view of a semiconductor module 30 ′, except for the Figure 2In addition to the features illustrated in FIG. 4 , the semiconductor module 30′ further includes a second polymer layer 54 disposed on the second major surface 46 of the semiconductor module 30′. The second polymer layer 54 may also be a curable polymer (such as a thermosetting polymer composition) and in some embodiments includes an epoxy resin.

[0096] In such Figure 3A In some embodiments of the embodiment illustrated in FIG. 3 , the second polymer layer 54 may be arranged at the peripheral edge of the semiconductor module 30 ′ and arranged to contact the portion of the first polymer layer 47 arranged adjacent to the side 48 of the first electronic component 31 and the second electronic component 33. The second polymer layer 54 may also be arranged between the conductive areas of the second main surface 46 of the semiconductor module 30 ′. For example, Figure 3A In the embodiment illustrated in , the second polymer layer is arranged between the further layer 51 and the drain pad 43. In some embodiments, the second epoxy layer 54 may cover the outer peripheral area of ​​the drain pad 43 and the conductive layer 51.

[0097] In such Figure 3B In some of the embodiments illustrated in , conductive layer 51 is completely covered by second polymer layer 54 and at least a portion of drain pad 43 remains uncovered by second polymer layer 54 .

[0098] exist Figure 2 In the embodiment illustrated in FIG. 3 , the first electronic device 31 and the second electronic device 33 are transistor devices and the circuit formed is a half-bridge circuit. However, the type of electronic devices arranged in the first device region and the second device region of the semiconductor module is not limited to transistor devices. For example, one of the electronic devices may be a transistor device and the other of the electronic devices may be a driver device, such as a gate driver device, or a portion of a gate driver device such as a pull-down FET for driving the gate of a transistor device, or a diode or a passive device such as an inductor, a capacitor or a resistor. Further, the module is not limited to including only two electronic devices and may include three or more electronic devices. For example, a module may include two transistor devices coupled to form a half-bridge circuit, and also a driver device, or a portion of a gate driver device such as a pull-down FET for driving the gates of two transistor devices.

[0099] As mentioned above, in embodiments where the module includes a redistribution structure having a vertical portion extending between the first and second major surfaces of the module, the vertical portion may be provided by one or more conductive vias positioned in one or more of the electronic devices. In these embodiments, the sidewalls of the vias are formed by the semiconductor material (e.g., silicon) of the electronic device. In other embodiments, the vertical portion of the redistribution structure may be positioned laterally adjacent to the electronic device.

[0100] Figure 4 A module 60 is shown, which includes a first electronic device 61 and a second electronic device 62, which are arranged adjacent to each other in the lateral direction and embedded in a first polymer layer 63, which covers at least a portion of the side 64 of both the first electronic device 61 and the first electronic device 62. In some embodiments, the first polymer layer 63 can cover the first major surface 65 of the first electronic device 61 and the peripheral area and edge of the first major surface 66 of the second electronic device 62, and the first major surface 66 of the second electronic device 62 is positioned to be adjacent to the first major surface 65 of the first electronic device 61 in the lateral direction and can be substantially coplanar with the first major surface 65 of the first electronic component 61. The portion of the first polymer layer 63 arranged between the first electronic device 61 and the second electronic device 62 can be described as a non-device area 67, wherein the first electronic device 61 is arranged in a first device area 68 and the second electronic device 62 is arranged in a second device area 69.

[0101] In this embodiment, the conductive via 70 is arranged in the non-device area 67. The conductive via 70 has a sidewall 71 formed by the material of the first polymer layer 63. The conductive via 70 may have an elongated shape in a plan view. The conductive via 70 may include a conductive material, such as a metal such as copper. In some embodiments, the sidewall 71 defining the via 70 in the first polymer layer 63 may be lined with one or more metal layers that can be used to improve adhesion to the material of the first polymer layer 63 and one or more conductive layers having a thickness suitable for carrying the current required by a specific application. In some embodiments, the via 70 may be substantially filled with a conductive material.

[0102] The semiconductor module 60 also includes a first metallization structure 73 arranged at a first main surface 74 of the module 60. The first metallization layer 73 may include two or more conductive portions, wherein one or more conductive portions are arranged on a first main surface 65 of the first semiconductor device 61 and a first main surface 66 of the second semiconductor device 62. Similarly, the semiconductor module 60 may include a second metallization layer 75 arranged at a second main surface 76 of the module 60, which is configured to provide one or more portions on a second surface 77 of the first electronic device 61 and a second surface 78 of the second electronic device 62, respectively. The conductive via 70 may be electrically coupled to a portion of the first metallization structure 73 that extends from one of the electronic devices (e.g., the second electronic device 62) to the conductive via 70. The conductive via 70 may be coupled to another of the electronic devices (e.g., the first electronic device 61) through a portion of the second metallization layer 75 arranged on an opposite side of the module 76, the portion of the second metallization layer 75 extending between the first electronic device 61 and the conductive via 70.

[0103] In the case where the first electronic device 61 and the second electronic device 62 are transistor devices and the desired circuit is a half-bridge configuration, a portion of the second metallization structure 75 can extend from a drain pad located at the second surface 77 of the first electronic device 61 to the conductive via 70, and a portion of the first metallization layer 73 can extend from the conductive via 70 to a source pad arranged at the first main surface 66 of the second electronic device 62.

[0104] The portion of the second metallization structure 75 extending from the second surface 77 of the first electronic device 61 to the second surface 78 of the second electronic device 62 is electrically insulated from further portions of the second metallization structure 75 arranged on the second surface 78 of the second electronic device 62, such as the contact pad 82. The electrical insulation may be provided by an insulating layer 63 lining the sidewalls of the via 70 and extending through the second surface 78 of the second electronic component 62 in the region adjacent to the via 70 and being arranged directly on the second surface 78 of the second electronic component 62. The portion of the second metallization structure 75 positioned on the second surface 78 of the second electronic device 62 is arranged on the insulating layer 63. The insulating layer 55 also serves to electrically insulate the second surface 78 of the second electronic device 62 from the second surface 77 of the first electronic device 61.

[0105] In other embodiments, the conductive layer 75 has a lateral extent such that it does not extend onto the semiconductor body of the first electronic device 61 but instead extends only into the conductive material in the via 70 .

[0106] Figure 5An enlarged top view and an enlarged side view of a conductive via 70 in a semiconductor module 60 are shown. The first electronic component 61 includes a contact pad 79 on its first main surface 65, which can be a source pad, for example, if the first electronic component is a transistor device, and the first electronic component 61 includes a second contact pad 80 on its second main surface 77, which can be a drain pad, for example. The second electronic component 62 also includes a contact pad 81 on its first main surface 66 and a contact pad 82 on its second main surface 78. If the second electronic component is a transistor device, the contact pad 81 can be a source pad and the contact pad 82 can be a drain pad. Each transistor device can also include Figure 5 The gate pad cannot be seen in the view of FIG. The edge region of the first electronic device 61 formed between the first main surface 65 and the side 64 is partially covered by the first polymer layer 63. The entire side 64 of the first electronic component 61 can be covered by the first polymer layer 63. Similarly, the edge region 85 of the second electronic device 62 formed between the first main surface 66 and the side 64 can be covered by the first polymer layer 63. The first polymer layer 63 can be adjacent to the contact pads 79, 81 arranged on the first main surface 65 of the first electronic device 61 and the first main surface 66 of the second electronic device 62, respectively.

[0107] A redistribution structure 86 for coupling a contact pad 80 with a contact pad 81 disposed on an opposite side of the module 60 may be formed by a conductive path extending from the contact pad 80 through the through hole 70 to the contact pad 81 to electrically couple the drain of the first electronic device 61 to the source of the second electronic device 62. The redistribution structure 86 includes a through hole 70 formed in the first polymer layer 64, the through hole 70 extending substantially parallel to the side 64 of the first electronic device 61 and the second electronic device 62. The through hole 70 may have a roughened sidewall 71 to improve adhesion to the conductive material positioned within the through hole 70. The sidewall 71 of the through hole 70 may also be lined with one or more adhesion layers. The redistribution structure 86 may be formed using several parts. For example, the conductive through hole 70 extending through the first polymer layer 63 may be filled with a conductive material and a lateral layer 87 applied to the upper surface of the through hole 70, the lateral layer 87 extending from the through hole 70 to the contact pad 81. A second lateral layer 88 may be applied to the opposite back side of module 60, extending from contact pads 80 to the lower surface of conductive vias 70. In other embodiments, a conductive layer may be applied that extends from contact pads 81 into vias 70, and the two conductive layers join and create a continuous conductive path in vias 70 adjacent to side 64 by virtue of the layer extending from contact pads 80 into vias 71.

[0108] A semiconductor module according to any one of the embodiments described herein can be used to form a circuit by mounting the module to a higher level substrate (e.g., a circuit board such as a printed circuit board) including a redistribution structure. In other embodiments, the semiconductor module can be packaged. Packaged semiconductor modules enable the module to be provided in a package having a standard footprint and a standard outline, which can help simplify the use of the module in a particular application.

[0109] Figure 6 The figure shows the package 90. Figure 3B Schematic top view of a semiconductor module 30' of FIG. 30 . In the illustrated embodiment, the package 90 includes a die pad 91, five leads 92 to 96, and a plastic housing 97. The die pad 91 and the inner portions of the leads 92 to 96 are located within the plastic housing 97. Portions of the leads 92 to 96 extend to the outside of the plastic housing 97 and provide external contacts for the package 90. In this embodiment, the leads 92 to 96 are positioned adjacent to a single side of the die pad 91, wherein the middle one of the five leads, i.e., lead 94, is integrated with the die pad 91. The module 30' is mounted on an upper surface 98 of the die pad 91.

[0110] Because the drain pad 43 of the second electronic device 33 is exposed at the second main surface 46 of the semiconductor module 30', and the drain pad 38 of the electronic device 61, the further conductive layer 51 and the conductive via 50 are covered by the second polymer layer 54 by mounting the second main surface 46 of the module 30' to the upper surface 98 of the die pad 90, the drain pad 43 of the second electronic device 33 can be electrically coupled to the die pad 91 and thus to the intermediate lead 94. The pads 35, 36, 40, 41 arranged at the first main surface 45 of the module 30' face upwards and can be electrically coupled to the leads 92, 93, 95, 96, which are spaced apart from the die pad 91 by conductive connections, such as one or more bonding wires, conductive ribs or contact clips. Source pad 36 may be coupled to first lead 92 , gate pad 35 may be coupled to lead 93 , and source pad 41 and gate pad 40 of second electronic device 33 may be coupled to leads 95 , 96 , respectively.

[0111] Still Figure 6 Illustrated in the top view of FIG. 3 is a non-device region 100 of the module 30'. The device regions 32, 34 are indicated by dashed lines. The conductive via 50 is located below the source pad 41 and is also indicated by dashed lines.

[0112] The package is not limited to Figure 6The package may include the arrangement of die pads, leads, connections, and housing as shown in FIG. For example, the package may be a surface mount device such as a Super SO8 package or a QFN (Quad Flat No Lead) package. For example, contact clips may be used instead of bond wires for power connections (e.g., connections other than the connection to the gate).

[0113] A method for preparing a semiconductor module according to some embodiments will now be described with reference to FIG. 7 .

[0114] Fig. 7A A cross-sectional view of a semiconductor wafer 110 is shown comprising a first main surface 111 and a second main surface 112 opposite the first main surface 111. The semiconductor wafer 110 comprises a plurality of component locations, two of which 113, 113' are illustrated in FIG7. Adjacent component locations are spaced apart from each other by separation regions 114. The semiconductor wafer 110 may comprise silicon and may be a silicon single crystal wafer, or a silicon single crystal wafer comprising an epitaxial silicon layer with semiconductor devices formed therein on top, whereby the epitaxial layer provides the first main surface 111 and the silicon single crystal wafer provides the second main surface 112.

[0115] The component locations 113 are typically arranged in rows and columns to form a regular grid so that the separation regions 114 provide a shape having substantially orthogonal strips in a plan view. Each component location 113 includes two or more device regions 115, 116 separated by a non-device region 117 that does not include any device structure. The wafer 110 also includes a first metallization structure 118 on its first major surface 111. The first metallization structure 118 can be constructed so that it is located only in the device regions 115, 116 and that the non-device region 117 is free of the first metallization structure 118.

[0116] One of the device locations of the component locations 113 (e.g., the device region 116) includes one or more conductive vias 134 extending from the first metallization structure 118 into the wafer 110 to a certain depth. The conductive vias 134 may be in the form of blind vias 135 having a bottom located at a certain depth from the first major surface 111, the depth being greater than, for example, Figure 7B The blind via 135 may include an insulating material (not seen in the figure) covering at least the sidewalls of the blind via 135 and a conductive material disposed on the insulating material. The conductive material may include one or more liner layers lining the sidewalls of the blind via and one or more further conductive materials on the liner layers. The conductive material may fill the remainder of the blind via 135. The conductive material may include one or more metals or alloys and / or polysilicon.

[0117] Figure 7B The wafer 110 is shown after forming a first trench 119 that has been inserted into the first main surface 111 in the separation region 114 and after forming a second trench 120 that has been inserted into the first main surface 111 in the non-device region 117. The trenches 119, 120 may have a thickness slightly greater than the predetermined final thickness t of the electronic component. f and is less than the initial thickness t of the wafer 110 i The depth d. .

[0118] Figure 7C The wafer 110 is shown after a first polymer layer 121 (which in this embodiment comprises epoxy) has been inserted into the first trench 119 and the second trench 120. In this embodiment, the first polymer layer 121 also extends over the peripheral region of the discrete portions of the first metallization layer 118 and thus has an uppermost outer surface 122 that is located in a plane above an outer surface 123 of the first metallization structure 118. In other embodiments, the first polymer layer may be adjacent to portions of the first metallization layer and form a substantially coplanar surface.

[0119] Fig.7D Wafer 110 is shown after carrier 124 has been applied to outer surface 122 of first polymer layer 121. Because outer surface 122 of first polymer layer 121 is arranged at a plane above outer surface 123 of first metallization layer 118, cavity 125 is formed between carrier 124 and first metallization structure 118.

[0120] Fig. 7E The diagram shows that a portion of the second main surface 112 of the semiconductor wafer 110 is removed, so that the initial thickness t i is reduced to the final desired thickness t f The portions of the first polymer layer 121 disposed in the separation region 114 and the non-device region 117 are exposed in the processed second surface 126, and the conductive material in the blind via 134 disposed in the second device position 116 is exposed at the processed second surface to generate a through contact or a through silicon via (TSV). Fig. 7E The removal of a portion of the wafer 110 is schematically indicated in FIG by arrows 127. For example, a portion of the second surface 112 of the semiconductor wafer 110 may be removed by grinding and / or chemical mechanical polishing.

[0121] Figure 7FThe second metallization structure 128 is shown applied to the processed second surface 126. In some embodiments, one or more insulating layers (e.g., oxide layers) may be applied to the processed second surface 126 and structured before the second metallization structure 128 is applied to the processed second surface. The second metallization layer 128 may include a seed layer 129 and a further conductive layer 130 applied to the seed layer 129. The second metallization layer 128 may be applied such that it forms a closed layer extending through the exposed portions of the first polymer layer 121, the processed second surface 131 of the device regions 115, 116, and the portions of the conductive material in the vias 134 exposed at the processed second surface 126. The conductive layer 130 may be as shown. Figure 7G As shown, the separation region 114 is structured so that there is no conductive layer. The second metallization layer 128 can be structured so that an electrical connection is formed between the first device region 115 and the second device region 116 in each component location 113. Depending on the desired electrical connection for the circuit, one or more further discrete conductive regions can also be formed in one or both component locations 113.

[0122] The conductive via 134 can be electrically coupled to a structured portion 136 of the second metallization layer 128, which extends through the non-device area 117 to other devices, such as at Figure 7G 1 , the vias extend from the second device region 116 to the first device region 115. One or more further dispersed structured portions 137 separated from the structured portion 136 may be formed on the first device region 115 and / or the second device region 116. The device region including the through hole may include dispersed portions and portions extending onto adjacent device regions.

[0123] In some embodiments, the second polymer layer 131 may be applied to the separation area 114 and the non-device area 117 at the processed second surface 126. Figure 7HIn some embodiments of the embodiment illustrated in FIG. 1 , the second metallization layer 128 may be constructed such that both the conductive layer 130 and the seed layer 129 and some portions of the first polymer layer 121 disposed at the processed second surface 126 in the separation region 114 are removed. The second polymer layer 131 may be applied in the separation region 114 such that it is in contact with the first polymer layer 121 and overlaps the peripheral region of the second metallization layer 128 formed in the assembly location 113. The interface between the first polymer layer and the second polymer layer 131 may be positioned adjacent to the sidewalls of the device regions 115, 116. The semiconductor modules 132 may then be singulated from the wafer by inserting separation lines 133, for example by sawing along the separation region 114. The width of the separation lines may be less than the width of the separation region 114 so that the outermost sides of the individual modules 132 are covered by the first epoxy layer 121 and the second epoxy layer 131.

[0124] In some embodiments, semiconductor module 132 includes a redistribution structure including a vertical portion extending substantially perpendicular to the first lateral main surface and the second lateral main surface. As discussed above, the vertical portion can be provided by a conductive via 134, which can be located in one or more of the device regions 115, 116 and thus have sidewalls formed by the semiconductor material of the electronic device. The sidewalls of the via can be lined with an insulating material to electrically insulate the conductive material in the via from the semiconductor material of the electronic device. The conductive material can include one or more metals.

[0125] In other embodiments, the conductive via may be located in the non-device region 117 and formed by inserting a further trench in the polymer material in the non-device region 117. Such a conductive via extends substantially parallel to the sides of the adjacent device regions 115, 116. The conductive material in the via is electrically insulated from the semiconductor material of the device regions 115, 116 by the polymer material. The sidewalls of the conductive via are formed of the polymer material. This embodiment may be used to manufacture Figure 4 and Figure 5 The semiconductor module 60 is shown in FIG.

[0126] In some embodiments, the vertical portion of the redistribution structure may be formed of a semiconductor material and may be formed of a portion or island of semiconductor material located within the device region.

[0127] Figure 8 A cross-sectional view of the module 140 is shown. Figure 21 and 2. As in the embodiment illustrated in FIG. 1 , the semiconductor module 140 includes a first electronic device 31 arranged in a first device region 32 and a second electronic device 33 formed in a second device region 34. The semiconductor module 140 differs in the shape of the vertical portion of the redistribution structure between the drain pad 38 on the second surface 39 of the first electronic device 31 and the source pad 41 arranged on the first surface 42 of the second electronic device 33. In this embodiment, the second device region 34 includes an island 141 of semiconductor material, which is electrically insulated from further semiconductor material 142 of the second electronic device 33 by an insulating material 143. The insulating layer 143 extends from the first surface 42 to the second surface 44 to isolate the island 141 from the rest of the second electronic device 33.

[0128] exist Figure 8 In the embodiment illustrated in , the island 141 is formed at the periphery of the second electronic component 33 and is bounded on at least one side by a portion of a first polymer layer 47 of a polymer material, the first polymer layer 47 being arranged between the side 48 of the first electronic device 31 and the second electronic device 33 .

[0129] The island 141 may include a semiconductor material having a conductivity higher than that of the semiconductor material 142 of the electronic device. The island 141 may be more highly doped than the semiconductor material of the electronic device. In embodiments where the electronic devices 31, 33 are formed by a semiconductor wafer including an epitaxial layer on a substrate, the epitaxial layer may be processed to form a transistor device structure at the first surface 37, 42. The substrate may be highly doped and have sufficient conductivity to form a portion of the drain region and the redistribution structure. In these embodiments, the upper epitaxial layer may be removed from the substrate at the upper portion of the island 141 and replaced by a material having a higher conductivity so as to form a vertical conductive connection from the first surface 42 to the opposite second surface 44. Alternatively, the conductivity of the epitaxial layer may be locally increased in the island 141 by increasing the doping level (e.g., by implantation), a contact extending through the upper epitaxial layer to the underlying substrate may be used, or a combination of a contact extending through the upper epitaxial layer and a locally increased doping level may be used.

[0130] Conductive island 141 may be electrically coupled to source pad 41 disposed on first surface 42 of second electronic component 33 by conductive layer 144 extending between island 141 and source pad 41. Conductive island 141 may be electrically coupled to drain pad 38 disposed on second surface 39 of first electronic component 31 by conductive layer 51 extending from drain pad 38 to island 141 on the opposite side of island 141. Conductive layer 51 has a lateral extent such that its periphery is disposed on insulating material 143 and stops close to the semiconductor body of second electronic device 33 so that it is not disposed on rear side 44 of electronic device 33.

[0131] In other embodiments, the island may be formed within the semiconductor material of the device region such that it is surrounded on all sides by insulating material 143 .

[0132] The second polymer layer 54 may be arranged on the second surface 39 of the first electronic device 31 and the second surface 44 of the second electronic device 33 between the further conductive layer 51 and the drain pad 38 and at the periphery of the module. The second polymer layer 54 may also completely cover the further conductive layer 51 .

[0133] Fig. 9 The semiconductor module 150 is shown, which includes Figure 2 The semiconductor module 150 further includes a first electronic device 31 arranged in a first device region 32 and a second electronic device 33 formed in a second device region 34 in the embodiment illustrated in FIG. Figure 8 1 and 2. The embodiment shown in FIG. 1 is a redistribution structure between a drain pad 38 on a second surface 39 of a first electronic device 31 and a source pad 41 arranged on a first surface 42 of a second electronic device 33 in the form of a conductive island 141 of semiconductor material. The conductive island 141 is electrically insulated from a further semiconductor material 142 of the second electronic device 33 by an insulating material 143.

[0134] The semiconductor module 150 and Figure 8 The semiconductor module 140 of the present invention is different in that the separation region 151 formed between the outermost facing sides 48 of the device regions 32, 34 of the module 150 and the non-device region 152 extending between the sides 48 include an insulating material 153 separated from the first polymer layer 47 and the second polymer layer 54. The insulating material 153 may be the same as or different from the insulating material 143 that electrically insulates the conductive island 141 providing the vertical redistribution structure from the body of the second semiconductor device 33. The insulating material 153 may include, for example, an oxide or a nitride, such as SiO 2 .

[0135] The insulating material 153 has a thickness corresponding to the thickness of the first electronic device 31 and the second electronic device 33, and extends from the first surface 37 to the second surface of the first electronic device 31 and from the first surface 42 to the second surface 44 of the second electronic device 33. The first polymer layer 47 is arranged on the insulating material 153 in the separation area 151 and the non-device area 152. The second polymer layer 54 is arranged on the insulating material 153 in the separation area 151.

[0136] Conductive layer 51 extends from drain pad 38 through second major surface 37 of first electronic device 31 and through insulating material 153 in non-device region 151. Conductive layer 51 has a lateral extent such that its periphery is arranged on insulating material 143 that insulates island 141 from the semiconductor body of second electronic device 33 and stops near the semiconductor body of second electronic device 33 so that it is not arranged on or electrically coupled to the back side 44 of electronic device 33.

[0137] As in Figure 3B In the embodiment shown in FIG. 1 , the further conductive layer 51 may be formed as in Fig. 9 As shown in FIG. 5 , the second polymer layer 54 is completely covered, or as shown in FIG. Figure 8 As in the embodiment shown in FIG. 5 , a further conductive layer 51 is adjacent thereto.

[0138] In summary, the embodiments described herein combine the advantages of multi-chip dies (such as closer chip distances), single pick-up of multi-chip dies, and front-side contacts of gate and sense pads, and can be used to cost-effectively and efficiently provide modules and electronic components with desired circuits.

[0139] In such as Figure 2 In some embodiments of those illustrated in FIG. 3 and FIG. 7 , at least one of the semiconductor devices 33 of the semiconductor modules 30 , 30 ′; 132 includes: a conductive via 50 ; 134 including a conductive material extending from a front surface to a rear surface of a semiconductor body of the semiconductor device in a through hole or via. The conductive via 50 ; 134 may be manufactured by inserting a through hole into the front surface 111 of the semiconductor wafer 110 as in the embodiment illustrated in FIG. 7 a . In other embodiments, the conductive via 50 ; 134 may be formed by inserting a through hole into the opposite rear surface 112 of the semiconductor wafer 110 .

[0140] Now, reference will be made to FIGS. 10 to Fig.15 Embodiments for forming conductive vias are described with respect to a semiconductor package including a single semiconductor device. However, these embodiments can also be used in a semiconductor module including two or more semiconductor devices (e.g., see Figures 1 to 9Conductive vias are prepared in the module described above, whereby one, two or all of the semiconductor devices of the module may include conductive vias.

[0141] 10 a illustrates a cross-sectional view of a semiconductor wafer 160 comprising a first main surface 161 and a second main surface 162 opposite the first main surface 161. The semiconductor wafer 160 may comprise silicon and may be a silicon single crystal wafer, or a silicon single crystal wafer comprising an epitaxial silicon layer on top in which semiconductor devices are formed, whereby the epitaxial layer provides the first main surface 161 and the silicon single crystal wafer provides the second main surface 162.

[0142] The semiconductor wafer 160 includes a plurality of component locations 163, two of which are illustrated in FIG. 10. The method will be described with reference to a single component location 163. However, in practice the method is performed on all component locations in the wafer 160. Adjacent component locations 163 are spaced apart from each other by separation regions 164. Component locations 163 are typically arranged in rows and columns to form a regular grid so that separation regions 164 provide a shape having substantially orthogonal strips in a plan view. Each component location 163 includes a single device region 165, which includes a single semiconductor device 167 in this embodiment. Device region 165 may include a power device 167, such as a transistor device, particularly a transistor device with a vertical drift path, which is generally referred to as a vertical transistor device. For example, the vertical transistor device may be a MOSFET device or an IGBT.

[0143] The vertical transistor device may have a first power electrode and a control electrode located on a first surface and a second power electrode located on an opposite second surface. The first power electrode may be a source of a MOSFET device or an emitter of an IGBT device, the second power electrode may be a drain of a MOSFET device or a collector of an IGBT device, and the control electrode may be a gate of a MOSFET device or a gate of an IGBT device.

[0144] At least one first trench 166 is formed in the first surface 161 of the semiconductor wafer 160 in the device region 165 of the component location 163. The first trench 166 may have an elongated shape in a plan view or may have a substantially circular or square shape in a plan view. In some embodiments, a plurality of first trenches may be formed in each component location 163. The first trench 166 has a bottom 171 and a sidewall 170 and may have a depth that is less than the thickness of the semiconductor wafer 160. The depth of the first trench 166 may also be slightly greater than the intended final thickness of the semiconductor die, for example, about 10% deeper than the intended final thickness. The first trench 166 may be formed by etching.

[0145] In some embodiments, first trench 166 has a width to depth ratio of 0.5:1.0 to 1.5:1.0 (eg, about 1:1). This ratio can be used to assist in reliably depositing conductive material into first trench 166, such as by electrodeposition.

[0146] 10 b, a first metallization structure 168 is formed on the first main surface 161 and a conductive material 169 is inserted into the first trench 166. The conductive material 169 may include one or more sub-layers and may fill the first trench 166. In an embodiment not shown, the conductive material 169 lines the sidewalls 170 and the bottom 171 of the first trench, leaving a gap in the center. The conductive material 169 may include multiple sub-layers.

[0147] The first metallization layer 168 may include a plurality of sub-layers. Fig.12 An enlarged view of a structure that may be used for the first metallization structure 168 is shown and the various sub-layers are illustrated. The conductive material 169 located in the first trench 166 may include the same structure as the first metallization layer.

[0148] Fig.12 The structure of the sub-layers illustrated in FIG. 4 may also be used to form a first metallization layer of a semiconductor module comprising two or more devices that are electrically connected together to form a circuit, such as a half-bridge configuration. Fig.12 The structure of the sublayers shown in FIG. 1 can also be used to form Figures 1 to 9 The first metallization layer of the semiconductor module shown in FIG.

[0149] Located in Fig.12 The structure of the sub-layer in the first trench 166 shown in FIG. 1 can also be used for conductive vias in semiconductor modules, whereby the conductive vias can be formed as in FIG. Figure 2 3 and 7, or in the semiconductor die as in the embodiments illustrated in FIG. Figure 4 and Figure 5 As in the embodiment shown in FIG. , the semiconductor die are located between the semiconductor dies.

[0150] exist Fig.12 In the embodiment illustrated in , the first metallization layer 168 includes sublayers of the items arranged on the first surface 161 in the following order: titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum copper alloy (AlCu) and copper (Cu). In other embodiments, the structure of the first metallization layer 168 may include sublayers of titanium silicon alloy (TiSi), whereby silicon is deposited together with titanium onto the first surface 161, titanium nitride (TiN), tungsten (W), aluminum copper alloy (AlCu) and copper (Cu). The copper layer can be deposited by a combination of physical vapor deposition (PVD) techniques and galvanic techniques (such as electroplating or electroless plating). In Fig. 10B Two copper layers 172, 173 of the first metallization structure 168 are indicated in . The copper layer 172 deposited by PVD may have a thickness of about 5 μm and the copper layer 173 deposited by galvanic techniques may have a thickness of about 10 μm.

[0151] In some embodiments, the conductive material 169 in the first trench 166 may include sublayers of the items arranged on the sidewalls 170 and the bottom 171 of the first trench 166 in the following order: titanium (Ti), titanium tungsten (TiW) and copper (Cu), or sublayers of the items arranged on the sidewalls 170 and the bottom 171 of the first trench 166 in the following order: titanium (Ti) and copper (Cu). The conductive material 169 may be inserted into the first trench 166 using two or more different processes. For example, the titanium sublayer and the titanium tungsten sublayer may be deposited by physical vapor deposition (PVD) such as sputtering, and the copper may be deposited using a galvanic technique. The copper layer may be deposited by a combination of physical vapor deposition techniques and galvanic techniques. Before depositing the conductive material 169, an insulating layer may also be used to line the first trench 166.

[0152] The first metallization layer 168 provides external contacts 174 of the final semiconductor package that form package footprints 175. In some embodiments, a further protective layer 176 is located on the outermost surface of the copper of the first metallization layer 168.

[0153] The protective layer 176 may include a material to protect the underlying first metallization layer 168 from oxidation or corrosion, since the metallization layer 168 provides external contacts of the final semiconductor package. The protective layer 176 may include a metal or alloy, such as Sn or Ag in the case of a copper outer layer of the first metallization layer 168, and may also be present in the solder connection formed between the external contacts of the final semiconductor package and a higher level circuit board. The protective layer 176 may also be formed of soft solder.

[0154] As illustrated in FIG. 10c, a second trench 177 is inserted into the first surface 161 of the semiconductor wafer 160 in the separation region 164. The second trench 177 has a bottom that is located within and formed by the semiconductor material of the semiconductor wafer 160. The second trench 177 may have a depth that is slightly greater than the desired thickness of the semiconductor die. The second trench 177 may have approximately the same depth as the first trench 166.

[0155] As illustrated in FIG. 10 d , a first polymer layer 178 is applied to the first major surface 161 so that the edge regions of the second grooves 177 and the component locations 163 adjacent to the separation regions 164 are covered with the first polymer layer 178. The first polymer layer 178 may include an epoxy resin. In some embodiments, the edge regions of the first metallization layer 168 are also covered with the first polymer layer 178 so that the central region of the protective layer 176 remains exposed from the first polymer layer 178. In these embodiments, the first polymer layer 178 is used to define the external contacts 174 and the package placeholders 175.

[0156] The method then continues by removing portions of the second surface 162 of the semiconductor wafer 160 (as schematically indicated by arrows 179 in FIG. 10 d ) to expose portions of the first polymer layer 178 in the separation region 164 and portions of the conductive material 169 in the first trench 166 and produce a processed second surface 162 ′. The first side 161 of the semiconductor wafer 160 may be mounted on a carrier such as glass, and the second surface 162 is removed by grinding and / or chemical mechanical polishing to reduce the thickness of the semiconductor wafer 160 to a desired thickness. The desired final thickness may be in the range of 5 μm to 60 μm, for example, 15 μm to 30 μm.

[0157] As illustrated in Figure 10e, a second metallization layer 180 is applied to the processed second surface 162'. Because the second metallization layer 180 is in direct contact with the conductive material 169 in the first groove 166, the second metallization layer 180 is operably coupled to the conductive material 169 in the first groove 166 and is operably coupled to the external contact pad 174 on the first main surface 161. The second metallization layer 180 can also include a plurality of sublayers, such as titanium and copper. Copper can be deposited using two different techniques, for example, physical vapor deposition techniques can be used to deposit a first copper layer that can serve as a seed layer, and further copper layers are deposited on the first copper layer by galvanic techniques. A protective layer can also be located on the copper layer. The protective layer can be, for example, silver or tin. In some embodiments, the protective layer applied to the second metallization layer 180 can be electrically insulated because the second metallization layer 180 does not provide external contact in the final semiconductor package.

[0158] In an embodiment where device 167 is a vertical transistor device, second metallization layer 180 is coupled to a drain region of the transistor device and conductive material 169 within first trench 166 provides a vertical conductive path or via 182 from the drain region to a contact pad 174 that provides a drain external contact 186 for the semiconductor package.

[0159] The semiconductor package 183 is separated from the wafer 160 by cutting through the first polymer layer 178 located on the separation area 164, and in particular, cutting through the first polymer layer 178 located in the second groove 177. In an embodiment in which the width of the cut inserted into the second groove 177 is smaller than the width of the second groove 177, the side 184 of the final second semiconductor package 183 may be covered by the first remaining portion of the first polymer layer 178. The resulting semiconductor package 183 is illustrated in FIG. 10f.

[0160] In Figures 10e and 10f, cross-sectional views of semiconductor wafer 160 are illustrated, in which drain external contacts 186, gate external contacts 187 and source external contacts 188 of semiconductor package 183 can be seen. Source electrodes 193 and gate electrodes 194 arranged on first surface 161 of component location 163 and transistor device 167, and drain electrodes 195 arranged on second surface of component location 163 and transistor device 167 are also illustrated in the cross-sectional views of Figures 10e and 10f.

[0161] In some embodiments, as shown in Fig.7I As described with respect to the fabrication of the semiconductor module, after forming the second metallization layer 180 and before singulating the packages 183 from the wafer 160 , a second insulating layer, which may include a polymer such as an epoxy, is applied to the processed second surface 162 ′.

[0162] In some embodiments, solder 185 is applied to the outer surface of external contact 174. Solder 185 may be applied before separating semiconductor package 183 from semiconductor wafer 160. In some embodiments, protective layer 176 of first metallization layer 168 may be omitted and solder 185 may serve as a protective layer.

[0163] Semiconductor packages 183 may be singulated or separated from wafer 160 by laser cutting through first polymer layer 178 and then removed from the dicing tape by a pick and place machine and placed into a carrier entity for delivery to a customer. Electrical testing of package 183 may be performed prior to singulation.

[0164] Thus, in some embodiments, a semiconductor package 183 including a first transistor device 167 is formed. The first semiconductor device 163 includes: a first surface 161 and a second surface 162' opposite to the first surface 161; a first power electrode, such as a source electrode; and a control electrode, such as a gate electrode, arranged on the first surface 161; and a second power electrode, such as a drain electrode, arranged on the second surface 162'. The semiconductor package 183 includes a first metallization structure 168 arranged on the first surface, the first metallization structure 168 including a plurality of external contact pads 186, 187, 188, and the external contact pads 186, 187, 188 include a protective layer 176 of solder (Ag or Sn). The semiconductor package 183 further includes: a second metallization structure 180 arranged on the second surface 162'; a conductive connection 169 extending from the first surface 161 to the second surface 162' and electrically connecting the second power electrode to the external contact pad 186 of the first metallization structure 168. A first epoxy layer 178 is disposed on the side 184 of the transistor device 163 and on the first surface 161 of the transistor device 163 , the first epoxy layer 178 including openings defining lateral dimensions of the external contact pads 186 , 187 , 188 and the package footprint 175 .

[0165] In some embodiments, the semiconductor package further includes a second epoxy layer on the second surface 162 ′, wherein the second epoxy layer covers an edge region of the second surface 162 ′ and leaves a region of the second metallization layer 180 exposed, or the second epoxy layer completely covers the second metallization layer 180 .

[0166] In the method illustrated with reference to FIG. 10 , both the first trench 166 for preparing the conductive via 182 and the second trench 177 for separating the semiconductor package 183 from the wafer 160 are introduced into the wafer 160 from the first side 161. In an alternative embodiment, the second trench 177 is inserted into the first main surface 161 of the semiconductor wafer 160, and the first trench 166 is introduced into the semiconductor wafer 160 from the second side 162 of the semiconductor wafer 160. After the processing of the first side is completed and the first trench 166 is introduced into the semiconductor wafer 160 after the semiconductor wafer 160 has been thinned, the processed second surface 162′ has been formed and the polymer layer 178 located in the second trench 177 has been exposed in the processed second surface 162′. This embodiment will be described with reference to FIG. 11 .

[0167] 11 a shows a semiconductor wafer 160 comprising a first main surface 161 and a second main surface 162 opposite the first main surface 161. The wafer 160 comprises component sites 163 separated by separation regions 164, wherein semiconductor devices 167 are located in device regions 165 of the component sites 163.

[0168] The first metallization structure 168 is formed on the first surface 161 of the semiconductor wafer 160 above the component location 163 and is structured to produce a plurality of external contacts 174 forming a package footprint 175. The first metallization structure 168 may have Fig.12 A second trench 177 is then formed in the first surface 161 of the semiconductor wafer 160 in the separation region 164, and a first insulating layer 178 including an epoxy resin is applied to the first surface 161 so that it fills the second trench 177. The first polymer layer 178 may further extend through the peripheral edge region of the component location 163, and in some embodiments may also extend through the peripheral region of the first metallization layer 168, and thus through the peripheral region of the external contact 174 of the package location 175 provided by the first metallization layer 168.

[0169] 11b, portions of the second surface 162 of the semiconductor wafer are then removed, exposing portions of the first polymer layer 178 located in the second grooves 177 of the separation regions 164. The first surface including the first polymer layer 178 may be mounted on a carrier such as a glass carrier, and the second surface 162 removed by grinding and / or chemical mechanical polishing to reduce the thickness of the semiconductor wafer 160 to a desired final thickness, which may be in the range of 5 μm to 60 μm, and produce a processed second surface 162'.

[0170] As illustrated in FIG. 11c , a first trench 166 is inserted into the processed second surface 162′ in the device region 165 of the component location 163. The first trench 166 is used to form a vertical conductive connection between the processed second surface 162′ and the first surface 161 of the semiconductor wafer 160. The first trench 166 has a certain depth so that it has a bottom 170 formed by the first metallization layer 168. The first trench 166 extends through the entire thickness of the thinned semiconductor wafer 160.

[0171] As in Fig.11D As shown in FIG. 1 , a conductive material 169 is inserted from the processed second surface 162 ′ into the first groove 166. The conductive material 169 may include two or more sub-layers. Fig.121 and 2 illustrate an embodiment in which the conductive material 169 comprises sub-layers of the items on the sidewall 171 in the order of: titanium, titanium tungsten, and copper, or comprises sub-layers of the items on the sidewall 171 in the order of: titanium and copper. The copper may be deposited using two or more different methods, for example using physical vapor deposition such as sputtering to deposit a first copper layer, and using galvanic deposition to deposit further copper layers and increase the thickness filling the second trench 166.

[0172] The first trench 166 may be inserted into the processed second surface 162' by etching the processed second surface 162'. A sublayer of the first metallization layer may be used as an etch stop. In some embodiments, for example, for a Fig.12 For the first metallization layer 168 of the structure illustrated in FIG. 1 , the tungsten sublayer may be used as an etch stop. The titanium sublayer of the conductive material 169 may be in direct contact with the tungsten layer of the first metallization layer 168 .

[0173] As illustrated in Figure 11d, a second metallization layer 180 is then applied to the processed second surface 162' so that it contacts the conductive material 169 located in the first trenches 166 and so that it is operably connected to the external contacts on the first surface 161 of the semiconductor wafer 160. The semiconductor package 183 is then singulated from the wafer 160 by cutting through the separation areas 164 and in particular through the first polymer layer 178 located in the second trenches 177, as schematically indicated by arrows in Figure 11d, to produce a semiconductor package 183 as illustrated in Figure 10f.

[0174] As discussed above, the first metallization structure 168 on the first major surface 161 of the semiconductor wafer 160 provides external contacts 174 for the semiconductor package 183. The semiconductor package 183 is mounted to a higher level circuit board via the external contacts 174 arranged on the first surface 161 of the semiconductor package 183. Solder connections may be used and may be applied to the external contacts 174, as illustrated in FIG. 10 f.

[0175] Each of the external contacts 174 has a lateral size and arrangement within the outer contour of the lower surface of the semiconductor package 183, which is referred to as a package footprint 175. The external contacts 174 may have different arrangements and provide different package footprints.

[0176] 13 illustrates two examples of package footprints that may be provided by first metallization layer 168 of package 183. Package 183 includes a power transistor device 167 such as a vertical MOSFET device or a vertical IGBT device and includes a footprint 175 including a drain external contact 186, a gate external contact 187, and a source external contact 188.

[0177] In the embodiment illustrated in FIG. 13 a , the drain external contact 186 has a U-shape and extends along three sides of the package footprint 183. The source contact 188 and the gate contact 187 are located between the arms of the U, wherein the gate contact 187 is positioned opposite the bottom of the U-shaped drain contact 186. The external contacts 186, 187, 188 are separated from each other by a region of the first polymer layer 178 including epoxy resin.

[0178] FIG. 13 b illustrates a perspective view of a package footprint 190 for a semiconductor package 183 according to another embodiment. Package 183 includes a power transistor device 167 such as a vertical MOSFET device or a vertical IGBT device, and includes a footprint 190, which includes a drain external contact, a gate external contact 187, and a source external contact 188. In package footprint 190, the source external contact 188 has a generally rectangular shape as in package footprint 175. The drain external contact includes a plurality of drain contact pads 191 arranged in two rows. These rows are arranged on two opposite sides of the first surface 161 of the semiconductor package 183, wherein the source pad 188 is arranged between the two rows. The gate external contact 187 includes two gate contact pads 192, which are positioned adjacent to the source pad 188 and between two rows of drain contact pads 191 (four drain contact pads in one row). Each of the drain contact pad 191 and the gate contact pad 192 may have a circular shape. However, other shapes (such as an elongated square) may be used.

[0179] Fig.14Flowchart 200 of a method for preparing a semiconductor package is illustrated. In frame 201, at least one first groove is formed in a first surface of a semiconductor wafer in a device region, wherein the semiconductor wafer includes a separation region arranged between component locations of the semiconductor wafer, the component location including the device region, and the device region includes an electronic device. In frame 202, a first metallization structure is formed on the first surface in the component location, the first metallization structure includes a plurality of external contact pads forming a package position, and a conductive material is inserted into the first groove. In frame 203, at least one second groove is formed in a first surface of the semiconductor wafer in the separation region. In frame 204, a first epoxy layer is applied to the first surface of the semiconductor wafer so that the edge region of the second groove and the component location is covered with the first epoxy layer. In frame 205, a portion of the second surface of the semiconductor wafer is removed, the second surface is opposite to the first surface, and a portion of the first epoxy layer in the separation region and the conductive material in the first groove are exposed and a processed second surface is produced. In block 206, a second metallization layer is applied to the processed second surface and operably coupled to the conductive material and external contact pads on the first major surface. In block 207, the first epoxy layer is cut through in the separation regions to form a plurality of separated semiconductor packages.

[0180] In this embodiment, a through hole in the form of a first trench is inserted into the first surface of the wafer and the conductive material is inserted into the through hole from the first surface. The first trench may be a blind via and the conductive material in the blind via is exposed at the rear surface by removing part of the second surface.

[0181] Fig.15A flowchart 210 of a method for preparing a semiconductor package is illustrated. In frame 211, a first metallization structure is formed on a first surface of a semiconductor wafer, wherein the semiconductor wafer includes a separation region arranged between component locations, the component locations include a device region, the device region includes an electronic device, the first metallization structure is arranged on the component location and includes a plurality of external contacts forming a package location. In frame 212, at least one second groove is formed in a first surface of the semiconductor wafer in the separation region. In frame 213, a first epoxy layer is applied to the first surface of the semiconductor wafer so that the second groove and the edge region of the component location are covered with the first epoxy layer. In frame 214, a portion of the second surface of the semiconductor wafer is removed, the second surface is opposite to the first surface, and a portion of the first epoxy layer in the separation region is exposed. In frame 215, at least one first groove is formed in a processed second surface of the semiconductor wafer in the device region of the component location. In frame 216, a conductive material is inserted into the first groove. In block 217, a second metallization layer is applied to the processed second surface and operably coupled to the conductive material and the external contact pads on the first major surface. In block 218, the first epoxy layer is cut through in the separation regions to form a plurality of separated semiconductor packages.

[0182] In this embodiment, a through hole in the form of a first groove is inserted into the processed second surface of the wafer and the conductive material is inserted into the through hole from the processed second surface. The through hole is inserted into the processed second surface so that it extends through the entire thickness of the semiconductor wafer and so that the bottom of the first groove is formed by a portion of the first metallization structure. The conductive material in the first groove is directly deposited onto the portion of the first metallization layer exposed at the bottom of the first groove. The second metallization layer is applied to the conductive material in the first groove arranged at the processed second surface.

[0183] The semiconductor package includes external contacts formed above the semiconductor material providing the semiconductor device. For example, for a vertical transistor device, a drain external contact, a source external contact, and a gate external contact forming a package placeholder are arranged on a first main surface of the semiconductor device, wherein a drain region on an opposite second main surface of the semiconductor device is electrically coupled to the drain external contact disposed on the opposite first main surface by using a conductive via (or a through silicon via) located in the semiconductor device. The sides and portions of the first main surface arranged between the external contacts are covered with an insulating layer, which is typically a polymer layer such as an epoxy resin product. These structures are formed at the wafer level so that a separate packaging step (such as a molding step or mounting the semiconductor device in a metal housing) is not used.

[0184] Example

[0185] Example 1. A method comprising:

[0186] forming at least one first trench in a first surface of a semiconductor wafer in a device region, wherein the semiconductor wafer includes a separation region disposed between component locations of the semiconductor wafer, the component locations including the device region, the device region including an electronic device;

[0187] forming a first metallization structure disposed on the first surface in the component location, the first metallization structure including a plurality of external contact pads forming a package placeholder, and inserting a conductive material into the first trench;

[0188] forming at least one second trench in the first surface of the semiconductor wafer in the separation region;

[0189] applying a first epoxy layer to the first surface of the semiconductor wafer such that the second trench and edge regions of the component location are covered with the first epoxy layer;

[0190] removing a portion of a second surface of the semiconductor wafer, the second surface being opposite the first surface and exposing a portion of the first epoxy layer in the separation region and the conductive material in the first trench and producing a processed second surface;

[0191] applying a second metallization layer to the processed second surface and operably coupling the second metallization layer to the conductive material and to the external contact pads on the first major surface;

[0192] The first epoxy resin layer in the separation area is cut through to form a plurality of separated semiconductor packages.

[0193] Example 2. A method comprising:

[0194] forming a first metallization structure on a first surface of a semiconductor wafer, wherein the semiconductor wafer includes separation regions arranged between component locations, the component locations including device regions, the device regions including electronic devices, the first metallization structure being arranged over the component locations and including a plurality of external contacts forming package footprints;

[0195] forming at least one second trench in the first surface of the semiconductor wafer in the separation region;

[0196] applying a first epoxy layer to the first surface of the semiconductor wafer such that the second trench and edge regions of the component location are covered with the first epoxy layer;

[0197] removing a portion of a second surface of the semiconductor wafer, the second surface being opposite to the first surface and exposing a portion of the first epoxy resin layer in the separation region;

[0198] forming at least one first trench in the processed second surface of the semiconductor wafer in a device region at a component location; inserting a conductive material into the first trench;

[0199] applying a second metallization layer to the processed second surface and operably coupling the second metallization layer to the conductive material and to the external contact pads on the first major surface;

[0200] The first epoxy resin layer in the separation area is cut through to form a plurality of separated semiconductor packages.

[0201] Example 3. The method of Example 1 or Example 2, wherein cutting through the first epoxy comprises: forming a cut having a width less than a width of the second groove, so that at least a portion of the side surfaces of the plurality of separated semiconductor packages include a portion of the first epoxy layer.

[0202] Example 4. The method according to any one of Examples 1 to 3, wherein the first epoxy resin layer further covers an edge region of the first metallization structure.

[0203] Example 5. The method of Example 4, wherein the openings in the first epoxy layer define lateral dimensions of the external contact pads and the package footprint.

[0204] Example 6. The method of any one of Examples 1 to 5, further comprising applying a protective layer to the external contact pads, wherein the protective layer comprises solder or Ag or Sn.

[0205] Example 7. The method of any one of Examples 1 to 6, wherein the first trench has a width to depth ratio of 1:1 and the conductive material is inserted by electrodeposition.

[0206] Example 8. The method of any one of Examples 1 to 7, wherein the first metallization layer is formed by applying in the order of: a Ti-containing layer, a W layer, an Al-containing layer, and a Cu layer.

[0207] Example 9. The method of Example 8, further comprising applying a TiN layer between the Ti-containing layer and the W layer.

[0208] Example 10. The method of any one of Examples 1 to 9, wherein the second metallization layer is formed by applying a Ti-containing layer and a Cu layer.

[0209] Example 11. The method of Example 10, further comprising applying a TiW layer between the Ti-containing layer and the Cu layer.

[0210] Example 12. The method according to one of Examples 2 to 11, wherein the first trench is inserted into the processed second surface of the semiconductor wafer by etching, and the W layer of the first metallization structure arranged on the first surface of the semiconductor wafer acts as an etch stop.

[0211] Example 13. The method according to any one of Examples 1 to 12 further includes applying a second epoxy resin layer to the processed second surface so that the second epoxy resin layer covers the edge area of ​​the component location and optionally covers the edge area of ​​the second metallization layer, or so that the second epoxy resin layer completely covers the second metallization layer.

[0212] Example 14. The method of any one of Examples 1 to 12, wherein the component location of the semiconductor wafer further includes a further electronic device, the further device region being laterally separated from the device region by a non-device region.

[0213] Example 15. The method of Example 14, wherein the first trench is positioned in a non-device region.

[0214] Example 16. The method of Example 14 or Example 15, wherein a second metallization layer is further applied to a further electronic device, and the further electronic device is operably coupled to the conductive material and the external contact pads on the first major surface and the electronic device.

[0215] Example 17. A semiconductor package comprising:

[0216] A first transistor device comprising:

[0217] a first surface and a second surface opposite to the first surface; a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface;

[0218] A first metallization structure disposed on the first surface, the first metallization structure comprising a plurality of external contact pads, the external contact pads comprising a protective layer of solder, the solder being Ag or Sn;

[0219] a second metallization structure disposed on the second surface;

[0220] an electrically conductive connection extending from the first surface to the second surface and electrically connecting the second power electrode to an external contact pad of the first metallization structure; and

[0221] A first epoxy layer is disposed on the sides of the transistor device and on the first surface of the transistor device, the first epoxy layer including openings defining lateral dimensions of external contact pads and package footprints.

[0222] Example 18. The semiconductor package of Example 17, further comprising a second epoxy layer on the second surface, wherein the second epoxy layer covers an edge region of the second surface and leaves a region of the second metallization layer exposed, or the second epoxy layer completely covers the second metallization layer.

[0223] Example 19. The semiconductor package of Example 17 or Example 18, further comprising a second device, wherein the first conductive connection forms part of a conductive redistribution structure electrically coupling the first transistor device with the second device to form a circuit, wherein the conductive redistribution structure further comprises a conductive layer arranged on the conductive connection and on at least one of the second surfaces of the first transistor device and the second device.

[0224] Example 20. The semiconductor package of claim 19, wherein:

[0225] the second electronic device is a transistor device and the circuit is a half-bridge circuit, or

[0226] The second electronic device is a driver device, or

[0227] The second electronic device is an inductor or a capacitor or a resistor.

[0228] Example 21. A method comprising:

[0229] forming at least one trench in a separation region of the first surface of the semiconductor wafer;

[0230] forming at least one trench in a non-device region of a first surface of a semiconductor wafer, wherein a separation region is arranged between component locations of the semiconductor wafer, the component locations including at least two electronic devices for forming a circuit, the non-device region is arranged between a first device region including a first electronic device and a second device region including a second electronic device, and a first metallization structure is arranged on the first surface in the first device region and the second device region;

[0231] applying a first epoxy layer to the first surface of the semiconductor wafer so that the trench, the edge region of the component location, the edge region of the first device region, and the edge region of the second device region are covered with the first epoxy layer;

[0232] removing a portion of a second surface of the semiconductor wafer, the second surface being opposite the first surface, exposing portions of the first epoxy layer in the separation region and in the non-device region and producing a processed second surface;

[0233] applying a second metallization layer to the processed second surface and operably coupling the first electronic device to the second electronic device to form a circuit;

[0234] Separation lines are inserted through the first epoxy resin layer in the separation region to form a plurality of separated semiconductor modules including the circuit.

[0235] Example 22. The method according to Example 21, further comprising:

[0236] inserting a via into the second device region;

[0237] inserting a conductive material into the through hole; and

[0238] A conductive material is electrically coupled to the first electronic device and the second electronic device.

[0239] Example 23. The method according to Example 22, wherein

[0240] inserting a through hole into a first surface of the semiconductor wafer and thereafter into a first metallization structure, and applying a first epoxy layer to the first surface and removing a portion of a second surface of the semiconductor wafer, or

[0241] A through-hole is inserted into the processed second surface of the semiconductor wafer.

[0242] Example 24. The method according to Example 21, further comprising:

[0243] inserting a conductive material into a trench formed in a non-device region, and

[0244] A conductive material is electrically coupled to the first electronic device and the second electronic device.

[0245] Example 25. A method according to Example 24, wherein a first epoxy resin layer is inserted into a groove formed in a non-device area, a through hole is formed in the first epoxy resin layer in the non-device area so that the sides of the first device area and the second device area defining the through hole are covered with the first epoxy resin layer, and a conductive material is applied to the first epoxy resin layer in the through hole, and the conductive material extends from the first metallization structure in the second device area to the processed second surface.

[0246] Example 26. A method according to Example 21, wherein a conductive via from the first surface of the semiconductor wafer to the processed second surface of the semiconductor wafer is formed by a conductive portion of the first device region or the second device region, and the conductive portion extends from the first surface of the semiconductor wafer to the processed second surface of the semiconductor wafer.

[0247] Example 27. The method of any of Examples 21 to 26, wherein a second metallization layer is applied to the conductive material within the via to operably couple the first electronic device to the second electronic device.

[0248] Example 28. The method of any of Examples 21 to 27, wherein the second metallization layer is applied such that it extends from the first device region through the non-device region to the second device region.

[0249] Example 29. The method of any one of Examples 21 to 28, wherein the separation line has a width smaller than a width of the trench in the separation region so that at least a portion of the side surfaces of the plurality of separated semiconductor modules includes a portion of the first epoxy resin layer.

[0250] Example 30. The method of any one of Examples 21 to 29, wherein the first epoxy layer further covers an edge region of the first metallization structure.

[0251] Example 31. The method of any one of Examples 21 to 30, further comprising applying a second epoxy layer to the processed second surface, the second epoxy layer covering at least the first epoxy layer disposed in the separation area.

[0252] Example 32. The method of Example 21, wherein the second epoxy layer covers the second metallization layer disposed on the first device region and exposes the second metallization layer disposed on the second device region.

[0253] Example 33. A module comprising:

[0254] a first electronic device in a first device region,

[0255] a second electronic device in a second device region,

[0256] wherein the first electronic device is operably coupled to the second electronic device to form a circuit,

[0257] a first main surface comprising at least one contact pad,

[0258] a second major surface comprising at least one contact pad, the second major surface being opposite to the first major surface,

[0259] a first epoxy layer disposed on the first major surface that leaves at least a portion of the first contact pad exposed,

[0260] wherein the side surface of the first electronic device and the side surface of the second electronic device are embedded in the first epoxy resin layer and are in direct contact with the first epoxy resin layer, and

[0261] A conductive redistribution structure electrically couples a first electronic device with a second electronic device to form a circuit, wherein the conductive redistribution structure includes: a conductive via extending from a first major surface to a second major surface; and a conductive layer arranged on the conductive via and on at least one of the first device region and the second device region.

[0262] Example 34. A module according to Example 33, wherein

[0263] the first electronic device is a transistor device, the second electronic device is a transistor device and the circuit is a half-bridge circuit, or

[0264] the first electronic device is a transistor device and the second electronic device is a driver device, or

[0265] The first electronic device is a transistor device and the second electronic device is an inductor or a capacitor or a resistor.

[0266] Example 35. An electronic assembly comprising:

[0267] The module of Example 33 or Example 34;

[0268] a plurality of leads, wherein the first contact pad is coupled to a first lead of the plurality of leads and the second contact pad is coupled to a second lead of the plurality of leads, and a plastic housing component, wherein the plastic housing component covers the first epoxy layer, the second epoxy layer and portions of the plurality of leads.

[0269] Spatially relative terms such as "above", "below", "below", "above", and "above" are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to cover various different orientations of the device in addition to those different orientations depicted in the various figures. Further, terms such as "first" and "second" are also used to describe various elements, regions, sections, etc. and are not intended to be limiting. The same terms refer to the same elements throughout the description.

[0270] As used herein, the terms "having," "comprising," "including," and "containing," etc. are open-ended terms that indicate the presence of the elements or features claimed but do not exclude the elements or features of the appendices. Unless the context clearly indicates otherwise, the quantifiers and pronouns "a," "an," and "the" are intended to include the plural as well as the singular. It is to be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically indicated.

[0271] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. It is therefore intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor module, comprising: a first electronic device in a first device region; a second electronic device in a second device region, wherein the first electronic device is coupled to the second electronic device to form a circuit; a first major surface including at least one contact pad; a second major surface including at least one contact pad, the second major surface being opposite to the first major surface; a first epoxy layer disposed on the first major surface that leaves at least a portion of the first contact pad exposed; wherein the side surface of the first electronic device and the side surface of the second electronic device are embedded in the first epoxy resin layer and are in direct contact with the first epoxy resin layer, and A conductive redistribution structure electrically couples a first electronic device with a second electronic device to form a circuit, wherein the conductive redistribution structure comprises: a conductive via extending from a first main surface to a second main surface; and a conductive layer arranged on the first main surface or the second main surface and arranged on the conductive via, the conductive layer extending from a first device region through a non-device region to a second device region, coupling the first electronic device to the second electronic device, The conductive via is located in the first electronic device or in the second electronic device and is electrically coupled to the first electronic device or the second electronic device where it is located.

2. The module according to claim 1, wherein The first electronic device is a transistor device, the second electronic device is a transistor device, and the circuit is a half-bridge circuit, or the first electronic device is a transistor device and the second electronic device is a driver device, or The first electronic device is a transistor device and the second electronic device is an inductor or a capacitor or a resistor. 3 . The module of claim 1 , further comprising a second metallization layer positioned on the second major surface and positioned on the conductive via. 4 . The module of claim 1 , wherein the conductive via comprises a conductive portion of the first device region or a conductive portion of the second device region. 5 . The module of claim 1 , wherein a conductive layer is disposed on the second major surface and on the conductive vias and couples the first electronic device to the second electronic device. The module according to claim 1 , wherein the first epoxy layer further covers edge regions of the contact pads. 7 . The module according to claim 1 , further comprising a second epoxy layer on the second major surface, the second epoxy layer covering at least the first epoxy layer disposed on a side of the first electronic device and a side of the second electronic device. 8 . The module according to claim 7 , wherein the second epoxy resin layer covers a first region of the conductive layer disposed on the first device region and exposes a second region of the conductive layer disposed on the second device region.

9. An electronic component comprising: The module according to claim 1; a plurality of leads, wherein a first contact pad is coupled to a first lead of the plurality of leads and a second contact pad is coupled to a second lead of the plurality of leads, and A plastic housing component covers the first epoxy resin layer and portions of the plurality of leads.

10. A method for manufacturing a semiconductor module according to any one of claims 1 to 8, comprising: forming at least one trench in a separation region of the first surface of the semiconductor wafer; forming at least one trench in a non-device region of a first surface of a semiconductor wafer, wherein a separation region is arranged between component locations of the semiconductor wafer, the component locations including at least two electronic devices for forming a circuit, the non-device region is arranged between a first device region including a first electronic device and a second device region including a second electronic device, and a first metallization structure is arranged on a first surface in the first device region and on a first surface in the second device region; applying a first epoxy resin layer to the first surface of the semiconductor wafer so that the at least one trench in the separation area, the at least one trench in the non-device area, an edge area of ​​the component location, an edge area of ​​the first device area, and an edge area of ​​the second device area are covered with the first epoxy resin layer; removing a portion of a second surface of the semiconductor wafer, the second surface being opposite to the first surface, to expose portions of the first epoxy layer in the separation region and the non-device region and produce a processed second surface; applying a second metallization layer to the processed second surface and coupling the first electronic device to the second electronic device to form a circuit; inserting separation lines through the first epoxy resin layer in the separation region to form a plurality of separated semiconductor modules including circuits, inserting through-holes into the first device region or the second device region; inserting a conductive material into the through hole; and A conductive material is electrically coupled to the first electronic device and the second electronic device.

11. The method of claim 10, wherein the through-hole is inserted into the first surface of the semiconductor wafer and thereafter into the first metallization structure, and a first epoxy layer is applied to the first surface and a portion of the second surface of the semiconductor wafer is removed, or the through-hole is inserted into the processed second surface of the semiconductor wafer.

12. The method of claim 10, wherein the conductive via from the first surface of the semiconductor wafer to the processed second surface of the semiconductor wafer is formed by a conductive portion of the first device region or the second device region, the conductive portion extending from the first surface of the semiconductor wafer to the processed second surface of the semiconductor wafer.

13. The method of claim 12, wherein a second metallization layer is applied to the conductive material within the via to couple the first electronic device to the second electronic device. 14 . The method of claim 10 , wherein the second metallization layer extends from the first device region through the non-device region to the second device region. 15 . The method according to claim 10 , wherein the separation line has a width smaller than a width of the at least one trench in the separation region so that at least a portion of a side surface of the plurality of separated semiconductor modules includes a portion of the first epoxy layer. The method of claim 10 , wherein the first epoxy layer further covers an edge region of the first metallization structure.

17. The method of claim 10, further comprising applying a second epoxy layer to the processed second surface, the second epoxy layer covering at least the first epoxy layer disposed in the separation area. 18 . The method of claim 17 , wherein the second epoxy layer covers the second metallization layer disposed on the first device region and exposes the second metallization layer disposed on the second device region.

19. The method of claim 10, wherein the separate semiconductor modules each comprise: a first device region including a first electronic device; A second device region comprising a second electronic device; and the at least one trench in the non-device region, wherein the at least one trench in the non-device region of the separated semiconductor module is disposed between the first device region and the second device region and is filled with the epoxy material from the first epoxy layer.

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