Negative voltage detection and voltage surge protection

Abstract

The present invention relates to negative voltage detection and voltage surge protection. In one general aspect, a circuit may include a reference current generator configured to generate a first current signal representing a threshold voltage. The circuit may also include a current comparator configured to mirror the first current signal, generate a second current signal representing a received voltage, and compare the second current signal with the first current signal. The current comparator may also be configured to provide a detection signal at a first logic value to indicate that the received voltage is lower than the threshold voltage when the comparison of the second current signal with the first current signal indicates that the received voltage is less than the threshold voltage.

Description

Technical Field

[0001] The present disclosure relates to circuits for detecting negative voltages. More specifically, the present disclosure relates to circuits that can be used to protect electronic devices (eg, systems, other circuits, etc.) from negative voltages while also withstanding positive and negative voltage surges. Background Art

[0002] Electrical devices and systems (such as consumer electronic devices) can be susceptible to damage due to changes in voltage applied to such devices and systems. For example, in some cases, the application of a negative voltage to a signal terminal (e.g., a data terminal, etc.) of a device can cause damage to the circuitry of the device. Detection circuits can be used to detect such negative voltages and indicate the occurrence or detection of the negative voltage (e.g., via an interrupt signal). Protective measures can then be taken in response to such an interrupt signal to protect the device from damage that may be caused by the negative voltage.

[0003] However, current implementations of circuits for detecting negative voltages have disadvantages. For example, current implementations of such detection circuits may not be able to tolerate positive and negative voltage variations that may occur on a signal terminal performing negative voltage detection. Such voltage variations may result in damage to the detection circuit and / or a device protected by implementing the detection circuit. Current implementations of such detection circuits may also have undesirable static power consumption, for example, when no negative voltage is present on a signal terminal monitored for negative voltage by such detection circuits. Summary of the invention

[0004] In one general aspect, a circuit may include a reference current generator configured to generate a first current signal representing a threshold voltage. The circuit may also include a current comparator configured to mirror the first current signal, generate a second current signal representing a received voltage, and compare the second current signal with the first current signal. The current comparator may also be configured to provide a detection signal at a first logic value to indicate that the received voltage is lower than the threshold voltage when a comparison of the second current signal with the first current signal indicates that the received voltage is less than the threshold voltage.

[0005] In another general aspect, a circuit may include a first current comparator configured to generate an enable signal based on a comparison of a first current signal representing a received voltage with a second current signal representing a first threshold voltage. The circuit may also include a reference current generator configured to generate a third current signal representing a second threshold voltage in response to the enable signal, the second threshold voltage being less than the first threshold voltage. The circuit may also include a second current comparator configured to mirror the third current signal and compare the third current signal with the first current signal. The second current comparator may also be configured to provide a detection signal at a first logic value to indicate that the received voltage is less than the second threshold voltage when a comparison of the third current signal with the first current signal indicates that the received voltage is less than the second threshold voltage.

[0006] In another general aspect, a method of operating a circuit may include generating a first current signal representing a threshold voltage by a current generator, mirroring the first current signal by a current comparator, generating a second current signal representing a received voltage by the current comparator, and comparing the second current signal with the first current signal by the current comparator. The method may also include providing a detection signal at a first logic value by the current comparator to indicate that the received voltage is lower than the threshold voltage when a comparison of the second current signal with the first current signal indicates that the received voltage is less than the threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a block diagram showing a circuit in which a current comparator for negative voltage detection is implemented.

[0008] Figure 1B is a block diagram showing a switch including Figure 1A Negative voltage detection circuit.

[0009] Figure 2 It is shown Figure 1A A schematic diagram of an embodiment of a negative voltage detection circuit is shown with a voltage selection block identified.

[0010] Figure 3 yes Figure 2 A schematic diagram of the circuit with the enable block identified.

[0011] Figure 4 yes Figure 2 A schematic diagram of the circuit with the reference current generator block identified.

[0012] Figure 5 yes Figure 2 A schematic diagram of the circuit with the current comparator block identified.

[0013] Figure 6 yes Figure 2 Schematic diagram of the circuit with the voltage clamp block identified.

[0014] FIG. 7A to FIG. 7C is a graph showing simulation results, which illustrate Figure 1A and Figures 2 to 6 The circuit has negative voltage detection and hysteresis.

[0015] FIG. 8A to FIG. 8B is a graph showing simulation results, which illustrate Figure 1A and Figures 2 to 6 Negative voltage detection of the circuit.

[0016] 9A to 9E is a graph showing simulation results, which illustrate Figure 1A and Figures 2 to 6 The circuit operates across a certain voltage range.

[0017] FIG. 10A to FIG. 10D is a graph showing simulation results, which illustrate Figure 1A and Figures 2 to 6 The operation of the circuit in response to a positive voltage surge.

[0018] FIG. 11A to FIG. 11D is a graph showing simulation results, which illustrate Figure 1A and Figures 2 to 6 The operation of the circuit in response to a negative voltage surge.

[0019] Fig. 12A and Fig. 12B It shows that Figure 1A and Figures 2 to 6 Flow chart of a method for detecting negative voltage implemented in a circuit.

[0020] The same reference numbers in the various drawings indicate the same and / or similar elements. DETAILED DESCRIPTION

[0021] The present disclosure relates to methods, such as circuits and associated methods, for detecting negative voltages. Such circuits and methods may be implemented in a variety of electronic devices and systems (collectively referred to as devices). For example, embodiments described herein may be implemented in a universal serial bus (USB) switch to detect a negative voltage on a common signal pin, such as a data pin (DP / DM) on a common (e.g., host-side) port of a USB switch.

[0022] In certain embodiments, when an unexpected negative voltage is detected using the embodiments disclosed herein, an interrupt signal indicating the occurrence or detection of the negative voltage may be sent to an associated device on which the negative voltage has been detected, such as a controller or processor of a USB switch. In response to the interrupt signal, the device may take appropriate action to protect the device on which the negative voltage is detected and / or devices connected to the device. For example, in a USB switch embodiment, a controller or processor of the USB switch may receive the interrupt signal, and in response to the interrupt signal, may disable the common port of the switch to prevent the detected negative voltage from being transmitted to a device (e.g., a computer, tablet, etc.) connected to the common port, which may prevent damage to the switch and / or any connected devices.

[0023] Although the present disclosure relates specifically to methods of negative voltage detection in the context of a USB switch, these methods may also be implemented in other devices to detect negative voltages, and provide corresponding indications of such detection so that appropriate action can be taken to protect the device on which the negative voltage is detected, as well as any operatively connected devices that may be adversely affected by such negative voltages.

[0024] In certain embodiments, such as USB switches, negative voltage detection circuits (such as those described herein) can be used to detect negative voltages on signal terminals that can also be subject to wide direct current (DC) voltage ranges and / or DC voltage surges. For example, in certain embodiments, a USB switch may be specified, rated, etc. to withstand ±24 volts (V) DC on its common data pins (such DP and DM data pins of a common USB port to which the switch's other USB ports are switched). Additionally, in some embodiments, the USB switch may be specified to withstand ±24V DC voltage surges on the common data pins. The negative voltage detection circuit embodiments disclosed and described herein are capable of detecting negative voltages (e.g., -1V) on signal terminals (such as common data pins) and providing a signal indicating the detection of a negative voltage while withstanding the above-mentioned voltage ranges and voltage surges without damage to the components of the negative voltage detection circuit.

[0025] Furthermore, during typical operation, such as when no negative voltage is detected and no voltage surges are present, embodiments of the negative voltage detection circuits described herein can operate at very low (e.g., zero or near zero) quiescent power consumption. Additionally, as described herein, such negative voltage detection circuits can be implemented with hysteresis when a negative voltage is detected, which can prevent associated detected oscillations or interrupt signals. For example, detection hysteresis in the range of hundreds of millivolts (mV) can be implemented to prevent such oscillations.

[0026] Figure 1A 1 is a block diagram showing a circuit 100 in which a current comparator is used for negative voltage detection. Figure 1AAs shown, the circuit 100 includes a voltage selection block 105, an enable block 110, a current generator block 115, and a current comparator block 120. In the circuit 100, the voltage selection block 105 can be configured to select a lower voltage (e.g., which can be referred to as the most negative voltage) from a power supply voltage VCC (which can be a power supply voltage of an element of the circuit 100) that can be provided on a terminal 107 and a voltage VCOM applied to a signal terminal 109, wherein the circuit 100 is configured to monitor the voltage on the signal terminal 109 (such as a common data pin DP or DM of a USB switch) and detect whether the selected voltage is lower than a negative voltage detection threshold. In an example embodiment, the circuit 100 can be configured to detect a negative voltage of -1.0V. For the purpose of discussion and illustration, this example embodiment will be referenced in the following discussion. In some embodiments, other voltage levels (negative or non-negative) can be detected using the methods described herein.

[0027] like Figure 1A As shown, in the circuit 100, the voltage selector block 105 is coupled to the enable block 110. In the above example where the circuit 100 is configured to detect a negative voltage of -1V, the enable block 110 may be configured to generate an enable signal. The enable signal may be generated when the voltage (e.g., the most negative voltage) provided and / or selected to the enable block 110 by the voltage selection block 105 is lower than an enable threshold voltage, wherein the enable threshold voltage is greater than a negative voltage detection threshold (such as -1V in this example) or more positive than the negative voltage detection threshold. For example, the enable threshold voltage may be -0.9V in this example. That is, if the voltage (e.g., as the most negative voltage) provided or selected by the voltage selection block 105 is less than or equal to -0.9V, the enable block 110 may be configured to generate an enable signal (which may be a logic "1" enable signal or a logic "0" enable # signal), which is provided to the current generator block 115 and the current comparator block 120 to enable, turn on, etc. these blocks. The current generator block 115 and the current comparator block 120 may then be configured to detect whether the voltage provided by the voltage selection block 105 drops below a negative voltage detection threshold of -1V.

[0028] In some embodiments, if the voltage selected and provided by the voltage selection block 105 increases above the enable threshold before or after the circuit 100 detects a negative voltage less than or equal to the negative voltage detection threshold, the enable block 110 may change or switch the enable signal from a logic "1" to a logic "0" or vice versa for the enable# signal, thereby disabling the current generator block 115 and the current comparator block 120. Furthermore, in some embodiments, the enable threshold of the enable block 110 before or after detecting a negative voltage less than or equal to the negative voltage detection threshold may be set to a higher (e.g., less negative) voltage than described above, such as -0.6V, for example, to allow for hysteresis for negative voltage detection such as described herein.

[0029] In circuit 100, current generator block 115 may generate a reference current corresponding to a negative voltage detection threshold (e.g., -1V in this example) when enabled by enable block 110. Current comparator 120 may be configured to mirror the reference current generated by current generator block 115, and further configured to compare the mirrored current with a current representing, corresponding to, or otherwise matching a voltage (e.g., the most negative voltage) selected by voltage selection block 105 and provided to current comparator block 120.

[0030] In the circuit 100, if the voltage provided to the current comparator 120 by the voltage selection block 105 becomes equal to or less than the negative voltage detection threshold, the current comparator 120 may provide a signal on the signal terminal 122, indicating that a negative voltage less than or equal to the negative voltage detection threshold has been detected. The signal on the signal terminal 122 may be provided, for example, as an interrupt signal to a controller of a device on which the negative voltage is detected, and / or one or more devices coupled to the device on which the negative voltage is detected. In response to the signal indicating the detection of the negative voltage, one or more actions may be taken to protect devices and / or circuits that may be adversely affected by the negative voltage (e.g., damaged), such as opening a switch, powering off a circuit or device, etc.

[0031] In some embodiments, the negative voltage detection threshold and the corresponding reference current may be a first negative voltage detection threshold and a first reference current. In such embodiments, in response to a signal indicating detection of a negative voltage based on the first negative voltage detection threshold, the current comparator 120 may be configured to generate a second reference current representing a second negative voltage detection threshold that is greater (e.g., less negative) than the first negative voltage detection threshold. For example, continuing from the above example, the second negative voltage detection threshold may be -0.7V, which may cause negative voltage detection to be performed with a hysteresis of 300mV, such as in this example where the first negative voltage detection threshold is -1.0V and the second negative voltage detection threshold is -0.7V.

[0032] In such methods, the enabling block 100 may be configured such that at least when the current generator generates the second reference current, the enabling threshold is at a voltage that is less negative than the second negative voltage detection threshold. Such methods may prevent the enabling block 110 from disabling the current generator block 115 and the current comparator block 120 when the voltage provided by the voltage selection block 105 is within a hysteresis voltage range, such as a voltage range between the first negative voltage detection threshold and the second negative voltage detection threshold.

[0033] Figure 1B is a block diagram showing a USB switch 150, which includes Figure 1A The negative voltage detection circuit 100. Figure 1BAs shown, the switch 150 may include a plurality of switched USB ports 155 to 160. Although only two switched USB ports (eg, Figure 1B 160), but the switch 150 may include an additional switched USB port. The switch 150 also includes a port switch 165, a common USB port 170, and a controller 175. The controller 175 may be configured to operate the port switch 165 to change which of those USB devices are coupled to the common USB port 170 based on the operation of the USB devices connected to the switched USB ports 155 to 160. Thus, the switch 150 may allow multiple USB devices connected to the switched USB ports 155 to 160 to communicate with a host device coupled to the switch 150 via the common USB port 170.

[0034] like Figure 1B As shown, the switch 150 may include a negative voltage detection circuit 100, which may be coupled to the common USB port 170 and the controller 175. In some embodiments, the negative voltage detection circuit 100 may be connected to detect a negative voltage on a signal terminal of the common USB port 170 (e.g., a data pin DP and / or DM of the common USB port 170). In some embodiments, the switch 150 may include multiple instances of the negative voltage detection circuit 100 for each signal terminal monitored for occurrence of a negative voltage.

[0035] In the switch 150, in response to detecting a negative voltage that is less than or equal to the negative voltage detection threshold of the switch 150, the negative voltage detection circuit 100 may provide a signal, such as an interrupt signal, indicating the detection of the negative voltage to the controller 175. In response to receiving the signal indicating the detection of the negative voltage, the controller 175 may take one or more actions to prevent the negative voltage detected from causing negative effects. Such actions may include, for example, instructing the port switch 165 to disconnect all the switched USB ports 155 to 160 from the common USB port 170, which may prevent the detected negative voltage from being transmitted to a device (e.g., a host computing device) coupled to the common USB port 170 and prevent any potential damage.

[0036] Figures 2 to 6 is a schematic diagram showing a circuit 200 that can implement Figure 1A The negative voltage detection circuit 100. Figures 2 to 6 In each of the figures, the circuit 200 is shown and the corresponding blocks of the circuit 200 are specifically indicated, the corresponding blocks including Figure 1A The illustrated implementation of the negative voltage detection circuit 100 is as follows, Figure 2 The voltage selection block in Figure 3 The enable block in Figure 4 The reference current generator block in Figure 5In addition to the current comparator block in Figures 2 to 5 In addition to the implementation of the blocks of the circuit 100 of FIG. 1 indicated and described, Figure 6 Circuit 200 is also shown and the voltage clamp block is indicated. Figures 2 to 6 The corresponding discussion of each refers to the specific blocks indicated for the corresponding figure, but reference numerals and elements of other blocks may be referenced in the various descriptions as appropriate.

[0037] Figure 2 2 is a schematic diagram showing circuit 200, wherein voltage selection block 210 is identified. As discussed below, and with respect to 9A to 11D As further discussed in the simulation results shown, the voltage selection block 210 of the circuit 200 may also provide high voltage protection against voltages higher than the supply voltage of the device (such as the switch 150) in which the circuit 200 is implemented.

[0038] like Figure 2 As shown, the voltage selection block 210 may include a terminal 215 to which a power supply voltage VCC may be applied and a terminal 220 to which a voltage VCOM is applied, the voltage VCOM being derived from a signal terminal monitoring an applied negative voltage, such as Figure 1B The common data pin (e.g., DP or DM) of the common port 170 in the USB switch 150 of the circuit 200 may be connected to the common data pin (e.g., DP or DM) of the common port 170 in the USB switch 150 of the circuit 200. The voltage selection block 210 of the circuit 200 may also include a resistor 225 that can operate as a supply current (ICC) limiting resistor and a resistor 230 that can operate as an electrostatic discharge (ESD) protection resistor to help protect the circuit 200 from large voltage transients on at least the terminal 220. Figure 2 The voltage selection block 210 also includes a Zener diode 235 and a high voltage n-type metal oxide semiconductor (NMOS) transistor 240 .

[0039] As discussed above with respect to voltage selection block 105 of circuit 100, voltage selection block 210 of circuit 200 may be configured to select a lower voltage (e.g., a most negative voltage) between VCC applied at terminal 215 and VCOM applied at terminal 220, and provide the selected voltage at terminal 245 as voltage VRAIL, as shown. Figure 2 For example, when VCOM is less than VCC, NMOS transistor 240 will operate in its linear mode and VCOM will be applied to terminal 245 as VRAIL with some voltage drop across resistor 230 .

[0040] However, when VCOM is greater than VCC, the NMOS transistor 240 clamps the VRAIL terminal 245 to approximately VCC minus the threshold voltage of the NMOS transistor 240 because of the Zener diode 235, thereby preventing high voltage (e.g., up to 24V DC in the example discussed above) from being applied to other blocks of the circuit 200, such as the enable block and the current comparator block. The Zener diode 235 can clamp the gate-source voltage of the NMOS transistor 240 to prevent damage to the gate of the NMOS transistor 240. In some embodiments, other methods can be used to clamp the gate-source voltage of the NMOS transistor 240. For example, multiple PN diodes connected in series or other voltage clamping circuits can be used instead of the Zener diode 235.

[0041] When circuit 200 is configured to detect when VCOM is less than or equal to a negative voltage threshold, clamping VRAIL to VCC when VCOM exceeds VCC (which may be in the range of 2.5V to 5V in embodiments) does not inhibit circuit 200 from detecting such negative voltages, and may also protect circuit 200 and any connected devices from such high VCOM voltages.

[0042] Figure 3 yes Figure 2 FIG. 2 is a schematic diagram of a circuit 200 of FIG. 1 , wherein an enable block 300 is identified. Figure 3 As shown, the enable block 300 includes a current source 305, such as a pull-up resistor; a terminal 310 for providing a voltage corresponding to a threshold voltage of the enable block 300 (which may be referred to as an enable threshold); and an NMOS transistor 315 configured to receive a voltage representing the enable threshold voltage at its gate terminal. In some embodiments, the voltage applied to the terminal 310 may be determined based on a normal operating point (such as VCOM being greater than zero) and a given negative threshold voltage. For example, in order to reduce power dissipation during normal operation (e.g., when VCOM is greater than 0V), the voltage applied to the terminal 310 may be selected to ensure that the NMOS transistor 315 is disconnected during normal operation. In addition, the voltage applied to the terminal 310 may be selected to ensure that the enable block provides a logic 1 enable signal to enable when VCOM is less than a second negative voltage detection threshold (e.g., a hysteresis threshold). Figure 4 The reference current generator block and Figure 5 In other words, the voltage applied on terminal 310 should be selected so that the NMOS transistor is turned off during normal operation and so that the NMOS transistor 315 is turned on when VCOM is less than or equal to the hysteresis threshold.

[0043] Enable block 300 also includes resistors 320 and 325, which can adjust the pull-down current of enable block 300, for example, from VRAIL. In some implementations, resistor 320 can be omitted.

[0044] When the gate-source voltage of NMOS transistor 315 applied across gate terminal 310 of NMOS transistor 315 and VRAIL terminal 245 is greater than the threshold voltage of transistor 315 (e.g., when VCOM becomes sufficiently negative and reaches the enable threshold voltage), transistor 315 will turn on, causing the input terminal of inverter 330 of enable block 300 to change to a logic low, thereby causing the enable signal ENB on the output terminal 335 of inverter 330 to change to a logic high, which will enable the reference current generator block and the current comparator block of circuit 200 as discussed herein.

[0045] Conversely, when the gate-source voltage of NMOS transistor 315 is less than the threshold voltage of transistor 315 (e.g., when VCOM becomes sufficiently positive and more positive than the enable threshold voltage), transistor 315 will be turned off, causing the input terminal of inverter 330 of enable block 300 to change to a logic high, thereby causing the enable signal ENB on the output terminal 335 of inverter 330 to change to a logic low, which will disable the reference current generator block and the current comparator block of circuit 200 as discussed herein.

[0046] like Figure 3 As shown, the signal ENB at the terminal 335 can be applied to the gate terminal of the p-type metal oxide semiconductor (PMOS) transistor 340 of the enable block 335. When the signal ENB changes to a logic high, the PMOS transistor 340 will be turned off, thereby causing VCC to no longer be applied to the pull-up terminal of the current comparator block of the circuit 200. Blocking the application of VCC to the pull-up terminal of the current comparator block will enable the current comparator block to detect negative voltages in conjunction with the reference current generator block, as described herein, such as relative to at least Figure 4 and Figure 5 described.

[0047] Also like Figure 3 As shown, the enable block 300 includes a terminal 345 at which a voltage VC1 is present. In some cases, such as for negative VCOM voltages, a voltage such as VCOM may be used. Figure 6 VC1 is clamped by a voltage clamp block indicated in the schematic diagram of the illustrated circuit 200 and described below. Figure 3 The diode shown within the enable block 300 in FIG. 1 is part of the voltage clamp block and is therefore not related to the Figure 3 to describe, but relative to Figure 6 Give a description.

[0048] Figure 4 yes Figure 2 FIG. 2 is a schematic diagram of a circuit 200 of FIG. 1 , wherein a reference current generator block 400 is identified. Figure 4 As shown, the reference current generator block 400 may include an NMOS transistor 402 having a gate terminal coupled to the terminal 335, an enable signal ENB from Figure 3 The enable block 300 of the circuit 200 is transmitted to the terminal 335. Therefore, when the signal ENB is logic high, the NMOS transistor 402 is turned on, which enables the reference current generator block 400 of the circuit 200 to generate a reference current for negative voltage detection. When the signal ENB is low, the transistor 402 is turned off and the reference current generator block 400 has zero or near-zero static power dissipation because no reference current is generated.

[0049] like Figure 4 As shown, the reference current generator block 400 of the circuit 200 includes a terminal 405 at which a voltage representing a first negative voltage detection threshold can be applied to the source terminal of the NMOS transistor 415. Continuing from the above example, the voltage applied to the terminal 405 can correspond to the first negative voltage detection threshold of -1V (although in some embodiments, the voltage applied to the terminal 405 can vary from the first negative voltage detection threshold, such as based on other voltages applied in the circuit 200, thresholds of other transistors, etc.).

[0050] like Figure 4 As shown, the gate terminal of the NMOS transistor 415 is coupled to the terminal 425, to which a signal DTCT# may be applied, wherein DTCT# is a current comparator (eg, Figure 5 When DTCT# is logic high, the signal indicates that circuit 200 has not detected or is not currently detecting a negative voltage equal to or less than the first negative voltage detection threshold, such as the VRAIL voltage. In this case, the voltage on terminal 405 representing the first negative voltage detection threshold will be transmitted through transistor 415. When DTCT# changes to logic low (which indicates that a negative voltage equal to or less than the first negative voltage detection threshold has been detected), transistor 415 will be turned off, thereby blocking the voltage on terminal 405 from being transmitted through transistor 415.

[0051] In cooperation with terminal 405, transistor 415, and the DTCT# signal on terminal 425, reference current generator block 400 also includes terminal 410 at which a voltage representing a second negative voltage detection threshold (e.g., a hysteresis negative voltage detection threshold) can be applied to the source terminal of NMOS transistor 425. Continuing from the above example, the voltage applied to terminal 410 can correspond to the second negative voltage detection threshold of -0.7V to implement hysteresis for negative voltage detection, but in some embodiments, the voltage applied to terminal 410 can vary from the second negative voltage detection threshold based on other voltages applied in circuit 200, thresholds of other transistors, etc.

[0052] The gate terminal of the NMOS transistor 420 is coupled to a terminal 430, to which a signal DTCT inverted from the signal DTCT# may be applied, wherein DTCT is Figure 5 DTCT is generated by the current comparator indicated in . DTCT indicates when logic high that circuit 200 has detected a negative VRAIL voltage equal to or less than the first negative voltage detection threshold. In this case, the voltage at terminal 410 representing the second (hysteresis) negative voltage detection threshold will be transmitted through transistor 420, while the voltage at terminal 405 is blocked by transistor 415.

[0053] When DTCT changes from a logic high to a logic low, this may indicate that a negative voltage equal to or less than the second (hysteresis) negative voltage detection threshold can no longer be detected. In this case, transistor 420 will be turned off, thereby blocking the voltage on terminal 410 from being transmitted through transistor 420. However, as described above, transistor 415 will then be turned on in response to DTCT# changing from a logic zero to a logic 1. When using the DTCT and DTCT# signals as described above, reference current generator 410 can implement negative voltage detection with hysteresis by switching between generating a first reference current representing a first negative voltage detection threshold and generating a second current representing a second negative voltage detection threshold (such as a hysteresis threshold).

[0054] In the circuit 200, the reference current generator block 400 further includes a PMOS transistor 440 that provides a current source for the reference current generator block 400, wherein the generated reference current flows through an NMOS transistor 435, a resistor 445, and an NMOS transistor 402, the NMOS transistor being used to enable the reference current generator block 400. When DTCT# is logic high, the reference current generated by the reference current generator block 400 may be determined by the difference between the voltage applied to the terminal 405 (which indicates the first negative voltage detection threshold) and the threshold of the NMOS transistor 435 divided by the resistance of the resistor 445. When DTCT is logic high, the reference current generated by the reference current generator block 400 may be determined by the difference between the voltage applied to the terminal 410 (which indicates the second hysteresis negative voltage detection threshold) and the threshold of the NMOS transistor 435 divided by the resistance of the resistor 445. The amount of hysteresis for negative voltage detection in the circuit 200 may be determined as the difference between the voltage applied to the terminal 405 and the voltage applied to the terminal 410.

[0055] Figure 5 yes Figure 2 FIG. 5 is a schematic diagram of a circuit of FIG. 5 , in which a current comparator block 500 is identified. Figure 5 As shown, the current comparator block 500 includes a PMOS transistor 505, which operates as a current mirror of the PMOS transistor 440 of the reference current generator block 400. That is, when the current comparator block 500 and the reference current generator block 400 are enabled by the signal ENB of the enable block 300, for example, the PMOS transistor 505 can mirror the reference current generated by the reference current generator block 400.

[0056] like Figure 5 As shown, the current comparator also includes a terminal 510 coupled to the gate of the NMOS transistor 515, a resistor 520, and a resistor 525. In some embodiments, the resistor 520 may be omitted. The voltage applied to the terminal 510, together with the voltage used by the reference current generator block 400 to generate the reference current, determines the negative voltage detection threshold used by the current comparator block 500. In order to accurately detect negative voltages or other voltages using the circuit 200, the NMOS transistor 435 of the reference current generator block 400 and the NMOS transistor 515 of the current comparator should be closely matched in terms of their operating parameters, size, physical layout, etc. In addition, in this example embodiment, for the accuracy of the current comparison, the resistor 445 of the reference current generator block 400 and the resistor 525 of the current comparator should be closely matched in terms of impedance size, physical layout, etc.

[0057] In the current comparator block 500 of the circuit 200, if the pull-down current flowing through the NMOS transistor 515 and the resistor 525 is greater than the pull-up current mirrored from the reference current generator block 400, the DTCT signal on the terminal 430 will change to a logic high and the DTCT# signal on the terminal 425 will change to a logic low, thereby indicating that the circuit 200 has detected a negative voltage less than or equal to the current negative voltage detection threshold (e.g., as represented by the pull-up current of the current comparator block 500 mirrored by the PMOS transistor 505). Conversely, if the pull-down current flowing through NMOS transistor 515 and resistor 525 is less than the pull-up current mirrored from reference current generator block 400, the DTCT signal on terminal 430 (e.g., from inverter 540) will change to a logic low and the DTCT# signal on terminal 425 (e.g., from inverters 530 and 535) will change to a logic high, thereby indicating that circuit 200 has not detected or can no longer detect a negative voltage less than or equal to the current negative voltage detection threshold (e.g., as represented by the pull-up current of current comparator block 500 mirrored by PMOS transistor 505).

[0058] Also like Figure 5 As shown, current comparator block 500 includes terminal 545 at which voltage VC2 is present. In some cases, such as for negative VCOM voltages, a current comparator block 500 may be used, for example, Figure 6 The voltage clamp block indicated in the schematic diagram of the illustrated circuit 200 and described below is used to clamp VC2 and enable VC1 in block 300 . Figure 5 The diode shown within the current comparator block 500 in FIG. 5 is part of the voltage clamp block and is therefore not shown with respect to FIG. Figure 5 to describe, but relative to Figure 6 Give a description.

[0059] Figure 6 yes Figure 2 FIG. 6 is a schematic diagram of a circuit of FIG. 1 , in which a voltage clamp block 600 is identified. Figure 6 As shown, the voltage clamp block 600 includes a first diode 610 and a second diode 615, which are coupled between the electrical ground terminal and the respective drain terminals of the transistors 315 and 515. 9A to 11D As shown in the simulation results of the circuit 200, diodes 610 and 615 operate at negative VRAIL and negative VCOM voltages to clamp the voltages of terminals 345 and 545, respectively, to protect transistors 315 and 515, respectively, from such negative VRAIL and negative VCOM voltages. For example, in some embodiments, diodes 610 and 615 can clamp the drain terminals of transistors 315 and 515, respectively, to approximately a negative diode threshold, such as approximately -0.7V.

[0060] 7A to 11Dis a graph showing Figures 2 to 6 1 and 2 show simulation results (eg, voltage, current, and / or timing) of an embodiment of the circuit 200 under various operating conditions. Therefore, the simulation results will be discussed further with reference to these figures. 7A to 11D The values ​​(e.g., voltage, current, time) shown in the simulation results of may be actual or empirical values ​​obtained from simulations of embodiments of circuit 200, or may be normalized values ​​in some cases. For example, in some embodiments, 7A to 11D The values ​​shown in the simulation results of may correspond to the examples discussed previously, where a negative voltage detection circuit (such as circuit 200) is implemented using a first negative voltage detection threshold of -1V and a second negative detection threshold of -0.7V with hysteresis. 9A to 11D As shown in the simulation results of FIG. 1 , the circuit 200 of the example embodiment tolerates voltages of ±24V DC on a data pin of a common port such as a USB switch (e.g., a VCOM voltage), and tolerates ±24V DC voltages such as VCOM surges. 7A to 11D For each group of simulation result graphs in , the common time scale applied to each graph of the corresponding group is included in the bottommost graph of each group.

[0061] FIG. 7A to FIG. 7C is a graph showing simulation results, which illustrate Figures 2 to 6 The circuit 200 has negative voltage detection and hysteresis. Fig. 7A is a graph 710 including a trace 715 showing the voltage of VCOM on which circuit 200 , such as discussed above, performs negative voltage detection. Figure 7B is a graph 720 including a trace 725 showing the relationship between Fig. 7A For the VCOM trace 715 , the negative voltage detection of the circuit 200 corresponds to the signal DTCT. Figure 7C is shown with Fig. 7A and Figure 7B Graph 730 of a trace 735 of the supply current of circuit 200 corresponding to negative voltage detection.

[0062] exist FIG. 7A to FIG. 7C , reference voltages V1 and V2 representing the first negative voltage detection threshold and the second negative voltage detection threshold are shown. V1 and V2 (with reference to FIG. 7A to FIG. 7C The corresponding vertical line shows that VCOM is Fig. 7A The time points at which the corresponding voltages V1 and V2 intersect. For example, V1 indicates Figure 7C , where the trace 715 of VCOM, which changes from positive to negative, crosses (eg, meets) a first negative detection threshold (eg, −1 V in the previous example), and the circuit 200 detects a negative VCOM signal by Figure 7BThe signal DTCT of trace 725 in FIG. 1 changes from logic low to logic high to indicate the detection of a negative voltage. V2 indicates Figure 7C , where the trace 715 of VCOM going from negative to positive crosses (e.g., meets) the second (hysteresis) negative detection threshold (e.g., -0.7V in the previous example), and the circuit 200 detects the VCOM signal by Figure 7B The signal DTCT of trace 725 in FIG. 1 changes from logic high to logic low to indicate that the negative voltage can no longer be detected, but with a delay.

[0063] like Figure 7C As shown, the supply current of circuit 200 is zero or near zero except for current peaks 740, 745, 750, and 755. Current peaks 740 and 745 correspond in this example to enabling block 300 enabling and disabling reference current generator 400 and current comparator 500 of circuit 200, respectively. Current peaks 750 and 755 correspond in this example to switching currents for causing DTCT to change from low to high at peak 750 and from high to low at peak 755, respectively.

[0064] FIG. 8A to FIG. 8B are graphs 810 and 820 showing simulation results illustrating Figures 2 to 6 The circuit 200 is for negative voltage detection. Fig. 8A and Figure 8B The simulation results in Figure 2 show the signal traces of VCOM and DTCT, which are FIG. 7A to FIG. 7C The time scale and FIG. 7A to FIG. 7C Negative voltages are detected at a much finer time scale and with much steeper VCOM vertical edges compared to the much shallower VCOM slope in the CMOS image sensor.

[0065] Continuing from the previous example, for Fig. 8A and Figure 8B According to simulation results of the circuit 200 in FIG. 1 , the first negative voltage detection threshold is −1V, and the second (hysteresis) negative voltage detection threshold is −0.7V. Fig. 8A Included is trace 815 showing VCOM in an embodiment of circuit 200 , which starts at 0V, switches to −1.5V, and then switches back to 0V. Figure 8B Trace 825 includes a signal DTCT in circuit 200, where when Fig. 8A When compared to trace 815 in FIG. 8 , trace 825 shows the switching delay D1 in response to VCOM changing from 0V to -1.5V. Fig. 8A When compared with trace 815, Figure 8B Trace 825 of the DTCT signal in FIG. 8 also shows the switching delay D2 in response to VCOM changing from -1.5V to 0V.

[0066] In with Fig. 8A and Figure 8B In the embodiment of the circuit 200 corresponding to the simulation results, the time scale can be measured in microseconds (μs), and FIG. 7A to FIG. 7C The time scale in can be milliseconds (ms). Fig. 8A and Figure 8B As shown, the switching delay D1 may be approximately 0.2 μs, while the switching delay D2 may be approximately 0.4 μs.

[0067] 9A to 9E are graphs 910, 920, 930, 940 and 950 showing simulation results, which illustrate Figures 2 to 6 The circuit 200 operates across a certain voltage range (e.g., a certain VCOM voltage range). 9A to 9E In the simulation of FIG. 2 , a supply voltage VCC of approximately 5 V is applied to terminal 215 of circuit 200 during the time period shown.

[0068] Fig. 9A Graph 910 of includes a trace 915 showing VCOM across a range of voltages (eg, from approximately -24 V to +24 V) over a period of time. Fig. 9B Graph 920 includes a graph showing the cross section of circuit 200. Fig. 9A The VCOM range of VRAIL is shown as trace 925. Fig. 9A and Fig. 9B As shown, when VCOM is approximately -24 V, VRAIL is also approximately -24 V. As VCOM increases, the VRAIL rail voltage also increases (e.g., corresponding to VCOM) until VCOM becomes greater than VCC. Fig. 9A and Fig. 9B As shown, when VCOM exceeds VCC, VRAIL may be clamped at approximately 5V by voltage selection circuit 210 even if VCOM reaches approximately +24V at the end of the time period shown.

[0069] Fig. 9C and Fig.9D Graphs 930 and 940 of FIG. 2 include trace 935 showing VC1 in circuit 200 and trace 945 showing VC2, respectively. Fig. 9A , Fig. 9C and Fig.9DAs shown, when VCOM is approximately -24V, VC1 345 may be clamped at approximately -1.1V by diode 610 of voltage clamp block 600, and VC2 may be clamped at approximately -1.6V by diode 615 of voltage clamp block 600. As described above, such clamping of VC1 and VC2 may prevent damage to transistors 315 and 515 of circuit 200 due to application of a large negative VCOM voltage (e.g., relative to the power supply voltage of circuit 200) to terminal 220 of circuit 200 (such as to a common data pin of a common USB port in a USB switch). As also shown in FIG. Fig. 9A , Fig. 9C and Fig.9D As shown in Figure 1, once VCOM increases to the clamping voltages VC1 and VC2, those clamping voltages increase with VCOM until Fig. 9B VRAIL is shown clamped at VCC, which also clamps VC1 and VC2 to approximately VCC.

[0070] Fig.9E Graph 950 includes trace 955 showing the circuit 200 across Fig. 9A The supply current for the VCOM range shown is Fig. 9A and Fig.9E As shown, when VCOM is approximately -24V, there is a supply current of approximately 0.3 mA in this example, which is a quiescent current because the voltage selection block 210, the reference current generator block 400, and the current comparator 500 are enabled. As VCOM increases (becomes less negative), the supply current decreases (as Fig. 9A and Fig.9E As shown), until a current spike 960 occurs, wherein the current spike 960 may be a switching current caused by the signal DTCT switching from logic high to logic low, and a switching current caused by the reference current generator block 400 and the current comparator 500 being disabled by the enable block 300.

[0071] FIG. 10A to FIG. 10D are graphs 1010, 1020, 1030 and 1040 showing simulation results, which illustrate Figures 2 to 6 The circuit 200 operates in response to a positive voltage (VCOM) surge. Fig. 10A Graph 1010 includes trace 1015 showing a VCOM voltage surge from 0V to approximately 24V and then exponentially decaying back to zero. Fig. 10B The graph 1020 includes a trace 1025 showing the response of Fig. 10A The voltage surge of VRAIL. Fig. 10C The graph 1030 includes a trace 1035 showing the response to Fig. 10A The voltage surge of VC1. Fig. 10DThe graph 1040 includes a trace 1045 showing the response to Fig. 10A The voltage surge of VC2. FIG. 10A to FIG. 10D As shown, when VCOM fluctuates from 0V to 24V, each of the voltages VRAIL, VC1, and VC2 increases until they are clamped at VCC by the voltage selection block 210, such as has been discussed above. FIG. 10A to FIG. 10D As shown, when VCOM decays from 24V to 0V in an exponential manner, each of the voltages VRAIL, VC1, and VC2 remains clamped at VCC until VCOM decays to less than VCC. Once VCOM has decayed to less than VCC, the voltages VRAIL, VC1, and VC2 also decay in correspondence with VCOM.

[0072] FIG. 11A to FIG. 11D are graphs 1110, 1120, 1130 and 1140 showing simulation results, which illustrate Figures 2 to 6 The circuit 200 operates in response to a negative voltage (VCOM) surge. Fig.11A Graph 1110 includes trace 1115 showing a VCOM voltage surge from 0V to approximately -24V and then increasing exponentially back to zero. Fig. 11B The graph 1120 includes a trace 1125 showing the response of Fig.11A The voltage surge of VRAIL. Fig. 11C The graph 1130 includes a trace 1135 showing the response to Fig.11A The voltage surge of VC1. Fig.11D The graph 1140 includes a trace 1145 showing the response to Fig.11A The voltage surge of VC2. FIG. 11A to FIG. 11D As shown, when VCOM fluctuates from 0V to -24V, VRAIL follows VCOM, while VC1 and VC2 decrease until the diodes 610 and 615 of the voltage clamp block 600 clamp them at, for example, the voltages above with respect to Fig. 9C and Fig.9D The clamping voltages of VC1 and VC2 discussed above. FIG. 11A to FIG. 11D As shown, when VCOM increases exponentially from -24V to 0V, VRAIL also increases exponentially corresponding to VCOM, while VC1 and VC2 increase slowly due to the respective gate-source voltages of transistors 315 and 515 decreasing, for example, due to VCOM and VRAIL becoming less negative.

[0073] Fig. 12A and Fig. 12B It shows that Figure 1A and Figures 2 to 6200 and 1250 are flow charts of methods 1200 and 1250 for detecting negative voltages implemented in a circuit of FIG. 200. In some embodiments, methods 1200 and 1250 may be performed in conjunction with each other. For example, method 1250 may be implemented in conjunction with method 1200 to implement negative voltage detection with hysteresis such as has been described herein. In addition, for illustration purposes and by way of example, methods 1200 and 1250 will be further described with reference to circuit 200.

[0074] exist Fig. 12A , the method 1200 may include, at block 1205, generating, by the reference current generator 400, a first current signal representing a first (negative voltage detection) threshold voltage. At block 1210, the method 1200 may include mirroring, by the current comparator 500, the first current signal. At block 1215, the method 1200 may include generating, by the current comparator 500, a second current signal representing a received voltage. At block 1220, the method 1200 may include comparing, by the current comparator 500, the second current signal with the first current signal. At block 1225, the method may include providing, by the current comparator 500, a detection signal at a first logic value to indicate that the received voltage is below the first threshold voltage if the comparison of the second current signal with the first current signal at block 1220 indicates that the received voltage is less than the first threshold voltage.

[0075] As mentioned above, Fig. 12B The method 1250 can be used with Fig. 12A The method 1200 may be implemented in conjunction with, for example, the circuit 200 to implement negative voltage detection with hysteresis. Fig. 12B At block 1255 of the method 1250, the method 1250 may include generating, by the reference current generator 400, a third current signal representing a second negative voltage detection threshold voltage (e.g., a hysteresis threshold voltage) in response to the detection signal indicating that the received voltage is less than the first threshold voltage. The second threshold voltage may be greater than the first threshold voltage, e.g., less negative. At block 1260, the method 1250 may include mirroring the third current signal by the current comparator 500. At block 1265, the method 1250 may include comparing, by the current comparator 200, the second current signal corresponding to the received voltage with the third current signal. At block 1270, the method 1250 may include, if the comparison of the second current signal with the third current signal indicates that the received voltage is greater than the second threshold voltage, then: providing a detection signal at a second logic value to indicate that the received voltage is greater than the second threshold voltage; and disabling the current comparator 500. Block 1270 may also include disabling the reference current generator 400 if the comparison of the second current signal with the third current signal indicates that the received voltage is greater than the second threshold voltage.

[0076] The various devices and techniques described herein can be implemented using various semiconductor processing and / or packaging technologies. Some embodiments can be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc.

[0077] It should also be understood that when an element such as a layer, region, or substrate is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to another element, or one or more intermediate elements may exist. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intermediate elements or layers.

[0078] Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled to an element may be referred to in such a manner. The claims of the present application may be amended to recite exemplary relationships described in the specification or shown in the drawings.

[0079] As used in this specification, singular forms may include plural forms unless the context clearly indicates a specific case. Spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent may include lateral adjacent or horizontal adjacent.

[0080] Although certain features of the described embodiments have been described as described herein, those skilled in the art will now appreciate that many modifications, alternatives, variations, and equivalents are contemplated. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example, not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A circuit comprising: a reference current generator configured to generate a first current signal representing a threshold voltage; A voltage selector, the voltage selector being configured to: selecting a lower voltage between a power supply voltage of the circuit and an externally provided voltage; and providing the selected voltage to the current comparator as the received voltage; and The current comparator is configured as follows: mirroring the first current signal; generating a second current signal representative of the received voltage; comparing the second current signal with the first current signal; and When the comparison of the second current signal with the first current signal indicates that the received voltage is less than the threshold voltage, providing a detection signal at a first logic value to indicate that the received voltage is lower than the threshold voltage, wherein The voltage selector includes a voltage clamp circuit configured to clamp the received voltage to the power supply voltage of the circuit when the externally provided voltage exceeds the power supply voltage of the circuit.

2. The circuit according to claim 1, wherein: The voltage clamping circuit includes a Zener diode.

3. The circuit of claim 1, wherein: the threshold voltage is a first negative threshold voltage, the circuit further comprising an enable circuit configured to generate an enable signal to enable the reference current generator if the received voltage is less than a second negative threshold voltage, the second negative threshold voltage being greater than the first negative threshold voltage; and The current comparator is a first current comparator and the enable circuit includes a second current comparator configured to generate the enable signal based on a comparison of the second current signal representing the received voltage and a third current signal representing the second negative threshold voltage.

4. The circuit according to claim 1, wherein the threshold voltage is a first threshold voltage, The reference current generator is further configured to generate a third current signal representing a second threshold voltage in response to the detection signal indicating that the received voltage is less than the first threshold voltage, the second threshold voltage being greater than the first threshold voltage, and The current comparator is further configured as: mirroring the third current signal; comparing the second current signal representing the received voltage with the third current signal; and In response to the comparison of the second current signal and the third current signal indicating that the received voltage is greater than the second threshold voltage: providing the detection signal at a second logic value to indicate that the received voltage is greater than the second threshold voltage; and Disable the current comparator.

5. A circuit comprising: an enable block configured to generate an enable signal based on a comparison of the received voltage and a first threshold voltage; a reference current generator configured to generate a first current signal representing a second threshold voltage greater than the first threshold voltage in response to the enable signal indicating that the received voltage is lower than the first threshold voltage; A current comparator, the current comparator being configured to: mirroring the first current signal; comparing the first current signal to a second current signal representative of the received voltage; and When the comparison of the first current signal and the second current signal indicates that the received voltage is less than the second threshold voltage, generating a detection signal at a first logic value to indicate that the received voltage is lower than the second threshold voltage; and A voltage selector, the voltage selector being configured to: selecting a lower voltage between a power supply voltage of the circuit and an externally provided voltage; and providing the selected voltage to the enable block and the current comparator as the received voltage, The voltage selector includes a voltage clamp circuit configured to clamp the received voltage to the power supply voltage of the circuit when the externally provided voltage exceeds the power supply voltage of the circuit. 6 . The circuit of claim 5 , wherein the first threshold voltage and the second threshold voltage are a first negative threshold voltage and a second negative threshold voltage, respectively.

7. The circuit of claim 5, wherein: The reference current generator is further configured to generate a third current signal representing a third threshold voltage in response to the detection signal indicating that the received voltage is less than the second threshold voltage, the third threshold voltage being greater than the second threshold voltage, and The current comparator is further configured as: mirroring the third current signal; comparing the second current signal representing the received voltage with the third current signal; and If a comparison of the second current signal with the third current signal indicates that the received voltage is greater than the third threshold voltage, then: providing the detection signal at a second logic value to indicate that the received voltage is greater than the third threshold voltage; and A disable signal is provided to the current comparator, the disable signal disabling the current comparator.

8. A method of operating a circuit, the method comprising: generating, by a current generator, a first current signal representing a first negative threshold voltage; mirroring the first current signal by a current comparator; generating, by the current comparator, a second current signal representative of the received voltage; comparing the second current signal with the first current signal by the current comparator; When the comparison of the second current signal with the first current signal indicates that the received voltage is less than the first negative threshold voltage, providing a detection signal at a first logic value by the current comparator to indicate that the received voltage is lower than the first negative threshold voltage; as well as In response to the received voltage being less than a second negative threshold voltage, generating an enable signal to enable the current generator, the second negative threshold voltage being greater than the first negative threshold voltage, wherein The method further comprises: selecting a lower voltage between a power supply voltage of the circuit and an externally provided voltage; providing the selected lower voltage to the current comparator as the received voltage; and When the externally provided voltage exceeds the power supply voltage of the circuit, the received voltage is clamped to the power supply voltage of the circuit.

9. The method according to claim 8, wherein: The current comparator is a first current comparator, and the method further includes generating, by a second current comparator, the enable signal based on a comparison of the second current signal representing the received voltage and a third current signal representing the second negative threshold voltage.

10. The method according to claim 8, further comprising: generating, by the current generator, a third current signal representing a third negative threshold voltage in response to the detection signal indicating that the received voltage is less than the first negative threshold voltage, the third negative threshold voltage being greater than the second negative threshold voltage, mirroring the third current signal by the current comparator; comparing, by the current comparator, the second current signal representing the received voltage with the third current signal; as well as If a comparison of the second current signal with the third current signal indicates that the received voltage is greater than the third negative threshold voltage, then: providing the detection signal at a second logic value to indicate that the received voltage is greater than the third negative threshold voltage; and Disable the current comparator.

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