Current sensing and control for transistor power switches

Abstract

In described examples, an apparatus (600) includes a first power transistor (B-FET) having a first current conduction path coupled between an input (VIN) to receive a supply voltage and a node (VMID) and a first gate terminal coupled to a first gate control signal (BGATE); a second power transistor (HS-FET) having a second current conduction path coupled between the node (VMID) and an output terminal (VOUT) to supply a load current (IL) to a load; and a second gate terminal (HGATE) coupled to a second gate control signal; and a current sense transistor (SENSE FET) having a third gate terminal coupled to the first gate control signal (BGATE) and outputting a sense current (IS 感测 ) that is a function of the load current (IL). The apparatus further includes a differential amplifier (607) having an output signal; a feedback transistor (FB-FET) having a gate terminal coupled to the output signal of the differential amplifier; and a resistor (RMON) coupled between a monitor node (VMON) and ground.

Description

[0001] The present invention generally relates to power switches and corresponding control circuits, and more specifically to circuits for controlling circuits comprising transistor power switches that supply current to a load. Background Technology

[0002] An electronic fuse (“fuse”) circuit controls the connection between an input voltage source and a load coupled at the output terminal. An electronic fuse may contain a series power transistor that connects the load to the input power source. For example, a circuit board may draw power from a bus. When the circuit board is inserted into a bus socket, contacts in the bus socket connect the circuit board to the power source. Electronic fuses often provide: overcurrent control; short-circuit protection; inrush current limiting; dv / dt or startup voltage ramp control; and reverse current protection. An electronic fuse can reduce the available current to the load or even completely disconnect the power supply to the load in the presence of an overcurrent.

[0003] In practical applications, a power transistor has a drain terminal coupled to a voltage source and a source terminal coupled to the load at the output terminal. When power is supplied to the load at the output terminal, the gate of the power transistor needs to be at a sufficient voltage to turn on the power transistor and couple the load to the power source. A sensing circuit is used to monitor the load current. If the current flowing through the series power transistor exceeds the current limit, the gate voltage of the power transistor can be reduced to limit the load current, or the gate voltage can be changed to turn off the power transistor. It needs to be disconnected before it can cause any physical damage to the power transistor. If a short circuit to ground occurs at the output terminal or a short circuit occurs in the load circuit, the load current may exceed the current limit. Summary of the Invention

[0004] In the described example, a device includes: a first power transistor having a first current conduction path between a first current conduction terminal and a second current conduction terminal, the first current conduction path of the first power transistor being coupled between an input terminal for receiving a power supply voltage and a node, the first power transistor having a first gate terminal coupled to a first gate control signal for controlling the first power transistor; a second power transistor having a second current conduction path between a third current conduction terminal and a fourth current conduction terminal, the second current conduction path of the second power transistor being coupled between the node and an output terminal for supplying load current to a load; the second power transistor having a second gate terminal coupled to a second gate control signal; and a current sensing transistor having a current conduction terminal coupled to the node and the first power transistor, a third gate terminal coupled to the first gate control signal, and outputting a sensed current at another current conduction terminal. The device further includes: a differential amplifier having a first input terminal coupled to one of the first current conduction terminals and the second current conduction terminal of the first power transistor and a second input terminal coupled to the other of the first current conduction terminal and the second current conduction terminal, and having an output signal responsive to a voltage difference between the first input terminal and the second input terminal; a feedback transistor having another current conduction path coupled in series between the current sensing transistor and the monitoring node, and a feedback transistor gate terminal coupled to the output terminal of the differential amplifier; and a resistor coupled between the monitoring node and ground, through which the sensed current flows, the sensed current being proportional to the load current flowing through the second power transistor. Attached Figure Description

[0005] Figure 1 This is a circuit diagram of a power transistor circuit.

[0006] Figure 2 It is a circuit diagram of a conventional power transistor circuit that includes a current monitor and a current limiting circuit.

[0007] Figure 3 This is another circuit diagram of an alternative conventional power transistor circuit with a current monitor.

[0008] Figure 4 This is a circuit diagram of a conventional high-side current sensing circuit.

[0009] Figure 5 This is a circuit diagram of an embodiment used in an electric fuse circuit that includes a current monitor.

[0010] Figure 6 It is a combination Figure 5The circuit diagram of an embodiment of the current monitor.

[0011] Figure 7 This is a circuit diagram of an embodiment of a high-side transistor with a current monitoring circuit.

[0012] Figure 8 This is a circuit diagram of an embodiment circuit with a fast trip comparator and current limit.

[0013] Figure 9 This is a circuit diagram illustrating the operation of a portion of the fast trip comparator used in conjunction with the embodiments.

[0014] Figure 10 This is a circuit diagram of an embodiment of a bidirectional current path in a power transistor circuit having a current monitor for load current flowing in both directions.

[0015] Figure 11A and 11B Is with Figure 10 The circuit diagram of the circuit system used in the embodiments.

[0016] Figure 12 This is a system block diagram of an embodiment of an electric fuse system that includes a power transistor integrated circuit coupled to a controller integrated circuit. Detailed Implementation

[0017] In the accompanying drawings, unless otherwise specified, the corresponding numbers and symbols generally refer to the corresponding parts. The drawings are not necessarily drawn to scale.

[0018] In this specification, the term “coupled” may include a connection established with the intervention element, and there may be additional elements and various connections between any “coupled” elements.

[0019] Figure 1 This is a simplified diagram of power supply circuit 100. Power supply circuit 100 includes circuit 101 coupled between power supply terminal VIN and output terminal VOUT. Circuit 101 is a power transistor circuit that can form part of an electric fuse circuit. Draw the current load (...). Figure 1The high-side transistor HS-FET (not shown) is coupled to the VOUT terminal. The high-side transistor HS-FET acts as a switch between the power supply VIN and the load coupled to the VOUT terminal. A control circuit (not shown) is coupled to the gate terminal of the high-side transistor HS-FET and supplies the gate control voltage HGATE. In circuit 101, a blocking transistor B-FET is coupled between node VMID and the input voltage VIN. The blocking transistor has a body diode (shown by a dashed line to indicate that the body diode is an intrinsic device) between its source coupled to node VMID and its drain coupled to VIN, which blocks current from flowing from the output terminal VOUT to the input terminal VIN, which can be considered a “reverse” current. The gate of the blocking FET B-FET is coupled to the gate control voltage BGATE. BGATE is supplied from the control circuit (not shown).

[0020] In applications where an output voltage is supplied from an input voltage, the fuse circuit including circuit 100 is arranged to protect the input power supply, load device, and expensive FET device from damage due to overcurrent conditions. By sensing the current flowing through the HS-FET, the control circuit in the fuse can use the gate control signal HGATE to turn off the transistor HS-FET. Limiting the current or shutting down the circuit is to protect the HS-FET and the load.

[0021] exist Figure 1 In circuit 101, a current sensing device (SENSE FET) is included. The current sensing device is coupled to the same gate voltage (BGATE) as a blocking device (B-FET) and to the same voltage (VMID) at the drain terminal. Because the sensing FET is built on the same substrate as the blocking B-FET and using the same semiconductor process, the current flowing through the SENSE FET should be proportional to the load current (IL) flowing through the blocking transistor (B-FET). However, in practice, in situations such as... Figure 1 In the standard configuration shown, the sensing current "I" 感测 "Insufficient accuracy is lacking, especially when the gate-source voltage (Vgs) is small. The lack of accuracy is because the threshold voltage of the SENSE FET (which is manufactured to a much smaller size than the HS-FET and the blocking B-FET) does not match the threshold voltage of the blocking transistor B-FET under all conditions."

[0022] An important aspect of circuit 101 is determined by current power FET technology. Recently, the development of low-resistance MOSFET devices fabricated using vertical FET processes has resulted in enhanced circuit performance. These devices are rapidly replacing existing device types in power supply applications, such as bipolar transistors, lateral FETs like DMOS FETs, and conventional trench FETs. An example advanced FET device is the NexFET from Texas Instruments Incorporated. TM Technical device. "NexFET" is a trademark of Texas Instruments for power MOSFETs. TM The devices feature very low on-resistance Rdson, high device performance, robustness, relatively small silicon area, and can carry very high voltages and currents, such as up to 100 volts. Examples may utilize NexFETs. TM The device can be implemented using other power FET technologies, vertical FETs, and other FET arrangements.

[0023] exist Figure 1 In this circuit, the power transistor circuit 101 can be implemented on a single semiconductor substrate containing all the FET devices. However, in order to use vertical FETs, it is necessary to form the circuit in an efficient manner. Figure 1 In the device, a common substrate node VMID is coupled to one terminal of the FET transistor. Figure 1 In the fuse 101, the drains of the three devices—B-FET, HS-FET, and SENSE FET—are all coupled to the substrate at node VMID. Because the drains are coupled to the substrate at the bottom of the vertical FET structure, this is referred to as a "drain-down" configuration. This common drain configuration limits the arrangement of the current sensing circuit that can be used. Therefore, further improvements are needed to increase the sensed current I. 感测 Accuracy under a wide range of conditions. The examples are applicable to arrangements formed with vertical FET devices.

[0024] This section provides an overview of conventional FET current sensing methods. Figure 2 A conventional power supply circuit 200 with current sensing and current limiting is depicted. Figure 2 The components similarly marked in the middle perform the power supply circuit 100 ( Figure 1 The components have similar functions. For example, Figure 1 The high-side device marked HS-FET is used in conjunction with Figure 2 It operates in the same way as the high-side device HS-FET.

[0025] exist Figure 2In the diagram, current sensing path 201 (labeled as sensing path) is shown as being coupled in parallel to power supply current path 203 (labeled as power supply path). In sensing path 201, the input voltage VIN is coupled to the source terminal of sensing transistor SENSE FET, which can be scaled (using device W / L area) to be smaller than a power FET. Various scaling factors can be used. The drain of SENSE FET is coupled to supply current IMON (monitoring current) to feedback transistor 209. Operational amplifier (op-amp) 207 is coupled as a comparator. The output of operational amplifier 207 changes in response to the voltage difference at the positive and negative terminals. The source of sensing transistor SENSE FET is coupled to the positive input terminal of op-amp 207 (e.g., ...). Figure 2 The "+" symbol is shown in the image. The negative terminal of op-amp 207 (e.g.) Figure 2 The "-" symbol (as shown in the figure) is coupled to the common drain terminal VMID between the blocking transistor B-FET and the high-side transistor HS-FET. The high-side transistor HS-FET carries the load current IL from the input voltage source coupled at node VIN to the output terminal VOUT and to the load coupled to VOUT (not shown for clarity).

[0026] The op-amp 207 is coupled in a feedback configuration using a feedback transistor 209. A dummy ground condition exists at the input of the operational amplifier 207. During operation, the op-amp 207 adjusts the voltage at the gate of the feedback transistor 209 to maintain the positive and negative terminals (in...) Figure 2 The voltages at the points marked "+" and "-" are equal. Then, the current IMON will be proportional to the load current IL. This proportion will be determined by scaling between the sensing transistor (SENSE-FET) and a power transistor such as an HS-FET. In this example, the scaling is such that the sensed current is 1 / 1000 of the load current IL, but other scaling factors can be used, and the magnitude of the sensed current relative to the load current will change accordingly.

[0027] In operation, current limiting box 211 controls the high-side transistor HS-FET. When the high-side transistor HS-FET delivers current IL to the load, the drain-source voltage of the blocking transistor B-FET in power path 203 will be equal to the drain-source voltage of the sensing transistor SENSE FET. If the drain voltages are not equal, operational amplifier 207 will change the voltage at the gate of feedback transistor 209 until the drain voltages are equal. By matching the devices SENSE FET and B-FET, the current flowing through the devices can be made proportional to the size ratio of the devices. This is true because the devices are matched; the source terminals of the two devices are at the same potential (VIN, input supply voltage) and their gate terminals are both bound to the same gate control voltage BGATE. When the two devices carry the same (proportional) current, the drain voltages will also be equal.

[0028] exist Figure 2 In this circuit, the current IMON provides an output voltage at terminal VMON, which can be used to control the power transistor circuit and provide a current limit. The output terminal VMON can be used to control the current limit by providing a user-defined value to resistor RMON. By setting the size of resistor RMON, a monitoring voltage VMON proportional to the current IMON can be generated. The monitoring voltage VMON can be observed through current limiting control block 211. The gate voltage signal HGATE, coupled to the high-side transistor HS-FET, is output through current limiting block 211. When the voltage VMON exceeds a threshold or reference voltage, current limiting block 211 can limit or reduce the gate voltage HGATE and reduce the load current IL, or even prevent the load current IL from flowing through the high-side transistor HS-FET to the load. Additional optional outputs can be created to provide an indication that a current-limiting condition is occurring for use by the user or the controller in the system. The voltage VMON can be coupled to observe the current IMON flowing in the system, which is proportional to the load current IL.

[0029] The connections in circuit 200 require that the drain terminals of the sensing transistor SENSE FET and the power transistors B-FET and HS-FET be physically separated. However, in the production of vertical FET devices for power applications (such as NexFET), TM In the device, the transistors on the power integrated circuit have coupling to, for example, Figure 1 The node shown is a current-carrying terminal (source or drain) of a common substrate node such as VMID. Therefore, conventional circuitry 200 cannot be used to sense current in these advanced power devices.

[0030] Figure 3 This is a simplified diagram of another conventional power supply circuit 300. Figure 3 The components similarly marked in the middle perform the power supply circuit 200 ( Figure 2The components in the middle (of the text) have similar functions. For example, Figure 3 The transistor HS-FET performs with Figure 2 The transistor HS-FET has the same function. Power supply circuit 300 is the same as power supply circuit 200 (see...). Figure 2 The difference is that the sensing transistor (SENSE FET), blocking transistor (B-FET), and high-side transistor (HS-FET) have a common drain connection at node VMID. Because of this common drain connection, these transistors can be implemented in a drain-down vertical FET device.

[0031] Circuit 300 includes a sensing path 301 and a power supply path 303. In sensing path 303, op-amp 307 is configured as a virtual ground comparator. The source voltage of the SENSE FET is at the positive input terminal of operational amplifier 307, and the source voltage of the blocking transistor B-FET, which is coupled to the input power supply voltage VIN, is at the negative input terminal. The gate voltages of both the SENSE FET and B-FET are coupled to the control voltage BGATE. Therefore, the SENSE FET and B-FET are matched, and the current ISENSE flowing through the SENSE FET in the sensing path will be proportional to the load current IL flowing through the blocking transistor B-FET.

[0032] During operation, current sensing occurs when the output of op-amp 307 controls the gate of feedback FET 309, which regulates the current ISENSE to match the load current IL. The mirror transistor 310 outputs the sensed current as the monitoring current IMON, and an output voltage proportional to IMON is available at the output terminal VMON. The voltage VMON can be controlled by selecting the value of resistor RMON. The user can set a limit voltage and use a current-limiting circuit. Figure 3 (Not shown in the diagram) to limit current. The gate signal of the high-side transistor HS-FET can be controlled by a current-limiting circuit and thus provides current-limiting functionality.

[0033] Figure 3 The conventional circuit 300 requires a charge pump (not shown for clarity) to provide the voltage VCP. Because operational amplifier 307 has an input coupled to the input voltage VIN, a voltage higher than VIN needs to be supplied to operational amplifier 307. A charge pump is needed to supply this higher voltage, and the charge pump is also used to supply the current ISENSE flowing in the sensing path and the monitoring current IMON. It is not desirable to use a charge pump to provide the voltage VCP and the currents ISENSE and IMON. Charge pumps require considerable power and silicon area, are relatively inefficient, and are expensive to manufacture.

[0034] Figure 4This is a circuit diagram of a power supply circuit 400 that includes current sensing and current limiting. Figure 4 The components similarly marked in the middle perform the power supply circuit 300 ( Figure 3 The components have similar functions. For example, Figure 4 The high-side transistor HS-FET in the middle is used with Figure 3 It operates in the same way as the high-side transistor HS-FET.

[0035] exist Figure 4 In this circuit, power path 401 includes a high-side transistor HS-FET for coupling the input voltage at input terminal VIN to output terminal VOUT, at which a load (not shown) receives a load current IL. Figure 4 In this circuit, the power path includes a blocking transistor, B-FET, controlled by the gate control voltage B-GATE. When the voltage at the output terminal exceeds the voltage at the input terminal VIN, the intrinsic body diode of the B-FET transistor (not shown for simplicity) prevents current from flowing from the output terminal VOUT to the input terminal VIN.

[0036] exist Figure 4 In this circuit, sensing path 403 includes a sensing circuit system. In this conventional circuit, current sensing is performed by a transistor SENSE FET, which is coupled to match a high-side transistor HS-FET. The high-side transistor HS-FET is controlled by a current-limiting amplifier A2, labeled 413, which provides a gate control signal HGATE to both the HS-FET and the sensing transistor SENSE-FET.

[0037] The current sensing circuit system includes an op-amp 407 coupled to a virtual ground circuit at the input terminal. The drain terminal of the sensing transistor SENSE-FET is coupled to the positive input terminal, while the drain terminal of the high-side transistor HS-FET is coupled to the negative input terminal. The op-amp 407 is configured for feedback, with transistor M3 acting as the feedback transistor.

[0038] In operation, the sensing circuit system 403 senses the load current IL by matching the drain-source voltages of the high-side transistor HS-FET and the sensing transistor SENSE-FET. Operational amplifier 407 is used to control the current passing through the feedback transistor M3. The current ISENSE will be matched proportionally to the load current IL.

[0039] exist Figure 4In circuit 400, a blocking transistor (B-FET), a high-side transistor (HS-FET), and a current-sensing transistor (SENSE-FET) with a common drain connection are used at node VMID. Because the drain terminals are coupled, these three devices can be coupled together on the substrate in a vertical FET device, such as a NexFET, where the drains are configured drain-down. TM Implemented in the device.

[0040] However, in Figure 4 In this configuration, the current I output by the SENSE FET transistor is... 感测 The accuracy is limited. The sensing transistor SENSE FET has a gate terminal coupled to the gate connection HGATE of the HS-FET. Under current-limiting conditions, the voltage across the user-specified resistor RMON is compared to a reference voltage Vref. If the current through resistor RMON exceeds the current limit, the voltage VMON will exceed the reference voltage Vref, and the current-limiting amplifier 413 will limit the current through the HS-FET by reducing the gate voltage HGATE. When HGATE decreases, the gate voltage at the sensing transistor SENSE FET decreases, which will cause the gate-source voltage (Vgs) of the sensing transistor to drop. At low gate-source voltages, the threshold match between the sensing transistor SENSE FET and the high-side transistor HS-FET is poor, resulting in poor accuracy of the sensed current. Figure 4 Conventional circuits in this field often suffer from a lack of accuracy, especially under current-limiting conditions, where the accuracy of the sensed current is of paramount importance.

[0041] Figure 5 This is a circuit diagram of a current sensing circuit used in high-side power applications. Similarly labeled components perform the same actions as the power supply circuit 400. Figure 4 The components have similar functions. For example, Figure 5 The blocking transistor B-FET in the middle is used to... Figure 4 The B-FET device operates in a similar manner. Figure 5 The image shows sensing path 503, and a portion of the corresponding power path 501. The complete power path is shown in... Figure 5 The features of the embodiments are not shown in the diagram but are further described below. These features are applicable to the use of NexFETs. TM The arrangement of the device and other FET devices; and the embodiments are not limited to any particular type of FET device.

[0042] exist Figure 5In this circuit, a blocking transistor B-FET is included, having a current conduction path between a first current conduction terminal and a second current conduction terminal, the first and second current conduction terminals being coupled in series between an input terminal VIN for receiving a power supply voltage and a common node VMID. Figure 5 In this configuration, the first current conduction terminal is the source terminal of the B-FET transistor, and the second current conduction terminal is the drain terminal of the B-FET transistor. The blocking transistor has a gate control terminal coupled to the signal BGATE. The sensing transistor SENSE-FET has a first current conduction terminal coupled to the common node VMID and is coupled to provide a sensing current output I. 感测 The current conduction path between the second current conduction terminals. The gate of the sensing transistor SENSE-FET is coupled to the gate control signal BGATE.

[0043] exist Figure 5 In this configuration, current sensing is located across the blocking transistor B-FET. The sensing transistor SENSE-FET is matched to the sensing transistor B-FET. Operational amplifier 507 is configured as a unity-gain amplifier with a gain of "-1". The current sensing across the blocking transistor B-FET... Figure 5 The drain-source voltage labeled "vd1" is applied to the drain-source voltage labeled "vd2" of the SENSE-FET. Operational amplifier 507 will adjust the gate voltage of the feedback transistor FB-FET until the equation vd2 = vd1 * (R2 / R1) is satisfied. The unity gain described for operational amplifier 507 assumes that resistors R1 and R2 have the same value; however, in alternative embodiments, as shown in the equation, changing the ratio of resistors R1 to R2 can provide additional adjustment to the gain of operational amplifier 507. By using a resistor ratio of R2 to R1 of less than 1, additional scaling can be achieved, allowing for smaller sense current and a corresponding reduction in power consumption.

[0044] In operation, the current flowing through the sensing transistor SENSE-FET is proportional to the load current IL (scaled to the device size ratio, such as by a scaling factor of 1 / 1000). The sensing current is more accurate due to the use of operational amplifier 507 and feedback transistor FB-FET. The operational amplifier adjusts the gate voltage of the feedback transistor FB-FET in response to any voltage difference between the drain-source voltage vd1 of the blocking transistor B-FET carrying the load current IL and the drain-source voltage vd2 of the sensing transistor SENSE-FET carrying the sensing current through its current conduction path. The voltage at terminal VMON is provided by the sensing current, which is therefore proportional to the load current IL. The value of resistor RMON can be adjusted to change the voltage VMON for a given monitored current IMON, and voltage VMON can be used to set a current limit for use by a current-limiting circuit (not shown).

[0045] Figure 5 The embodiment provides a common drain node VMID for the blocking transistor B-FET and the sensing transistor SENSE-FET. This common connection can be further extended to include the drain of the high-side FET (in... Figure 5 (Not shown in the diagram, but described further below). Because the drain terminals are connected at a common node, these three FETs can be used in a manner similar to NexFET. TM This is implemented on vertical FET devices such as [device name missing]. Because a blocking transistor (B-FET) is used to sense the load current, [the following is likely a separate point about FET implementation]. Figure 5 Sensing current I in the embodiment 感测 The accuracy is high. The blocking transistor B-FET has a gate voltage B-GATE independent of the gate voltage of the high-side transistor (not shown). When current limiting occurs, the gate voltage B-GATE does not change, so that even when the high-side gate voltage is controlled to limit the load current, the sensing transistor SENSE FET and the blocking transistor B-FET will have high gate voltages. Because the gate-source voltages of both the B-FET and the sensing transistor SENSE-FET remain high during current limiting events, the sensed current remains accurate when the sensing transistor and the blocking transistor are well matched and both maintain the voltage BGATE at the gate terminal in the linear operating region. Although Figure 5 The embodiments can be used with a common drain node in a vertical FET device, but the embodiments can also be used with non-vertical FET devices such as lateral FET devices, and provide accurate current sensing in part due to the use of operational amplifiers and feedback transistors.

[0046] Figure 6 This is a circuit diagram of the power supply circuit 600 of the embodiment, showing... Figure 5 The current sensing arrangement in the circuit is used to provide current limiting functionality within the power supply circuit. Figure 6 The component marked similarly in the middle executes the circuit 503 ( Figure 5 The corresponding components of ) have similar functions. For example, Figure 6 The blocking transistor B-FET in the middle is used to... Figure 5 It operates in a similar manner to the blocking transistor B-FET in the circuit.

[0047] exist Figure 6 In this circuit, power path 601 includes a high-side transistor HS-FET and a blocking transistor B-FET coupled to supply current and voltage from an input voltage source coupled to terminal VIN to output terminal VOUT. Load current IL will flow into a load coupled to output terminal VOUT (not shown). Power path 601 is coupled to sensing path 603, which includes [missing information - likely related to a specific circuit or circuit]. Figure 5 The components are arranged in a similar manner to those in the embodiment and further include a current-limiting amplifier 613. When resistors R1 and R2 have the same value, operational amplifier 607 is coupled in a unity-gain configuration with a gain of -1, as described above. Figure 5 As described. This gain can be modified by changing the R2 / R1 ratio, thus providing additional adjustments. Figure 6 In the diagram, resistor RMON is shown as being implemented using an adjustable resistor. By adjusting the value of resistor RMON, the voltage appearing at terminal VMON can be adjusted. Current limiting can be achieved by setting the selected current-limiting monitoring voltage VMON to a voltage greater than the reference voltage Vref. In an alternative embodiment, the reference voltage Vref can also be adjusted to adjust the limit.

[0048] During operation, when the high-side transistor H-FET delivers current IL to the load (not shown) coupled to the output terminal VOUT, the current I... 感测 This will be proportional to the load current IL. The ratio is determined by the device area (W / L) ratio between the blocking transistor B-FET and the sensing transistor SENSE-FET. In this example, it is scaled to 1000, making the current I... 感测 It is 1 / 1000 of the load current IL. In additional embodiments, other scaling factors can be used. The ratio of resistors R1 to R2 provides additional scaling. A ratio of 5:1 can be used, or a ratio other than 1:1 can be used.

[0049] When the voltage at the voltage monitoring terminal VMON exceeds the reference voltage Vref, the current limiting amplifier 613 will limit the current flowing into the load at the output terminal VOUT. Control is achieved by modifying the gate voltage control signal HGATE. Because the gate control signal HGATE of the high-side transistor is controlled, and the gate control signal BGATE remains the same during the current limiting event, the sensed current I... 感测 The accuracy will not be affected.

[0050] In an exemplary implementation, the blocking transistor B-FET, the high-side transistor HS-FET, and the sensing transistor SENSE-FET are formed on a vertical FET semiconductor device with a "drain-down" configuration, such that node VMID is coupled to the semiconductor substrate. Operational amplifier 607 and current-limiting amplifier 613 can be implemented on separate conventional CMOS semiconductor devices. Resistors R1 and R2 can be formed on the CMOS device or alternatively provided using external resistors. The adjustable resistor RMON can be provided by the designer for a specific application and can have a fixed, adjustable, or programmable value. The reference voltage Vref can also be a fixed or adjustable value; alternatively, the value can be selected from a pre-programmed voltage level.

[0051] Figure 7 This is a circuit diagram of another embodiment of circuit 700 arranged for applications without current interruption. Figure 7 There is no blocking transistor. In applications, current can be allowed to flow from the output terminal VOUT back to the input terminal VIN under certain conditions. Figure 7 An embodiment includes a high-side transistor labeled H-FET, the high-side transistor having a current conduction path coupled between an input terminal VIN and an output terminal VOUT. Figure 7 In this context, H-FET provides compatibility with devices such as NexFET. TM This embodiment is compatible with "source-down" vertical FET devices, such as those described above. Other power FET devices can also be used. Figure 7 In this configuration, both the high-side transistor H-FET and the sensing transistor SENSE-FET have a first current conduction terminal, and their respective source terminals are coupled together in a common source circuit, enabling these FETs to be implemented in a "source-down" vertical FET device with the source terminals at the substrate.

[0052] exist Figure 7In this circuit, power path 701 contains only a high-side transistor H-FET coupled between the input terminal VIN for the power supply voltage and the output terminal VOUT for coupling the load to the circuit. The load current IL flows through the transistor H-FET and to the output terminal VOUT.

[0053] The control signal HGATE controls the gate voltage of the H-FET transistor. The sensing path 703 includes an op-amp 707 in a unity-gain configuration, resistors R1 and R2, and a feedback transistor FB-FET coupled to the gate terminal of the operational amplifier 707's output. A closed loop exists where the op-amp 707 has the drain-source voltage of the H-FET transistor, labeled "vd1" at its positive and negative terminals. The amplifier reflects this voltage to the node receiving the drain-source voltage "vd2" of the sensing transistor SENSE-FET. The op-amp 707 adjusts the gate voltage of the feedback transistor FB-FET to make the equation vd2 = vd1 * R2 / R1 true. When the SENSE-FET has the same drain-source voltage as the H-FET, the sensing current I... 感测 This will be proportional to the load current IL. As in the embodiment described above, the ratio is determined by the device area ratio of the H-FET device to the sensing transistor SENSE-FET. In this example, the ratio is 1 / 1000, such that the sensing current I... 感测 It is scaled to 1 / 1000 of the load current IL.

[0054] During operation, the value of the monitoring resistor RMON outside the integrated circuit sets the voltage VMON. Then, the current-limiting circuit controls the gate voltage HGATE. Figure 7 (Not shown in the image) can be used together with VMON and a reference voltage to control the load current.

[0055] Figure 7 An advantage of the circuit arrangement in this embodiment is that the sensing transistor and the high-side transistor H-FET can be implemented using vertical FET technology with a common source node on the substrate, such as a "source-down" device. However, because the gate voltage of the sensing transistor SENSE-FET is at the same node as the gate voltage of the high-side transistor H-FET, the accuracy of the sensed current under low gate voltage conditions is reduced compared to other embodiments. When the current limit is reached and the voltage HGATE decreases to limit the load current IL, the two devices, SENSE-FET and H-FET, will no longer be tightly matched, and the sensed current will not accurately track the load current IL.

[0056] The embodiment provides a current monitoring output that can be used to provide current limiting for a FET delivering current to a load. In the event of a sudden increase in load current, the circuit described above may not be fast enough to shut off the current conduction path of the power transistor to prevent damage. This can occur if the output is suddenly short-circuited to ground or if a short circuit occurs in the load device.

[0057] Figure 8 This is a circuit diagram of an alternative embodiment 800 having a fast-trip comparator and a fast-trip output signal that can be used for a power path to quickly shut down the circuit. The fast-trip output signal can also be used to limit the load current to a safe level. The fast-trip comparator circuit is triggered when the load current exceeds a multiple of the current limit value. It is generally desirable to have a short-circuit threshold (a multiple used to trigger the fast-trip comparator) that scales with the current limit. For example, the short-circuit current threshold can be set to twice the current limit. In the example embodiment, if the current limit increases, the short-circuit current will increase proportionally with the increase of the current limit.

[0058] exist Figure 8 In the power path 801, a blocking transistor BFET and a high-side transistor HS-FET are coupled in series with the current conduction path between the terminal VIN for the input voltage and the output terminal VOUT for the output voltage. A load (not shown) can receive a load current IL flowing through the transistors B-FET and HS-FET. In the sensing path 803, a sensing transistor SENSE FET is coupled to match the blocking transistor B-FET and has a drain terminal at the common drain node VMID, and has a gate terminal coupled together with the gate of the blocking transistor B-FET to the gate control signal BGATE.

[0059] The current-limiting amplifier 811 is coupled to node (B) and also to the common drain node VMID and the drain of the blocking transistor B-FET at node (A). Node (B) is also coupled to the source terminal of the blocking transistor B-FET via a resistor R1 with a value of 3R. Therefore, these two inputs of the differential amplifier 811 are coupled to receive the drain-source voltage of the blocking transistor B-FET. The sensing transistor SENSE-FET is coupled to output current I. 限制 As described above, because the source and gate terminals of the sensing transistor are coupled together with the source and gate terminals of the blocking transistor B-FET, the sensed current I... 限制 It will be proportional to the load current IL. The output of the current-limiting amplifier 811 controls the gate terminal of the high-side transistor HS-FET.

[0060] Instead of providing the monitoring output terminal VMON, Figure 8An embodiment is arranged to limit the load current IL to a specific limit current I set by operational amplifier 815, reference voltage Vref, transistor 817, and limiting resistor Rlim. 限制 This circuit acts as a voltage-to-current converter and will limit the current I. 限制 Set to equal to the current level Vref / Rlim. When the load current rises to the limit current I... 限制 At this time, the control loop formed by the current limiting amplifier 811 via the high-side transistor HS-FET becomes active, and the control signal HGATE is used to reduce the voltage at the gate of the high-side FET, thereby controlling the load current IL and preventing it from rising further.

[0061] During operation, when the current limit is met, the current limiting amplifier 811 will control the current IL to match the current I by changing the gate signal HGATE of the HS-FET. 限制 .in addition, Figure 8 The embodiment provides a fast trip function. The fast trip comparator 813 compares the voltage at the common node (A) belonging to the source terminals of the transistor with the voltage at node (C). Node (C) is the voltage generated using a resistor divider. Figure 8 In the diagram, resistor R1 has a value of 3R, while resistor R2 is implemented using a series resistor R2A (=R) + R2B (=2R). For example... Figure 8 As shown, resistors R1 and R2 can be equal. These two resistors R2A and R2B are used in a trapezoidal configuration to form resistor R2, which generates a voltage at node (C) for use by the fast trip comparator 813.

[0062] Figure 9 A simplified circuit diagram is shown for further description of the operation of the fast trip comparator circuitry, intended for use in the embodiments. Figure 9 In the figure, similar reference numerals are used to correspond with Figure 8 Similar components to those in [the text]. For example, in [the text]. Figure 9 In the middle, comparator 913 and Figure 8 The comparator 813 in the code corresponds to this.

[0063] exist Figure 9In this circuit, a Wheatstone bridge is formed, consisting of a resistor ladder (R1 (=3R) and resistor R2A (=R) in series) with a value of 4R, a blocking transistor B-FET, and a sensing transistor SENSE-FET. Comparator 913 is triggered when the voltage at node (C) exceeds the voltage at node (A). The load current IL will typically cause the voltage at node (A) to exceed the voltage at node (C). In the event of a sudden and rapid increase in the load current IL, the voltage at node (A) will drop rapidly (compared to the voltage at node (C)). Comparator 913 will respond by quickly tripping the signal at O / P with its output signal. Figure 9 In the diagram, the voltage drop across the resistor is shown to be 30 millivolts, and the corresponding voltage drop across the blocking transistor B-FET is 20 millivolts, while the voltage drop across the sensing transistor is 10 millivolts. The load current IL flows through the blocking transistor B-FET but not through the sensing transistor SENSE-FET. When the load current IL suddenly increases, the fast comparator 913 is triggered when the drain-source voltage across the blocking transistor B-FET suddenly increases, causing the voltage at node (A) to drop while the voltage at node (C) remains unaffected by the increased load current IL.

[0064] This specific example of a fast trip circuit implements the current limit I. 限制 The fast trip signal is triggered when the current IL suddenly exceeds twice the short-circuit current threshold (i.e., the current at which the fast trip output signal becomes active). For example, if the current limit is 1 amp, the fast trip signal FAST TRIP will be triggered when the current IL suddenly exceeds 2 amps. Figure 8 This occurs when a sudden short circuit happens at the output terminal VOUT of the circuit. In this case, the rise rate of the load current IL may be faster than the response time of the current limiting loop containing amplifier 811. Different current limiting thresholds can be selected by changing the arrangement and value of the resistors.

[0065] Figure 10 This is a circuit diagram of an additional alternative embodiment circuit 1000. Figure 10 The reference numerals in the attached figures are similar to Figure 8 Reference numerals for similar components in the accompanying drawings. For example, Figure 10 The amplifier 1007 in the middle is similar to Figure 8 Amplifier 807 in the middle. Figure 10 In this configuration, load current can flow in either direction from the terminal VIN (for receiving power supply voltage) to the output terminal VOUT, or alternatively, load current can flow in the opposite direction. In some applications, the VIN and VOUT terminals can couple two devices that can receive or supply current. For example, a USB-C connector interface can be located between two battery-powered devices, and current can flow in either direction. Figure 10In one embodiment, the circuitry is arranged to share amplifier 1007. Amplifier 1007 can be a differential amplifier and can be implemented as an operational amplifier. By sharing this portion of the circuitry, silicon area and cost are reduced. However, as described below, additional transistors are used to couple the voltage required for amplifier 1007, depending on the current direction. In alternative embodiments, additional amplifiers can be used, but at the cost of increased silicon area.

[0066] exist Figure 10 In this configuration, the blocking transistor B-FET and the high-side transistor HS-FET are coupled to a current conduction path located between the input terminal VIN and the output terminal VOUT. When power path 1001 is active, the load current IL flows through both the blocking transistor B-FET and the high-side transistor HS-FET. System 1000 has two current sensing transistors, sensing transistor SENSE-FET B and sensing transistor SENSE-FET H. Each sensing transistor shares a common node with the power transistor at node VMID. Figure 10 The embodiment is compatible with a "drain-down" configuration, allowing the drain terminals of the blocking transistor B-FET, the blocking sensing transistor SENSE-FET B, the high-side transistor HS-FET, and the high-side current sensing transistor SENSE-FET H to be coupled to node VMID. Therefore, the device in power path 1001 can use devices with features such as NexFET. TM The device is implemented using a semiconductor device with a vertical FET arrangement. However, other power FET transistors can also be used with the current sensing circuit system of the embodiment, whether they are vertical FETs or other transistors. Discrete FET devices can be used.

[0067] When the input voltage at terminal VIN is greater than the output voltage at terminal VOUT Figure 10 The embodiments in the example are in conjunction with Figure 8 The embodiment operates in a similar manner. The sensing circuit in sensing path 1003 uses a resistor network R1, R2 and transistor M5 to couple one terminal of amplifier 1007 to the source terminal of a blocking transistor B-FET, which is coupled to terminal VIN. In this example, the signal RV is at a "low" potential when the circuit operates in a positive direction with current IL flowing from VIN to VOUT. The opposite terminal of amplifier 1007 is coupled to a common drain node VMID via transistor M6, which is also controlled by signal RV. Figure 10In an example embodiment, transistors M5, M6, M7, and M8 are P-channel transistors and are active when a "low" potential is present at their gate terminals. These transistors form a selection circuit that selects the input to the positive terminal of operational amplifier 1007 between the node between R1 and R2 and the output of the high-side sensing FET SENSE FET-H according to the current direction indicated by control signals RV, RV_. The selection circuit selects the input to the negative input terminal of operational amplifier 1007 between VMID and the voltage at the output voltage terminal VOUT. Operational amplifier 1007 controls the current flowing in the feedback transistor FB-FET so that the current flowing through the monitoring resistor RMON is proportional to the load current IL. In the example embodiment, amplifier 1007 is an operational amplifier coupled in a closed-loop configuration.

[0068] exist Figure 10 In this embodiment, the system 1000 can also sense current when the load current IL reverses direction and flows from the output terminal VOUT to the input terminal VIN. In this configuration, the current IL flows to terminal VIN through the high-side transistor HS-FET and the blocking transistor B-FET. This occurs when the voltage at terminal VOUT is greater than the voltage at terminal VIN. The sensing transistor SENSE-FET H is coupled, wherein the gate of the sensing transistor shares the same voltage as the gate of the high-side transistor (the signal HGATE is coupled to both gate terminals), and the drains of both devices are coupled to a common drain node VMID. Therefore, the sensing transistor SENSE FET-H is matched with the high-side transistor HS-FET. The sensed current flowing through the high-side sensing transistor SENSE FET-H will be proportional to the load current flowing through the high-side transistor HS-FET. Another selection circuit is formed by transistors M1, M2 and M3, M5 and selects between the output terminals of SENSE FET-B and SENSE FET-H according to control signals R_ and R_. When the current reverses as indicated by signal R, transistors M3 and M4 couple the high-side sensed current to the feedback transistor FB-FET, and the sensed current can be observed as the voltage at the monitoring terminal VMON. Operational amplifier 1007 is coupled to the source of the high-side transistor (coupled to terminal VOUT) via transistor M8, while the drain terminal of the high-side transistor is coupled to the opposite terminal of amplifier 1007 via transistor M7. Transistors M7 and M8 both have a direction signal RV coupled to the gate terminal. Transistors M3 and M4 have a direction signal R coupled to the gate terminal.

[0069] Signals RV and RV_ are direction signals indicating when the current IL flows in opposite directions and the voltage level is shifted to the VMID domain. Signals R and R_ are direction signals indicating when VOUT is greater than VIN and when the load current IL flows in opposite directions. Signals RV and RV_ are coupled to a first selection circuit that selects the signals to the positive and negative input terminals of operational amplifier 1007. Signals R and R_ are coupled to a second selection circuit that selects the sense current input to the feedback transistor FB-FET.

[0070] In operation, the sensed current flowing through the feedback transistor FB-FET is proportional to the load current as described above; the ratio is determined by the device area ratio between the sense transistors SENSE FET_B and SENSE FET-H and the power transistors B-FET and HS-FET. In this example, the sense transistor is 1 / 1000th the device size of the power transistors, and the sensed current is therefore 1 / 1000th the magnitude of the load current IL.

[0071] By detecting the direction of the load current and by enabling the appropriate sensing current path and sensing device. Figure 10 The embodiments can provide sensing current under the following two conditions: VIN>VOUT and load current flows from VIN to VOUT; and VOUT>VIN and load current flows from VOUT to VIN in the opposite direction.

[0072] exist Figure 10 In this circuit, signals R and R_, as well as corresponding level shift signals RV and RV_, are required for the operation of circuit 1000. Figure 11A It is a circuit diagram of an arrangement used to provide direction signals R and R_. Figure 11B This is a circuit diagram of the level shifting circuit that generates signals RV and RV_.

[0073] exist Figure 11A In this circuit, voltage comparator 1101 compares the voltage at input terminal VIN with the voltage at output terminal VOUT and determines when VOUT is at a higher voltage than VIN. When the output voltage VOUT is higher, signal R becomes active, thereby indicating current reversal. Signal R_inverted is then simply output through inverter 1103. Figure 11B This is a circuit for shifting a signal R to the VMID voltage using a buffer powered by the VMID voltage. Buffer 1107 outputs level-shifted versions of signals R and RV. Inverter 1109, which also receives the VMID voltage, outputs an inverted signal RV_. Current bias 1111 provides current to the level-shifting circuit. Other arrangements of the level-shifting circuit can be made for use with this embodiment.

[0074] Figure 12 This is a block diagram of an embodiment of an electric fuse system. Figure 12 In this first integrated circuit 1203, a power transistor and a sensing transistor are included in a single device. Figure 12 In this embodiment, power path for an electric fuse system comprising a blocking transistor, a high-side transistor, and a sensing transistor can be implemented on a single semiconductor substrate using power transistor technology. In this example, a vertical FET device can be used. In this example, a NexFET from Texas Instruments can be used. TM Devices. However, the current sensing and current limiting embodiments described above can also be used with other power FET technologies. Discrete FET devices on a circuit board can be used to form embodiments.

[0075] exist Figure 12 In this circuit, the control IC 1201 may include the sensing path devices, operational amplifier, resistor divider circuitry, and feedback FET device as described above. Because the sensed current can be scaled to be much smaller than the load current, and because the circuitry in the control IC 1201, which includes the operational amplifier, can be powered by commonly used low-current IC supply voltages, conventional high-voltage, low-current CMOS semiconductor devices can be used to implement the control IC 1201. Using low-current devices results in lower system cost and reduced power consumption.

[0076] In operation, control IC 1201 can supply BGATE and HGATE signals to enable power IC 1203 to supply current to a load (not shown) coupled to the output terminal. Power IC 1203 can couple the current conduction path of the power transistor in series between the output terminal and the input voltage at the input terminal VIN. The load current can be sensed by a sensing transistor on the power IC, and the sensed current is output via the ISENSE signal. The operational amplifier and feedback transistor in the control IC can be used to provide the output voltage VMON using an external resistor RMON. In an exemplary embodiment, a current-limiting circuit can also be included within control IC 1201. When an excessive load current occurs, the gate voltage HGATE can be reduced to control the load current. This can be performed as described above when the voltage VMON exceeds a reference voltage.

[0077] In embodiments, one or more power transistors and sensing transistors may share a common drain node or a common source node. Advanced FET semiconductor devices, such as vertical FETs, can be used to implement power transistors and sensing transistors on a single substrate, wherein a shared drain node or a shared source node is formed on the substrate. In alternative embodiments, lateral FET devices for power transistors can also be used in conjunction with the current sensing circuitry and current limiting circuitry described above.

[0078] Alternative arrangements that could form additional embodiments include increasing the level of integration to form a single integrated circuit comprising a current sensing circuitry system and a power circuitry system. However, because the semiconductor process for power FETs is optimized for high-voltage, high-current-capability transistors and is more expensive than conventional CMOS processes, manufacturing such... Figure 12 The arrangement shown, with two integrated circuits, would be more cost-effective.

[0079] In one example, a device includes: a first power transistor having a first current conduction path between a first current conduction terminal and a second current conduction terminal, the first current conduction path of the first power transistor being coupled between an input terminal for receiving a power supply voltage and a node, the first power transistor having a first gate terminal coupled to a first gate control signal for controlling the first power transistor; a second power transistor having a second current conduction path between a third current conduction terminal and a fourth current conduction terminal, the second current conduction path of the second power transistor being coupled between the node and an output terminal for supplying load current to a load; the second power transistor having a second gate terminal coupled to a second gate control signal; and a current sensing transistor having a current conduction terminal coupled to the node and the first power transistor, having a coupling... The sensor provides a third gate terminal to the first gate control signal and outputs a sensed current at another current conduction terminal; a differential amplifier having a first input terminal coupled to one of the first and second current conduction terminals of the first power transistor and a second input terminal coupled to the other of the first and second current conduction terminals, and having an output signal responsive to the voltage difference between the first and second input terminals; a feedback transistor having another current conduction path coupled in series between the current sensing transistor and the monitoring node, and having a feedback transistor gate terminal coupled to the output of the differential amplifier; and a resistor coupled between the monitoring node and ground, through which the sensed current flows, and the sensed current being proportional to the load current flowing through the second power transistor.

[0080] In a further example, in the above-described device, the current sensing transistor and the first power transistor are formed on a semiconductor substrate, and the device area of ​​the current sensing transistor is smaller than the device area of ​​the first power transistor.

[0081] In another example, in the device described above, the sensed current flowing through the current-sensing transistor is proportional to the load current. In an additional example, in the device described above, the first power transistor, the second power transistor, and the current-sensing transistor are field-effect transistor (FET) devices formed on a single integrated circuit. In a further example, the FET device forming the power transistor is selected from vertical FET devices and non-vertical FET devices.

[0082] In yet another example, in the aforementioned device, the node is formed in the semiconductor substrate of the single integrated circuit.

[0083] In an alternative arrangement, the device further includes a fast trip comparator coupled between the node and a voltage divider coupled to the input to output a fast trip signal in response to a drop in voltage at the node when the load current increases rapidly.

[0084] In yet another example, the device further includes a current-limiting circuit coupled to the second gate terminal of the second power transistor to limit the voltage of the second gate control signal when the sensed current exceeds the current limit.

[0085] In another example, in the aforementioned device, the first current-conducting terminal of the first power transistor is a first source terminal, the second current-conducting terminal of the first power transistor is a first drain terminal, the third current-conducting terminal of the second power transistor is a second drain terminal, the fourth current-conducting terminal of the second power transistor is a second source terminal, and the current-sensing transistor has a third drain terminal as the current-conducting terminal, the third drain terminal being coupled at the node to the first drain terminal of the first power transistor and the second drain terminal of the second power transistor.

[0086] In yet another example, as in the example above, the differential amplifier is an operational amplifier. In a still further example, the operational amplifier is coupled to the feedback transistor in a closed loop.

[0087] In another example, a circuit system includes: a first field-effect transistor having a first source terminal and a first drain terminal, the first source terminal being coupled to an input terminal for receiving power and the first drain terminal being coupled to a node; and having a first gate terminal for receiving a first gate control signal; a second field-effect transistor having a second drain terminal and a second source terminal, the second drain terminal being coupled to the node and the second source terminal being coupled to an output terminal for supplying load current to a load; and having a second gate terminal for receiving a second gate control signal; a current-sensing transistor having a third drain terminal coupled to the node and a first drain terminal coupled to a second source terminal. The current sensing transistor has a third source terminal for outputting the sensed current, the current sensing transistor having a third gate control terminal coupled to the first gate control signal; a first current limiting amplifier having a first input terminal coupled to the input terminal and a second input terminal coupled to the node and outputting the second gate control signal; and an operational amplifier coupled to a feedback transistor having a voltage reference at the first input terminal and a current limiting output terminal at the second input terminal, and an output terminal coupled to the gate terminal of the feedback transistor having a current conduction path coupled between the sensed current output terminal of the current sensing transistor and the current limiting output terminal.

[0088] In yet another example, the circuit system described above further includes a first resistor and a second resistor, the first resistor being coupled between the input terminal and the first input terminal of the current-limiting amplifier, and the second resistor being coupled between the first resistor and the third source terminal of the current-sensing transistor.

[0089] In yet another example, in the circuit system described above, the second resistor further includes a third resistor and a fourth resistor arranged in a resistance ladder configuration.

[0090] In yet another example, the circuit system described above further includes a fast trip comparator coupled to compare the voltage between the third resistor and the fourth resistor with the voltage at the node, so as to output a fast trip output signal in response to a drop in the voltage at the node, the drop indicating a rapid increase in the load current.

[0091] In yet another additional example, the circuit system further includes a current-limiting resistor coupled between the current-limiting output terminal and ground. In another additional example, as in the example described above, the first field-effect transistor, the second field-effect transistor, and the current-sensing transistor are on an integrated circuit.

[0092] In yet another example, a device includes: a voltage input terminal for receiving a power supply voltage; a voltage output terminal for coupling to a load; a first power transistor having a first current conduction path coupled between the voltage input terminal and a common node and having a first gate terminal coupled to a first gate control signal; and a second power transistor having a second current conduction path coupled between the common node and the voltage output terminal and having a second gate terminal coupled to a second gate control signal. The device further includes: a first current sensing transistor having a third current conduction path coupled to the common node and a third gate terminal coupled to the first gate control signal for outputting a first sensing current proportional to the load current flowing from the voltage input terminal to the voltage output terminal; a second current sensing transistor having a fourth current conduction path coupled to the common node and a fourth gate terminal coupled to the second gate control signal, and outputting a second sensing current proportional to the load current flowing from the output terminal to the input terminal; a differential amplifier having a first input terminal and a second input terminal and having an output signal corresponding to the difference between the voltages at the first input terminal and the second input terminal; and a feedback transistor coupled to a monitoring resistor at a monitoring node and having a current conduction path coupled to one of the first sensing current and the second sensing current, and having a gate control terminal coupled to the output of the differential amplifier.

[0093] In yet another example, the device further includes a first selection circuit for coupling the first input terminal of the differential amplifier to one of the following in response to a signal indicating the direction of the load current: a resistor coupled to the input voltage terminal and a resistor coupled to the second current sensing transistor.

[0094] In yet another example, the device further includes a second selection circuit for coupling the feedback transistor to one of the first sense current from the first current sensing transistor and the second sense current from the second current sensing transistor in response to a signal indicating the direction of the load current.

[0095] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An apparatus comprising: a first power transistor having a first current conduction path between a first current conduction terminal and a second current conduction terminal, the first current conduction path of the first power transistor coupled between an input for receiving a supply voltage and a node, the first power transistor having a first gate terminal coupled to a first gate control signal for controlling the first power transistor; a second power transistor having a second current conduction path between a third current conduction terminal and a fourth current conduction terminal, the second current conduction path of the second power transistor coupled between the node and an output terminal for supplying a load current to a load; the second power transistor having a second gate terminal coupled to a second gate control signal; a current sense transistor having one current conduction terminal coupled to the node and to the first power transistor, having a third gate terminal coupled to the first gate control signal and outputting a sense current at another current conduction terminal; a differential amplifier having a first input coupled to one of the first current conduction terminal and the second current conduction terminal of the first power transistor and having a second input coupled to the other of the first current conduction terminal and the second current conduction terminal, and having an output signal responsive to a voltage difference between the first input and the second input; a feedback transistor having another current conduction path coupled in series between the current sense transistor and a monitor node, having a feedback transistor gate terminal coupled to an output of the differential amplifier; and a resistor coupled between the monitor node and ground, the sense current flowing through the resistor, the sense current being proportional to the load current flowing through the second power transistor.

2. The apparatus of claim 1, wherein the current sense transistor and the first power transistor are formed on a semiconductor substrate, and a device area of the current sense transistor is less than a device area of the first power transistor.

3. The apparatus of claim 1, wherein the sense current flowing through the current sense transistor is proportional to the load current.

4. The apparatus of claim 1, wherein the first power transistor, the second power transistor, and the current sense transistor are field effect transistor (FET) devices formed on a single integrated circuit.

5. The apparatus of claim 4, wherein the FET devices are selected from vertical FET devices and non-vertical FET devices.

6. The apparatus of claim 4, wherein the node is formed in a semiconductor substrate of the single integrated circuit.

7. The apparatus of claim 1, further comprising a fast trip comparator coupled between the node and a voltage divider coupled to the input for outputting a fast trip signal responsive to a drop in voltage at the node when the load current rapidly increases. ​ 8. The apparatus of claim 1, further comprising a current limiting circuit coupled to the second gate terminal of the second power transistor for limiting a voltage of the second gate control signal when a sensed current exceeds a current limit.

9. The apparatus of claim 1, wherein the first current conducting terminal of the first power transistor is a first source terminal, the second current conducting terminal of the first power transistor is a first drain terminal, the third current conducting terminal of the second power transistor is a second drain terminal, the fourth current conducting terminal of the second power transistor is a second source terminal, and the current sense transistor has a third drain terminal as the current conducting terminal, the third drain terminal coupled to the first drain terminal of the first power transistor and the second drain terminal of the second power transistor at the node.

10. The apparatus of claim 1, wherein the differential amplifier is an operational amplifier.

11. The apparatus of claim 10, wherein the operational amplifier is connected in a closed loop with the feedback transistor.

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