High electron mobility transistor with deep carrier gas contact structure

Abstract

A method for forming a semiconductor device, comprising providing a heterojunction semiconductor body. The heterojunction semiconductor body comprises a III-V semiconductor back barrier region, a III-V semiconductor channel layer formed on the back barrier region, and a III-V semiconductor barrier layer formed on the back barrier region. A first two-dimensional carrier gas is located at an interface between the channel and the barrier layer. A second two-dimensional carrier gas is arranged below the first two-dimensional carrier gas. A deep contact structure is formed in the heterojunction semiconductor body, the deep contact structure extending through the channel layer and forming an interface with the second two-dimensional carrier gas. The first semiconductor region comprises a first contact material, which provides a conductive path for the majority carriers of the second two-dimensional carrier gas at an interface with the second two-dimensional carrier gas.

Description

Background Art

[0001] Semiconductor transistors are used in a wide variety of applications, especially field effect controlled switching devices such as MISFET (Metal Insulator Semiconductor Field Effect Transistor), hereinafter also referred to as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and HEMT (High Electron Mobility Field Effect Transistor) (also known as Heterostructure FET (HFET) and Modulation Doped FET (MODFET)). HEMT is a transistor having a junction between two materials with different band gaps, such as GaN and AlGaN. In GaN / AlGaN based HEMTs, a two-dimensional electron gas (2DEG) appears at the interface between the AlGaN barrier layer and the GaN channel layer. In HEMTs, the 2DEG forms the channel of the device. Similar principles can be used to select the channel and barrier layers, which form a two-dimensional hole gas (2DHG) as the channel of the device. 2DEG or 2DHG is often referred to as a two-dimensional carrier gas. In the absence of further measures, the heterojunction configuration results in a self-conducting (i.e., normally-on) transistor. Measures must be taken to prevent the channel region of the HEMT from being in a conducting state in the absence of a positive gate voltage.

[0002] Due to the high electron mobility of the two-dimensional carrier gas in the heterojunction configuration, HEMTs provide high conduction and low losses compared to many conventional semiconductor transistor designs. For example, these favorable conduction characteristics make HEMTs desirable in applications including, but not limited to, use in power supplies and power converters, electric vehicles, air conditioners, and as switches in consumer electronics.

[0003] The HEMT may include a so-called back barrier region below the heterostructure portion, i.e., below the channel layer. The back barrier region may be formed of a III-V type semiconductor having a different bandgap than the channel region, such as AlGaN in the case of a GaN channel region. The back barrier region is used to increase electron confinement in the device channel and thus change the threshold voltage of the device. An example of a HEMT with a back barrier region is disclosed in U.S. application Ser. No. 15 / 352,115 to Curatola, the contents of which are hereby incorporated by reference in their entirety.

[0004] Although the back barrier region can improve the performance of the HEMT, one problem with the design of the HEMT including the back barrier region is that a secondary intrinsic two-dimensional carrier gas (e.g., 2DHG) is formed at the interface between the channel and the back barrier region due to the difference in band gap between the channel and the back barrier region materials. The secondary intrinsic two-dimensional carrier gas forms an electrically floating channel in the device, which may adversely affect device reliability. Summary of the invention

[0005] A method for forming a semiconductor device is disclosed. According to an embodiment, the method includes: providing a heterojunction semiconductor body. The heterojunction semiconductor body includes: a III-V type semiconductor back barrier region; a III-V type semiconductor channel layer, which is formed on the back barrier region and has a band gap different from the back barrier region; and a III-V type semiconductor barrier layer, which is formed on the channel layer and has a band gap different from the barrier layer. The first two-dimensional carrier gas is at an interface between the channel and the barrier layer. The second two-dimensional carrier gas is arranged below the first two-dimensional carrier gas. A deep contact structure is formed in the heterojunction semiconductor body. The deep contact structure extends through the channel layer and forms an interface with the second two-dimensional carrier gas. The deep contact structure includes a first contact material, which provides a conductive path for the majority carriers of the second two-dimensional carrier gas at the interface with the second two-dimensional carrier gas.

[0006] A semiconductor device is disclosed. According to an embodiment, the semiconductor device includes a heterojunction semiconductor body. The heterojunction semiconductor body includes: a III-V type semiconductor back barrier region; a III-V type semiconductor channel layer, which is formed on the back barrier region and has a band gap different from the barrier region; and a III-V type semiconductor barrier layer, which is formed on the channel layer and has a band gap different from the barrier layer. A first two-dimensional carrier gas is formed at an interface between the channel and the barrier layer. A second two-dimensional carrier gas is arranged below the first two-dimensional carrier gas. A deep contact structure is formed in the heterojunction semiconductor body. The deep contact structure extends through the channel layer and forms an interface with the second two-dimensional carrier gas. The deep contact structure includes a first contact material, which provides a conductive path for the majority carriers of the second two-dimensional carrier gas at an interface with the second two-dimensional carrier gas.

[0007] According to another embodiment, a semiconductor device includes a heterojunction semiconductor body. The heterojunction semiconductor body includes: a III-V semiconductor back barrier region, a III-V semiconductor channel layer formed on the back barrier region, and a III-V semiconductor barrier layer formed on the channel layer. A two-dimensional electron gas is formed at the interface between the barrier and the channel layer. The two-dimensional hole gas is arranged below the two-dimensional electron gas. Conductive source and drain electrodes are formed on the heterojunction semiconductor body and are in ohmic contact with the two-dimensional electron gas. A gate structure is formed on the heterojunction semiconductor body and is configured to control the conductive connection between the source electrode and the drain electrode by controlling the conductive state of the two-dimensional electron gas. A deep contact structure is formed in the heterojunction semiconductor body. The deep contact structure provides an electrical connection that sets the potential of the holes in the two-dimensional hole gas to the potential of the source electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and described in detail in the specification below.

[0009] Figure 1 A semiconductor device having a deep contact structure according to an embodiment is illustrated.

[0010] Figure 2 A semiconductor device having a deep contact structure according to another embodiment is illustrated.

[0011] Figure 3 A semiconductor device having a deep contact structure according to another embodiment is illustrated.

[0012] Figure 4 It is illustrated that a heterostructure semiconductor body is provided in a method of forming a semiconductor device according to an embodiment.

[0013] Figure 5 Forming a contact trench in a heterostructure semiconductor body in a method of forming a semiconductor device according to an embodiment is illustrated.

[0014] Figure 6 It is illustrated that a doped semiconductor layer and a metal layer are formed on a heterostructure semiconductor body in a method of forming a semiconductor device according to an embodiment.

[0015] Figure 7 FIG. 1 illustrates structured doped semiconductor layers and metal layers in a method of forming a semiconductor device according to an embodiment.

[0016] Figure 8 It is illustrated that a first dielectric layer is formed on a structured region in a method of forming a semiconductor device according to an embodiment.

[0017] Fig. 9 It is illustrated that a first dielectric layer is patterned to form a contact opening in a method of forming a semiconductor device according to an embodiment.

[0018] Fig.10 It is illustrated that first and second input-output electrodes are formed in a contact opening in a method of forming a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0019] According to embodiments described herein, a semiconductor device that can be configured as a HEMT includes a deep contact structure that is directly bonded to one or more secondary two-dimensional hole gases (2DEG) of the device. The secondary two-dimensional hole gas is located below the primary two-dimensional electron gas (2DEG) that forms the channel of the device. The deep contact structure provides a conductive connection between the input-output terminal (e.g., source terminal) of the device and the secondary two-dimensional hole gas. Therefore, the deep contact structure sets (one or more) secondary two-dimensional hole gases to a fixed potential, such as a source potential. This improves the reliability and dynamic performance of the device. In particular, a conductive path for electron-hole recombination between holes of (one or more) secondary two-dimensional hole gases and electrons of the two-dimensional electron gas is provided. Therefore, compared with a device with a floating (one or more) secondary two-dimensional hole gas, the electron-hole recombination effect is significantly improved. In addition, by setting the potential of (one or more) secondary two-dimensional hole gases to match the source potential, potentially dangerous electrical gradients under the device can be avoided. In addition, during the transition from OFF to ON, the carrier density of the two-dimensional electron gas between the first and second input-output electrodes decreases. Therefore, the device (e.g., R DSON )'s dynamic performance.

[0020] The deep contact structure may be formed from a semiconductor material or a metal. In an advantageous method for forming the deep contact structure, a single epitaxial semiconductor layer is used to form the deep contact structure and is used to provide a portion of a gate structure of a normally-off device.

[0021] Reference Figure 1 , a semiconductor device 100 is depicted according to an embodiment. The semiconductor device 100 includes a heterojunction semiconductor body 102. The heterojunction semiconductor body 102 includes a back barrier region 104, a channel layer 106 formed on the back barrier region 104, and a barrier layer 108 formed on the channel layer 106. The barrier layer 108 has a band gap different from that of the channel layer 106. Due to the difference in the band gap, a first two-dimensional carrier gas 110 intrinsically appears near the interface between the channel layer 106 and the barrier layer 108. In addition, the material of the back barrier region 104 has a band gap different from that of the material of the channel layer 106. Due to the difference in the band gap, a second two-dimensional carrier gas 112 intrinsically appears near the interface between the channel layer 106 and the back barrier region 104. The second two-dimensional carrier gas 112 has a majority carrier type opposite to that of the first two-dimensional carrier gas 110. For example, in the case where the first two-dimensional carrier gas 110 is a two-dimensional electron gas (2DEG), the second two-dimensional carrier gas 112 is a two-dimensional hole gas (2DHG), and vice versa.

[0022] In general, the channel layer 106 and the barrier layer 108 may be formed of any semiconductor material in which the band gap can be manipulated to form the first two-dimensional carrier gas 110. Examples of such materials include III-V type semiconductor materials (e.g., gallium nitride, gallium arsenide, etc.) into which metal elements (e.g., aluminum, indium, etc.) are introduced to adjust the band gap. The material properties (e.g., thickness, band gap, etc.) of the back barrier region 104 are selected to increase carrier confinement in the first two-dimensional carrier gas 110 and prevent device leakage through the region below the heterojunction semiconductor body 102.

[0023] The heterojunction semiconductor body 102 additionally includes a transition region 114 and a base substrate 116. The transition region 114 is formed on the base substrate 116, and the back barrier region 104 is formed on the transition region 114. The base substrate 116 includes: a semiconductor material suitable for epitaxial growth technology, for example, silicon, carbon, silicon carbide, sapphire, etc. The transition region 114 is a so-called lattice transition region 114, which is configured to relieve mechanical stress, which is attributable to the lattice mismatch between the IV-type semiconductor material (for example, silicon) of the base substrate 116 and the III-V-type semiconductor material (for example, GaN, AlGaN) of the channel layer 106 and the barrier layer 108. For example, the transition region 114 may include a III-V-type semiconductor material, a metal layer, and an electrical insulator. In addition, the metal concentration of the transition region 114 may be changed in a manner to relieve mechanical stress, for example, having a metal concentration that decreases as it moves away from the base substrate 116.

[0024] According to an embodiment, the heterojunction semiconductor body 102 is a gallium nitride (GaN)-based semiconductor body. In this embodiment, the base substrate 116 is provided by a commercially available batch wafer such as a silicon wafer. In addition, in this embodiment, the transition region 114 includes aluminum gallium nitride (AlGaN) having an aluminum content that gradually decreases as it moves away from the base substrate 116. Alternatively, the transition region 114 may include an aluminum nitride (AlN) layer periodically inserted between multiple GaN layers or GaN-based layers. In addition, in this embodiment, the back barrier region 104 may be a region of aluminum gallium nitride (AlGaN) having a uniform aluminum content (within the process capability) between 2% and 10%, for example, throughout the entire back barrier region 104. In addition, in this embodiment, the channel layer 106 may be an intrinsic layer of pure or substantially pure GaN. Alternatively, the channel layer 106 may include AlGaN having a very low Al content (e.g., less than 10%), and may additionally or alternatively include dopant atoms (such as, for example, carbon or iron). Furthermore, in this embodiment, the barrier layer 108 may be a layer of AlGaN having a higher Al content (e.g., greater than 10%, 15%, 20%, etc.) than the channel layer 106.

[0025] The semiconductor device 100 additionally includes: a first conductive input-output electrode 118 and a second conductive input-output electrode 120. The first and second input-output electrodes 118, 120 are both formed on the barrier layer 108. The first and second input-output electrodes 118, 120 may include metals (e.g., nickel, copper, titanium, alloys thereof), metal nitrides (e.g., AlN, TiN), and highly doped semiconductors (e.g., polysilicon).

[0026] Both the first and second input-output electrodes 118, 120 form ohmic contact with the first two-dimensional carrier gas 110. This can be provided by direct physical contact between the first and second input-output electrodes 118, 120 and the first two-dimensional carrier gas 110. However, if Figure 1 As shown in , direct physical contact between the first two-dimensional carrier gas 110 and the first and second input-output electrodes 118, 120 is not required.

[0027] The semiconductor device 100 further includes a gate structure 122. The gate structure 122 is formed on the barrier layer 108 between the first and second input-output electrodes 118, 120. The gate structure 122 includes a second semiconductor region 124 formed on an upper surface of the barrier layer 108. The material properties (e.g., doping concentration, thickness, etc.) of the second semiconductor region 124 are selected so that the second semiconductor region 124 (in the absence of any external bias) applies an electric field to the first two-dimensional carrier gas 110, which locally depletes the first two-dimensional carrier gas 110 below the gate structure 122.

[0028] According to an embodiment, the second semiconductor region 124 includes p-type GaN. The gate structure 122 further includes a conductive gate electrode 126 formed on the doped semiconductor region. The gate electrode 126 may include a metal (e.g., nickel, copper, titanium, alloys thereof), a metal nitride (e.g., AlN, TiN), and a highly doped semiconductor (e.g., polysilicon).

[0029] The semiconductor device 100 further includes a first dielectric layer 128 formed on the heterojunction semiconductor body 102. The first dielectric layer 128 covers and may directly contact the channel layer 106, which is in the region between the gate structure 122 and the first input-output electrode 118, and also in the region between the gate structure 122 and the second input-output electrode 120. Exemplary materials suitable for the first dielectric layer 128 include silicon nitride (SiN), silicon dioxide (SiO2), and silicon oxynitride (SiO x N y ), or more generally, any of a variety of photoresist materials, to name a few. According to an embodiment, the first dielectric layer 128 includes Si3N4.

[0030] According to an embodiment, the semiconductor device 100 is configured as a high electron mobility transistor, wherein the first input-output electrode 118 provides a drain of the device, the second input-output electrode 120 provides a source of the device, and the gate electrode 126 provides a voltage-controlled gate terminal that controls the electrical connection between the source and drain terminals of the device. The first two-dimensional carrier gas 110 serves as a channel of the device and provides a conductive connection between the first and second input-output electrodes 118, 120. A control signal in the form of a voltage is applied to the gate electrode 126 to locally deplete (or refill) the first two-dimensional carrier gas 110, and thus complete or interrupt the conductive connection between the first and second input-output electrodes 118, 120. Due to the provision of the second semiconductor region 124, the device is configured as a so-called "normally off" device. That is, in the absence of a voltage applied to the gate electrode 126, the conductive connection between the first and second input-output electrodes 118, 120 does not exist, and a sufficient voltage (i.e., a threshold voltage V) applied to the gate electrode 126 is not present. TH ) refills the depletion region of the first two-dimensional carrier gas 110 and thereby completes the conductive connection between the first and second input-output electrodes 118 , 120 .

[0031] The semiconductor device 100 additionally includes a deep contact structure 130. The deep contact structure 130 provides a conductive connection between the second two-dimensional carrier gas 112 and the second input-output electrode 120. Due to the electrical connection between the first contact material 132 and the second input-output electrode 120, a low-resistance path is provided for the majority carriers present in the second two-dimensional carrier gas 112 to flow into and out of the second input-output electrode 120. Therefore, through the deep contact structure 130, the potential of the second two-dimensional carrier gas 112 is set to the potential of the second input-output electrode 120.

[0032] The deep contact structure 130 includes a first contact material 132 that extends through the barrier layer 106 and the channel layer 108 and directly interfaces with the second two-dimensional carrier gas 112. The first contact material 132 is selected to allow holes from the two-dimensional carrier gas 112 to easily pass through the interface between the first contact material 132 and the second two-dimensional carrier gas 112.

[0033] In one embodiment, the first contact material 132 includes a doped semiconductor material such as p-type GaN. The material may be appropriately doped to provide a low energy barrier (e.g., no greater than 0.2 eV) to the majority carriers of the two-dimensional carrier gas 112. The low energy barrier allows the majority carriers of the two-dimensional carrier gas 112 to pass through the interface between the channel layer 108 and the first contact material 132 (e.g., via thermal electron emission).

[0034] In another embodiment, the first contact material 132 includes a conductive metal such as tungsten, aluminum, copper, titanium, titanium nitride, etc., and alloys thereof. The non-rectifying junction between the second two-dimensional carrier gas 112 and the first contact material 132 can be achieved by selecting a material that minimizes the barrier width and / or barrier height so that the majority carriers of the two-dimensional carrier gas 112 can pass through the interface (e.g., via thermal electron emission or tunneling).

[0035] The first contact material 132 of the deep contact structure 130 is electrically connected to the second input-output electrode 120. In the depicted embodiment, the deep contact structure 130 further includes: a first conductive region 134, which is formed on top of the first contact material 132 and is in direct contact with the second input-output electrode 120, thus providing an electrical connection between the deep contact structure 130 and the first contact material 132. The first conductive region 134 may include a metal (e.g., aluminum, nickel, copper, titanium, alloys thereof), a metal nitride (e.g., AlN, TiN), and a highly doped semiconductor (e.g., polysilicon). More generally, the first contact material 132 may be electrically connected to the second input-output electrode 120 in any conventionally known manner, and may optionally directly contact the second input-output electrode 120.

[0036] The inventors have studied the impact of the deep contact structure 130 as compared to various corresponding device designs that do not include the deep contact structure 130. That is, the inventors compared the impact of setting the potential of the secondary two-dimensional carrier gas(es) to a fixed potential to allow the secondary two-dimensional carrier gas(es) to electrically float. In each device comparison, including the deep contact structure 130 beneficially reduced the dynamic drain-source on-resistance (R DSON This is due to the fact that, among other things, the deep contact structure 130 provides a source / sink for free carriers in the back barrier region 104 to escape during switching of the device.

[0037] Reference Figure 2 , a semiconductor device 100 is depicted according to another embodiment. In the exception case of a configuration with a back barrier region 104, Figure 2 The semiconductor device 100 is similar to the reference Figure 1The semiconductor device 100 described is the same as described above. In this embodiment, the back barrier region 104 is a graded back barrier region. The back barrier region 104 can be similar to or the same as the graded back barrier region described in Curatola's U.S. application 15 / 352,115. According to the design, the back barrier region 104 includes: a first back barrier region 103 directly below the channel region 106, and a second back barrier region 105 below the first back barrier region 103. The first and second back barrier regions 103, 105 are both regions of III-V type semiconductor materials having band gaps different from each other. For example, the first back barrier region 103 can be a first layer of AlGaN, and the second back barrier region 105 can be a second layer of AlGaN having a higher aluminum content than the first back barrier region 103. A deliberately doped region of AlGaN (e.g., a carbon-doped AlGaN region) (not shown) can be provided below the second back barrier region 105. Due to the material configuration of the first and second back barrier regions 103, 105, two types of carrier gases are formed. The second two-dimensional carrier gas 112 is formed near the interface between the channel region 106 and the first back barrier region 103. The third two-dimensional carrier gas 113 is formed near the interface between the first back barrier region 103 and the second back barrier region. Due to the material properties of the first and second back barrier regions 103, 105, the second two-dimensional carrier gas 112 is mostly depleted, while the third two-dimensional carrier gas 113 contains the majority of free carriers in the back barrier region 104.

[0038] In this embodiment, the deep contact structure 130 is configured such that the first contact material 132 extends through the back barrier region 104 to reach the third two-dimensional carrier gas 113. In this way, the dynamic drain-source on-resistance (R DSON ) a beneficial reduction in performance.

[0039] Reference Figure 3 , a semiconductor device 100 is depicted according to another embodiment. With the following differences, Figure 3 The semiconductor device 100 is similar to the reference Figure 1 The semiconductor device 100 described above is the same as that described above. Figure 3 In the semiconductor device 100, the barrier layer 108 is modified to include a thinner portion 136 and a thicker portion 138. Second, Figure 3 The semiconductor device 100 includes: a drain bias structure 140 between the gate structure 122 and the first input-output electrode 118. Figure 3 In the semiconductor device 100 , the second input-output electrode 120 extends across the channel and the gate structure 122 to form a field plate structure.

[0040] The thinner portion 136 and the thicker portion 138 of the barrier layer 108 are laterally adjacent to each other with a transition 142 provided between the thicker portion 136 and the thinner portion 138. The thinner portion 136 has a first thickness and the thicker portion 138 has a second thickness greater than the first thickness. The thickness of the thinner portion 136 and the thicker portion 138 is measured between a lower surface 144 of the barrier layer 108 facing the channel layer 106 and an upper surface 146 of the barrier layer 108 opposite to the lower surface 144. For example, an exemplary thickness value of the second thickness (i.e., the thickness of the thinner portion 136) can be in the range of 5-20 nanometers. For example, an exemplary thickness value of the second thickness (i.e., the thickness of the thicker portion 138) can be in the range of 20-50 nanometers. According to an embodiment, one or both of the thinner portion 136 and the thicker portion 138 have a substantially uniform thickness along the entire lateral span of these regions. That is, the upper surface 146 of the barrier layer 108 extends parallel to the lower surface 144 of the barrier layer 108 in one or both of the thinner portion 136 and the thicker portion 138. At the transition 142, the upper surface 146 of the barrier layer 108 is arranged at an oblique angle relative to the immediately adjacent upper surface 146 of the barrier layer 108 in the thinner portion 136. The oblique angle can be a perpendicular angle (i.e., as depicted), or more generally, can be any oblique angle (e.g., 30 degrees, 45 degrees, 60 degrees, etc.).

[0041] The gate structure 122 is formed on the thinner portion 136 of the barrier layer 108 at a location that is laterally spaced from a transition 142 between the thicker portion 136 and the thinner portion 138. The first input-output electrode 118 is formed on the thicker portion 138 of the barrier layer 108 and may also be laterally spaced from the transition 142 between the thicker portion 136 and the thinner portion 138. In the depicted embodiment, the second input-output electrode 120 is formed on the second thicker portion 148 of the barrier layer 108, and the second input-output electrode 120 has the same thickness as the thicker portion 138 of the barrier layer 108 (i.e., the region on which the first input-output electrode 118 is formed). In other embodiments, the second thicker portion 138 may have a third thickness that is different from the second thickness and greater than the first thickness. In yet other embodiments, the second input-output electrode 120 may be formed on the thinner portion 136 of the barrier layer 108. That is, both the gate structure 122 and the second input-output electrode 120 may be formed on the same thinner portion 136 of the barrier layer 108 .

[0042] Structuring the barrier layer 108 in the manner described above to include a thinner portion 136 and a thicker portion 138, and laterally positioning the gate structure 122, the first input-output electrode 118, and the second input-output electrode 120, produces a device having advantageous properties. By providing the gate structure 122 on the thinner portion 136, the gate structure 122 is formed on a portion of the barrier layer 108 that has a reduced carrier density in the underlying first two-dimensional carrier gas 110. Thus, by setting the thickness of the thinner region 136 and the thicker region 138, the threshold voltage (V TH ) and drain-source on-resistance (R DSON ). In addition, due to the reduced carrier density of the first two-dimensional carrier gas 110, the reliability of the device is improved because the gate structure 122 is exposed to a lower electric field.

[0043] The drain biasing structure 140 is formed on the thicker portion 138 of the barrier layer 108 between the transition 142 and the first input-output electrode 118. The drain biasing structure 140 includes: a third semiconductor region 150 formed on an upper surface 146 of the barrier layer 108. The third semiconductor region 150 may include a semiconductor material of the same type and doping concentration as the second semiconductor region 132 and the first contact material 124 (e.g., p-type GaN). The drain biasing structure 140 additionally includes a conductive connection between the third semiconductor region 150 and the first input-output electrode 118. Therefore, the third semiconductor region 150 is set to the same potential (e.g., drain potential) as the first input-output electrode 118. In the depicted embodiment, the drain biasing structure 140 includes a third conductive region 152 formed on top of the third semiconductor region 150. The third conductive region 152 may include a metal (e.g., aluminum, nickel, copper, titanium, alloys thereof), a metal nitride (e.g., AlN, TiN), and a highly doped semiconductor (e.g., polysilicon). In the depicted embodiment, the first input-output electrode 118 is formed on a portion of the third conductive region 152, a portion of which is exposed from the first dielectric layer 128 and thus directly contacts the third conductive region 152. Thus, electrical connection between the third semiconductor region 150 and the first input-output electrode 118 is provided by the third conductive region 152. More generally, the third semiconductor region 150 may be electrically connected to the first input-output electrode 118 in any conventionally known manner, and may optionally directly contact the first input-output electrode 118.

[0044] During operation of the semiconductor device 100, the drain bias structure 140 injects holes into the barrier layer 108 and the channel layer 106. In doing so, dynamic switching losses caused by charge trapping and / or lattice defects are mitigated.

[0045] Reference Figure 4-10 , showing selected process steps for forming a semiconductor device 100 according to an embodiment. In combination with conventionally known processing methods (not shown), these steps can be used to form a semiconductor device 100 according to reference Figure 1-3 The semiconductor device 100 of any one of the described embodiments.

[0046] Reference Figure 4 , a heterostructure semiconductor body 102 is provided. According to an embodiment, the heterostructure semiconductor body 102 is formed using an epitaxial growth technique. According to the process, a base substrate 116 is initially provided. The base substrate 116 may be provided by a commercially available batch wafer (e.g., a silicon wafer), or alternatively, may be provided by an epitaxially grown material. After providing the base substrate 116, a nucleation layer (not shown) may be formed on the base substrate 116. The nucleation layer may be a thin (e.g., in the range of tens to hundreds of nanometers) material layer that is conducive to the growth of III-V type semiconductors thereon. An example of such a material is AlN (aluminum nitride). After the nucleation layer is formed, the transition region 114, the back barrier region 104, the channel layer 106, and the barrier layer 108 may all be sequentially formed using an epitaxial deposition technique. During the epitaxial deposition of these layers, the metal content and / or doping concentration of each of these layers may be controlled to achieve the values ​​previously described. After completing any of the transition region 114 , the back barrier region 104 , the channel layer 106 , and the barrier layer 108 , additional doping steps may be performed.

[0047] During the epitaxial growth process described above, the barrier layer 108 is grown with a uniform thickness. Subsequently, further processing steps are performed to structure the barrier layer 108 to have a thinner portion 136 and a thicker portion 138.

[0048] According to one embodiment, further processing steps performed to construct the barrier layer 108 to have a thinner portion 136 and a thicker portion 138 include: a mask etching sequence. According to the technique, the barrier layer 108 is initially formed to have a thickness corresponding to a first thickness (e.g., between about 10-50 nm). A first mask (not shown) is formed on the upper surface 146 of the barrier layer 108. The first mask is patterned (e.g., using known photolithography techniques) with the desired geometry of the thicker portion 138. The material of the first mask is configured to allow etching of the barrier layer 108 to be selective to the first mask. Exemplary materials for the first mask include silicon nitride (SiN), silicon dioxide (SiO2), and silicon oxynitride (SiO x N y), or more generally, any of a variety of photoresist materials, to name a few. After patterning the first mask, an etching process is performed to remove semiconductor material from the portions of barrier layer 108 exposed from the first mask. According to an embodiment, an anisotropic etching process (e.g., an anisotropic wet chemical etching process) is used to remove the semiconductor material. The etching process is performed until the etched area has a second thickness (e.g., between 5 and 20 nm).

[0049] According to another embodiment, further processing steps performed to construct the barrier layer 108 to have a thinner portion 136 and a thicker portion 138 include a two-step epitaxial growth process. According to this technique, the barrier layer 108 initially formed has a second thickness (e.g., between 5 and 10 nm). Subsequently, a mask is formed on the upper surface 146 of the barrier layer 108 and patterned to cover the desired area of ​​the thinner portion 136. The mask is formed of an epitaxial growth inhibiting material such as, for example, silicon dioxide (SiO2). Subsequently, an epitaxial deposition process is performed, thereby forming the same material as the barrier layer 108 (e.g., AlGaN) on the uncovered portion of the barrier layer 108. The epitaxial deposition process is performed until the uncovered portion of the barrier layer 108 has a first thickness.

[0050] Reference Figure 5 After the heterostructure semiconductor body 102 has been provided, a contact trench 154 for the deep contact structure 130 is formed. According to an embodiment, a mask etching technique is used to form the contact trench 154. According to this technique, a second mask 156 is formed on the upper surface 146 of the barrier layer 108. Exemplary materials for the second mask 156 include silicon nitride (SiN), silicon dioxide (SiO2), and silicon oxynitride (SiO x N y ), or more generally, any of a variety of photoresist materials, to name a few. The second mask 156 is patterned with the desired geometry of the deep contact structure 130. After patterning the second mask 156, an etching process is performed to remove semiconductor material from portions of the barrier layer 108 and the channel layer 110. The etching process is performed until the contact trench 154 reaches the back barrier region 104.

[0051] Reference Figure 6, after forming the contact trench 154 and removing the second mask 156, a multilayer deposition step is performed. According to the process, a first layer of doped semiconductor material 158 is formed on the exposed surface of the heterostructure semiconductor body 102. This can be done using an epitaxial growth process. The first layer of doped semiconductor material 158 has a doping type opposite to the majority carriers of the first two-dimensional carrier gas 110 and a doping type the same as the majority carriers of the second two-dimensional carrier gas 112. For example, in the case of the AlGaN / GaN / AlGaN heterostructure semiconductor body 102 as described previously, the first layer of doped semiconductor material 158 includes p-type GaN. The first layer of doped semiconductor material 158 is grown so that it completely fills the contact trench 154 and covers the upper surface 146 of the barrier layer 108, which includes a thinner portion 136, a thicker portion 138 and a transition 142. The first layer of doped semiconductor material 158 may have a total (net) doping concentration of approximately 1e 19 / cm 3 , where the concentration of the first conductivity type (eg, p-type) dopant is between 1e 19 / cm 3 to about 1e 17 / cm 3 within the range.

[0052] After forming the first layer of doped semiconductor material 158, a first conductive layer 160 is formed on top of the first layer of doped semiconductor material 158. This can be done using deposition techniques such as electroless deposition or electroplating. The material of the first conductive layer 160 corresponds to the material of the first conductive region 134, the second conductive region 126, and the third conductive region 152 as previously described, i.e., aluminum, nickel, copper, titanium, etc., metal nitrides (e.g., AlN, TiN, etc.) and alloys thereof.

[0053] Reference Figure 7 After forming the first layer of doped semiconductor material 158 and the first conductive layer 160, a common photolithography process is performed to structure the first layer of doped semiconductor material 158 and the first conductive layer 160 into discrete regions. According to the technique, a third mask (not shown) is formed over the first conductive layer 160 and patterned with the desired geometry of the gate structure 122, the drain bias structure 140, and the deep contact structure 130. Subsequently, an etching process is performed, whereby the portions of the first layer of doped semiconductor material 158 and the first conductive layer 160 exposed from the third mask are etched away. The etching process may be a multi-step process, whereby different etchant chemistries are used to remove the first layer of doped semiconductor material 158 and the first conductive layer 160. As a result, the upper surface 146 of the barrier layer 108 between the gate structure 122, the drain bias structure 140, and the deep contact structure 130 is exposed.

[0054] Reference Figure 8 After constructing the first layer of doped semiconductor material 158 and the first conductive layer 160, a first dielectric layer 128 is formed. For example, this can be done using a deposition technique such as chemical vapor deposition (CVD). The first dielectric layer 128 is conformally deposited so as to cover the gate structure 122, the drain bias structure 140, and the deep contact structure 130, as well as the exposed upper surface 146 of the barrier layer 108 between these structures.

[0055] Reference Fig. 9 , after forming the first dielectric layer 128, the first dielectric layer 128 is patterned to include first, second, third and fourth openings 162, 164, 166, 168. This can be done using a mask etching technique, whereby a fourth mask (not shown) is provided over the first dielectric layer 128 and patterned with a desired geometry including the first, second, third and fourth openings 162, 164, 166, 168. Subsequently, the exposed material of the first dielectric layer 128 is etched away. The first opening 162 is formed directly over the deep contact structure 130. The second opening 164 exposes the upper surface 146 of the barrier layer 108 between the deep contact structure 130 and the gate structure 122. The third opening 166 is formed to partially overlap the drain bias structure 140 so as to expose a portion of the upper surface of the third conductive region 152 and a portion of the heterostructure semiconductor body 102 that is immediately adjacent to the drain bias structure 140. The fourth opening 168 exposes the upper surface 146 of the barrier layer 108 at a location near the drain bias structure 140 .

[0056] Reference Fig.10 , a second conductive layer 170 is formed on the patterned first dielectric layer 128. This can be accomplished using any of a variety of deposition techniques, including electroplating, electroless deposition, and epitaxy. The material of the second conductive layer 170 may include metals (e.g., nickel, copper, titanium, alloys thereof), metal nitrides (e.g., AlN, TiN), and highly doped semiconductors (e.g., polysilicon).

[0057] Thus, the first input-output electrode 118 and the second input-output electrode 120 are formed. The first input-output electrode 118 and the second input-output electrode 120 contact the third conductive region 152 and the first conductive region 134, respectively, and thus form a direct electrical connection therebetween. By forming another opening (not shown) in another cross-sectional area of ​​another cross-sectional view and depositing the second conductive layer 170 in the other opening, a gate connection pad can be formed by the second conductive layer 170.

[0058] Reference Figure 4-10 The described technique illustrates the use of the reference Figure 31 and 1 , and the semiconductor device 100 includes a structured barrier layer having a thinner portion 136 and a thicker portion 138. A corresponding semiconductor device 100 does not include any one or both of these features and can be implemented by omitting the relevant steps (e.g., referring to Figure 3 ) and / or by appropriately performing lithography steps for omitting these structures (e.g., referring to Figure 6 1 and 2) to form a corresponding semiconductor device 100 that does not include either or both of these features.

[0059] The processing steps described above advantageously provide a reliable and cost-effective method for forming the semiconductor device 100. One particular advantage of the method is that it reduces process complexity by forming several of the device features together using common lithography steps. In particular, as described with reference to Figure 6-7 As described, the deep contact structure 130, the gate structure 122, and the drain bias structure 140 are formed by a common process, whereby a single layer of doped III-V type semiconductor material and a single layer of conductive material are used to form the doped semiconductor region and the metal region for each of these structures, respectively, and a single mask is used to define each of these features.

[0060] In the embodiments described above, the transition region 114, the back barrier region 104, the channel layer 106 and the barrier layer 108 are described as regions of AlGaN, AlGaN, AlGaN and AlGaN, respectively. These materials are for illustrative purposes only. More generally, any combination of various combinations of III-V semiconductor materials can be used to provide the device concepts described herein. Examples of these III-V semiconductor materials for these regions include any III-nitride-based compound semiconductor materials. For example, GaN can be combined with AlGaN or InGaN to form an electron gas inversion region as a channel. The semiconductor device 100 can have an AlInN / AlN / GaN barrier / spacer / channel layer structure. In general, the normally-off compound semiconductor transistor can be implemented using any suitable III-nitride technology, such as GaN, which allows the formation of opposite polarity inversion regions caused by the piezoelectric effect. In a broad sense, the compound semiconductor transistors described herein may be formed from any binary, ternary or quaternary Group III-nitride compound semiconductor material in which the piezoelectric effect is responsible for the device concept.

[0061] The term HEMT is also commonly referred to as HFET (heterostructure field effect transistor), MODFET (modulation doped FET), and MESFET (metal semiconductor field effect transistor). The terms HEMT, HFET, MESFET, and MODFET are used interchangeably herein to refer to any III-nitride-based compound semiconductor transistor that contains a junction between two materials with different band gaps (i.e., a heterojunction) as a channel.

[0062] As used in this specification, the terms "coupled" and / or "electrically coupled" do not mean that elements must be directly coupled together - intermediate elements may be provided between the "coupled" or "electrically coupled" elements. The term "electrically connected" is intended to describe a low-ohmic electrical connection between elements that are electrically connected together, for example, a connection via metal and / or highly doped semiconductors.

[0063] As used herein, the terms "having," "comprising," "including," "consisting of," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0064] In view of the above range of variations and applications, it should be understood that the present invention is not limited to the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the appended claims and their legal equivalents.

Claims

1. A method for forming a semiconductor device, the method comprising: A heterojunction semiconductor body is provided, wherein the heterojunction semiconductor body comprises: III-V type semiconductor back barrier region; A III-V type semiconductor channel layer formed on the back barrier region and having a band gap different from that of the back barrier region; a III-V type semiconductor barrier layer formed on the channel layer and having a band gap different from that of the channel layer; A first two-dimensional carrier gas formed at an interface between the channel and the barrier layer; and a second two-dimensional carrier gas disposed below the first two-dimensional carrier gas; forming a deep contact structure in the heterojunction semiconductor body, the deep contact structure extending through the channel layer and comprising a first contact material, the first contact material forming a direct interface with the second two-dimensional carrier gas, The first contact material provides a conductive path for majority carriers of the second two-dimensional carrier gas to pass through a direct interface between the first contact material and the second two-dimensional carrier gas.

2. The method according to claim 1, further comprising: forming first and second conductive input-output electrodes on the heterojunction semiconductor body, the first and second input-output electrodes both being in ohmic contact with the first two-dimensional carrier gas; as well as forming a gate structure on the heterojunction semiconductor body, the gate structure being configured to control a conductive connection between the first and second input-output electrodes, Wherein, the first contact material of the deep contact structure is directly electrically connected to the second input-output electrode.

3. The method according to claim 2, wherein the gate structure comprises: A second semiconductor region is formed on an upper surface of the barrier layer, and a conductive gate electrode is formed on the second semiconductor region, wherein the second semiconductor region is configured to locally deplete the first two-dimensional carrier gas so that the semiconductor device is normally off.

4. The method according to claim 3, wherein the back barrier region and the barrier layer both comprise aluminum gallium nitride, wherein the channel layer comprises gallium nitride, wherein the first two-dimensional carrier gas is a two-dimensional electron gas, wherein the second two-dimensional carrier gas is a two-dimensional hole gas, and wherein the first contact material is p-type gallium nitride. The method according to claim 3 , wherein the first contact material of the deep contact structure comprises a conductive metal. The method of claim 3 , wherein the first contact material of the deep contact structure comprises a doped first semiconductor material. 7 . The method according to claim 6 , wherein the first contact material of the deep contact structure and the second semiconductor region are formed together by a first layer of first semiconductor material which is deposited on the heterojunction semiconductor body and subsequently patterned in a common lithography step.

8. The method of claim 7, further comprising forming a drain bias structure, the drain bias structure comprising: a third semiconductor region arranged on an upper surface of the barrier layer between the gate structure and the first input-output electrode; and a conductive connection between the third semiconductor region and the first input-output electrode, wherein the third semiconductor region is formed by the first layer of first semiconductor material together with the first contact material of the deep contact structure and the second semiconductor region, the first layer of first semiconductor material being epitaxially grown on the heterojunction semiconductor body and subsequently patterned in a common lithography step.

9. The method according to claim 1, wherein the III-V type semiconductor back barrier region comprises: A first back barrier region and a second back barrier region, wherein the first back barrier region is formed directly below the III-V type semiconductor channel layer, and the second back barrier region is formed below the first and second back barrier regions, wherein a third two-dimensional carrier gas is formed near an interface between the first and second back barrier regions, and wherein the deep contact structure forms an interface with the third two-dimensional carrier gas.

10. The method according to claim 2, wherein the barrier layer comprises: a thicker portion and a thinner portion, wherein the gate structure is formed on the thinner portion, wherein the first input-output electrode is formed on the thicker portion, and wherein the gate structure is laterally spaced apart from a transition between the thicker and thinner portions.

11. A semiconductor device comprising: A heterojunction semiconductor body, wherein the heterojunction semiconductor body comprises: III-V type semiconductor back barrier region; A III-V type semiconductor channel layer formed on the back barrier region and having a band gap different from that of the back barrier region; a III-V type semiconductor barrier layer formed on the channel layer and having a band gap different from that of the channel layer; A first two-dimensional carrier gas formed at an interface between the channel and the barrier layer; and a second two-dimensional carrier gas disposed below the first two-dimensional carrier gas; a deep contact structure formed in the heterojunction semiconductor body, the deep contact structure extending through the channel layer and comprising a first contact material, the first contact material forming a direct interface with the second two-dimensional carrier gas, The first contact material provides a conductive path for majority carriers of the second two-dimensional carrier gas to pass through a direct interface between the first contact material and the second two-dimensional carrier gas. 12 . The semiconductor device of claim 11 , wherein the first contact material is a doped III-V type semiconductor material, wherein a majority carrier type of the doped III-V type semiconductor material is the same as a majority carrier type of the second two-dimensional carrier gas.

13. The semiconductor device of claim 12, wherein the back barrier region and the barrier layer comprise aluminum gallium nitride, wherein the channel layer comprises gallium nitride, wherein the first two-dimensional carrier gas is a two-dimensional electron gas, wherein the second two-dimensional carrier gas is a two-dimensional hole gas, and wherein the doped III-V type semiconductor material is p-type gallium nitride.

14. The semiconductor device according to claim 12, further comprising: first and second input-output conductive electrodes on the heterojunction semiconductor body, the first and second input-output electrodes both being in ohmic contact with the first two-dimensional carrier gas; as well as a gate structure on the heterojunction semiconductor body, the gate structure being configured to control a conductive connection between the first and second input-output electrodes, Wherein, the first semiconductor region of the deep contact structure is directly electrically connected to the second input-output electrode.

15. The semiconductor device according to claim 14, wherein the gate structure comprises: A second semiconductor region is formed on the upper surface of the barrier layer, and a conductive gate electrode is formed on the second semiconductor region, wherein the second semiconductor region is configured to locally deplete the first two-dimensional carrier gas so as to prevent a conductive connection between the first and second input-output electrodes in the absence of any bias applied to the gate electrode, and wherein the second semiconductor region comprises a doped III-V type semiconductor material. 16 . The semiconductor device according to claim 11 , wherein the first contact material of the deep contact structure comprises a conductive metal.

17. The semiconductor device according to claim 11, wherein the III-V type semiconductor back barrier region comprises: A first back barrier region and a second back barrier region, wherein the first back barrier region is formed directly below the III-V type semiconductor channel layer, and the second back barrier region is formed below the first and second back barrier regions, wherein a third two-dimensional carrier gas is formed near an interface between the first and second back barrier regions, and wherein the deep contact structure forms an interface with the third two-dimensional carrier gas.

18. The semiconductor device according to claim 14, wherein the barrier layer comprises: a thicker portion and a thinner portion, wherein the gate structure is formed on the thinner portion, wherein the first input-output electrode is formed on the thicker portion, and wherein the gate structure is laterally spaced apart from a transition between the thicker and thinner portions.

19. A semiconductor device comprising: A heterojunction semiconductor body, comprising: a III-V type semiconductor back barrier region, a III-V type semiconductor channel layer formed on the back barrier region, and a III-V type semiconductor barrier layer formed on the channel layer, a two-dimensional electron gas formed at an interface between the barrier and the channel layer, and a two-dimensional hole gas formed at an interface between the channel and the back barrier region. A conductive source electrode and a drain electrode formed on the heterojunction semiconductor body and in ohmic contact with the two-dimensional electron gas; a gate structure formed on the heterojunction semiconductor body and configured to control a conductive connection between the source electrode and the drain electrode by controlling a conductive state of the two-dimensional electron gas; A deep contact structure is formed in the heterojunction semiconductor body, wherein the deep contact structure provides an electrical connection that sets the potential of holes in the two-dimensional hole gas to the potential of the source electrode.

20. The semiconductor device according to claim 19, wherein the source electrode is in ohmic contact with the two-dimensional electron gas, and wherein the deep contact structure comprises: A semiconductor region is bonded to the two-dimensional electron gas and is electrically connected to the source electrode.

21. The semiconductor device according to claim 19, wherein the source electrode is in ohmic contact with the two-dimensional electron gas, and wherein the deep contact structure comprises: A conductive metal bonded to the two-dimensional electron gas and electrically connected to the source electrode.

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