Semiconductor Package

Abstract

The present invention provides a semiconductor package. The semiconductor package includes a semiconductor package substrate. An insulating layer is disposed on the semiconductor package substrate. A semiconductor chip is disposed on the semiconductor package substrate and covered by the insulating layer. A reflective layer is disposed on the insulating layer and is spaced apart from the semiconductor chip. The reflective layer is configured to selectively transmit radiation to the insulating layer. A protective layer is disposed on the reflective layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0029714 filed on March 14, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a reflective layer having selective transmittance. Background Art

[0004] During the manufacturing process, semiconductor devices are subjected to defect inspection procedures to detect any potential defects in the device. X-rays are usually used in the defect inspection process. However, X-ray exposure itself may degrade the characteristics of semiconductor devices due to charge leakage.

[0005] X-rays used for defect inspection may include hard X-rays with shorter wavelengths and energies greater than 10 keV and soft X-rays with longer wavelengths and energies typically in the range of 100 eV to 10 keV. Summary of the invention

[0006] A semiconductor package includes a semiconductor package substrate. An insulating layer is disposed on the semiconductor package substrate. A semiconductor chip is disposed on the semiconductor package substrate and covered by the insulating layer. A reflective layer is disposed on the insulating layer and is spaced apart from the semiconductor chip. The reflective layer is configured to selectively transmit radiation to the insulating layer. A protective layer is disposed on the reflective layer.

[0007] The semiconductor package includes a semiconductor package substrate. A molding layer is disposed on the semiconductor package substrate. A semiconductor chip is disposed on the semiconductor package substrate and covered by the molding layer. The semiconductor package is configured to be more transmissive to hard X-rays than to soft X-rays.

[0008] The semiconductor package comprises a semiconductor package substrate. An insulating layer is arranged on the semiconductor package substrate. A semiconductor chip is arranged on the semiconductor package substrate and covered by the insulating layer. A reflective layer is arranged on the insulating layer and is spaced apart from the semiconductor chip, and the reflective layer comprises a metal material with an atomic number greater than 12. A protective layer is arranged on the reflective layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0010] Figure 1is a perspective view showing a semiconductor package according to some exemplary embodiments of the inventive concept;

[0011] Figure 2 is along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0012] Figure 3 is a diagram illustrating auxiliary films 131 and 133 included in a semiconductor package according to some exemplary embodiments of the inventive concept;

[0013] Figure 4 is a graph showing materials of a reflective layer 131 included in a semiconductor package according to some exemplary embodiments of the inventive concept;

[0014] Figure 5 is a diagram illustrating auxiliary films 131 and 133 included in a semiconductor package according to some exemplary embodiments of the inventive concept;

[0015] Figure 6 is along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0016] Figure 7 is along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0017] Figure 8 , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig. 11C , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 are cross-sectional views of semiconductor packages according to some exemplary embodiments of the inventive concept, respectively; and

[0018] Figures 17 to 27 1 is a diagram illustrating an intermediate stage of a method of manufacturing a semiconductor package according to some exemplary embodiments of the inventive concept. DETAILED DESCRIPTION

[0019] The following will refer to Figures 1 to 5 Semiconductor packages according to some exemplary embodiments of the inventive concept are described.

[0020] Figure 1 is a perspective view illustrating a semiconductor package according to some exemplary embodiments of the inventive concept. Figure 2 is along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0021] refer to Figure 1 and Figure 2 , a semiconductor package according to some exemplary embodiments of the inventive concept may include a semiconductor package substrate 101, an external connection terminal 103, a semiconductor chip 110, and a molding layer. The molding layer may include an insulating layer 121 and an auxiliary film. The auxiliary film may include a reflective layer 131 and a first protective layer 133.

[0022] The semiconductor package substrate 101 may be a package substrate, and may be, for example, a printed circuit board (PCB) or a ceramic substrate. In some exemplary embodiments of the present inventive concept, the semiconductor package substrate 101 may be a wafer, a bare silicon (Si) chip, or a silicon interposer.

[0023] The semiconductor package substrate 101 may include an upper surface 101U and a lower surface 101L facing each other. The semiconductor chip 110 may be mounted on the upper surface 101U of the semiconductor package substrate 101. For example, the external connection terminal 103 may be attached to the lower surface 101L of the semiconductor package substrate 101. In the accompanying drawings, the external connection terminal 103 is illustrated as having seven parts, but the technical concept of the inventive concept is not limited thereto, and the number of external connection terminals 103 is illustrated as a simple example of the intended structure. For example, the external connection terminals 103 attached to the lower surface 101L of the semiconductor package substrate 101 may be less than seven or more than seven.

[0024] The external connection terminal 103 may be a conductive ball or a solder ball, but the technical concept of the inventive concept is not limited thereto. The external connection terminal 103 may be, for example, a conductive bump, a conductive spacer, or a pin grid array (PGA). The semiconductor package may be electrically connected to an external device, for example, through the external connection terminal 103.

[0025] The semiconductor chip 110 may be mounted on the semiconductor package substrate 101. The lower surface of the semiconductor chip 110 may be a semiconductor element circuit region 111. The semiconductor chip 110 may be in the form of, for example, a flip chip. However, the technical concept of the inventive concept is not limited thereto. For example, the semiconductor chip 110 may be mounted on the semiconductor package substrate 101 in various ways (for example, by wire bonding). Figure 7 This is described in detail.

[0026] The semiconductor chip 110 may be, for example, a memory chip, a logic chip, etc. Although the figure shows that one semiconductor chip 110 is mounted on the semiconductor package substrate 101, the technical concept of the inventive concept is not limited thereto. For example, a plurality of semiconductor chips may be mounted side by side and / or stacked on the semiconductor package substrate 101.

[0027] The first connection element 113 may be provided in the semiconductor element circuit region 111. The first connection element 113 may be, for example, a solder ball or a conductive bump.

[0028] The semiconductor chip 110 can be electrically connected to the semiconductor package substrate 101 through the first connection element 113. In the accompanying drawings, although nine first connection elements 113 are shown, the technical concept of the present invention is not limited thereto. For example, the first connection element 113 may have less than nine or more than nine parts, and the number of first connection elements 113 is illustrated as a simple example of the expected structure. The first connection element 113 can be connected to, for example, a silicon through-hole (TSV, through silicon vias) that runs through the semiconductor chip 110.

[0029] The insulating layer 121 may be disposed on the semiconductor package substrate 101. For example, the insulating layer 121 may be disposed on the upper surface 101U of the semiconductor package substrate 101 so as to completely cover the upper surface 101U of the semiconductor package substrate 101. For example, the upper surface 101U of the semiconductor package substrate 101 may be covered by the insulating layer 121 so as not to be exposed.

[0030] For example, the insulating layer 121 may completely fill the space between the semiconductor chip 110 and the upper surface 101U of the semiconductor package substrate 101. The insulating layer 121 may completely surround the side surface of the semiconductor chip 110. The insulating layer 121 may completely cover the upper surface of the semiconductor chip 110. Therefore, the semiconductor chip 110 may be buried inside the insulating layer 121.

[0031] The insulating layer 121 may have a certain height from the upper surface 101U of the semiconductor package substrate 101. For example, a portion of the insulating layer 121 may be disposed on the semiconductor chip 110. For example, with the upper surface 101U of the semiconductor package substrate 101 as a reference, the height of the insulating layer 121 may be greater than the height of the upper surface of the semiconductor chip 110. Here, the upper surface of the semiconductor chip 110 may be an opposite side surface of the semiconductor element circuit region 111, and the upper surface of the semiconductor chip 110 faces the semiconductor element circuit region 111.

[0032] In some exemplary embodiments of the present inventive concept, the insulating layer 121 may include, for example, an insulating material that insulates the semiconductor chip 110 from other constituent elements. In some exemplary embodiments of the present inventive concept, the insulating layer 121 may be, for example, an epoxy mold compound (EMC).

[0033] A reflective layer 131 and a first protective layer 133 (hereinafter also referred to as auxiliary films 131 and 133) may be disposed on the insulating layer 121. The auxiliary films 131 and 133 may be spaced apart from the semiconductor chip 110. In some exemplary embodiments of the present inventive concept, the auxiliary films 131 and 133 may selectively transmit radiation to the auxiliary films 131 and 133 and allow the radiation to enter the insulating layer 121.

[0034] The reflective layer 131 may be disposed on the insulating layer 121 and spaced apart from the semiconductor chip 110. With the upper surface 101U of the semiconductor package substrate 101 as a reference, the lower surface of the reflective layer 131 may be higher than the upper surface of the semiconductor chip 110. The reflective layer 131 may completely cover the upper surface of the insulating layer 121. Due to the presence of the reflective layer 131, the insulating layer 121 is not exposed.

[0035] The reflective layer 131 may be in the form of a flat plate material or a thin foil, for example. The reflective layer 131 may be in the form of a metal plate material or a metal foil, for example.

[0036] The first protective layer 133 may be disposed on the reflective layer 131. The first protective layer 133 may completely cover the upper surface of the reflective layer 131. Due to the presence of the first protective layer 133, the reflective layer 131 is not exposed.

[0037] In some exemplary embodiments of the present inventive concept, the first protective layer 133 may include, for example, the same material as that included in the insulating layer 121. Alternatively, the first protective layer 133 may include, for example, a metal oxide.

[0038] The reflective layer 131 may selectively transmit radiation to the insulating layer 121. The first protective layer 133 may prevent corrosion of the reflective layer 131. In addition, the first protective layer 133 may prevent the reflective layer 131 from being exposed to lasers used to mark semiconductor packages. A detailed explanation of selective transmission and laser marking will be provided below.

[0039] Figure 3 1 is a diagram illustrating auxiliary films 131 and 133 included in a semiconductor package according to some exemplary embodiments of the inventive concept. Figure 4 is a graph illustrating materials of the reflective layer 131 included in a semiconductor package according to some exemplary embodiments of the inventive concept.

[0040] refer to Figure 3 According to some exemplary embodiments of the inventive concept, the auxiliary films 131 and 133 may selectively transmit radiation radiated to the auxiliary films 131 and 133 to the insulating layer 121 .

[0041] In some exemplary embodiments according to the inventive concept, the transmittance of the reflective layer 131 to soft X-rays (SX) may be lower than the transmittance of the reflective layer 131 to hard X-rays (HX). For example, when X-rays are radiated to the reflective layer 131, the rate at which the soft X-rays (SX) pass through the reflective layer 131 may be lower than the rate at which the hard X-rays (HX) pass through the reflective layer 131.

[0042] In some exemplary embodiments of the present inventive concept, the reflective layer 131 may shield soft X-rays (SX) from among the X-rays radiated into the semiconductor package, and may transmit hard X-rays into the insulating layer 121. For example, the reflective layer 131 shields soft X-rays from among the X-rays incident on and passing through the first protective layer 133, and may transmit hard X-rays (HX) into the insulating layer 121.

[0043] For example, X-rays radiated to the semiconductor package may be incident on the first protective layer 133 and may pass through the first protective layer 133. However, among the X-rays incident on the first protective layer 133 and passing through the first protective layer 133, the soft X-rays (SX) may not be substantially transmitted into the insulating layer 121. For example, the soft X-rays (SX) may not substantially pass through the reflective layer 131. Here, the soft X-rays (SX) may be X-rays having a photon energy in the range of, for example, about 100 eV to about 10000 eV.

[0044] refer to Figure 4 According to some exemplary embodiments of the present inventive concept, the reflective layer 131 may include a metal material having an atomic number greater than 12. For example, the reflective layer 131 may include aluminum, copper, platinum, or nickel.

[0045] In some exemplary embodiments of the present inventive concept, the reflective layer 131 may include a ceramic material or an inorganic material. For example, the reflective layer 131 may include tungsten oxide, zinc oxide, or antimony oxide (SbO2). 2 O 3 ).

[0046] In some exemplary embodiments of the present inventive concept, the reflective layer 131 may include BaSO 4 、(PbCO 3 ) 2 ·Pb(OH) 2 、TiO 2 , ZnS or Al 2 O 3 .

[0047] exist Figure 4In the curve of , the x-axis may represent the photon energy of the X-ray (in arbitrary units (Au)), and the y-axis may represent the X-ray transmittance of the X-ray radiated to the reflective layer 131 (in arbitrary units Au). Figure 4 In the curve of , the X-rays with photon energies within the range of K2[Au] to K4[Au] may be, for example, soft X-rays. For example, the X-rays with photon energies within the range of K4[Au] to K5[Au] may be, for example, hard X-rays.

[0048] The first curve (ga) shows the transmittance of X-rays directly incident on the semiconductor package when the semiconductor package does not include the reflective layer 131 and the insulating layer 121. Referring to the first curve (ga), soft X-rays and hard X-rays can directly pass through the semiconductor package that does not include the reflective layer 131 and the insulating layer 121.

[0049] The second curve (gb) shows the transmittance of X-rays incident on the semiconductor package (e.g., the reflective layer 131) when the semiconductor package includes the insulating layer 121 and the reflective layer 131. The reflective layer 131 may contain magnesium with an atomic number of 12. Referring to the second curve (gb), hard X-rays substantially directly pass through the semiconductor package containing magnesium, and a considerable amount of soft X-rays pass through the semiconductor package. In the case where the reflective layer contains magnesium with an atomic number of 12, charge leakage may occur.

[0050] The third curve (gc) shows the transmittance of X-rays incident on the semiconductor package (e.g., the reflective layer 131) when the semiconductor package includes the insulating layer 121 and the reflective layer 131. The reflective layer 131 may contain aluminum having an atomic number of 13. Referring to the third curve (gc), when the semiconductor package includes the insulating layer 121 and the reflective layer 131 and the reflective layer 131 contains aluminum, the transmittance of soft X-rays becomes lower than when the reflective layer 131 of the semiconductor package contains magnesium.

[0051] The fourth curve (gd) shows the transmittance of X-rays incident on the semiconductor package (e.g., the reflective layer 131) when the semiconductor package includes the insulating layer 121 and the reflective layer 131. The reflective layer 131 may include platinum having an atomic number of 78. Referring to the fourth curve (gd), when the semiconductor package includes the insulating layer 121 and the reflective layer 131 and the reflective layer 131 includes platinum, the transmittance of soft X-rays is substantially close to 0 compared to the case where the reflective layer 131 of the semiconductor package includes aluminum.

[0052] In the semiconductor package according to some exemplary embodiments of the present invention, when the semiconductor package is defect-checked, the X-rays radiated to the semiconductor package can be selectively made to be incident into the semiconductor package. The soft X-rays among the X-rays used for defect inspection of the semiconductor package may degrade the characteristics of the semiconductor chip 110. According to some exemplary embodiments of the present invention, the reflective layer 131 included in the semiconductor package may reduce the transmittance of the soft X-rays or substantially block the transmission of the soft X-rays. Therefore, when the semiconductor package is defect-checked, the problem of degradation of the semiconductor chip 110 that may be caused by the X-rays can be prevented.

[0053] Furthermore, in the semiconductor package according to some exemplary embodiments of the inventive concept, by providing the auxiliary films 131 and 133 on the upper portion of the semiconductor package, the degree of freedom in designing the internal structure of the insulating layer 121 and the semiconductor package may be increased.

[0054] Furthermore, in the semiconductor package according to some exemplary embodiments of the present inventive concept, with the first protection layer 133 included on the reflective layer 131 , it is possible to prevent the reflective layer 131 from being corroded.

[0055] Figure 5 1 is a diagram illustrating auxiliary films 131 and 133 included in a semiconductor package according to some exemplary embodiments of the inventive concept.

[0056] refer to Figure 5 According to some exemplary embodiments of the present inventive concept, when the upper surface of the semiconductor package is laser-marked, a recess 133r is formed in the first protective layer 133. For example, the laser irradiated to the auxiliary films 131 and 133 is not incident on the reflective layer 131. For example, the reflective layer 131 does not transmit the laser irradiated to the first protective layer 133 into the insulating layer 121.

[0057] The recess 133r formed in the first protective layer 133 due to the laser marking may expose the upper surface of the reflective layer 131. In this case, since the first protective layer 133 is formed thick enough for laser marking, the laser is not incident on the reflective layer 131. For example, the laser marking of the semiconductor package may be performed only on the first protective layer 133.

[0058] According to some exemplary embodiments of the present inventive concept, since the semiconductor package includes the first protective layer 133 disposed on the reflective layer 131, corrosion of the reflective layer 131 can be prevented and loss of the reflective layer 131 can be prevented when laser marking is performed. In addition, since laser marking is performed only on the first protective layer 133, the overall thickness of the semiconductor package can be reduced. In addition, since the first protective layer 133 can prevent loss of the insulating layer 121 and can protect the semiconductor chip 110 buried inside the insulating layer 121, etc., the design freedom of the package can be improved.

[0059] Below, we will refer to Figure 6 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0060] Figure 6 is along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0061] refer to Figure 6 In some exemplary embodiments of the present inventive concept, the reflective layer 131' may be a woven metal mesh. In some exemplary embodiments of the present inventive concept, the reflective layer 131' may be a woven metal mesh and may contain a resin. In some exemplary embodiments of the present inventive concept, for example, when the reflective layer 131' is a woven metal mesh containing a resin, for example, the first protective layer 133 may be omitted, and it may be assumed that the omitted description is at least similar to the description of the corresponding element that has been described.

[0062] When the reflective layer 131 ′ is a woven metal mesh, the adhesive force between the insulating layer 121 and the reflective layer 131 ′ may be increased.

[0063] Below, we will refer to Figure 7 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. In the following description, for clear explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements already described.

[0064] Figure 7 is along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0065] refer to Figure 7The semiconductor chip 110 buried inside the insulating layer 121 can be electrically connected to the semiconductor package substrate 101 through the second connection element 115. The semiconductor chip 110 can be mounted on the semiconductor package substrate 101 by, for example, a wire bonding method. The upper surface of the semiconductor chip 110 can be a semiconductor element circuit region 111.

[0066] The second connection element 115 may connect the semiconductor element circuit region 111 of the semiconductor chip 110 and the pad 101 p .

[0067] The pad 101p may be formed on the upper surface 101U of the semiconductor package substrate 101. In the drawings, the upper surface of the pad 101p is illustrated as being on the same plane as the upper surface 101U of the semiconductor package substrate 101, but the technical concept of the inventive concept is not limited thereto. For example, the upper surface of the pad 101p may protrude from the upper surface of the semiconductor package substrate 101.

[0068] The insulating layer 121 may completely fill the gap between the semiconductor chip 110 and the second connecting element 115. The insulating layer 121 may completely cover the second connecting element 115. The semiconductor chip 110 and the second connecting element 115 may be completely buried inside the insulating layer 121.

[0069] Although Figure 7 1 and 2 show that one semiconductor chip is mounted on the semiconductor package substrate 101 , but the technical concept of the inventive concept is not limited thereto. For example, a plurality of semiconductor chips 110 may be mounted on the semiconductor package substrate 101 .

[0070] Below, we will refer to Figure 8 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0071] Figure 8 are diagrams illustrating semiconductor packages according to some exemplary embodiments of the inventive concept. Figure 8 For example, along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0072] refer to Figure 8 According to some exemplary embodiments of the inventive concept, the semiconductor package may include a second protective layer 134. For example, the auxiliary film according to the technical concept of the inventive concept may include a reflective layer 131 and a second protective layer 134.

[0073] The second protective layer 134 may include a thermochromic material and / or a photochromic material. The thermochromic material and / or the photochromic material may include a leuco dye. The thermochromic material is a conjugated system of an electron-donating material or an electron-accepting material that can change structure to develop color at a specific temperature (e.g., room temperature). In some cases, the thermochromic material develops color reversibly and can be induced to develop color irreversibly by a color developer, a sensitizer, or an addition reaction.

[0074] For example, the leuco dye may include a xanthene leuco dye, a thioxanthene leuco dye, an acridine leuco dye, a phenoxazine leuco dye, a phenazine leuco dye, a merocyanine leuco dye, a thiazine leuco dye, an oxazine leuco dye, an azine leuco dye, a methane leuco dye, an azo leuco dye, a pyrazoline ...pyrazoline leuco dye, a thiazine leuco dye, an oxazine leuco dye, Leuco dyes, stilbene leuco dyes, coumarin leuco dyes, triarylmethane leuco dyes, spiropyran leuco dyes, phthalide leuco dyes, fluoran leuco dyes, acyl leuco dyes, auramine leuco dyes, rhodamine-lactam leuco dyes, chromene leuco dyes, quinine leuco dyes, aminohydrocinnamic acid leuco dyes, leuco dyes, 2-(p-hydroxyphenyl)-4,5-diphenylimidazole leuco dyes, indanone leuco dyes, indamine leuco dyes, hydrazine leuco dyes, indigoid leuco dyes, amino-2,3-dihydroanthraquinone leuco dyes, tetrahalo-p,p'-biphenol leuco dyes, phenylethyl aniline leuco dyes or mixtures thereof.

[0075] The second protective layer 134 may further include a color developer for realizing various colors. The color developer may include crystal violet lactone, malachite green lactone, bis-indolyl phthalide dye, diamino fluoran dye, or xanthene dye. By freely adjusting the color of the first protective layer 133 using the color developer, the desired aesthetic feeling may be realized.

[0076] The second protective layer 134 may further include a light stabilizer and / or a sensitizer. The light stabilizer may enhance the stability of the thermochromic material and / or the photochromic material. The sensitizer may adjust the coloring temperature of the second protective layer 134 or improve the color changing efficiency.

[0077] The thermochromic material and / or the photochromic material may have a crystal structure including the first crystal grains 21. The first crystal grains 21 may be uniformly dispersed in the second protective layer 134.

[0078] When the reflective layer 131 and the second protective layer 134 (hereinafter also referred to as auxiliary films 131 and 134) are irradiated with laser 50, the thermochromic material and / or photochromic material under the area irradiated by the laser 50 reacts with the laser, and the color may change. For example, a color-changing grain 22 may be formed from the first grain 21. In this way, a color-changing region (CP) that can be recognized by a user may be formed in the second protective layer 134. From a planar perspective, the color-changing region (CP) may display information such as a semiconductor package. When using the laser 50, the energy of the laser 50 may be transmitted only to a specific area.

[0079] The irradiated laser 50 only causes a reaction in the second protective layer 134 and is reflected by the reflective layer 131 without passing through the second protective layer 134. Therefore, the energy of the laser 50 is not transferred to the insulating layer 121 or the semiconductor chip 110.

[0080] The second protective layer 134 may have a surface gloss caused by, for example, a thermochromic material and / or a photochromic material. Alternatively, the second protective layer 134 may have a gloss on its surface by including a brightener.

[0081] Alternatively, the second protective layer 134 may include a reinforcing agent. When the second protective layer 134 includes a reinforcing agent, the mechanical strength (e.g., tensile strength) of the auxiliary films 131 and 134 may be increased. The reinforcing agent may be, for example, glass fiber. In some exemplary embodiments of the present inventive concept, the auxiliary films 131 and 134 may further include a reinforcing layer for increasing mechanical strength, and the reinforcing layer may include a reinforcing agent.

[0082] In the semiconductor package of some exemplary embodiments of the present invention, by providing the auxiliary films 131 and 134 on the insulating layer 121, the semiconductor chip 110 can be protected and the marking process can be effectively performed at the same time. Since the thickness of the insulating layer 121 is reduced, the overall thickness of the semiconductor package can be further reduced. In addition, by increasing the thickness of the second protective layer 134 or by adding a reinforcing agent, the mechanical strength of the auxiliary films 131 and 134 can be improved. When the mechanical strength of the auxiliary films 131 and 134 is enhanced, the auxiliary films 131 and 134 can prevent the semiconductor package from warping. Moreover, by adjusting the thermochromic material and / or the photochromic material in the second protective layer 134, a gloss can be generated on the surface of the semiconductor package. In addition, by adjusting the thermochromic material and / or the photochromic material in the second protective layer 134, the color of the second protective layer 134 and the color of the color change area (CP) can be freely adjusted.

[0083] Below, we will refer to Fig. 9 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0084] Fig. 9 are diagrams illustrating semiconductor packages according to some exemplary embodiments of the inventive concept.

[0085] refer to Fig. 9 According to some exemplary embodiments of the inventive concept, the semiconductor package may further include a first insertion layer 137. For example, according to the technical concept of the inventive concept, the auxiliary film may include a reflective layer 131, a first insertion layer 137, and a first protective layer 133.

[0086] The first insertion layer 137 may be inserted between the reflective layer 131 and the first protective layer 133. The first insertion layer 137 may reflect, for example, laser irradiated to the semiconductor package. The first insertion layer 137 may allow, for example, X-rays irradiated to the semiconductor package to pass therethrough.

[0087] In some exemplary embodiments of the present inventive concept, the second protective layer ( Figure 8 134 ) may be disposed on the first insertion layer 137 instead of the first protection layer 133 .

[0088] Below, we will refer to Fig.10 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0089] Fig.10 are diagrams illustrating semiconductor packages according to some exemplary embodiments of the inventive concept. Fig.10 It can be, for example, along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0090] refer to Fig.10 According to some exemplary embodiments of the present inventive concept, the semiconductor chip 110 of the semiconductor package may be in direct contact with the reflective layer 131. For example, the insulating layer 121 may not be interposed between the semiconductor chip 110 and the reflective layer 131.

[0091] When the semiconductor chip 110 is in direct contact with the reflective layer 131 , the overall thickness of the semiconductor package may be reduced.

[0092] Below, we will refer to FIG. 11A to FIG. 11C Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0093] FIG. 11A to FIG. 11C are diagrams illustrating semiconductor packages according to some exemplary embodiments of the inventive concept. FIG. 11A to FIG. 11C Each of the graphs in can be, for example, Figure 1 A cross-sectional view taken along line AA' in FIG.

[0094] refer to FIG. 11A to FIG. 11C According to some exemplary embodiments of the inventive concept, the semiconductor package may further include shielding layers 123 a , 123 b , and 123 c .

[0095] Shielding layers 123a, 123b, and 123c may be disposed between the semiconductor package substrate 101 and the reflective layer 131. The shielding layers 123a, 123b, and 123c may surround the insulating layer 121. The shielding layers 123a, 123b, and 123c may be disposed on the semiconductor package substrate 101 and spaced apart from the semiconductor chip 110.

[0096] exist Fig.11A In the embodiment of the present invention, the shielding layer 123a may extend from the upper surface 101U of the semiconductor package substrate 101 to the lower surface 131L of the reflective layer 131. The upper surface of the shielding layer 123a may contact the lower surface 131L of the reflective layer 131, and the lower surface of the shielding layer 123a may contact the lower surface 101L of the semiconductor package substrate 101. In addition, the side surface of the shielding layer 123a may contact the side surface of the insulating layer 121.

[0097] exist Fig. 11BIn the embodiment of the present invention, the shielding layer 123 b may extend through the auxiliary films 131 and 133 . When the shielding layer 123 b extends through the auxiliary films 131 and 133 , the upper surface of the shielding layer 123 b may be located on substantially the same plane as the upper surface of the first protective layer 133 .

[0098] exist Fig. 11C In the embodiment of the present invention, the shielding layer 123c may extend through the auxiliary films 131 and 133 and the semiconductor package substrate 101. When the shielding layer 123c extends through the auxiliary films 131 and 133 and the semiconductor package substrate 101, the upper surface of the shielding layer 123c may be located on substantially the same plane as the upper surface of the first protective layer 133, and the lower surface of the shielding layer 123c may be located on substantially the same plane as the lower surface 101L of the semiconductor package substrate 101. Figure 2 By performing, for example, a sputtering process, a spraying process, and / or a dipping process to form the shielding layer 123 c , a semiconductor package including the shielding layer 123 c extending through the auxiliary films 131 and 133 and the semiconductor package substrate 101 may be formed.

[0099] The shielding layers 123 a , 123 b , and 123 c may block EMI (Electromagnetic Interference), thereby protecting characteristics of the semiconductor chip 110 .

[0100] In some exemplary embodiments of the present inventive concept, the shielding layers 123a, 123b, 123c may include a material different from that of the reflective layer 131. Alternatively, in some exemplary embodiments of the present inventive concept, the shielding layers 123a, 123b, 123c may include the same material as that of the reflective layer 131. The shielding layers 123a, 123b, and 123c may include, for example, silver (Ag), but the technical concept of the present inventive concept is not limited thereto.

[0101] An electrical signal may be applied to the semiconductor package substrate 101. The electrical signal applied to the semiconductor package substrate 101 may be transmitted to the reflective layer 131, for example, through the shielding layers 123a, 123b, and 123c.

[0102] For example, the semiconductor package substrate 101 may be connected to a ground voltage. When the semiconductor package substrate 101 is connected to the ground voltage, the shielding layers 123 a , 123 b , and 123 c may be electrically connected to the ground voltage and the reflective layer 131 .

[0103] Below, we will refer to Fig.12 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0104] Fig.12are diagrams illustrating semiconductor packages according to some exemplary embodiments of the inventive concept. Fig.12 It can be, for example, along Figure 1 A cross-sectional view taken along line AA' in FIG.

[0105] refer to Fig.12 According to some exemplary embodiments of the inventive concept, a boundary surface 121 i between an insulating layer 121 and a reflective layer 131 included in a semiconductor package may be uneven.

[0106] For example, the lower surface of the reflective layer 131 may be uneven. For example, the lower surface of the reflective layer 131 may have unevenness. For example, the upper surface of the insulating layer 121 may be uneven. For example, the upper surface of the insulating layer 121 may have unevenness. The average roughness (Ra) of the boundary surface 121i between the insulating layer 121 and the reflective layer 131 may be, for example, greater than 0.3.

[0107] Since the boundary surface 121 i between the insulating layer 121 and the reflective layer 131 is uneven, the adhesive force between the insulating layer 121 and the reflective layer 131 may be increased.

[0108] Below, we will refer to Fig.13 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0109] Fig.13 2 is a diagram showing a semiconductor package according to some exemplary embodiments of the inventive concept. Fig.13 According to some exemplary embodiments of the present inventive concept, the semiconductor package may further include a second insertion layer 135 . The second insertion layer 135 may be inserted between the insulating layer 121 and the reflective layer 131 .

[0110] In some exemplary embodiments of the present inventive concept, the second insertion layer 135 may include an adhesive material. When the second insertion layer 135 includes the adhesive material, the reflective layer 131 may be attached to the top of the insulating layer 121 through the second insertion layer 135 .

[0111] In some exemplary embodiments of the present inventive concept, the second insertion layer 135 may include a material capable of blocking electrons from being transferred from the reflective layer 131 to the insulating layer 121 .

[0112] Below, we will refer to Fig.14 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0113] Fig.14 2 is a diagram showing a semiconductor package according to some exemplary embodiments of the inventive concept. Fig.14 , the reflective layer 131 of the semiconductor package according to some exemplary embodiments of the inventive concept includes a first reflective layer 131a, an adhesive layer 131b, and a second reflective layer 131c. The first reflective layer 131a may be disposed on the insulating layer 121. The second reflective layer 131c may be disposed on the first reflective layer 131a. The adhesive layer 131b may be interposed between the first reflective layer 131a and the second reflective layer 131c.

[0114] For example, the atomic number of the substance included in the first reflective layer 131a may be greater than the atomic number of the substance included in the second reflective layer 131c. The adhesive layer 131b may include an adhesive substance. The first reflective layer 131a and the second reflective layer 131c may be attached to each other through the adhesive layer 131b.

[0115] Below, we will refer to Fig.15 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0116] Fig.15 are diagrams illustrating semiconductor packages according to some exemplary embodiments of the inventive concept.

[0117] refer to Fig.15 The semiconductor package according to some exemplary embodiments of the present inventive concept may further include a heat conductive material layer 139. The heat conductive material layer 139 may be disposed in the insulating layer 121 between the semiconductor chip 110 and the reflective layer 131. The heat conductive material layer 139 may be interposed between the semiconductor chip 110 and the reflective layer 131.

[0118] The heat conductive material layer 139 may be, for example, a TIM (Thermal Interface Material).

[0119] In the drawings, the heat transfer material layer 139 is illustrated as being disposed only between the semiconductor chip 110 and the reflective layer 131, but the technical concept of the inventive concept is not limited thereto. For example, the heat transfer material layer 139 may be disposed between the side surface of the semiconductor chip 110 and the insulating layer 121. Alternatively, for example, the heat transfer material layer 139 may be disposed only on a portion of the upper surface of the semiconductor chip 110.

[0120] The semiconductor package according to some exemplary embodiments of the inventive concepts may effectively discharge heat generated by the semiconductor chip 110 to the outside of the semiconductor package by further including the heat conductive material layer 139 .

[0121] Below, we will refer to Fig.16 Semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0122] Fig.16 are diagrams illustrating semiconductor packages according to some exemplary embodiments of the inventive concept.

[0123] refer to Fig.16 , a semiconductor package according to some exemplary embodiments of the inventive concept may include an auxiliary film including a reflective layer 131 ′, a first insertion layer 137 , a first protective layer 133 , and a second protective layer 134 .

[0124] In some exemplary embodiments of the present inventive concepts, the reflective layer 131 ′ may be, for example, a woven metal mesh.

[0125] In the drawings, the reflective layer 131', the first insertion layer 137, the first protection layer 133, and the second protection layer 134 are illustrated as being sequentially stacked, but the inventive concept is not limited thereto. For example, the stacking order of the reflective layer 131', the first insertion layer 137, the first protection layer 133, and the second protection layer 134 may be changed. For example, the reflective layer 131', the first insertion layer 137, the second protection layer 134, and the first protection layer 133 may be sequentially stacked.

[0126] Below, we will refer to Figure 2 , Fig.17 and Fig.18 Methods of manufacturing semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0127] Fig.17 and Fig.18 1 is a diagram illustrating an intermediate stage of a method of manufacturing a semiconductor package according to some exemplary embodiments of the inventive concept.

[0128] refer to Fig.17 , the reflective layer 131 and the first protective layer 133 may be attached to the release film 203 .

[0129] The release film 203 may be attached to the first support 201 in order to release the molded product after molding without leaving residue in the mold. The insulating material 121 p may be disposed on the release film 203 and the reflective layer 131 .

[0130] The first support member 201 may be, for example, a die mold.

[0131] The release film 203 may include, for example, a base film and / or a release layer.

[0132] When the release film 203 includes both a base film and a release layer, the base film and the release layer may be sequentially stacked on the first support 201. Here, the release layer may be a layer for separating the auxiliary films 131 and 133 from the base film. The base film may support the release layer, the first protective layer 133, and the reflective layer 131.

[0133] The substrate film may include, for example but not limited to, polyethylene terephthalate, polyethylene (PE), polypropylene (PP), polymethyl methacrylate (PMMA), polycarbonate (PC), polyurethane (PU), polytetrafluoroethylene (PTFE), ethylene-polytetrafluoroethylene (ETFE) or a mixture thereof.

[0134] The release layer may include, but is not limited to, a silicon-based release agent, an epoxy-based release agent, or a fluorine-based release agent.

[0135] In some exemplary embodiments of the present inventive concept, a semiconductor package substrate 101 on which a plurality of semiconductor chips 110 are mounted may be located on an insulating material 121p and may be spaced apart from the insulating material 121p. The semiconductor package substrate 101 may be arranged so that the semiconductor chips 110 face the insulating material 121p. For example, an upper surface 101U of the semiconductor package substrate 101 may face the insulating material 121p. The insulating material 121p may be, for example, an epoxy resin mold compound.

[0136] In the drawings, the first protective layer 133 and the reflective layer 131 are illustrated as extending only along a portion of the release film 203 , but the inventive concept is not limited thereto. For example, the first protective layer 133 and / or the reflective layer 131 may extend along the contour of the release film 203 on the release film 203 .

[0137] refer to Fig.18 , an insulating layer 121 may be formed. For example, an insulating material ( Fig.17 The semiconductor chip 110 can be inserted into the insulating material ( Fig.17 121p). The semiconductor package substrate 101 and the insulating material ( Fig.17 121p), and between the plurality of semiconductor chips 110 and the insulating material ( Fig.17 A plurality of semiconductor chips 110 may be completely inserted into the insulating material ( Fig.17121p), thereby forming the insulating layer 121. Therefore, the plurality of semiconductor chips 110 may be buried in the insulating layer 121.

[0138] A portion of the release film 203 may be in contact with a portion of the upper surface 101U of the semiconductor package substrate 101 .

[0139] After that, the release film 203 and the first support member 201 can be removed. After the release film 203 and the first support member 201 are removed by a singulation process or the like, the width of the insulating layer 121 and the width of the semiconductor package substrate 101 can be made the same as the corresponding widths of the reflective layer 131 and the first protective layer 133.

[0140] The external connection terminals 103 are attached to the semiconductor package substrate 101 from which the release film 203 and the first support member 201 are removed, so that Figure 2 semiconductor packages.

[0141] In the method of manufacturing a semiconductor package according to some exemplary embodiments of the inventive concept, by attaching the reflective layer 131 and the first protective layer 133 to the release film 203 to mold the plurality of semiconductor chips 110 , the complexity of the semiconductor package manufacturing process may be reduced.

[0142] Furthermore, in the method of manufacturing a semiconductor package according to some exemplary embodiments of the inventive concept, by simultaneously performing a molding process on each of the plurality of semiconductor chips 110 , the complexity of the semiconductor package manufacturing process may be reduced.

[0143] Below, we will refer to Figure 2 , Fig.18 and Fig.19 Methods of manufacturing semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0144] Fig.19 1 is a diagram illustrating an intermediate stage of a method of manufacturing a semiconductor package according to some exemplary embodiments of the inventive concept.

[0145] refer to Fig.19 , the insulating material 121p may be disposed only on the reflective layer 131 and the first protective layer 133. For example, the width of the insulating material 121p may be substantially the same as the width of each of the reflective layer 131 and the first protective layer 133.

[0146] refer to Fig.18 , an insulating layer 121 may be formed.

[0147] Below, we will refer to Figure 2 , Fig. 20 and Fig.21 Methods of manufacturing semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated descriptions will be simplified or omitted, and it may be assumed that the omitted descriptions are at least similar to those of corresponding elements that have been described.

[0148] Fig. 20 and Fig.21 1 is a diagram illustrating an intermediate stage of a method of manufacturing a semiconductor package according to some exemplary embodiments of the inventive concept.

[0149] refer to Fig. 20 , the semiconductor package substrate 101 on which the semiconductor chip 110 is mounted may be disposed on the second support 211 .

[0150] The auxiliary films 131 and 133 and the release film 203 may be disposed under the first support member 201. The first support member 201 may include a decompression portion 205. For example, vacuum (VC) may be applied to the first support member 201 through the decompression portion 205. With the help of the vacuum (VC), the auxiliary films 131 and 133 and the release film 203 may wrap around the inner wall of the first support member 201.

[0151] refer to Fig.21 , the first support 201 and the second support 211 may be coupled together. As the first support 201 and the second support 211 are coupled together, the insulating layer 121 may mold the semiconductor chip 110 while covering the semiconductor package substrate 101 .

[0152] For example, the inner space (S) may be formed by coupling the first support member 201 and the second support member 211. The insulating material contained in the insulating layer 121 may be disposed in the inner space (S). For example, since the vacuum (VC) provided on the first support member 201 decompresses the inner space (S), the insulating material may be provided in the inner space (S).

[0153] refer to Figure 2 , the first support member 201 and the second support member 211 may be separated from the semiconductor package substrate 101. When the first support member 201 is separated, the release film 203 may be separated from the auxiliary films 131 and 133. Therefore, the auxiliary films 131 and 133 may be formed on the insulating layer 121.

[0154] Below, we will refer to Fig.11A , Figure 22 to Figure 24Methods of manufacturing semiconductor packages according to some exemplary embodiments of the inventive concept are described. For clarity of explanation, repeated steps will be simplified or omitted, and it may be assumed that the omitted description is at least similar to that of the corresponding elements already described.

[0155] Figure 22 to Figure 24 1 is a diagram illustrating an intermediate stage of a method of manufacturing a semiconductor package according to some exemplary embodiments of the inventive concept.

[0156] refer to Fig. 22 , a free shielding layer 123 ap may be formed between the plurality of semiconductor chips 110 .

[0157] refer to Fig.23 , an insulating layer 121 may be formed. A plurality of semiconductor chips 110 and a free shielding layer 123ap may be completely inserted into the insulating material ( Fig. 22 121p) to form the insulating layer 121. The plurality of semiconductor chips 110 and the free shielding layer 123ap may be buried in the insulating layer 121.

[0158] refer to Fig.24 , the first support member 201 and the release film 203 can be removed. Afterwards, the single-piece separation process can be used to form Fig.11A Shielding layer 123a.

[0159] Below, we will refer to Fig. 11B and Figure 25 to Figure 27 , a method of manufacturing a semiconductor package according to some exemplary embodiments of the inventive concept is described. For the sake of clear explanation, repeated descriptions will be simplified or omitted, and it can be assumed that the omitted descriptions are at least similar to the descriptions of the corresponding elements that have been described.

[0160] Figure 25 to Figure 27 1 is a diagram illustrating an intermediate stage of a method of manufacturing a semiconductor package according to some exemplary embodiments of the inventive concept. Fig.25 It can be that after the first support member 201 and the release film 203 are separated and the Fig.18 Figure 2 after the single-wafer singulation process.

[0161] refer to Fig.25 and Fig.26 , a trench (T) may be formed between the plurality of semiconductor chips 110. The trench (T) may be formed in the auxiliary films 131 and 133 and the insulating layer 121. The bottom surface of the trench (T) may be defined by the upper surface 101U of the semiconductor package substrate 101. The sidewall of the trench (T) may be defined by the auxiliary films 131 and 133 and the insulating layer 121.

[0162] refer to Fig. 27, a shielding material is filled in the groove (T), and a free shielding layer 123bp can be formed. After that, a single chip segmentation process can be used to form Fig. 11B Shielding layer 123b.

[0163] Although the inventive concept has been illustrated and described with reference to the exemplary embodiments of the inventive concept, it is obvious to those skilled in the art that various modifications may be made to the invention in form and detail without departing from the spirit and scope of the inventive concept. For example, elements and / or features of different exemplary embodiments may be combined with each other and / or replaced with each other within the scope of the present disclosure and the appended claims.

Claims

1. A semiconductor package, comprising: Semiconductor packaging substrate; an insulating layer, the insulating layer being disposed on the semiconductor package substrate; a semiconductor chip, wherein the semiconductor chip is disposed on the semiconductor package substrate and is covered by the insulating layer; a reflective layer, the reflective layer being directly disposed on the insulating layer and spaced apart from the semiconductor chip, the reflective layer comprising a metal material having an atomic number greater than 12, and the reflective layer being configured to selectively transmit radiation for inspecting the semiconductor package to the insulating layer so that a transmittance of soft X-rays included in the radiation is reduced or the transmission of the soft X-rays is blocked and hard X-rays included in the radiation are transmitted; a protective layer, the protective layer being disposed on the reflective layer; as well as an insertion layer, the insertion layer being between the reflective layer and the protective layer, The insertion layer is configured to reflect laser light radiated to the semiconductor package and allow X-rays radiated to the semiconductor package to pass therethrough, the X-rays including the soft X-rays and the hard X-rays.

2. The semiconductor package according to claim 1, wherein: The reflective layer is configured to be more transmissive to the hard X-rays than to the soft X-rays.

3. The semiconductor package according to claim 1, wherein: The reflective layer is configured to block the soft X-rays.

4. The semiconductor package according to claim 1, wherein: The reflective layer is configured to block the laser light.

5. The semiconductor package according to claim 1, wherein: The protection layer includes the same material as the insulating layer.

6. The semiconductor package according to claim 1, wherein: The reflective layer completely covers the upper surface of the insulating layer.

7. The semiconductor package according to claim 1, further comprising: a shielding layer, the shielding layer being spaced apart from the semiconductor chip and surrounding the insulating layer between the semiconductor package substrate and the reflective layer, The shielding layer extends from the upper surface of the semiconductor package substrate to the lower surface of the reflective layer.

8. The semiconductor package according to claim 1, wherein: The protective layer comprises a thermochromic material and / or a photochromic material, and Wherein, the thermochromic material and / or the photochromic material has a crystal structure including crystal grains.

9. The semiconductor package according to claim 1, further comprising: A heat conductive material layer is disposed in the insulating layer between the semiconductor chip and the reflective layer.

10. A semiconductor package, comprising: Semiconductor packaging substrate; A molding layer, the molding layer being disposed on the semiconductor package substrate; as well as a semiconductor chip, the semiconductor chip being disposed on the semiconductor package substrate and covered by the molding layer, Wherein, the molding layer comprises: an insulating layer, the insulating layer being disposed on the semiconductor package substrate and the semiconductor chip being included in the insulating layer, a reflective layer, the reflective layer being directly disposed on the insulating layer and spaced apart from the semiconductor chip, a protective layer, the protective layer being arranged on the reflective layer, an insertion layer, the insertion layer being between the reflective layer and the protective layer, wherein the insertion layer is configured to reflect laser irradiated to the semiconductor package and allow X-rays irradiated to the semiconductor package to pass therethrough, the X-rays including soft X-rays and hard X-rays, and Wherein, the reflective layer includes a metal material with an atomic number greater than 12, and the reflective layer is configured to selectively transmit radiation used to inspect the semiconductor package so that the transmittance of the soft X-rays included in the radiation is reduced or the transmission of the soft X-rays is blocked and the hard X-rays included in the radiation are transmitted.

11. The semiconductor package according to claim 10, wherein: The semiconductor package is configured to block the soft X-rays.

12. The semiconductor package according to claim 10, wherein: The reflective layer is configured to transmit hard X-rays included in the radiation more than the soft X-rays.

13. The semiconductor package according to claim 10, wherein: The reflective layer is a woven metal mesh, and Wherein, the molding layer further includes a protective layer, and the protective layer is arranged on the reflective layer.

14. The semiconductor package according to claim 13, wherein: The reflective layer is configured to block the soft X-rays and transmit the hard X-rays into the insulating layer.

15. The semiconductor package according to claim 13, wherein: The reflective layer is configured to block the laser light.

16. A semiconductor package, comprising: Semiconductor packaging substrate; an insulating layer, the insulating layer being disposed on the semiconductor package substrate; a semiconductor chip, wherein the semiconductor chip is disposed on the semiconductor package substrate and is covered by the insulating layer; a reflective layer directly disposed on the insulating layer and spaced apart from the semiconductor chip, the reflective layer comprising a metal material having an atomic number greater than 12 to selectively transmit radiation for inspecting the semiconductor package, so that a transmittance of soft X-rays included in the radiation is reduced or the transmission of the soft X-rays is blocked and hard X-rays included in the radiation are transmitted; a protective layer, the protective layer being disposed on the reflective layer; as well as an insertion layer, the insertion layer being between the reflective layer and the protective layer, The insertion layer is configured to reflect laser light radiated to the semiconductor package and allow X-rays radiated to the semiconductor package to pass therethrough, the X-rays including the soft X-rays and the hard X-rays.

17. The semiconductor package according to claim 16, wherein: The reflective layer is configured to be more transmissive to the hard X-rays than to the soft X-rays.

18. The semiconductor package according to claim 16, wherein: The reflective layer is configured to block the soft X-rays.

19. The semiconductor package according to claim 16, wherein: The reflective layer is configured to block the laser light.

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