Substrate structure, semiconductor packaging structure and semiconductor process

Abstract

A substrate structure includes a wiring structure and a support member. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure, and the second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The support member is disposed on the first dielectric structure adjacent to the wiring structure and defines at least one through-hole corresponding to the exposed pad portion of the first circuit layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 644,200, filed March 16, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a substrate structure, a semiconductor package structure, and a semiconductor process, and also to a coreless substrate structure, a semiconductor package structure, and a semiconductor process for forming or testing the substrate structure. Background Art

[0004] In the manufacturing process for forming a package structure, a wiring structure comprising multiple circuit layers and dielectric layers is first formed on a carrier. Next, a semiconductor die is attached and electrically connected to the wiring structure. However, because the lower surface of the wiring structure is covered by the carrier, a probe cannot reach the bottommost circuit layer of the wiring structure. Therefore, it is impossible to test for electrical connection defects (e.g., open circuits) between the topmost and bottommost circuit layers. Summary of the Invention

[0005] In some embodiments, a substrate structure includes a wiring structure and a supporter. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure, and the second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The supporter is disposed on the first dielectric structure adjacent to the wiring structure and defines at least one through-hole corresponding to the exposed pad portion of the first circuit layer.

[0006] In some embodiments, a semiconductor package structure includes a wiring structure, a support member, a semiconductor die, and an encapsulant. The wiring structure has a first surface and a second surface opposite the first surface, and includes at least one dielectric structure and at least one circuit layer. A pad portion of the circuit layer is exposed from the first surface. The support member is disposed adjacent to the first surface of the wiring structure and defines at least one through-hole corresponding to the exposed pad portion of the circuit layer. The semiconductor die is electrically connected to the second surface of the wiring structure. The encapsulant covers the semiconductor die and the second surface of the wiring structure.

[0007] In some embodiments, a semiconductor process includes: (a) providing a support member defining at least one through-hole; (b) forming or placing a plugging material in the through-hole of the support member; and (c) forming a wiring structure on the support member, wherein the wiring structure has a first surface and a second surface opposite to the first surface, and includes at least one dielectric structure and at least one circuit layer, a pad portion of the circuit layer is exposed from the first surface, the first surface faces the support member, and the through-hole of the support member corresponds to the exposed pad portion of the circuit layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of some embodiments of the present disclosure will be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale, and that the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 Cross-sectional views illustrating examples of substrate structures according to some embodiments of the present disclosure.

[0010] Figure 2 Cross-sectional views illustrating examples of substrate structures according to some embodiments of the present disclosure.

[0011] Figure 3 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0012] Figure 4 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0013] Figure 5 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of the present disclosure.

[0014] Figure 6 Cross-sectional views illustrating examples of semiconductor devices according to some embodiments of the present disclosure.

[0015] Figure 7 Cross-sectional views illustrating examples of semiconductor devices according to some embodiments of the present disclosure.

[0016] Figure 8 Cross-sectional views illustrating examples of semiconductor devices according to some embodiments of the present disclosure.

[0017] Figure 9 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0018] Figure 10 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0019] Figure 11 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0020] Figure 12 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0021] Figure 13 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0022] Figure 14 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0023] Figure 15 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0024] Figure 16 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0025] Figure 17 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0026] Figure 18 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0027] Figure 19 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0028] Figure 20 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0029] Figure 21One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0030] Figure 22 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described.

[0031] Figure 23 One or more stages of an example semiconductor process according to some embodiments of the present disclosure are described. DETAILED DESCRIPTION

[0032] The present disclosure will be readily understood from the detailed description taken in conjunction with the accompanying drawings, wherein common reference numerals are used throughout the drawings to designate the same or similar components.

[0033] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed or arranged in direct contact, and may also include an embodiment in which an additional feature may be formed or arranged between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0034] In the manufacturing process of a semiconductor package structure, a wiring structure is first formed by stacking multiple circuit layers and dielectric layers on a carrier. Next, a semiconductor die is attached and electrically connected to a portion of the topmost circuit layer of the wiring structure. A package body is then formed on the wiring structure to cover the semiconductor die. Next, the support member is removed to expose a portion of the bottommost circuit layer of the wiring structure, and the package body and wiring structure are singulated to form a semiconductor package structure.

[0035] Before attaching the semiconductor die to the wiring structure, the upper surface of the wiring structure can be subjected to automated optical inspection (AOI). AOI is used to test the integrity of the wiring structure's topmost circuit layer. However, because the wiring structure's lower surface is covered by a support, a probe cannot reach the wiring structure's bottommost circuit layer. Consequently, it is impossible to test for electrical connection defects (e.g., open circuits) between the topmost and bottommost circuit layers before attaching the semiconductor die and removing the support. Therefore, if the wiring structure has such an electrical connection defect, the semiconductor die attached to it will be wasted.

[0036] In a comparative process, a through-hole is formed on and through the support member to expose the bottommost circuit layer of the wiring structure, allowing a probe to reach the bottommost circuit layer of the wiring structure before removing the support member. The through-hole can be formed by laser or mechanical drilling. However, because the support member is typically made of a rigid material such as glass, the laser or mechanical drilling process must use relatively high power, which can easily damage the wiring structure.

[0037] Therefore, at least some embodiments of the present disclosure provide a substrate structure including a wiring structure defining a through-hole disposed on a support. The wiring structure can be tested before the support is removed. At least some embodiments of the present disclosure further provide a semiconductor package structure using the substrate structure, and a semiconductor process for forming and / or testing the substrate structure.

[0038] Figure 1 A cross-sectional view of a substrate structure 1 according to some embodiments of the present disclosure is illustrated. The substrate structure 1 may include a wiring structure 2, an insulation layer 14, a support member 16, and a plug material 3.

[0039] The wiring structure 2 has a first surface 201, a second surface 202 opposite to the first surface 201, and a side surface 203 extending between the first surface 201 and the second surface 202. The wiring structure 2 includes at least one dielectric structure (e.g., a first dielectric structure 21, a second dielectric structure 23, and a third dielectric structure 25) and at least one circuit layer (e.g., a first circuit layer 22 and a second circuit layer 24). For example, Figure 1 As shown in FIG. 2 , the wiring structure 2 includes a first dielectric structure 21 , a first circuit layer 22 , a second dielectric structure 23 , a second circuit layer 24 and a third dielectric structure 25 .

[0040] The first dielectric structure 21 has a first surface 211 and a second surface 212 opposite to the first surface 211. The first surface 211 of the first dielectric structure 21 may be part of the first surface 201 of the wiring structure 2. The first dielectric structure 21 defines at least one through hole 210. Figure 1 , the first dielectric structure 21 defines two through-holes 210. The first dielectric structure 21 may include or be formed of a curable photoimageable dielectric (PID) material including a photoinitiator, such as epoxy resin or polyimide (PI).

[0041] The first circuit layer 22 is disposed on the second surface 212 of the first dielectric structure 21. The first circuit layer 22 includes a plurality of first conductive traces 223 and at least one first pad portion 224. The first pad portion 224 may include a lower portion 225 and an upper portion 226. The traces 223, the lower portion 225, and the upper portion 226 of the first pad portion 224 may be formed integrally and concurrently. However, in other embodiments, the traces 223 and the upper portion 226 of the first pad portion 224 may be formed integrally and concurrently, while the lower portion 225 of the first pad portion 224 is formed separately, and a boundary may exist between the lower portion 225 and the upper portion 226 of the first pad portion 224. The lower portion 225 of the first pad portion 224 is disposed in the through-hole 210 of the first dielectric structure 21 and is exposed from the first surface 211 of the first dielectric structure 21. That is, the pad portion (e.g., first pad portion 224) of the circuit layer (e.g., first circuit layer 22) is exposed from the first surface 201 of the wiring structure 21. The first circuit layer 22 may be a redistribution layer. The line width / line space (L / S) of the first circuit layer 22 may be less than about 7 μm / about 7 μm (e.g., in a range from about 2 μm / about 2 μm to about 5 μm / about 5 μm). In some embodiments, the first circuit layer 22 may be the bottommost circuit layer of the wiring structure 2.

[0042] The second dielectric structure 23 is disposed on and covers the first dielectric structure 21 and the first circuit layer 22. The second dielectric structure 23 has a first surface 231 and a second surface 232 opposite the first surface 231. For example, the first surface 231 of the second dielectric structure 23 is in contact with the second surface 212 of the first dielectric structure 21. The second dielectric structure 23 defines at least one through-hole 230 to expose the upper portion 226 of the first pad portion 224 of the first circuit layer 22. The second dielectric structure 23 may include or be formed of a curable PI material, such as epoxy resin or polyimide (PI), containing a photoinitiator.

[0043] The second circuit layer 24 protrudes from the second dielectric structure 23. The second circuit layer 24 is disposed on the second surface 232 of the second dielectric structure 23. The second circuit layer 24 includes a plurality of second conductive traces 243 and at least one second pad portion 244. The bottom surfaces of the second conductive traces 243 of the second circuit layer 24 may be disposed on or stand on the second surface 232 of the second dielectric structure 23. In other words, the second conductive traces 243 of the second circuit layer 24 may not be embedded in the second dielectric structure 23. The second pad portion 244 may include a lower portion 245 and an upper portion 246. The traces 243, the lower portion 245, and the upper portion 246 of the second pad portion 244 may be molded simultaneously and integrally. However, in other embodiments, the traces 243 and the upper portion 246 of the second pad portion 244 may be molded simultaneously and integrally, while the lower portion 245 of the second pad portion 244 is molded separately, and a boundary may exist between the lower portion 245 and the upper portion 246 of the second pad portion 244. The lower portion 245 of the second pad portion 244 is disposed in the through-hole 230 of the second dielectric structure 23 to contact the first pad portion 224 of the first circuit layer 22, for example, the upper portion 226 of the first pad portion 224 of the first circuit layer 22. The second circuit layer 24 may be a redistribution layer. The line width / line spacing (L / S) of the second circuit layer 24 may be less than about 7 μm / about 7 μm (for example, in a range of about 2 μm / about 2 μm to about 5 μm / about 5 μm). In one embodiment, the line width / line spacing (L / S) of the second circuit layer 24 may be less than the line width / line spacing (L / S) of the first circuit layer 22. In some embodiments, the second circuit layer 24 may be the topmost circuit layer of the wiring structure 2. There may be more than one circuit layer and dielectric structure disposed between the second circuit layer 24 and the first circuit layer 22.

[0044] The third dielectric structure 25 is disposed on and covers the second dielectric structure 23 and the second circuit layer 24. The third dielectric structure 25 has a first surface 251 and a second surface 252 opposite the first surface 251. For example, the first surface 251 of the third dielectric structure 25 contacts the second surface 232 of the second dielectric structure 23. The second surface 252 of the third dielectric structure 25 may be part of the second surface 202 of the wiring structure 2. The third dielectric structure 25 defines at least one through-hole 250 to expose the upper portion 246 of the second pad portion 244 of the second circuit layer 24. The third dielectric structure 25 may include or be formed of a curable PI material, such as epoxy resin or polyimide (PI), containing a photoinitiator.

[0045] The insulating layer 14 is disposed on the first surface 201 of the wiring structure 2. Figure 1, the insulating layer 14 covers the entire first surface 201 of the wiring structure 2. For example, the insulating layer 14 covers the first surface 211 of the first dielectric structure 21 and the exposed pad portion 224 of the first circuit layer 22. The insulating layer 14 can be made of a dielectric material or can be a release film.

[0046] The support member 16 is disposed adjacent to the first surface 201 of the wiring structure 2. For example, the support member 16 may be disposed on the insulating layer 14 on the first surface 201 of the wiring structure 2. That is, the insulating layer 14 is disposed between the wiring structure 2 and the support member 16. However, in other embodiments, the insulating layer 14 may be omitted, and the support member 16 may be disposed directly on and in contact with the wiring structure 2 (e.g., Figure 5 ). Support member 16 has a first surface 161 and a second surface 162 opposite first surface 161. Second surface 162 faces wiring structure 2. Support member 16 defines at least one through-hole 160, which corresponds to an exposed pad portion (e.g., first pad portion 224) of a circuit layer (e.g., first circuit layer 22). Through-hole 160 penetrates support member 16 and extends between first surface 161 and second surface 162. Through-hole 160 may have a uniform width from first surface 161 to second surface 162. The material of support member 16 may be organic (e.g., core, epoxy resin, compound) or inorganic (e.g., Si, glass, metal). In some embodiments, the Young's modulus of support member 16 may be approximately 70 GPa (e.g., glass) to approximately 200 GPa (e.g., stainless steel), which is greater than the Young's modulus of wiring structure 2. Therefore, support member 16 is strong and can be used to support wiring structure 2 during its manufacturing process. By way of example, the support 16 may be part of a carrier which is usually used for forming the wiring structure 2 thereon.

[0047] The plug material 3 is disposed in the through hole 160 of the support member 16. The plug material 3 blocks the through hole 160 of the support member 16 so that the first surface 161 of the support member 16 is not connected to the second surface 162 through the through hole 160. For example, Figure 1As shown in FIG, plug material 3 fills through-hole 160 of support member 16. Plug material 3 may have a first surface 31 and a second surface 32 opposite first surface 31. First surface 31 of plug material 3 is substantially coplanar with first surface 161 of support member 16, and second surface 32 of plug material 3 is substantially coplanar with second surface 162 of support member 16. That is, two opposing surfaces of plug material 3 (e.g., first surface 31 and second surface 32) are coplanar with two opposing surfaces of support member 16 (e.g., first surface 161 and second surface 162), respectively. Plug material 3 may be made of a resin, such as an epoxy resin (e.g., PHP-900 IR6 manufactured by SAN-EI KAGAKU Co., Ltd.) or other suitable material. Therefore, plug material 3 can be removed by dissolving it with a solvent (e.g., potassium permanganate (VII)) or sodium permanganate (VII) solution) or by laser drilling at a relatively low power.

[0048] Because the support member 16 defines the through hole 160, a test step (e.g., open / short (O / S) test) can be performed to test the wiring structure 2 before attaching the semiconductor die to the wiring structure 2 and / or removing the support member 16. That is, the plug material 3 can be easily removed by dissolving it with a solvent or by laser drilling at a lower power, which may not damage the wiring structure 2. Then, a probe can be inserted through the support member 16 to contact the exposed pad portion (e.g., the first pad portion 224) of the circuit layer (e.g., the first circuit layer 22), as shown in FIG. Figure 16 As shown in .

[0049] During formation of the wiring structure 2, the plug material 3 blocks the through-holes 160 of the support member 16, thereby protecting the wiring structure 2 from contact with a reagent (e.g., a developer or an etching reagent) flowing into the through-holes 160 of the support member 16. In addition, the plug material 3 can serve as a target for accurately positioning the circuit layer (e.g., the first circuit layer 22) of the wiring structure 2.

[0050] Figure 2 A cross-sectional view illustrating an example of a substrate structure 1a according to some embodiments of the present disclosure. The substrate structure 1a is similar to Figure 1 The substrate structure 1 shown in FIG. 1 is different from the substrate structure 1 shown in FIG. 1 , except for the shape of the through hole 160 a of the support member 16 a and the shape of the plug material 3 a .

[0051] As in Figure 2As can be seen in the figure, the through hole 160a of the support member 16a gradually narrows toward the wiring structure 2. For example, the through hole 160a of the support member 16a gradually narrows from the first surface 161 of the support member 16a toward the second surface 162 of the support member 16a. The through hole 160a of the support member 16a is generally trapezoidal in shape. Therefore, the plug material 3a is generally trapezoidal in shape. In other embodiments, the through hole 160a of the support member 16a may gradually narrow from the second surface 162 of the support member 16a toward the first surface 161 of the support member 16a. In other embodiments, the through hole 160a of the support member 16a may have other shapes, such as a bow tie shape.

[0052] Figure 3 A cross-sectional view illustrating an example of a semiconductor package structure 4 according to some embodiments of the present disclosure. The semiconductor package structure 4 includes a substrate structure 1b (including a wiring structure 2, a support member 16b, and a connecting element 18), a semiconductor die 43, a first solder ball 45, a first underfill 46, and a package body 44.

[0053] Substrate structure 1b is similar to Figure 1 The substrate structure 1 shown in FIG. 1 is the same as that shown in FIG. 1 , except for the following differences. For example, Figure 3 As shown in the figure, it can be omitted Figure 1 The plug material 3 is formed in the insulating layer 14, and the insulating layer 14 defines a through hole 140. The through hole 140 of the insulating layer 14 corresponds to the through hole 160 of the support member 16b to expose the pad portion (e.g., the first pad portion 224) of the circuit layer (e.g., the first circuit layer 22). For example, Figure 3 As shown in FIG. 1 , the width of the through hole 140 of the insulating layer 14 is the same as the width of the through hole 160 of the support member 16b. The sidewalls of the through hole 140 of the insulating layer 14 are connected to the sidewalls of the through hole 160 of the support member 16b. Figure 3 The thickness of the support member 16b shown in FIG. Figure 1 However, in other embodiments, Figure 3 The thickness of the support member 16b shown in FIG. 1 may be substantially equal to Figure 1 The thickness of the support member 16 is shown in FIG.

[0054] Connecting elements 18 are placed in through-holes 140 of insulating layer 14 and through-holes 160 of support member 16b for external connection purposes. Connecting elements 18 contact exposed pad portions (e.g., first pad portions 224) of a circuit layer (e.g., first circuit layer 22). Connecting elements 18 may be solder balls, copper pillars, or copper pillars with solder caps.

[0055] The semiconductor die 43 is electrically connected to the second surface 202 of the wiring structure 2. For example, the semiconductor die 43 is electrically connected to the upper portion 246 of the second pad portion 244 of the second circuit layer 24 via a first solder ball 45 disposed between the semiconductor die 43 and the upper portion 246 of the second pad portion 244 of the second circuit layer 24. Figure 3 As shown in FIG. 4 , the semiconductor die 43 is attached to the second surface 202 of the wiring structure 2 by flip-chip bonding.

[0056] An underfill material 46 is disposed between the semiconductor die 43 and the second surface 202 of the wiring structure 2 and surrounds the first solder ball 45. An encapsulation body 44 covers the semiconductor die 43 and the second surface 202 of the wiring structure 2. For example, the encapsulation body 44 is disposed on the second surface 202 of the wiring structure 2 and encapsulates the semiconductor die 43. A side surface 443 of the encapsulation body 44 may be substantially coplanar with the side surface 203 of the wiring structure 2. The encapsulation body 44 may be made of a molding compound with or without fillers. In some embodiments, the first underfill material 46 may be omitted, and the encapsulation body 44 may be further disposed between the semiconductor die 43 and the second surface 202 of the wiring structure 2.

[0057] In the semiconductor package structure 4, the wiring structure 2 can be tested before the semiconductor die 43 is attached. That is, the wiring structure 2 is a known-good structure. Therefore, the yield rate of the semiconductor package structure 4 can be improved. Furthermore, the support member 16 b can support the wiring structure 2 mounted thereon, thereby reducing warpage of the wiring structure 2 during the manufacturing process of the semiconductor package structure 4 (e.g., the steps for attaching the semiconductor die 43 or forming the package body 44 on the wiring structure 2).

[0058] Figure 4 A cross-sectional view illustrating an example of a semiconductor package structure 4a according to some embodiments of the present disclosure. The semiconductor package structure 4a is similar to Figure 3 4 shows a semiconductor package structure 4 , excluding the substrate structure 1 c .

[0059] Figure 4 The support member 16a shown in FIG. 1 is similar to Figure 216a. That is, the through-hole 160a of the support member 16a is generally trapezoidal in shape. Furthermore, the substrate structure 1c further includes a plug material 3c disposed in the through-hole 160a of the support member 16a. The plug material 3c defines a through-hole 30 to expose a pad portion (e.g., first pad portion 224) of a circuit layer (e.g., first circuit layer 22). The sidewalls of the through-hole 30 of the plug material 3c are continuous with the sidewalls of the through-hole 140 of the insulating layer 14. The connecting element 18 is disposed in the through-hole 30 of the plug material 3c and contacts the pad portion (e.g., first pad portion 224) of the circuit layer (e.g., first circuit layer 22). Figure 4 The thickness of the support member 16a shown in FIG. Figure 2 However, in other embodiments, Figure 4 The support member 16a shown in FIG. 1 may have a Figure 2 The support member 16a shown in FIG. 1 has a smaller thickness.

[0060] Figure 5 A cross-sectional view illustrating an example of a semiconductor package structure 4b according to some embodiments of the present disclosure. The semiconductor package structure 4b is similar to Figure 3 , the semiconductor package structure 4 is shown except that the insulating layer 14 is omitted. Therefore, the support member 16 is directly disposed on the wiring structure 2 and contacts therewith.

[0061] Figure 6 A cross-sectional view illustrating an example of a semiconductor device 5 according to some embodiments of the present disclosure includes a semiconductor package structure 4 c , a package substrate 6 , and a second underfill material 54 .

[0062] The package substrate 6 includes a core 61, conductive vias 62, a top redistribution layer (RDL) 63, a bottom RDL 64, and a second solder ball 65. The conductive via 62 extends through the core 61. The conductive via 62 may include a conductive material surrounded by an insulating material. The top RDL 63 and the bottom RDL 64 are disposed on two opposing surfaces of the core 61 and are electrically connected to each other through the conductive vias 62. The top RDL 63 and the bottom RDL 64 may each include one or more redistribution layers. For example, the top RDL 63 includes a first dielectric layer, a first circuit layer, a second dielectric layer, a second circuit layer, a third dielectric layer, a third circuit layer, and a fourth dielectric layer, sequentially disposed on the top surface of the core 61. Each of the first circuit layer, the second circuit layer, and the third circuit layer may include at least one trace and at least one via, and the first circuit layer, the second circuit layer, and the third circuit layer may be electrically connected to each other. Similarly, bottom RDL 64 may also include a first dielectric layer, a first circuit layer, a second dielectric layer, a second circuit layer, a third dielectric layer, a third circuit layer, and a fourth dielectric layer sequentially disposed on the bottom surface of core 61. Second solder balls 65 are disposed on bottom RDL 64 for external connection purposes.

[0063] The semiconductor package structure 4c is similar to Figure 3 , except that the insulating layer 14 and the support member 16 are omitted. The semiconductor package structure 4c is disposed on and electrically connected to the top RDL 63 of the package substrate 6. For example, the wiring structure 2 is electrically connected to the top RDL 63 via the connecting element 18. The second underfill material 54 is disposed between the semiconductor package structure 4c and the package substrate 6 and surrounds the connecting element 18.

[0064] Available from Figure 1 The substrate structure 1 shown in FIG provides the wiring structure 2 in the substrate structure 4 c. That is, the wiring structure 2 can be tested before attaching the semiconductor die 43 to the wiring structure 2 and removing the support 16. Therefore, the wiring structure 2 is known to be good, thereby providing an improved yield for the semiconductor device 5.

[0065] Figure 7 A cross-sectional view illustrating an example of a semiconductor device 5a according to some embodiments of the present disclosure. The semiconductor device 5a is similar to Figure 6 The semiconductor device 5 shown in FIG. 5 has a semiconductor package structure 4c. Figure 3 That is, the semiconductor package structure 4 includes a support member 16 b and an insulating layer 14 .

[0066] Figure 8A cross-sectional view illustrating an example of a semiconductor device 5b according to some embodiments of the present disclosure. The semiconductor device 5b is similar to Figure 7 5 , except that the package body 44b further covers the wiring structure 2, the support 16 and the top RDL 63 of the package substrate 6. The side surface 443b of the package body 44b is substantially coplanar with the side surface 603 of the package substrate 6.

[0067] Figures 9 to 19 The semiconductor process according to some embodiments of the present disclosure is described. In some embodiments, the semiconductor process is used to test the wiring structure 2, manufacture the semiconductor package structure 4c and / or manufacture Figure 6 The semiconductor device 5 shown in FIG.

[0068] refer to Figure 9 , providing a support member 16. The support member 16 has a first surface 161 and a second surface 162 opposite to the first surface 161. The material of the support member 16 can be organic (eg, core, epoxy resin, compound) or inorganic (eg, Si, glass, metal).

[0069] refer to Figure 10 , at least one through hole 160 is formed on the support member 16 and passes through the support member 16 . In other words, the support member 16 defines at least one through hole 160 .

[0070] refer to Figure 11 , the plug material 3 is placed in the through hole 160 of the support member 16. The plug material 3 blocks the through hole 160 of the support member 16. For example, Figure 11 As shown in FIG, plug material 3 fills through-hole 160 of support member 16. Plug material 3 may have a first surface 31 and a second surface 32 opposite first surface 31. First surface 31 of plug material 3 is substantially coplanar with first surface 161 of support member 16, and second surface 32 of plug material 3 is substantially coplanar with second surface 162 of support member 16. That is, two opposing surfaces of plug material 3 (e.g., first surface 31 and second surface 32) are coplanar with two opposing surfaces of support member 16 (e.g., first surface 161 and second surface 162), respectively. Plug material 3 may be made of a resin, such as an epoxy resin (e.g., PHP-900IR6 manufactured by SAN-EI KAGAKU Co., Ltd.) or other suitable material. Therefore, plug material 3 can be easily removed by dissolving it with a solvent (e.g., potassium permanganate or sodium permanganate solution) or by laser drilling at a relatively low power.

[0071] refer to Figure 12, an insulating layer 14 is formed or disposed on the support 16 and the plug material 3. For example, the insulating layer 14 is formed or disposed on the second surface 162 of the support 16 and the second surface 32 of the plug material 3. The insulating layer 14 can be made of a dielectric material or can be a release film.

[0072] refer to Figure 13 , forming a wiring structure 2 on the support 16, for example, formed on the insulating layer 14 on the support 16. The wiring structure 2 has a first surface 201, a second surface 202 opposite to the first surface 201, and a side surface 203 extending between the first surface 201 and the second surface 202. The wiring structure 2 includes at least one dielectric structure (for example, a first dielectric structure 21, a second dielectric structure 23, and a third dielectric structure 25) and at least one circuit layer (for example, a first circuit layer 22 and a second circuit layer 24). For example, as Figure 13 As shown in FIG. 2 , the wiring structure 2 includes a first dielectric structure 21 , a first circuit layer 22 , a second dielectric structure 23 , a second circuit layer 24 and a third dielectric structure 25 .

[0073] The first dielectric structure 21 has a first surface 211 and a second surface 212 opposite the first surface 211. The first surface 211 of the first dielectric structure 21 may be part of the first surface 201 of the wiring structure 2. The first dielectric structure 21 defines at least one through-hole 210. The first dielectric structure 21 may include or be formed of a curable PI material including a photoinitiator, such as epoxy resin or polyimide (PI).

[0074] The first circuit layer 22 is disposed on the second surface 212 of the first dielectric structure 21. The first circuit layer 22 includes a plurality of first conductive traces 223 and at least one first pad portion 224. The first pad portion 224 may include a lower portion 225 and an upper portion 226. The traces 223, the lower portion 225 of the first pad portion 224, and the upper portion 226 may be simultaneously and integrally formed, for example, by plating. However, in other embodiments, the traces 223 and the upper portion 226 of the first pad portion 224 may be simultaneously and integrally formed, while the lower portion 225 of the first pad portion 224 is separately formed, and a boundary may exist between the lower portion 225 and the upper portion 226 of the first pad portion 224. The lower portion 225 of the first pad portion 224 is disposed in the through-hole 210 of the first dielectric structure 21 and is exposed from the first surface 211 of the first dielectric structure 21. That is, the pad portion (e.g., first pad portion 224) of the circuit layer (e.g., first circuit layer 22) is exposed from the first surface 201 of the wiring structure 21. The through hole 160 of the support member 16 corresponds to the exposed pad portion (e.g., first pad portion 224) of the circuit layer (e.g., first circuit layer 22). The first circuit layer 22 may be a redistribution layer. The line width / line space (L / S) of the first circuit layer 22 may be less than about 7 μm / about 7 μm (e.g., in a range of about 2 μm / about 2 μm to about 5 μm / about 5 μm).

[0075] The second dielectric structure 23 is disposed on and covers the first dielectric structure 21 and the first circuit layer 22. The second dielectric structure 23 has a first surface 231 and a second surface 232 opposite the first surface 231. For example, the first surface 231 of the second dielectric structure 23 is in contact with the second surface 212 of the first dielectric structure 21. The second dielectric structure 23 defines at least one through-hole 230 to expose the upper portion 226 of the first pad portion 224 of the first circuit layer 22. The second dielectric structure 23 may include or be formed of a curable PI material, such as epoxy resin or polyimide (PI), containing a photoinitiator.

[0076] The second circuit layer 24 is disposed on the second surface 232 of the second dielectric structure 23. The second circuit layer 24 includes a plurality of second conductive traces 243 and at least one second pad portion 244. The second pad portion 244 may include a lower portion 245 and an upper portion 246. The traces 243, the lower portion 245 of the second pad portion 244, and the upper portion 246 may be formed simultaneously and integrally, for example, by plating. However, in other embodiments, the traces 223 and the upper portion 246 of the second pad portion 244 may be formed simultaneously and integrally, while the lower portion 245 of the second pad portion 244 is formed separately, and a boundary may exist between the lower portion 245 and the upper portion 246 of the second pad portion 244. The lower portion 245 of the second pad portion 244 is disposed in the through-hole 230 of the second dielectric structure 23 to contact the first pad portion 224 of the first circuit layer 22, for example, the upper portion 226 of the first pad portion 224 of the first circuit layer 22. The second circuit layer 24 may be a redistribution layer. The line width / line space (L / S) of the second circuit layer 24 may be less than about 7 μm / about 7 μm (eg, in a range from about 2 μm / about 2 μm to about 5 μm / about 5 μm).

[0077] The third dielectric structure 25 is disposed on and covers the second dielectric structure 23 and the second circuit layer 24. The third dielectric structure 25 has a first surface 251 and a second surface 252 opposite the first surface 251. For example, the first surface 251 of the third dielectric structure 25 contacts the second surface 232 of the second dielectric structure 23. The second surface 252 of the third dielectric structure 25 may be part of the second surface 202 of the wiring structure 2. The third dielectric structure 25 defines at least one through-hole 250 to expose the upper portion 246 of the second pad portion 244 of the second circuit layer 24. The third dielectric structure 25 may include or be formed of a curable PI material, such as epoxy resin or polyimide (PI), containing a photoinitiator.

[0078] refer to Figure 14 , at least a portion of the plug material 3 is removed to expose a pad portion (e.g., first pad portion 224) of the circuit layer (e.g., first circuit layer 22). In some embodiments, the plug material 3 may be made of resin and may be removed by dissolving with a solvent (e.g., an alkaline solution) or laser drilling. Figure 14 As shown in , the entire plug material 3 can be removed.

[0079] refer to Figure 15 , and then a portion of the insulating layer 14 is removed. For example, the portion of the insulating layer 14 can be removed by laser drilling, thereby forming a through hole 140 to expose a pad portion (e.g., first pad portion 224) of a circuit layer (e.g., first circuit layer 22). Because the insulating layer 14 is made of a dielectric material or a release film, the power of the laser drilling can be relatively low and the wiring structure 2 can be prevented from being damaged.

[0080] In other embodiments, the plug material 3 may be partially removed. For example, a portion of the plug material 3 may be removed, such as Figure 4 As shown in FIG, the plug material 3c defines a through hole 30 to expose a pad portion (e.g., first pad portion 224) of a circuit layer (e.g., first circuit layer 22). In addition, portions of the plug material 3 and portions of the insulating layer 14 can be removed in the same laser removal process. Figure 4 As shown in FIG. 1 , the sidewalls of the through-hole 30 of the plug material 3 c are connected to the sidewalls of the through-hole 140 of the insulating layer 14 .

[0081] refer to Figure 16 , testing the electrical characteristics of the wiring structure 2, such as testing the electrical connection defects (e.g., open circuit) of the wiring structure 2. In one embodiment, an open / short (O / S) test is performed. For example, Figure 16 As shown in FIG, the electrical characteristics of the wiring structure 2 are tested using a first probe 85 and a second probe 86. The first probe 85 contacts the lower portion (e.g., lower portion 225) of the exposed pad portion (e.g., first pad portion 224) of the circuit layer (e.g., first circuit layer 22). The second probe 86 is electrically connected to the upper portion (e.g., upper portion 226) of the exposed pad portion (e.g., first pad portion 224) of the circuit layer (e.g., first circuit layer 22). Figure 16 As shown in FIG, a first probe 85 penetrates through the through hole 160 of the support member 16 and the through hole 140 of the insulating layer 14 to contact the lower portion 225 of the first pad portion 224 of the first circuit layer 22. A second probe 86 penetrates through the through hole 250 of the third dielectric structure 25 to contact the upper portion 246 of the second pad portion 244 of the second circuit layer 24. The second probe 86 is thereby electrically connected to the lower portion 225 of the first pad portion 224 of the first circuit layer 22 via the lower portion 245 of the second pad portion 244 of the second circuit layer 24 and the upper portion 226 of the first pad portion 224 of the first circuit layer 22. In one embodiment, if the current flowing from the first probe 85 to the second probe 86 is greater than a predetermined value, the electrical connection between the first pad portion 224 of the first circuit layer 22 and the second pad portion 244 of the second circuit layer 24 is determined to be good or acceptable. In other words, the connection between the first pad portion 224 of the first circuit layer 22 and the second pad portion 244 of the second circuit layer 24 is not an open circuit.

[0082] Because it is possible to attach the semiconductor die 43 (such as Figure 17 ) and / or before removing the support 16, the wiring structure 2 is tested, so it is guaranteed that the wiring structure 2 is known to be good before the semiconductor die 43 is attached to the wiring structure 2. That is, the wiring structure 2 can be tested in the process.

[0083] refer to Figure 17 , attaching and electrically connecting the semiconductor die 43 to the second surface 202 of the wiring structure 2. For example, the semiconductor die 43 is electrically connected to the upper portion 246 of the second pad portion 244 of the second circuit layer 24 via a first solder ball 45 disposed between the semiconductor die 43 and the upper portion 246 of the second pad portion 244 of the second circuit layer 24. Figure 17 As shown in FIG, semiconductor die 43 is attached to second surface 202 of wiring structure 2 via flip-chip bonding. Then, underfill 46 is placed between semiconductor die 43 and second surface 202 of wiring structure 2, surrounding first solder balls 45. Package 44 covers semiconductor die 43 and second surface 202 of wiring structure 2. For example, package 44 is placed on second surface 202 of wiring structure 2 and encapsulates semiconductor die 43. Package 44 can be made of an encapsulation material with or without a filler.

[0084] refer to Figure 18 , remove the support member 16 and the insulating layer 14 from the wiring structure 2. The support member 16 can be reused (e.g. Figure 10 Then, the connection element 18 is formed on the exposed pad portion (eg, the first pad portion 224) of the circuit layer (eg, the first circuit layer 22). Then, the wiring structure 2 and the package body 44 are singulated, thereby forming Figure 18 The side surface 443 of the package body 44 may thus be substantially coplanar with the side surface 203 of the wiring structure 2 .

[0085] refer to Figure 19 , providing a package substrate 6. The package substrate 6 includes a core 61, a guide via 62, a top redistribution layer (RDL) 63, a bottom RDL 64, and a second solder ball 65. The guide via 62 passes through the core 61. The guide via 62 may include a conductive material surrounded by an insulating material. The top RDL 63 and the bottom RDL 64 are respectively disposed on two opposite surfaces of the core 61 and are electrically connected to each other through the guide via 62. The top RDL 63 and the bottom RDL 64 may each include one or more redistribution layers. For example, the top RDL 63 includes a first dielectric layer, a first circuit layer, a second dielectric layer, a second circuit layer, a third dielectric layer, a third circuit layer, and a fourth dielectric layer sequentially disposed on the top surface of the core 61. Each of the first circuit layer, the second circuit layer, and the third circuit layer may include at least one trace and at least one via, and the first circuit layer, the second circuit layer, and the third circuit layer may be electrically connected to each other. Similarly, bottom RDL 64 may also include a first dielectric layer, a first circuit layer, a second dielectric layer, a second circuit layer, a third dielectric layer, a third circuit layer, and a fourth dielectric layer sequentially disposed on the bottom surface of core 61. Second solder balls 65 are disposed on bottom RDL 64 for external connection purposes.

[0086] Next, the semiconductor package structure 4c is placed on the top RDL 63 of the package substrate 6 and electrically connected to the top RDL. For example, the wiring structure 2 is electrically connected to the top RDL 63 via the connection element 18. A second underfill material 54 is placed between the semiconductor package structure 4c and the package substrate 6 and surrounds the connection element 18. Next, the package substrate 6 can be singulated to form a structure as shown in FIG. Figure 6 The semiconductor device 5 shown in FIG.

[0087] Figure 20 In some embodiments, the semiconductor process is used to test the wiring structure 2, manufacture Figure 3 The semiconductor package structure 4 shown in the embodiment and / or manufacturing Figure 7 The semiconductor device 5a shown in FIG. The initial stage of the process described is similar to Figures 9 to 17 The stages are the same or similar to those described in . Figure 20 depiction Figure 17 The stage following the stage depicted in .

[0088] refer to Figure 20 , then thinning the support member 16 to form the support member 16b. That is, the thickness of the support member 16 can be reduced by, for example, grinding to form a support member 16b. Figure 20 Next, the connecting element 18 is formed in the through hole 160 of the supporting member 16b and the through hole 140 of the insulating layer 14 to contact the pad portion (e.g., the first pad portion 224) of the circuit layer (e.g., the first circuit layer 22). Next, the wiring structure 2 and the package body 44 are singulated, thereby forming Figure 13 The semiconductor package 4 shown in FIG.

[0089] Then, similar to Figure 19 At the stage shown in FIG, the semiconductor package structure 4 is placed on the top RDL 63 of the package substrate 6 and electrically connected to the top RDL via the connecting element 18. Then, the package substrate 6 may be singulated, thereby forming a semiconductor package structure 4 as shown in FIG. Figure 7 The semiconductor device 5a shown in FIG.

[0090] In other embodiments, the Figure 12 In the figure, an insulating layer 14 is formed or disposed on a support 16. Figure 13 The wiring structure 2 formed in the stage shown in FIG can be formed directly on the support 16. Therefore, using Figures 14 to 17 and subsequent stages shown in 20, can form Figure 5 The semiconductor package structure 4b shown in FIG.

[0091] Figure 21 In some embodiments, the semiconductor process is used to test the wiring structure 2 and / or manufacture Figure 8 The semiconductor device 5b is shown in FIG. The initial stage of the process described is similar to Figures 9 to 16 The stages are the same or similar to those described in . Figure 21 depiction Figure 16 The stage following the stage depicted in .

[0092] refer to Figure 21 , then thinning the support member 16 to form the support member 16b. That is, the thickness of the support member 16 can be reduced by, for example, grinding to form a support member 16b. Figure 21 Then, the connecting element 18 is formed in the through hole of the supporting member 16b to contact the pad portion (for example, the first pad portion 244) of the circuit layer (for example, the first circuit layer 24). Then, the wiring structure 2 is singulated, thereby forming Figure 3 The substrate structure 1b of the semiconductor package structure 4 is shown in FIG.

[0093] refer to Figure 22 , providing a packaging substrate 6. The packaging substrate 6 is similar to Figure 19 Next, the substrate structure 1 b is placed on the top RDL 63 of the package substrate 6 and is electrically connected to the top RDL through the connection element 18 .

[0094] refer to Figure 23 , attaching and electrically connecting the semiconductor die 43 to the second surface 202 of the wiring structure 2. Next, an underfill material 46 is placed between the semiconductor die 43 and the second surface 202 of the wiring structure 2 and surrounds the first solder ball 45. The package body 44b is then formed on the package substrate 6 to cover the semiconductor die 43 of the substrate structure 1b. Next, the package substrate 6 and the package body 44b can be singulated, thereby forming Figure 8 The side surface 443b may thus be substantially coplanar with the side surface 603 of the package substrate 6.

[0095] Unless otherwise indicated, spatial descriptors such as "above," "below," "up," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper," "on," "below," etc., are indicated relative to the orientation shown in the Figures. It should be understood that the spatial descriptors used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, with the proviso that the advantages of the embodiments of the present disclosure do not deviate from such arrangements.

[0096] As used herein, the terms "substantially," "approximately," "substantially," and "about" are used to describe and explain small variations. When used in conjunction with an event or circumstance, the terms may refer to instances in which the event or circumstance clearly occurred as well as instances in which the event or circumstance closely approximates to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values ​​may be considered “substantially” the same or equal if the difference between them is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

[0097] Two surfaces may be considered coplanar or substantially coplanar if the displacement between the two surfaces does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm, or does not exceed 0.5 μm.

[0098] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise.

[0099] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to transfer an electric current. Conductive materials generally refer to those materials that present little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m, for example at least 10 5 S / m or at least 10 6 S / m, a material. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0100] In addition, amounts, ratios, and other numerical values ​​are sometimes presented herein in a range format. It should be understood that such range format is used for convenience and brevity and should be interpreted flexibly to include not only the values ​​explicitly specified as limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly specified.

[0101] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. Those skilled in the art will understand that various changes may be made and equivalents substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative and not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A substrate structure comprising: a wiring structure comprising a first dielectric structure, a first circuit layer, a second dielectric structure, and a second circuit layer, wherein the first circuit layer is disposed on the first dielectric structure, the second dielectric structure covers the first dielectric structure and the first circuit layer, a pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure; a support member disposed adjacent the first dielectric structure to the wiring structure and defining at least one through-hole corresponding to the exposed pad portion of the first circuit layer; an insulating layer disposed between the wiring structure and the support member, wherein the insulating layer is a release film; as well as A plug material is disposed in the at least one through-hole of the support, a first surface of the plug material being coplanar with the first surface of the support, and a second surface of the plug material being coplanar with the second surface of the support, wherein the plug material is a resin.

2. The substrate structure according to claim 1, wherein the first dielectric structure has a first surface and a second surface and defines at least one through-hole; the first circuit layer is disposed on the second surface of the first dielectric structure and includes a plurality of first conductive traces and at least one first pad portion, a lower portion of the first pad portion is disposed in the through-hole of the first dielectric structure and exposed from the first surface of the first dielectric structure; and the second dielectric structure defines at least one through-hole to expose an upper portion of the first pad portion of the first circuit layer.

3. The substrate structure according to claim 2 , wherein the second circuit layer is disposed on the second dielectric structure and comprises a plurality of second conductive traces and at least one second pad portion, a lower portion of the second pad portion being disposed in the through-hole of the second dielectric structure to contact the first pad portion of the first circuit layer; and the wiring structure further comprises: A third dielectric structure covers the second dielectric structure and the second circuit layer and defines at least one through hole to expose an upper portion of the second pad portion of the second circuit layer. 4 . The substrate structure according to claim 1 , wherein the wiring structure has a first surface and a second surface opposite to the first surface, wherein the insulating layer covers the entire first surface of the wiring structure.

5. The substrate structure of claim 4 , wherein the first dielectric structure has a first surface and a second surface opposite to the first surface, the first surface of the first dielectric structure is part of the first surface of the wiring structure, and the insulating layer covers the first surface of the first dielectric structure and the exposed pad portion of the first circuit layer. 6 . The substrate structure of claim 2 , wherein the plurality of first conductive traces, the lower portion of the first pad portion, and the upper portion of the first pad portion are formed simultaneously and integrally. The substrate structure according to claim 1 , wherein the plug material has a trapezoidal shape.

8. A substrate structure comprising: a wiring structure comprising a first dielectric structure, a first circuit layer, a second dielectric structure, and a second circuit layer, wherein the first circuit layer is disposed on the first dielectric structure, the second dielectric structure covers the first dielectric structure and the first circuit layer, a pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure; a support member disposed adjacent the first dielectric structure to the wiring structure and defining at least one through-hole corresponding to the exposed pad portion of the first circuit layer; an insulating layer disposed between the wiring structure and the support member and defining a through hole corresponding to the at least one through hole of the support member to expose the pad portion of the first circuit layer, wherein the insulating layer is a release film; a plug material disposed in the at least one through-hole of the support member, wherein the plug material is a resin; as well as A connecting element is disposed in the through hole of the plug material and contacts the pad portion of the circuit layer. 9 . The substrate structure according to claim 8 , wherein a sidewall of the through hole of the plug material is connected to a sidewall of the through hole of the insulating layer.

10. The substrate structure of claim 1 or 8, wherein the plug material is easily removable by dissolution with a solvent or by laser drilling at a relatively low power.

11. A semiconductor process comprising: (a) providing a support member defining at least one through-hole; (b) forming or placing a plug material in the at least one through-hole of the support member; (c) forming a wiring structure on the support member, wherein the wiring structure has a first surface and a second surface opposite to the first surface, and comprises at least one dielectric structure and at least one circuit layer, a pad portion of the at least one circuit layer is exposed from the first surface, the first surface faces the support member, and the at least one through hole of the support member corresponds to the exposed pad portion of the circuit layer; (d) removing at least a portion of the plug material to expose the pad portion of the at least one circuit layer; (e) testing the electrical characteristics of the wiring structure; as well as (f) Removing the support member from the wiring structure.

12. The semiconductor process of claim 11 , wherein after step (e), the semiconductor process further comprises: (e1) attaching and electrically connecting a semiconductor die to the second surface of the wiring structure; (e2) placing an underfill material on the semiconductor die and the second surface of the wiring structure; as well as (e3) Placing a package body on the second surface of the wiring structure and encapsulating the semiconductor die.

13. The semiconductor process according to claim 12, wherein in step (e), the electrical characteristics of the wiring structure are tested using a first probe and a second probe, the first probe penetrates the support member to contact the lower portion of the exposed pad portion of the at least one circuit layer, and the second probe is electrically connected to the upper portion of the exposed pad portion of the at least one circuit layer.

14. The semiconductor process according to claim 13, wherein after step (b), the semiconductor process further comprises: (b1) forming or disposing an insulating layer on the support member; In step (c), the wiring structure is formed on the insulating layer; Step (d) further includes removing a portion of the insulating layer to expose the pad portion; and In step (e), the first probe further penetrates the insulating layer to contact the lower portion of the exposed pad portion of the at least one circuit layer.

15. The semiconductor process of claim 11 , wherein after step (f), the semiconductor process further comprises: (g) providing a package substrate, wherein the package substrate comprises a core, a guide via, a top RDL, a bottom RDL, and a second solder ball, wherein the top RDL and the bottom RDL are respectively disposed on two opposite surfaces of the core and are electrically connected to each other through the guide via, and wherein the top RDL and the bottom RDL each comprise one or more redistribution layers; (h) electrically connecting the wiring structure to the top RDL via a connecting element; as well as (i) Disposing an underfill material to surround the connecting element.

16. The semiconductor process of claim 11, wherein in step (c), the wiring structure is formed on the support member before removing the plug material.

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