Execution Unit Sharing Hybrid Technology for Accelerated Computation on Graphics Processors

Abstract

Describes a mechanism for facilitating hybrid processing of the workload of a graphics processor in a computing device. As described herein, it includes detecting the workload of the graphics processor and checking the status of a shared functional unit (SFU) associated with the graphics processor to determine the distribution of the workload between the SFU and an execution unit (EU) associated with the graphics processor.

Description

Technical Field

[0001] The embodiments described herein generally relate to data processing and more particularly to facilitating a tool for facilitating an execution unit sharing hybrid technique for accelerated computing on a graphics processor of a computing device. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function computing units to process graphics data; however, recently, parts of the graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques (such as, pipelining operations) that attempt to parallel process as much graphics data as possible throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, multiple groups of parallel threads attempt to execute program instructions synchronously together as often as possible to improve processing efficiency. A general overview of the software and hardware for the SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37 - 51 (2013) and / or Nicholas Wilt's CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2 to 3.1.2 (June 2013).

[0004] Machine learning has been successful in solving many kinds of tasks. The computations that arise when training and using machine learning algorithms (e.g., neural networks) are naturally suited for efficient parallel implementation. Accordingly, parallel processors such as general-purpose graphics processing units (GPGPUs) have played an important role in the practical implementation of deep neural networks. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, multiple groups of parallel threads attempt to execute program instructions synchronously together as often as possible to improve processing efficiency. The efficiency provided by the implementation of parallel machine learning algorithms allows the use of high-capacity networks and enables the training of those networks on larger data sets.

[0005] Modern graphics processors provide a shared functionality (also known as "fixed functionality") pipeline and programmable execution units (EUs) or shader pipelines for use by applications. However, current solutions are limited to using either EUs or shared functional units ("SFUs", "shared functionality", or just "shaders"), which is inefficient and does not provide a balanced workload. This is particularly problematic with the rise of deep learning and convolutional neural networks (CNNs). BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following drawings, embodiments are illustrated by way of example and not by way of limitation, in which like reference numerals refer to similar elements. For a more particular description of the features briefly summarized above, reference may be made to the embodiments, some of which are illustrated in the drawings. It should be noted, however, that the drawings only illustrate typical embodiments and are not to be considered limiting of their scope, as the drawings may illustrate other equally effective embodiments.

[0007] Figure 1 is a block diagram of a computer system configured to implement one or more aspects of the embodiments described herein.

[0008] Figures 2A - 2D illustrates a parallel processor component according to an embodiment.

[0009] Figures 3A - 3B is a block diagram of a graphics multiprocessor according to an embodiment.

[0010] Figures 4A - 4F illustrates an exemplary architecture in which multiple graphics processing units are communicatively coupled to multiple multi-core processors.

[0011] Figure 5 is a conceptual diagram of a graphics processing pipeline according to an embodiment.

[0012] Figure 6 illustrates a computing device hosting a hybrid unit sharing mechanism according to one embodiment.

[0013] Figure 7 illustrates a hybrid unit sharing mechanism according to one embodiment.

[0014] Figure 8A illustrates a diagram showing the utilization of execution units for fixed-function based convolution.

[0015] Figure 8B illustrates a diagram showing the execution unit states for EU-based convolution.

[0016] Figure 8C illustrates a diagram showing convolution throughput.

[0017] Figure 8D Illustrates a conventional transaction sequence for the message flow between an execution unit and a shared functional pipeline.

[0018] Figure 9A Illustrates a comparison of pseudocode according to one embodiment.

[0019] Figure 9B Illustrates a framework for facilitating the hybrid use of an execution unit and a shared functional unit according to one embodiment.

[0020] Figure 9C Illustrates a transaction sequence for facilitating the hybrid use of an execution unit and a shared functional unit according to one embodiment.

[0021] Figure 9D Illustrates a framework for facilitating dynamic workflow balancing between an execution engine and a shared functional unit according to one embodiment.

[0022] Figure 10 Illustrates a machine learning software stack according to an embodiment.

[0023] Figure 11 Illustrates a highly parallel general-purpose graphics processing unit according to an embodiment.

[0024] Figure 12 Illustrates a multi-GPU computing system according to an embodiment.

[0025] Figures 13A - 13B Illustrates the layers of an exemplary deep neural network.

[0026] Figure 14 Illustrates the training and deployment of a deep neural network.

[0027] Figure 15 Illustrates the training and deployment of a deep neural network.

[0028] Figure 16 Is a block diagram illustrating distributed learning.

[0029] Figure 17 Illustrates an exemplary inference system-on-chip (SOC) 1700 suitable for performing inference using a trained model.

[0030] Figure 18 Is a block diagram of an embodiment of a computer system with a processor having one or more processor cores and a graphics processor.

[0031] Figure 19 Is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0032] Figure 20is a block diagram of an embodiment of a graphics processor that can be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores.

[0033] Figure 21 is a block diagram of an embodiment of a graphics processing engine for a graphics processor.

[0034] Figure 22 is a block diagram of another embodiment of a graphics processor.

[0035] Figure 23 is a block diagram of thread execution logic including an array of processing elements.

[0036] Figure 24 Illustrates a graphics processor execution unit instruction format according to an embodiment.

[0037] Figure 25 is a block diagram of another embodiment of a graphics processor including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a render output pipeline.

[0038] Figure 26A is a block diagram illustrating a graphics processor command format according to an embodiment.

[0039] Figure 26B is a block diagram illustrating a graphics processor command sequence according to an embodiment.

[0040] Figure 27 Illustrates an exemplary graphics software architecture for a data processing system according to an embodiment.

[0041] Figure 28 is a block diagram illustrating an IP core development system that can be used to fabricate an integrated circuit for performing operations according to an embodiment.

[0042] Figure 29 is a block diagram illustrating an exemplary system-on-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment.

[0043] Figure 30 is a block diagram illustrating an exemplary graphics processor of a system-on-chip integrated circuit.

[0044] Figure 31 is a block diagram illustrating an additional exemplary graphics processor of a system-on-chip integrated circuit. Detailed Description

[0045] Embodiments provide a novel technique for providing a hybrid mechanism to utilize both EU and SFU together for better performance and balanced workloads on a graphics processor. In one embodiment, queries can be inserted to check the state of the shared functional pipeline before dispatching workloads thereon. Now, for example, if it is determined that the SFU is busy, computations can be steered or fallback to the EU. This novel technique allows for dynamic balancing of workloads between the EU and the shared functional pipeline.

[0046] Note that terms or acronyms such as "convolutional neural network", "CNN", "neural network", "NN", "deep neural network", "DNN", "recurrent neural network", "RNN", etc. may be referred to interchangeably throughout this document. Additionally, terms such as "autonomous machine" or just "machine", "autonomous vehicle" or just "vehicle", "autonomous agent" or just "agent", "autonomous device" or "computing device", "robot", etc. may be referred to interchangeably throughout this document.

[0047] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., an internal processor bus / interconnect within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0048] In the following description, numerous specific details are set forth. However, embodiments as described herein may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0049] System Overview I

[0050] Figure 1FIG. is a block diagram of a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 that communicate via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within one or more of the processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, which may be included within one or more of the processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include a local display device, an internal display device, or an embedded display device.

[0051] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 that are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 may be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication fabric. In one embodiment, the one or more parallel processors 112 form a computationally concentrated parallel or vector processing system that includes a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that may output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable a direct connection to one or more display devices 110B.

[0052] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components that can be integrated into the platform, such as the network adapter 118 and / or the wireless network adapter 119, as well as various other devices that can be added via one or more plug-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless radio devices.

[0053] The computing system 100 can include other components not explicitly shown, such as USB or other port connectors, optical storage drives, video capture devices, etc., which can also be connected to the I / O hub 107. Figure 1 The communication paths interconnecting the various components can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocols known in the art).

[0054] In one embodiment, the one or more parallel processors 112 are combined with circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a Graphics Processing Unit (GPU). In another embodiment, the one or more parallel processors 112 are combined with circuitry optimized for general-purpose processing while retaining the underlying computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, the memory hub 105, the (one or more) processors 102, and the I / O hub 107 can be integrated into a System-on-Chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a System-in-Package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 can be integrated into a Multi-Chip Module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0055] It will be appreciated that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connection topology can be modified as needed, which includes the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, system memory 104 is connected directly to processors 102 rather than through a bridge, and other devices communicate with system memory 104 via memory hub 105 and processors 102. In other alternative topologies, parallel processors 112 are connected to I / O hub 107 or directly to one of one or more processors 102, rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 can be integrated into a single chip. Some embodiments can include two or more groups of processors 102 attached via multiple sockets, and these two or more groups can be coupled to two or more instances of parallel processors 112.

[0056] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of insertion cards or peripheral devices can be supported, or some components can be eliminated. Additionally, some architectures may use different terms for components similar to those illustrated Figure 1 herein. For example, in some architectures, memory hub 105 may be referred to as the north bridge, while I / O hub 107 may be referred to as the south bridge.

[0057] Figure 2A A parallel processor 200 is illustrated in accordance with an embodiment. The various components of parallel processor 200 can be implemented using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In accordance with an embodiment, the illustrated parallel processor 200 is Figure 1 a variant of one or more of the parallel processors 112 shown herein.

[0058] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface such as the memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, where the host interface 206 receives commands related to performing processing operations and the memory crossbar 216 receives commands related to performing memory operations.

[0059] When the host interface 206 receives command buffers via the I / O unit 204, the host interface 206 may direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled to a scheduler 210 that is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in an active state before distributing tasks to the processing clusters of the processing cluster array 212.

[0060] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B through cluster 214N). Each cluster 214A - 214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to the clusters 214A - 214N of the processing cluster array 212, and the scheduling and / or work distribution algorithms may vary according to the workload that occurs for each type of program or computation. Scheduling may be handled dynamically by the scheduler 210 or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the processing cluster array 212.

[0061] In one embodiment, different clusters 214A - 214N of the processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0062] The processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general - purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0063] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processors 200 are configured to perform graphics processing operations, the processing cluster array 212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 may be configured to execute graphics processing-related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing units 202 may transfer data from the system memory via the I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to the system memory.

[0064] In one embodiment, when the parallel processing units 202 are used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the multiple clusters 214A - 214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to generate a rendered image for display. Intermediate data generated by one or more of the clusters 214A - 214N may be stored in a buffer to allow the intermediate data to be transferred between the clusters 214A - 214N for further processing.

[0065] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include the data to be processed and indices of status parameters and commands defining how the data is to be processed (e.g., what program is to be executed), such as surface (patch) data, primitive data, vertex data, and / or pixel data. The scheduler 210 may be configured to obtain the index corresponding to the task or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured in a valid state before the workload specified in the incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0066] Each of one or more instances of the parallel processing unit 202 can be coupled to the parallel processor memory 222. The parallel processor memory 222 can be accessed via a memory crossbar 216 that can receive memory requests from the array of processing clusters 212 as well as the I / O unit 204. The memory crossbar 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include a plurality of partitioning units (e.g., partitioning unit 220A, partitioning unit 220B to partitioning unit 220N), each of which can be coupled to a portion (e.g., a memory unit) of the parallel processor memory 222. In one implementation, the number of partitioning units 220A - 220N is configured to be equal to the number of memory units such that the first partitioning unit 220A has a corresponding first memory unit 224A, the second partitioning unit 220B has a corresponding memory unit 224B, and the Nth partitioning unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partitioning units 220A - 220N may not be equal to the number of memory devices.

[0067] In various embodiments, the memory units 224A - 224N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM) which includes graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A - 224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A - 224N can vary and can be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps can be stored across the memory units 224A - 224N, allowing the partitioning units 220A - 220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 222. In some embodiments, a local instance of the parallel processor memory 222 can be excluded in favor of a unified memory design that utilizes system memory along with local cache memory.

[0068] In one embodiment, any one of the clusters 214A - 214N of the processing cluster array 212 can process data to be written to any of the memory units 224A - 224N within the parallel processor memory 222. The memory crossbar 216 can be configured to route the output of each cluster 214A - 214N to any of the partition units 220A - 220N or to another cluster 214A - 214N, which can perform additional processing operations on the output. Each cluster 214A - 214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has connections to the memory interface 218 to communicate with the I / O unit 204 and connections to local instances of the parallel processor memory 222, enabling processing units within different processing clusters 214A - 214N to communicate with system memory or other memory that is non - local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 can use virtual channels to separate the traffic flow between the clusters 214A - 214N and the partition units 220A - 220N.

[0069] Although a single instance of the parallel processing unit 202 is illustrated within the parallel processor 200, any number of instances of the parallel processing unit 202 can be included. For example, multiple instances of the parallel processing unit 202 can be provided on a single plug - in card, or multiple plug - in cards can be interconnected. Different instances of the parallel processing unit 202 can be configured to interoperate even if they have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example and in one embodiment, some instances of the parallel processing unit 202 can include floating - point units with higher precision relative to other instances. Systems incorporating one or more instances of the parallel processing unit 202 or the parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0070] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2AAn example of one of the partition units 220A - 220N. As illustrated, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. The L2 cache 221 outputs read misses and urgent writeback requests to the frame buffer interface 225 for processing. Dirty updates can also be sent to the frame buffer via the frame buffer interface 225 for opportunistic processing. In one embodiment, the frame buffer interface 225 docks with one of the memory cells in the parallel processor memory, such as (for example, within the parallel processor memory 222) Figure 2A the memory cells 224A - 224N.

[0071] In a graphics application, the ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. The ROP 226 then outputs the processed graphics data stored in the graphics memory. In some embodiments, the ROP 226 includes compression logic to compress z or color data written to the memory and decompress z or color data read from the memory. In some embodiments, the ROP 226 is included in each processing cluster (e.g., Figure 2A the clusters 214A - 214N) rather than in the partition unit 220. In such an embodiment, read and write requests for pixel data are transmitted through the memory crossbar 216 instead of pixel fragment data.

[0072] The processed graphics data can be displayed on a display device (such as Figure 1 one of the one or more display devices 110), routed for further processing by the (multiple) processors 102, or routed for further processing by Figure 2A one of the processing entities within the parallel processor 200.

[0073] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is Figure 2Aan instance of one of the processing clusters 214A - 214N. The processing clusters 214 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In some embodiments, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronous threads using a common instruction unit, which is configured to issue instructions to a set of processing engines within each of the processing clusters. Different from the SIMD execution regime where all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0074] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from Figure 2A a scheduler 210 and manages the execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures may be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and a data crossbar 240 can be used to distribute the processed data to one of a plurality of possible destinations including other shader units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0075] Each graphics multiprocessor 234 within the processing cluster 214 may include a set of identical functional execution logic (e.g., arithmetic logic units, load - store units, etc.). The functional execution logic can be configured in a pipelined manner, where new instructions can be issued before the previous instructions are completed. The functional execution logic can be provided. The functional logic supports a variety of operations, including integer and floating - point arithmetic comparison operations, boolean operations, shifts, and the calculation of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and there can be any combination of functional units.

[0076] Instructions transmitted to processing cluster 214 form threads. A set of threads executed across a set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycles in which the thread group is processed. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be executed in consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 234.

[0077] In one embodiment, graphics multiprocessor 234 includes an internal cache for performing load and store operations. In one embodiment, graphics multiprocessor 234 can forgo the internal cache and use the cache within processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 is also capable of accessing an L2 cache within a partition unit (e.g., Figure 2A partition units 220A - 220N) that is shared among all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data that can be stored in L1 cache 308.

[0078] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 can reside in Figure 2A memory interface 218. MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more discussion on tiling) and optionally to cache line indices. MMU 245 can include a translation lookaside buffer (TLB) or cache, which can reside within graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to allow for efficient request interleaving between partition units. Cache line indices can be used to determine whether a request to a cache line is a hit or a miss.

[0079] In graphics and computing applications, the processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. As needed, texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234 and fetched from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs a processed task to the data crossbar 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 216. The preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to the ROP units, which may be co-located with partition units (e.g., Figure 2A partition units 220A - 220N as described herein). The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0080] It will be appreciated that the core architectures described herein are illustrative and variations and modifications are possible. Any number of processing units, such as graphics multiprocessors 234, texture units 236, preROP 242, etc., may be included within the processing cluster 214. Additionally, although only one processing cluster 214 is shown, the parallel processing units as described herein may include any number of instances of the processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0081] Figure 2D A graphics multiprocessor 234 is shown in accordance with one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0082] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 may dispatch instructions as thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions may access any address space in the local, shared, or global address space by specifying an address within the unified address space. The address mapping unit 256 may be used to translate an address in the unified address space into a different memory address accessible by the load / store unit 266.

[0083] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for the operands of the data paths connected to the functional units (e.g., GPGPU core 262, load / store unit 266) of the graphics multiprocessor 324. In one embodiment, the register file 258 is partitioned among each of the functional units such that each functional unit is assigned a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned among different warps being executed by the graphics multiprocessor 324.

[0084] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of the graphics multiprocessor 324. According to embodiments, the GPGPU cores 262 may be similar in architecture or may be different in architecture. For example and in one embodiment, a first portion of the GPGPU cores 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU cores includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions such as copy rectangle or pixel blend operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0085] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfer between the GPGPU core 262 and the register file 258 has very low latency. The shared memory 270 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data transferred between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0086] Figures 3A - 3B Additional graphics multiprocessors according to embodiments are illustrated. The illustrated graphics multiprocessors 325, 350 are Figure 2C variants of the graphics multiprocessor 234. The illustrated graphics multiprocessors 325, 350 can be configured as streaming multiprocessors (SMs) capable of simultaneously executing a large number of execution threads.

[0087] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 includes multiple additional instances of the execution resource units associated with Figure 2D the graphics multiprocessor 234. For example, the graphics multiprocessor 325 can include multiple instances of instruction units 332A - 332B, register files 334A - 334B, and (multiple) texture units 344A - 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A - 336B, GPGPU cores 337A - 337B, GPGPU cores 338A - 338B) and multiple sets of load / store units 340A - 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346. The various components can communicate via an interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbars to enable communication between the various components of the graphics multiprocessor 325.

[0088] Figure 3Billustrates a graphics multi-processor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A - 356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load / store units, as Figure 2D and Figure 3A illustrated. The execution resources 356A - 356D can cooperate with (multiple) texture units 360A - 360D for texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A - 356D can share the instruction cache 354 and the shared memory 362 as well as multiple instances of texture and / or data caches 358A - 358B. Various components can communicate via an interconnect structure 352 similar to the interconnect structure 327 of Figure 3A .

[0089] Those skilled in the art will understand that Figure 1 , 2A - the architectures described in 2D and 3A - 3B are descriptive rather than restrictive in terms of the scope of embodiments of the present invention. Thus, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as Figure 2A the parallel processing unit 202), and one or more graphics processors or dedicated processing units, without departing from the scope of the embodiments described herein.

[0090] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions.

[0091] Techniques for GPU - to - Host Processor Interconnection

[0092] Figure 4AFIG. illustrates an exemplary architecture in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 440-443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the present invention are not limited to any specific communication protocol or throughput.

[0093] In addition, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which can be implemented using the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 can be connected via high-speed link 433, which can be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A all communication between the various system components shown in FIG. can be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the present invention are not limited to any specific type of interconnect technology.

[0094] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memories 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memories 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 can utilize the same or different memory access technologies. By way of example and not limitation, processor memories 401-402 and GPU memories 420-423 can be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories, such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory can be volatile memory while another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0095] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423 respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among all the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0096] Figure 4B Additional details of the interconnect between a multi-core processor 407 and a graphics acceleration module 446 in accordance with one embodiment are illustrated. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0097] The illustrated processor 407 includes multiple cores 460A-460D, each having a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The cores may include various other components for executing instructions and processing data (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.), which are not illustrated to avoid obscuring the basic principles of the present invention. The caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by a set of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 caches and one of the L3 caches are shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to a system memory 441, which may include the processor memories 401-402.

[0098] Consistency for data and instructions stored in various caches 462A - 462D, 456, and system memory 441 is maintained via inter - core communication through coherence bus 464. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein so as not to obscure the basic principles of the invention.

[0099] In one embodiment, proxy circuit 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. Specifically, interface 435 provides connectivity to proxy circuit 425 via high - speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0100] In one implementation, accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines 431, 432, N of graphics acceleration module 446. Graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, graphics processing engines 431, 432, N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431 - 432, N, or the graphics processing engines 431 - 432, N may be separate GPUs integrated on a common package, line card, or chip.

[0101] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in the cache 438 and the graphics memories 433-434, N is kept consistent with the core caches 462A-462D, 456 and the system memory 411. As mentioned, this can be done via the proxy circuit 425, which participates in the cache coherence mechanism on behalf of the cache 438 and the memories 433-434, N (e.g., sending updates related to the modification / access of cache lines on the processor caches 462A-462D, 456 to the cache 438 and receiving updates from the cache 438).

[0102] A set of registers 445 stores context data for the threads executed by the graphics processing engines 431-432, N, and the context management circuit 448 manages the thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore the contexts of various threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 448 may store the current register values into a specified area in memory (e.g., identified by a context pointer). It can then restore the register values when returning to that context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0103] In one implementation, the MMU 439 translates virtual / effective addresses from the graphics processing engine 431 into actual / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator modules 446 may be dedicated to a single application executed on the processor 407 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, where the resources of the graphics processing engines 431-432, N are shared among multiple applications or virtual machines (VMs). The resources may be divided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0104] Accordingly, the accelerator integrated circuit acts as a bridge to the system of the graphics acceleration module 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0105] Because the hardware resources of the graphics processing engines 431 - 432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431 - 432, N such that they appear to the system as independent units.

[0106] As mentioned, in the illustrated embodiment, one or more graphics memories 433 - 434, M are coupled to each of the graphics processing engines 431 - 432, N respectively. The graphics memories 433 - 434, M store the instructions and data being processed by each of the graphics processing engines 431 - 432, N. The graphics memories 433 - 434, M can be volatile memories such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non - volatile memories such as 3D XPoint or Nano - Ram.

[0107] In one embodiment, to reduce data traffic on the link 440, a biasing technique is used to ensure that the data stored in the graphics memories 433 - 434, M is the data that will be most frequently used by the graphics processing engines 431 - 432, N and is preferably not used (at least not frequently) by the cores 460A - 460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 431 - 432, N) within the caches 462A - 462D, 456 of the cores and the system memory 411.

[0108] Figure 4C Another embodiment is illustrated in which the accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431 - 432, N communicate directly with the accelerator integrated circuit 436 via interface 437 and interface 435 (again, which can utilize any form of bus or interface protocol) over a high - speed link 440. The accelerator integrated circuit 436 can perform the same operations as those described with respect to Figure 4B but may operate with higher throughput considering its close proximity to the coherence bus 462 and the caches 462A - 462D, 426.

[0109] One embodiment supports different programming models, which include a dedicated process programming model (without virtualization of the graphics acceleration module) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0110] In one embodiment of the dedicated process model, the graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. The single application can aggregate other application requests to the graphics engines 431-432, N, thus providing virtualization within the VM / partition.

[0111] In the dedicated process programming model, the graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize the graphics processing engines 431-432, N to allow access by each operating system. For a single-partition system without a hypervisor, the graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432, N to provide access to each process or application.

[0112] For the shared programming model, the graphics acceleration module 446 or a separate graphics processing engine 431-432, N uses a process handle to select a process element. In one embodiment, the process element is stored in the system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when it registers its context with the graphics processing engines 431-432, N (i.e., calls the system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0113] Figure 4D An exemplary accelerator integrated slice 490 is illustrated. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process elements 483 contain the process state for the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to the job request queue within the application's address space 482.

[0114] The graphics acceleration module 446 and / or the separate graphics processing engines 431-432, N can be shared by all or a subset of the processes in the system. Embodiments of the present invention include infrastructure for establishing a process state and sending a WD 484 to the graphics acceleration module 446 to start a job in a virtualized environment.

[0115] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owned partition, and the operating system initializes the accelerator integrated circuit 436 for the owned process when the graphics acceleration module 446 is assigned.

[0116] In operation, the WD fetch unit 491 in the accelerator integration slice 490 fetches the next WD 484, which includes an indication of the work to be done by one of the graphics processing engines in the graphics acceleration module 446. Data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447, and / or the context management circuit 446 as illustrated. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When performing a graphics operation, the MMU 439 converts the virtual address 493 generated by the graphics processing engines 431-432, N into a physical address.

[0117] In one embodiment, the same set of registers 445 is replicated for each of the graphics processing engines 431-432, N and / or the graphics acceleration module 446, and the same set of registers 445 can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integration slice 490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0118] Table 1 - Registers Initialized by the Hypervisor

[0119] 1 Slice Control Register 2 Real - Address (RA) Scheduled Process Region Pointer 3 Privilege Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real - Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Descriptor Register

[0120] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0121] Table 2 - Registers Initialized by the Operating System

[0122] 1 Process and Thread Identification 2 Effective - Address (EA) Context Save / restore Pointer 3 Virtual - Address (VA) Accelerator Utilization Record Pointer 4 Virtual - Address (VA) Storage Segment Table Pointer 5 Privilege Mask 6 Work Descriptor

[0123] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engines 431 - 432, N. It contains all the information that the graphics processing engines 431 - 432, N need to complete their work, or it can be a pointer to a memory location that points to a command queue where the work to be done has been established for the application.

[0124] Figure 4E Additional details of one embodiment of the shared model are illustrated. This embodiment includes a hypervisor real address space 498 in which a list of process elements 499 is stored. The hypervisor real address space 498 can be accessed via a hypervisor 496 that virtualizes the graphics acceleration module engine for the operating system 495.

[0125] The shared programming model allows all or a subset of the processes from all or a subset of the partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time - sliced sharing and graphics - directed sharing.

[0126] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functions available to all operating systems 495. To enable the graphics acceleration module 446 to support the virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The job requests of the application must be autonomous (i.e., do not need to maintain state between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees to complete the job requests of the application within a specified amount of time, including any translation faults, or the graphics acceleration module 446 provides the ability to preempt the processing of jobs. 3) When operating in the directed - sharing programming model, fairness of the graphics acceleration module 446 must be guaranteed between processes.

[0127] In one embodiment, for a shared model, the application 480 is required to use the graphics acceleration module 446 type, work descriptor (WD), access mask register (AMR) value, and context save / restore area pointer (CSRP) to make an operating system 495 system call. The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the following forms: a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure for describing the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the user access mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 can optionally apply the current access mask override register (AMOR) value before placing the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the valid address of a region in the application's address space 482 for the graphics acceleration module 446 to save and restore the context state. If saving state between jobs is not required or when a job is preempted, this pointer is optional. The context save / restore area can be pinned system memory.

[0128] Upon receiving the system call, the operating system 495 can verify that the application 480 is registered and has been granted permission to use the graphics acceleration module 446. The operating system 495 then uses the information shown in Table 3 to call the hypervisor 496.

[0129] Table 3 - OS Parameters for Hypervisor Call

[0130] 1 Work Descriptor (WD) 2 (Possibly Masked) Privilege Mask Register (AMR) Value 3 Effective - Address (EA) Context Save / restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual - Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0131] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 is registered and has been granted permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the linked list of process elements for the corresponding graphics acceleration module 446 type. The process element can include the information shown in Table 4.

[0132] Table 4 - Process Element Information

[0133] 1 Work Descriptor (WD) 2 (Possibly Masked) Privilege Mask Register (AMR) Value 3 Effective - Address (EA) Context Save / restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual - Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real - Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0134] In one embodiment, the hypervisor initializes a plurality of accelerator integrated slice 490 registers 445.

[0135] As Figure 4F Illustrated, one embodiment of the present invention employs a unified memory that can be addressed via a common virtual memory address space for accessing physical processor memories 401 - 402 and GPU memories 420 - 423. In this implementation, operations executed on GPUs 410 - 413 utilize the same virtual / effective memory address space to access processor memories 401 - 402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, and a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401 - 402 and GPU memories 420 - 423, allowing any processor or GPU to access any physical memory (using the virtual address mapped to that memory).

[0136] In one embodiment, bias / coherency management circuits 494A - 494E within one or more of MMUs 439A - 439E ensure cache coherency between the host processor (e.g., 405) and the caches of GPUs 410 - 413, and implement a biasing technique that indicates the physical memory in which certain types of data should be stored. Although multiple instances of bias / coherency management circuits 494A - 494E are illustrated Figure 4F in, the bias / coherency circuits can be implemented within the MMU of one or more host processors 405 and / or within accelerator integrated circuit 436.

[0137] One embodiment allows the GPU-attached memories 420-423 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) techniques without suffering the typical performance drawbacks associated with full-system cache coherence. The ability to access the GPU-attached memories 420-423 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access compute results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memories 420-423 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in the case of a large number of streaming write memory transactions, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 410-413. The efficiency of operand setting, result access, and GPU computation all play a role in determining the effectiveness of GPU offloading.

[0138] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granularity structure (i.e., controlled at the granularity of memory pages) that includes 1 or 2 bits per GPU-attached memory page. The bias table can be implemented in the stolen memory ranges of one or more of the GPU-attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., to cache frequently / most recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0139] In one implementation, the bias table entry associated with each access to the GPU-attached memories 420-423 is accessed prior to actually accessing the GPU memory, which causes the following operations. First, local requests from the GPUs 410-413 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memories 420-423. (e.g., via a high-speed link as discussed above) Local requests from the GPUs that find their pages in the host bias are forwarded to the processor 405. In one embodiment, requests from the processor 405 that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests involving GPU-bias pages can be forwarded to the GPUs 410-413. If the GPU is not currently using the page, the GPU can then convert the page to the host processor bias.

[0140] The bias state of a page can be changed by a software-based mechanism, a software mechanism assisted by hardware, or a pure hardware mechanism for a limited set of cases.

[0141] One mechanism for changing the bias state uses an API call (such as OpenCL), which in turn calls the device driver of the GPU. The device driver then sends a message (or enqueues a command descriptor) to the GPU to instruct it to change the bias state, and for certain transitions, a cache flush operation is performed in the host. The cache flush operation is required for the transition from the host processor 405 bias to the GPU bias, but not for the reverse transition.

[0142] In one embodiment, cache coherence is maintained by temporarily exposing GPU-biased pages that are non-cacheable by the host processor 405. To access these pages, the processor 405 can request access from the GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between the processor 405 and the GPU 410, it is beneficial to ensure that the GPU-biased pages are those that the GPU needs but not the host processor 405, and vice versa.

[0143] Graphics Processing Pipeline

[0144] Figure 5 Illustrated is a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein (such as Figure 2A the parallel processor 200), which in one embodiment is a variant of the (multiple) parallel processors 112 of Figure 1 Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit as described herein (e.g., Figure 2A the parallel processing unit 202). For example, a shader unit (e.g., Figure 2D the graphics multiprocessor 234 of Figure 3A may be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines and corresponding partitioning units within a processing cluster (e.g., Figure 2Cby partition units 220A - 220N). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more parts of the graphics processing pipeline 500 can be executed by parallel processing logic within a general - purpose processor (e.g., a CPU). In one embodiment, one or more parts of the graphics processing pipeline 500 can access on - chip memory (e.g., parallel processor memory 222 as in Figure 2A through a memory interface 528, and the memory interface 528 can be an Figure 2A instance of the memory interface 218 of

[0145] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to light and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data and can be programmed to transform the vertex data from an object - based coordinate representation to a world - space coordinate space or a normalized device coordinate space.

[0146] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., as supported by various graphics processing application programming interfaces (APIs).

[0147] The tessellation control processing unit 508 treats the input vertices as control points for geometric patches. The control points are transformed from an input representation (e.g., the basis of the patch) for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate tessellation factors for the edges of geometric patches. The tessellation factors apply to individual edges and quantify view - dependent levels of detail associated with the edges. The tessellation unit 510 is configured to receive the tessellation factors for the edges of a patch and subdivide the patch into multiple geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate vertex attributes and surface representations for each vertex associated with the geometric primitives.

[0148] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide a graphics primitive into one or more new graphics primitives and compute parameters for rasterizing the new graphics primitives.

[0149] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices that specify the new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing the geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0150] The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on the new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524.

[0151] The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 may be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operations unit 526. The fragment / pixel processing unit 524 may read data stored in the parallel processor memory or system memory for use in processing the fragment data. The fragment or pixel shader program may be configured to shade at a sample, pixel, tile, or other granularity according to the sampling rate configured for the processing unit.

[0152] The raster operations unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, etc., and outputs the pixel data as processed graphics data for storage in the graphics memory (e.g., the parallel processor memory 222 as in Figure 2A and / or as in Figure 1in the system memory 104) for display on one or more display devices 110 or for further processing by one of the one or more processors 102 or (a) parallel processor(s) 112. In some embodiments, the raster operation unit 526 is configured to compress z or color data written to memory and decompress z or color data read from memory.

[0153] Figure 6 FIG. illustrates a computing device 600 with a hosted hybrid unit sharing mechanism (“hybrid mechanism”) 610 according to one embodiment. The computing device 600 represents a communication and data processing device, which includes (but is not limited to) smart wearable devices, smart phones, virtual reality (VR) devices, head-mounted displays (HMDs), mobile computers, Internet of Things (IoT) devices, laptop computers, desktop computers, server computers, etc., and is similar or identical to Figure 1 the computing system 100; accordingly, for the sake of brevity, clarity, and ease of understanding, many of the details referred to above Figures 1 to 5 are not further discussed or repeated hereinafter.

[0154] The computing device 600 may further include (but is not limited to) autonomous machines or artificial intelligence agents, such as mechanical agents or machines, electronic agents or machines, virtual agents or machines, electromechanical agents or machines, etc. Examples of autonomous machines or artificial intelligence agents may include (but are not limited to) robots, autonomous vehicles (e.g., self-driving cars, self-flying airplanes, self-navigating ships, etc.), autonomous equipment (self-operating construction vehicles, self-operating medical equipment, etc.), and so on. Throughout this document, “computing device” may be interchangeably referred to as “autonomous machine” or “artificial intelligence agent” or simply “robot”.

[0155] It is contemplated that although “autonomous vehicle” and “self-driving” are referred to throughout this document, the embodiments are not so limited. For example, “autonomous vehicle” is not limited to automobiles, but may include any number and type of autonomous machines, such as robots, autonomous equipment, home autonomous devices, etc., and any one or more tasks or operations related to such autonomous machines may be interchangeably referred to with respect to self-driving.

[0156] The computing device 600 may further include (but is not limited to) large computing systems such as server computers, desktop computers, etc., and may further include set-top boxes (e.g., Internet-based cable TV set-top boxes, etc.), global positioning system (GPS)-based devices, etc. The computing device 600 may include mobile computing devices that act as communication devices, such as cellular phones including smart phones, personal digital assistants (PDAs), tablet computers, laptop computers, e-readers, smart TVs, TV platforms, wearable devices (e.g., glasses, watches, bracelets, smart cards, jewelry, clothing items, etc.), media players, etc. For example, in one embodiment, the computing device 600 may include a mobile computing device employing a managed integrated circuit (“IC”) such as a system on a chip (“SoC” or “SOC”), which integrates various hardware and / or software components of the computing device 600 on a single chip.

[0157] As illustrated, in one embodiment, the computing device 600 may include any number and type of hardware and / or software components, such as (but not limited to) a graphics processing unit (“GPU” or just “graphics processor”) 614, a graphics driver (also referred to as “GPU driver”, “graphics driver logic”, “driver logic”, user mode driver (UMD), UMD, user mode driver framework (UMDF), UMDF or just “driver”) 616, a central processing unit (“CPU” or just “application processor”) 612, a memory 608, network devices, drivers, etc. and input / output (I / O) sources 604 such as touchscreens, touch panels, touch pads, virtual or regular keyboards, virtual or regular mice, ports, connectors, etc. The computing device 600 may include an operating system (OS) 606, which acts as an interface between the hardware and / or physical sources of the computer device 600 and the user. It is contemplated that the graphics processor 614 and the application processor 612 may be Figure 1 one or more of the (multiple) processors 102.

[0158] It should be appreciated that for some implementations, systems with less or more equipment than the above examples may be preferred. Thus, the configuration of the computing device 600 may vary with the implementation depending on many factors such as price constraints, performance requirements, technological improvements, or other circumstances.

[0159] An embodiment can be implemented as any one or combination of the following: one or more microchips or integrated circuits interconnected using a motherboard, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and / or a field programmable gate array (FPGA). As an example, the terms "logic", "module", "component", "engine", and "mechanism" can include software or hardware and / or a combination of software and hardware.

[0160] In one embodiment, the hybrid mechanism 610 can be hosted or facilitated by the operating system 606 of the computing device 600. In another embodiment, the hybrid mechanism 610 can be hosted by, or be part of, the firmware of the graphics processing unit ("GPU" or just "graphics processor") 614 or the graphics processor 614. Similarly, in yet another embodiment, the hybrid mechanism 610 can be hosted by, or be part of, the central processing unit ("CPU" or just "application processor") 612. In yet another embodiment, the hybrid mechanism 610 can be hosted by, or be part of, any number and type of components of the computing device 600. For example, a portion of the hybrid mechanism 610 can be hosted by, or be part of, the operating system 606, another portion can be hosted by, or be part of, the graphics processor 614, another portion can be hosted by, or be part of, the application processor 612, and one or more portions of the hybrid mechanism 610 can be hosted by, or be part of, the operating system 606 and / or any number and type of devices of the computing device 600. It is contemplated that one or more portions or components of the hybrid mechanism 610 can be implemented as hardware, software, and / or firmware.

[0161] It is contemplated that the embodiments are not limited to any particular implementation or hosting of the hybrid mechanism 610, and the hybrid mechanism 610 and one or more of its components can be implemented as hardware, software, firmware, or any combination thereof.

[0162] The computing device 600 may host one or more host network interfaces to provide access to a network such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a mobile network (e.g., 3rd generation (3G), 4th generation (4G), etc.), an intranet, the Internet, and the like. The one or more network interfaces may include, for example, a wireless network interface having an antenna, which may represent one or more antennas. The one or more network interfaces may also include, for example, a wired network interface that communicates with a remote device via a network cable, which may be, for example, an Ethernet cable, a coaxial cable, an optical fiber cable, a serial cable, or a parallel cable.

[0163] Embodiments may be provided, for example, as a computer program product that may include one or more machine-readable media having machine-executable instructions stored thereon, which when executed by one or more machines such as a computer, a computer network, or other electronic devices, may cause the one or more machines to perform operations in accordance with the embodiments described herein. Machine-readable media may include, but are not limited to, floppy disks, optical disks, CD-ROMs (compact disc read-only memories), and magneto-optical disks, ROMs, RAMs, EPROMs (erasable programmable read-only memories), EEPROMs (electrically erasable programmable read-only memories), magnetic or optical cards, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions.

[0164] In addition, embodiments may be downloaded as a computer program product, where the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem and / or a network connection), embodied in a carrier wave or other propagation medium, and / or modulated by a carrier wave or other propagation medium, by one or more data signals.

[0165] Throughout this document, the term "user" may be interchangeably referred to as "viewer", "observer", "person", "individual", "end user", and / or the like. Note that throughout this document, terms such as "graphics domain" may be interchangeably referred to as "graphics processing unit", "graphics processor", or simply "GPU", and similarly, "GPU domain" or "host domain" may be interchangeably referred to as "computer processing unit", "application processor", or simply "CPU".

[0166] Note that throughout this document, terms such as "node", "compute node", "server", "server device", "cloud computer", "cloud server", "cloud server computer", "machine", "host", "device", "compute device", "computer", "compute system", etc. may be used interchangeably. Further note that throughout this document, terms such as "application", "software application", "program", "software program", "package", "software package", etc. may be used interchangeably. Similarly, throughout this document, terms such as "job", "input", "request", "message", etc. may be used interchangeably.

[0167] Figure 7 Illustrated is a Figure 6 hybrid mechanism 610 according to one embodiment. For brevity, many of the details discussed with reference to Figures 1 - 6 are not repeated or discussed hereinafter. In one embodiment, the hybrid mechanism 610 may include any number and type of components, such as (without limitation): detection / observation logic 701; status query / notification logic ("status logic") 703; decision / execution logic 705; communication / compatibility logic 707; and message logic 709.

[0168] As previously described, current graphics processors provide a shared functional pipeline and programmable EUs or shader pipelines for use by applications. The shared functions are typically hardware units that provide specialized complementary functions for the EUs. The EUs are considered to be highly programmable and flexible, while the SFUs are considered to be more efficient in terms of power and hardware area. However, conventional techniques have failed to utilize both the EUs and the SFUs.

[0169] In some embodiments, a communication mechanism called a message is used to perform calls to shared functions from EU threads. For example, on a particular platform, the number of SFUs may be limited and far fewer than the number of EU threads running simultaneously. If too many EU threads call a shared function, most of the EUs may need to queue up for their turn, which results in the EUs being stalled most of the time, while if the computation is done by the kernel, the EUs may remain active most of the time.

[0170] With the rise of deep learning and CNNs, GPUs (such as graphics processor 614) are widely used for accelerated computing in training and testing. The novel hybrid technique can be used to perform convolutions, such as video analysis (VA) that provides the ability to perform 2D convolutions, while the user can run OpenCL® kernels to perform convolutions.

[0171] Referring to Figure 8A, which illustrates the use of execution units that perform fixed-function convolutions, in FIG. 800. For example, the baseline could be a self-developed application that does convolution by using shared functionality and EU solutions. As illustrated, in the shared-function-based solution, the stall rate of the EU is quite high, reaching 88%. However, now referring to Figure 8B , which illustrates FIG. 820, which indicates that when the responsibility is placed on the EU, then in the EU-based solution, the stall percentage of the EU drops to only 8%.

[0172] Embodiments provide a novel technique for the hybrid use of EU and SFU together to achieve better processing results as facilitated by the hybrid mechanism 610. In one embodiment, detection / observation logic 701 can be used to detect and observe workload traffic, job requests, etc., and any information detected, received, or observed by the detection / dissent logic 701 can then be shared by the sharing logic 703 for further processing.

[0173] In one embodiment, the status logic 703 can be used to place a status query to check the status of the shared-function pipeline before dispatching any workload on the shared-function pipeline. For example, in response to placing the status query, the message gateway or any other eligible component in the pipeline can use the response or notification to indicate whether any SFU is busy or idle. For example, if the SFU is busy, any computation can only return to the EU, as determined and executed by the decision / execution logic 705. However, if it is determined that any SFU is available, any number and type of computational jobs, workloads, etc. can be forwarded to the available SFU for further processing, as determined and executed by the decision / execution unit 705. This novel hybrid technique allows for the dynamic balancing of workloads between the EU and SFU of the shared-function pipeline.

[0174] In one embodiment, as illustrated with respect to Figure 9A , the status logic 703 can be used to facilitate status queries and notifications between the message gateway unit and the instruction pipeline, such as placing a query to the message gateway unit to determine the status of the EU and / or SFU, and a notification indicating whether these units are busy or idle can be returned from the message gateway unit to the instruction pipeline.

[0175] As will be further illustrated in Figure 9A , in one embodiment, the message logic 709 can be used to perform one or more tasks involving messages, such as generating or creating messages that are transmitted from the instruction pipeline to the message register file, delivering messages to the SFU, and facilitating the processing of messages at and by the SFU. For example, the communication / compatibility logic 707 can be used to facilitate communication between the various components of the framework.

[0176] In one embodiment, the hybrid mechanism 610 provides the use of both EUs and SFUs to achieve better performance of the graphics processor 614. In one embodiment, as described above, the current state of the EUs and / or SFUs can be determined by simply inserting a query to check the state of the shared function pipeline before dispatching the workload on the shared function pipeline. If the shared function units are busy, the calculations can be done on the EUs. This novel technique allows the utilization of EUs and shared functions together, which further allows for the dynamic balancing of the workload between the EUs and SFUs, which in turn results in better EU utilization and overall performance.

[0177] Regarding improved EU utilization, regarding Figure 8C Illustrated is a conventional routed call to a shared function where the EU thread sends a message to the shared function pipeline, waits for the processing to complete, and retrieves the result. However, if all the shared function units are busy, the EUs are forced to wait, which results in the stalling of most EUs that can do nothing but wait.

[0178] The embodiment provides a novel technique that employs a query mechanism facilitated by state logic 703 to check the state before dispatching the workload and allows decision / execution logic 705 to facilitate the shared function pipeline to return the calculations to the EUs if the SFUs are busy.

[0179] Now, regarding load balancing, the embodiment provides dynamic load balancing between the EUs and SFUs. For example, when compared with some conventional static workload scheduling techniques, this novel hybrid technique facilitated by the hybrid mechanism 610 is based on an agnostic algorithm that can dynamically achieve load balancing. For example, in some simple cases of workload processing, the shared function may be 4 times faster than the EU; however, in some other complex cases of workload processing, this number may be as high as 8 times, which makes it difficult to determine the golden distribution in conventional static load balancing techniques.

[0180] Now refer to Figure 8C , which illustrates a graph 860 indicating the convolution throughput of the shared function 861, the EU 863, and the novel hybrid solution 865. Using two-dimensional (2D) convolution as an example, which is widely used in CNNs, the throughput 861 of the shared function solution is approximately 240 Gflop, while the throughput 863 of the EU is approximately 292 Gflop, which can vary with the kernel size and the size of the input data. Now, in one embodiment, as facilitated by the hybrid mechanism 610, the throughput 865 from the hybrid solution is almost 530 Gflop, which is the highest among the three, allowing the utilization of the computing power from two engines such as the EUs and SFUs to obtain better performance.

[0181] Refer back to Figure 7, the communication / compatibility logic 707 can be used to facilitate the required communication and compatibility between any number of devices of the computing device 600 and the various components of the hybrid mechanism 610.

[0182] The communication / compatibility logic 707 can be used to facilitate the dynamic communication and compatibility between the computing device 600 and the following while ensuring compatibility with changing technologies, parameters, protocols, standards, etc.: any number and type of other computing devices (such as mobile computing devices, desktop computers, server computing devices, etc.); processing devices or components (such as CPUs, GPUs, etc.); capture / sensing / detection devices (such as capture / sensing components, including cameras, depth-sensing cameras, camera sensors, red-green-blue (“RGB” or “rgb”) sensors, microphones, etc.); display devices (such as output components, including display screens, display areas, display projectors, etc.); user / context awareness components and / or identification / verification sensors / devices (such as biometric sensors / detectors, scanners, etc.); (multiple) databases 730, such as memory or storage devices, databases, and / or data sources (such as data storage devices, hard disk drives, solid state drives, hard disks, memory cards or devices, memory circuits, etc.); (multiple) communication media 725, such as one or more communication channels or networks (e.g., cloud networks, the Internet, intranets, cellular networks, proximity networks, such as Bluetooth, Bluetooth Low Energy (BLE), Bluetooth Smart, Wi-Fi Proximity, Radio Frequency Identification (RFID), Near Field Communication (NFC), Body Area Network (BAN), etc.); wireless or wired communication and related protocols (e.g., Wi-Fi®, WiMAX, Ethernet, etc.); connectivity and location management technologies; software applications / websites (such as social and / or business networking websites, etc., business applications, gaming and other entertainment applications, etc.); and programming languages, etc.

[0183] Furthermore, any use of specific trademarks, words, terms, phrases, names, and / or acronyms (such as "detection", "observation", "training", "mixing", "execution unit", "EU", "shared functional unit", "SFU", "shared function", "shader", "workload", "load balancing", "message", "message gateway", "agent", "machine", "vehicle", "robot", "drive", "CNN", "DNN", "NN", "execution unit", "EU", "shared local memory", "SLM", "graphics stream", "cache", "graphics cache", "GPU", "graphics processing unit", "GPU domain", "GPGPU", "CPU", "application processor", "CPU domain", "graphics drive", "workload", "application", "graphics pipeline", "pipelining process", "API", "3DAPI", "OpenGL®", "DirectX®", "hardware", "software", "agent", "graphics drive", "kernel mode graphics drive", "user mode drive", "user mode drive framework", "buffer", "graphics buffer", "task", "process", "operation", "software application", "game") should not be construed as limiting the embodiments to software or devices bearing that label in a product or in literature outside of this document.

[0184] It is envisioned that any number and type of components can be added to and / or removed from the hybrid mechanism 610 to facilitate various embodiments including adding, removing, and / or enhancing certain features. For the sake of brevity, clarity, and ease of understanding of the hybrid mechanism 610, many standard and / or known components, such as those of a computing device, are not shown or discussed here. It is envisioned that, as described herein, the embodiments are not limited to any particular technology, topology, system, architecture, and / or standard and are dynamic enough to adopt and adapt to any future changes.

[0185] Figure 8A Illustrated is a diagram 820 showing the utilization of an execution unit for fixed-function-based convolution as discussed above with reference to Figure 7 that.

[0186] Figure 8B Illustrated is a diagram 840 showing the state of an execution unit for EU-based convolution as discussed above with reference to Figure 7 that.

[0187] Figure 8C Illustrated is a diagram 860 showing the convolution throughputs 861, 863, 865 as discussed above with reference to Figure 7 that.

[0188] Figure 8DIllustrated is a conventional transaction 880 sequence of message flow between the EU and the shared functional pipeline. As illustrated, the communication between the EU and the shared pipeline is accomplished using packets of information called messages. Message transmission is requested via a send instruction. There are four basic phases of the message lifetime, such as: 1) message creation, where the EU thread at the instruction pipeline 881 assembles a message payload containing a message descriptor, input data, etc., and inputs it into the message register file (MRF) 883; 2) message delivery, where the EU thread issues a message for delivery from the MRF 883 to the SFU 885 via a send instruction; 3) message processing, where the target SFU 885 receives the message and services it accordingly; and 4) write-back response, where once the processing is complete, the SFU 865 sends the output data to the general register file (GRF) of the EU thread in response to the message.

[0189] Figure 9A Illustrated is a comparison 900 of the pseudocodes 901, 903 according to one embodiment. For the sake of brevity, many details previously referred to Figures 1 - 8D may not be discussed or repeated below. As illustrated, in the comparison of the conventional solution code 901 and the novel hybrid solution code 903, in one embodiment, changes to the compile time and the run time are provided. At compile time, as illustrated in the novel code 903, in one embodiment, the compiler is allowed to generate two branches for the built-in function, one of which is a branch to call the shared function via a message, and the other is used to call the EU instruction. At the start of the function, a query message can be created and sent to the message gateway to query the status of the shared functional pipeline. If the SFU is idle, the function can choose the shared function branch; otherwise, the EU branch can be chosen.

[0190] Figure 9B Illustrated is a framework 920 for facilitating the hybrid use of the EU and the SFU according to one embodiment. For the sake of brevity, many details previously referred to Figures 1 - 9A may not be discussed or repeated below. Any process involving the framework 920 can be executed by processing logic, which can include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof, as facilitated by Figure 6 the hybrid mechanism 610. For simplicity and clarity in the presentation, the processes associated with the framework 920 can be illustrated or described in a linear sequence; however, it is envisioned that any number of them can be executed in parallel, asynchronously, or in a different order. Additionally, the embodiments are not limited to any particular architectural arrangement, framework, or structure of components, such as the framework 920.

[0191] As illustrated, in one embodiment, the compiler is allowed to generate two branches for the built-in function, one of which is a branch that calls the shared function via a message, and the other is used to call the EU instruction. For example, in one embodiment, a message 931 can be generated by an EU thread at the instruction pipeline 921, and the message is then used by the message register file 923 and delivered 933 to the SFU 925, where it is processed 935 while writing back 937 a response to the instruction pipeline 921.

[0192] At the start of the function, in one embodiment, a status query message 941 can be created and sent to the message gateway 927 to query the status of the shared function pipeline, such as the status of the SFU 925. In one embodiment, in response to the status query message 941, the message gateway 927 issues a status notification message 943 with information on the status of the SFU 925 and the shared function pipeline. For example, if the status notification message 943 indicates that the SFU 925 is idle, the function can select the shared function branch; otherwise, the EU branch can be selected for processing.

[0193] In one embodiment, a query phase can be added at runtime, where the query phase includes generating and transmitting the status query message 941 and the status notification message 943. For example, the EU / instruction pipeline 921 sends the status query message 941 to the message gateway 927 and, in response, receives feedback, such as the status notification message 943, to indicate whether the shared function pipeline (such as the SFU 925) is busy or idle. The query is much faster than the computation in the shared function, where the criterion for being busy may mean that all shared function units (such as the SFU 925) are occupied or the length of the waiting queue exceeds a predefined threshold.

[0194] Figure 9C Illustrated is a transaction sequence 950 for facilitating the hybrid use of EU and SFU according to one embodiment. For the sake of brevity, many details previously referred to Figures 1 - 9B may not be discussed or repeated below. Any process involving the transaction sequence 950 can be executed by processing logic, which can include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof, as facilitated by Figure 6 the hybrid mechanism 610. For simplicity and clarity in the presentation, the processes associated with the transaction sequence 950 can be illustrated or described in a linear sequence; however, it is envisioned that any number of them can be executed in parallel, asynchronously, or in a different order. Additionally, the embodiments are not limited to any particular architectural arrangement, framework, or structure of components, such as the transaction sequence 950.

[0195] In the illustrated embodiment, the hosting message gateway 927 processes query messages 951 from EU threads. In one embodiment, the message gateway 927 pushes query requests or messages 951 through a first-in-first-out (FIFO) 953 and maintains a count to record the number of shared functional units such as SFU 955, 957, 959, 961 that are in use. If the count is less than a threshold, the EU thread may be instructed to be idle, such as IDLE, based on status notification messages related to SFU 955, 957, 959. For example, if one of the SFUs, such as SFU 961, is busy, a status notification message BUSY is returned. When an SFU 961 finishes its work, the count can then be decremented.

[0196] Figure 9D A framework 970 for facilitating dynamic workflow balancing between EUs and SFUs is illustrated according to one embodiment. For brevity, many details previously referenced may not be discussed or repeated below. Figures 1 - 9C Any process involving the framework 970 can be executed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof, as facilitated by Figure 6 the hybrid mechanism 610. For simplicity and clarity in the presentation, the processes associated with the framework 970 may be illustrated or described in a linear sequence; however, it is envisioned that any number of them may be executed in parallel, asynchronously, or in a different order. Additionally, embodiments are not limited to any particular architectural arrangement, framework, or structure of components, such as the framework 970.

[0197] In the illustrated embodiment, the workload 971 is shown to be dynamically balanced between the EU 975 and the shared functional pipeline 973. If the shared functional pipeline 973 is called busy, one or more of the workload 971 are directed or redirected back to the EU 975.

[0198] Machine Learning Overview

[0199] Machine learning algorithms are algorithms that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0200] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph where nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the inputs received by the input layer into representations useful for generating an output in the output layer. Network nodes are fully connected via edges to nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function that computes the state of the nodes in each successive layer of the network based on coefficients ("weights") associated respectively with each of the edges connecting these layers. Depending on the particular model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0201] Before a machine learning algorithm can be used to model a specific problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data that represents the problem being modeled by the network; and adjusting the weights until the network model exhibits a minimum error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output produced by the network in response to an input representing an instance in the training data set is compared with the "correct" labeled output for that instance; an error signal representing the difference between the output and the labeled output is computed; and the weights associated with the connections are adjusted to minimize the error as the error signal is propagated backward through the layers of the network. The network is considered "trained" when the error for each output generated from an instance in the training data set is minimized.

[0202] The accuracy of a machine learning algorithm is greatly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and may require a large amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks because the computations performed when adjusting the coefficients in a neural network are themselves naturally suited to parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0203] Figure 10is a generalized diagram of a machine learning software stack 1000. A machine learning application 1002 can be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. The machine learning application 1002 can include training and inference capabilities for neural networks and / or specialized software, which can be used to train a neural network before deployment. The machine learning application 1002 can implement any type of machine intelligence, including but not limited to: image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0204] Hardware acceleration for the machine learning application 1002 can be implemented via a machine learning framework 1004. The machine learning framework 1004 can provide a library of machine learning primitives. Machine learning primitives are the basic operations that machine learning algorithms typically perform. Without the machine learning framework 1004, developers of machine learning algorithms would need to create and optimize the main computational logic associated with the machine learning algorithm and then re-optimize the computational logic when a new parallel processor is developed. Instead, the machine learning application can be configured to perform the necessary computations using the primitives provided by the machine learning framework 1004. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 1004 can also provide primitives for implementing basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0205] The machine learning framework 1004 can process input data received from the machine learning application 1002 and generate appropriate inputs to a compute framework 1006. The compute framework 1006 can abstract the underlying instructions provided to a GPGPU driver 1008 so that the machine learning framework 1004 can utilize hardware acceleration via GPGPU hardware 1010 without the machine learning framework 1004 being very familiar with the architecture of the GPGPU hardware 1010. Additionally, the compute framework 1006 can implement hardware acceleration for the machine learning framework 1004 across multiple types and generations of GPGPU hardware 1010.

[0206] GPGPU Machine Learning Acceleration

[0207] Figure 11 Illustrates a highly parallel general-purpose graphics processing unit 1100 according to an embodiment. In one embodiment, a general-purpose processing unit (GPGPU) 1100 can be configured to be particularly efficient in processing this type of computational workload associated with training deep neural networks. Additionally, the GPGPU 1100 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster, thereby improving the training speed of particularly deep neural networks.

[0208] The GPGPU 1100 includes a host interface 1102 for implementing a connection with a host processor. In one embodiment, the host interface 1102 is a PCI Express interface. However, the host interface can also be a vendor-specific communication interface or communication fabric. The GPGPU 1100 receives commands from the host processor and uses a global scheduler 1104 to distribute execution threads associated with those commands to a set of compute clusters 1106A-H. The compute clusters 1106A-H share a cache memory 1108. The cache memory 1108 can act as a higher-level cache in the caches within the compute clusters 1106A-H.

[0209] The GPGPU 1100 includes memories 1114A-B that are coupled to the compute clusters 1106A-H via a set of memory controllers 1112A-B. In various embodiments, the memories 1114A-B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, the memory cells 224A-224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0210] In one embodiment, each compute cluster GPLAB06A-H includes a set of graphics multiprocessors, such as Figure 4A the graphics multiprocessor 400. The graphics multiprocessors of the compute clusters include various types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example and in one embodiment, at least a subset of the floating-point units in each of the compute clusters 1106A-H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0211] Multiple instances of GPGPU 1100 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 1100 communicate via host interface 1102. In one embodiment, GPGPU 1100 includes an I / O hub 1108 that couples GPGPU 1100 to GPU link 1110, which enables a direct connection to other instances of the GPGPU. In one embodiment, GPU link 1110 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1100. In one embodiment, GPU link 1110 is coupled to a high-speed interconnect for transferring and receiving data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 1100 are located in separate data processing systems and communicate via a network device that can be accessed via host interface 1102. In one embodiment, in addition to or as an alternative to host interface 1102, GPU link 1110 can be configured to enable connection to a host processor.

[0212] Although the illustrated configuration of GPGPU 1100 can be configured to train a neural network, one embodiment provides an alternative configuration of GPGPU 1100 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 1100 includes fewer computing clusters 1106A-H relative to the training configuration. Additionally, the memory technology associated with memories 1114A-B can differ between the inference and training configurations. In one embodiment, the inference configuration of GPGPU 1100 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions that are typically used during inference operations for deployed neural networks.

[0213] Figure 12 A multi-GPU computing system 1200 according to an embodiment is illustrated. The multi-GPU computing system 1200 can include a processor 1202 that is coupled to multiple GPGPUs 1206A-D via a host interface switch 1204. In one embodiment, host interface switch 1204 is a PCI Express switch device that couples processor 1202 to a PCI Express bus through which processor 1202 can communicate with this set of GPGPUs 1206A-D. Each of the multiple GPGPUs 1206A - 1206D can be Figure 11An instance of the GPGPU 1100. The GPGPUs 1206A-D can be interconnected via a set of high-speed point-to-point GPU-GPU links 1216. The high-speed GPU-GPU links can be connected to each of the GPGPUs 1206A-1206D via dedicated GPU links (such as, for example, the GPU link 1110 as shown in Figure 11 ). The P2P GPU links 1216 enable direct communication between each of the GPGPUs 1206A-D without having to communicate through the host interface bus to which the processor 1202 is connected. In the case of GPU-GPU traffic for the P2P GPU links, the host interface bus can still be used for system memory access or communication with other instances of the multi-GPU computing system 1200 (e.g., via one or more network devices). Although in the illustrated embodiment the GPGPUs 1206A-D are connected to the processor 1202 via the host interface switch 1204, in one embodiment, the processor 1202 includes direct support for the P2P GPU links 1216 and can be directly connected to the GPGPUs 1206A-D.

[0214] Machine Learning Neural Network Implementation

[0215] The computing architectures provided by the embodiments described herein can be configured to perform these types of parallel processing that are particularly suitable for training and deploying neural networks for machine learning. A neural network can generally be generalized as a network of functions having graph relationships. As is well known in the art, there are multiple types of neural network implementations used in machine learning. An exemplary type of neural network is the feedforward network as previously described.

[0216] A second exemplary type of neural network is a Convolutional Neural Network (CNN). A CNN is a specialized feedforward neural network for processing data with a known, grid-like topology, such as image data. Thus, CNNs are commonly used in computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized as a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in successive layers of the network. The computations used for a CNN include applying the convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function with respect to convolution can be referred to as the input, and the second function can be referred to as the convolution kernel. The output can be referred to as the feature map. For example, the input to a convolutional layer can be a multi-dimensional data array that defines the various color components of an input image. The convolution kernel can be a multi-dimensional parameter array, where the parameters are adapted through a training process for the neural network.

[0217] A Recurrent Neural Network (RNN) is a class of feedforward neural networks that includes feedback connections between layers. RNNs enable the modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. These loops represent the influence of the current value of a variable on its own value in the future, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature in which language data can be composed.

[0218] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe general processes for training and deploying each of those types of networks, respectively. It will be understood that the description is exemplary and non-limiting with respect to any particular embodiment described herein, and generally, the concepts illustrated can be applied to deep neural networks and machine learning techniques in general.

[0219] The exemplary neural networks described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error relative to shallow machine learning techniques.

[0220] Deep neural networks used in deep learning typically include a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without performing manual feature engineering for the model. Instead, the deep neural network can learn features based on the statistical structure or correlations within the input data. The learned features can be provided to the mathematical model, which can map the detected features to an output. The mathematical model used by the network is typically specific to the particular task to be performed, and different models will be used to perform different tasks.

[0221] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of error is a commonly used method for training neural networks. An input vector is presented to the network for processing. A loss function is used to compare the output of the network with the desired output, and an error value is calculated for each neuron in the output layer. These error values are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (such as the stochastic gradient descent algorithm) to update the weights of the neural network.

[0222] Figure 13A -Figure B illustrates an exemplary convolutional neural network. Figure 13A Illustrates the various layers within the CNN. As Figure 13A shown, an exemplary CNN for modeling image processing can receive an input 1302 that describes the red, green, and blue (RGB) components of the input image. The input 1302 can be processed by a plurality of convolutional layers (e.g., convolutional layer 1304, convolutional layer 1306). Optionally, the output from the plurality of convolutional layers can be processed by a set of fully connected layers 1308. Neurons in the fully connected layers have full connections to all the activations in the previous layer, as previously described for feedforward networks. The output from the fully connected layers 1308 can be used to generate an output result from the network. Matrix multiplication can be used instead of convolution to calculate the activations within the fully connected layers 1308. Not all CNN implementations use the fully connected layers 1308. For example, in some implementations, the convolutional layer 1306 can generate the output of the CNN.

[0223] The convolutional layer is sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 1308. Traditional neural network layers are fully connected such that each output unit interacts with each input unit. However, the convolutional layer is sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state values of each node in the receptive field) is input to the nodes of the subsequent layer, as illustrated. The kernel associated with the convolutional layer performs the convolution operation, and the output of the convolution operation is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables the CNN to scale to handle large images.

[0224] Figure 13B An exemplary computational stage within the convolutional layer of the CNN is illustrated. The input 1312 to the convolutional layer of the CNN can be processed in three stages of the convolutional layer 1314. These three stages can include a convolution stage 1316, a detector stage 1318, and a pooling stage 1320. The convolutional layer 1314 can then output the data to a successive convolutional layer. The last convolutional layer of the network can generate output feature map data or provide an input to the fully connected layer, for example, to generate a classification value for the input to the CNN.

[0225] A number of convolutions are performed in parallel in the convolution stage 1316 to produce a set of linear activations. The convolution stage 1316 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function connected to a specific region in the input (e.g., a neuron), which can be determined as the local region associated with the neuron. The neuron computes the dot product between the weights of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 1316 defines a set of linear activations to be processed by successive stages of the convolutional layer 1314.

[0226] The linear activations can be processed by the detector stage 1318. In the detector stage 1318, each linear activation is processed by a non - linear activation function. The non - linear activation function increases the non - linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non - linear activation functions can be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x)=max(0,x), such that the activation is thresholded at zero.

[0227] The pooling stage 1320 uses a pooling function that replaces the output of the convolutional layer 1306 with summary statistical values of nearby outputs. The pooling function can be used to introduce translational invariance into the neural network so that a slight translation of the input does not change the pooling output. Invariance to local translations can be useful in scenarios where the presence of features in the input data is more important than the exact location of the features. Various types of pooling functions can be used during the pooling stage 1320, including max pooling, average pooling, and L2 norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations substitute additional convolutional stages that have an increased stride relative to the previous convolutional stage.

[0228] Then, the output from the convolutional layer 1314 can be processed by the next layer 1322. The next layer 1322 can be either an additional convolutional layer or one of the fully connected layers 1308. For example, Figure 13A the first convolutional layer 1304 can output to the second convolutional layer 1306, and the second convolutional layer can output to the first of the fully connected layers 1308.

[0229] Figure 14 FIG. illustrates an exemplary recurrent neural network 1400. In a recurrent neural network (RNN), the previous state of the network affects the output of the network's current state. RNNs can be constructed in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, an RNN can be used to perform statistical language modeling to predict the upcoming word given a previous sequence of words. The illustrated RNN 1400 can be described as having the following: an input layer 1402 that receives an input vector; a hidden layer 1404 for implementing the recurrent function; a feedback mechanism 1405 for implementing the'memory' of the previous state; and an output layer 1406 for outputting the result. The RNN 1400 operates based on time steps. The state of the RNN at a given time step is affected based on the previous time step via the feedback mechanism 1405. For a given time step, the state of the hidden layer 1404 is defined by the previous state and the input at the current time step. The initial input (x 1 ) at the first time step can be processed by the hidden layer 1404. The second input (x 2 ) can be processed by the hidden layer 1404 using the state information determined during the processing of the initial input (x 1 ). A given state can be calculated as s t = f(Ux t + Ws t-1), where U and W are parameter matrices. The function f is typically non-linear, such as the hyperbolic tangent function (Tanh) or a variant of the rectifier function f(x) = max(0, x). However, the specific mathematical function used in the hidden layer 1404 can vary depending on the specific implementation details of the RNN 1400.

[0230] In addition to the basic CNN and RNN networks described, variations of those networks can also be implemented. An example RNN variant is the long short-term memory (LSTM) RNN. The LSTM RNN is capable of learning long-term dependencies that may be necessary for processing longer language sequences. A variant of the CNN is the convolutional deep belief network, which has a structure similar to the CNN and is trained in a manner similar to the deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. Greedy unsupervised learning can be used to train the DBN layer by layer. Then, the learned weights of the DBN can be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0231] Figure 15 Illustrated is the training and deployment of a deep neural network. Once a given network has been structured for a task, a training data set 1502 is used to train the neural network. Various training frameworks 1504 have been developed for implementing hardware acceleration of the training process. For example, Figure 10 the machine learning framework 1004 can be configured as the training framework 1504. The training framework 1504 can be hooked up to the untrained neural network 1506 and enable the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1508.

[0232] To initiate the training process, the initial weights can be selected randomly or by pre-training using a deep belief network. Then, the training loop can be performed in a supervised or unsupervised manner.

[0233] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training data set 1502 includes inputs (paired with their expected outputs), or when the training data set includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs to a set of expected or desired outputs. Then, the error is backpropagated through the system. The training framework 1504 can be adjusted to adjust the weights that control the untrained neural network 1506. The training framework 1504 can provide tools for monitoring how well the untrained neural network 1506 converges to a model suitable for generating correct answers based on the known input data. The training process occurs repeatedly as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 1508. Then, the trained neural network 1508 can be deployed to perform any number of machine learning operations.

[0234] Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1502 will include input data without any associated output data. The untrained neural network 1506 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1507 that can perform operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0235] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training data set 1502 includes a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used for further training of the model. Incremental learning enables the trained neural network 1508 to adapt to new data 1512 without forgetting the knowledge embedded in the network during initial training.

[0236] Regardless of whether it is supervised or unsupervised, the training process for particularly deep neural networks can be computationally intensive for a single computing node. A distributed network of computing nodes can be used instead of a single computing node to accelerate the training process.

[0237] Figure 16is a block diagram illustrating distributed learning. Distributed learning is the training of a model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. Each of the distributed computing nodes can include one or more host processors and one or more of general-purpose processing nodes, such as the highly parallel general-purpose graphics processing unit 1100 as in Figure 11 As illustrated, distributed learning can perform model parallelism 1602, data parallelism 1604, or a combination of model and data parallelism 1604.

[0238] In model parallelism 1602, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables the training of very large neural networks where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0239] In data parallelism 1604, different nodes of a distributed network have a complete instance of the model, and each node receives a different portion of the data. Then, the results from different nodes are combined. While different methods for data parallelism are possible, all data parallel training methods require a technique for combining the results and synchronizing the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that holds the parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of passing the parameters from the nodes to the parameter server, updates to the model are passed. Additionally, update-based data parallelism can be performed in a decentralized manner where the updates are compressed and passed between nodes.

[0240] For example, combined model and data parallelism 1606 can be implemented in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, where individual GPUs within each node are used to train different parts of the model.

[0241] Distributed training has increased overhead compared to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for implementing high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization.

[0242] Exemplary Machine Learning Applications

[0243] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The scope of applications of computer vision ranges from reproducing human visual capabilities (such as recognizing human faces) to creating new classes of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in objects visible in a video. Machine learning accelerated by parallel processors enables the use of training data sets that are significantly larger than previously feasible to train computer vision applications, and enables the deployment of inference systems using low-power parallel processors.

[0244] Machine learning accelerated by parallel processors has applications in autonomous driving, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein can enable the rapid training of increasingly complex neural networks for autonomous driving solutions, and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0245] Parallel-processor-accelerated deep neural networks have enabled machine learning methods for automatic speech recognition (ASR). ASR includes creating a function that computes the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled replacing the hidden Markov model (HMM) and Gaussian mixture model (GMM) previously used for ASR.

[0246] Parallel-processor-accelerated machine learning can also be used to accelerate natural language processing. An automatic learning program can use statistical inference algorithms to produce models that are robust to errors or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0247] The parallel processing platforms for machine learning can be divided into a training platform and a deployment platform. The training platform is typically highly parallel and includes optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 11 the highly parallel general-purpose graphics processing unit 1100 and Figure 12 the multi-GPU computing system 1200. In contrast, the deployed machine learning platforms typically include lower-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0248] Figure 17 An exemplary inference system-on-a-chip (SOC) 1700 suitable for performing inference using a trained model is illustrated. The SOC 1700 may integrate processing components, including a media processor 1702, a vision processor 1704, a GPGPU 1706, and a multi-core processor 1708. The SOC 1700 may additionally include on-chip memory 1705, which may implement a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1700 may be used as part of a main control system for an autonomous vehicle. When the SOC 1700 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards for deployment jurisdictions.

[0249] During operation, the media processor 1702 and the vision processor 1704 may work in concert to accelerate computer vision operations. The media processor 1702 may enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams may be written to a buffer in the on-chip memory 1705. Then, the vision processor 1704 may parse the decoded video and perform preliminary processing operations on the frames of the decoded video to prepare the frames for processing using a trained image recognition model. For example, the vision processor 1704 may accelerate convolutional operations for a CNN (for performing image recognition on high-resolution video data), and the backend model computations are performed by the GPGPU 1706.

[0250] The multi-core processor 1708 may include control logic to facilitate the ordering and synchronization of data transfers and shared memory operations performed by the media processor 1702 and the vision processor 2504. The multi-core processor 1708 may also act as an application processor to execute software applications that may use the inference computing capabilities of the GPGPU 1706. For example, at least a portion of the navigation and driving logic may be implemented as software executed on the multi-core processor 1708. Such software may directly issue a computational workload to the GPGPU 1706, or may issue a computational workload to the multi-core processor 1708, which may offload at least a portion of those operations to the GPGPU 1706.

[0251] The GPGPU 1706 may include a compute cluster, such as a low-power configuration of compute clusters 1106A-1106H within the highly parallel general-purpose graphics processing unit 1100. The compute clusters within the GPGPU 1706 may support instructions that are specifically optimized for performing inference computations on a trained neural network. For example, the GPGPU 1706 may support instructions for performing low-precision computations, such as 8-bit and 4-bit integer vector operations.

[0252] System Overview II

[0253] Figure 18 is a block diagram of a processing system 1800 according to an embodiment. In various embodiments, the system 1800 includes one or more processors 1802 and one or more graphics processors 1808, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1802 or processor cores 1807. In one embodiment, the system 1800 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile device, a handheld device, or an embedded device.

[0254] Embodiments of the system 1800 may include or be incorporated into the following: a server-based gaming platform; a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, the system 1800 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. The data processing system 1800 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), coupled to, or integrated within, the wearable device. In some embodiments, the data processing system 1800 is a television or set-top box device having one or more processors 1802 and a graphical interface generated by one or more graphics processors 1808.

[0255] In some embodiments, each of one or more processors 1802 includes one or more processor cores 1807 for processing instructions that, when executed, perform the operations of system and user software. In some embodiments, each of the one or more processor cores 1807 is configured to process a particular instruction set 1809. In some embodiments, the instruction set 1809 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). The multiple processor cores 1807 may each process a different instruction set 1809, which may include instructions for facilitating the emulation of other instruction sets. The processor cores 1807 may also include other processing devices, such as a digital signal processor (DSP).

[0256] In some embodiments, the processor 1802 includes a cache memory 1804. Depending on the architecture, the processor 1802 may have a single internal cache or multiple levels of internal caches. In some embodiments, the cache memory is shared among the various components of the processor 1802. In some embodiments, the processor 1802 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), and known cache coherence techniques may be used to share the external cache among the processor cores 1807. Additionally, a register file 1806 is included in the processor 1802, and the processor may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1802.

[0257] In some embodiments, the processor 1802 is coupled to a processor bus 1810 for transferring communication signals, such as addresses, data, or control signals, between the processor 1802 and other components in the system 1800. In one embodiment, the system 1800 uses an exemplary 'hub' system architecture that includes a memory controller hub 1816 and an input / output (I / O) controller hub 1830. The memory controller hub 1816 facilitates communication between the memory device and other components of the system 1800, while the I / O controller hub (ICH) 1830 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1816 is integrated within the processor.

[0258] The memory device 1820 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to act as a processing memory. In one embodiment, the memory device 1820 can operate as the system memory of the system 1800 to store data 1822 and instructions 1821 for use when one or more processors 1802 execute an application or process. The memory controller hub 1816 is also coupled to an optional external graphics processor 1812, which can communicate with one or more graphics processors 1808 in the processor 1802 to perform graphics and media operations.

[0259] In some embodiments, the ICH 1830 enables peripheral devices to be connected to the memory device 1820 and the processor 1802 via a high-speed I / O bus. The I / O peripheral devices include but are not limited to: an audio controller 1846, a firmware interface 1828, a wireless transceiver 1826 (e.g., Wi-Fi, Bluetooth), a data storage device 1824 (e.g., a hard disk drive, a flash memory, etc.), and a legacy I / O controller 1840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more universal serial bus (USB) controllers 1842 connect input devices such as a keyboard and mouse 1844 combination. A network controller 1834 can also be coupled to the ICH 1830. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1810. It will be appreciated that the system 1800 shown is exemplary and not restrictive, as other types of data processing systems configured in different ways can also be used. For example, the I / O controller hub 1830 can be integrated within one or more processors 1802, or the memory controller hub 1816 and the I / O controller hub 1830 can be integrated into a discrete external graphics processor (such as the external graphics processor 1812).

[0260] Figure 19 is a block diagram of an embodiment of a processor 1900 having one or more processor cores 1902A - 1902N, an integrated memory controller 1914, and an integrated graphics processor 1908. Figure 19Those elements having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto. The processor 1900 may include additional cores up to and including additional core 1902N represented by the dashed box. Each of the processor cores 1902A - 1902N includes one or more internal cache units 1904A - 1904N. In some embodiments, each processor core may also have access to one or more shared cache units 1906.

[0261] The internal cache units 1904A - 1904N and the shared cache units 1906 represent the cache memory hierarchy within the processor 1900. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid - level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest - level cache before the external memory is classified as the LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1906 and 1904A - 1904N.

[0262] In some embodiments, the processor 1900 may also include a set of one or more bus controller units 1916 and a system agent core 1910. The one or more bus controller units 1916 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1910 provides management functions for various processor components. In some embodiments, the system agent core 1910 includes one or more integrated memory controllers 1914 to manage access to various external memory devices (not shown).

[0263] In some embodiments, one or more of the processor cores 1902A - 1902N include support for simultaneous multithreading. In such embodiments, the system agent core 1910 includes components for coordinating and operating the cores 1902A - 1902N during multithreaded processing. Additionally, the system agent core 1910 may also include a power control unit (PCU) that includes logic and components for regulating the power states of the processor cores 1902A - 1902N as well as the graphics processor 1908.

[0264] In some embodiments, additionally, the processor 1900 further includes a graphics processor 1908 for performing graphics processing operations. In some embodiments, the graphics processor 1908 is coupled to the shared cache unit 1906 set and the system agent core 1910, and the system agent core includes one or more integrated memory controllers 1914. In some embodiments, the display controller 1911 is coupled to the graphics processor 1908 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1911 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1908 or the system agent core 1910.

[0265] In some embodiments, the ring-based interconnect unit 1912 is used to couple the internal components of the processor 1900. However, alternative interconnect units can be used, such as point-to-point interconnects, switched interconnects, or other techniques, including techniques well known in the art. In some embodiments, the graphics processor 1908 is coupled to the ring interconnect 1912 via an I / O link 1913.

[0266] The exemplary I / O link 1913 represents at least one of a plurality of varieties of I / O interconnects, including a package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1918 (such as an eDRAM module). In some embodiments, each of the processor cores 1902A - 1902N and the graphics processor 1908 uses the embedded memory module 1918 as a shared last-level cache.

[0267] In some embodiments, the processor cores 1902A - 1902N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 1902A - 1902N are heterogeneous in terms of the instruction set architecture (ISA), where one or more of the processor cores 1902A - N execute a first instruction set, and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 1902A - 1902N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled to one or more power-efficient cores with lower power consumption. Additionally, the processor 1900 can be implemented on one or more chips or as a SoC integrated circuit having the illustrated components among other components.

[0268] Figure 20is a block diagram of a graphics processor 2000, which can be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and uses commands placed in the processor memory. In some embodiments, the graphics processor 2000 includes a memory interface 2014 for accessing memory. The memory interface 2014 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0269] In some embodiments, the graphics processor 2000 further includes a display controller 2002 for driving display output data to a display device 2020. The display controller 2002 includes hardware for one or more overlapping planes of the display and the composition of multi-layer video or user interface elements. In some embodiments, the graphics processor 2000 includes a video codec engine 2006 for encoding media into one or more media coding formats, decoding media from one or more media coding formats, or transcoding media between one or more media coding formats, the one or more media coding formats including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG), and Motion JPEG (MJPEG) formats.

[0270] In some embodiments, the graphics processor 2000 includes a block image transfer (BLIT) engine 2004 for performing two-dimensional (2D) rasterization operations (including, for example, bit boundary block transfer). However, in one embodiment, 2D graphics operations are performed using one or more components of the graphics processing engine (GPE) 2010. In some embodiments, the graphics processing engine 2010 is a computing engine for performing graphics operations, the graphics operations including three-dimensional (3D) graphics operations and media operations.

[0271] In some embodiments, the GPE 2010 includes a 3D pipeline 2012 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2012 includes programmable and fixed-function elements that perform various tasks within the element and / or generate execution threads to the 3D / media subsystem 2015. Although the 3D pipeline 2012 can be used to perform media operations, embodiments of the GPE 2010 also include a media pipeline 2016 that is specifically for performing media operations, such as video post-processing and image enhancement.

[0272] In some embodiments, the media pipeline 2016 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, in place of or on behalf of the video codec engine 2006. In some embodiments, additionally, the media pipeline 2016 also includes a thread generation unit to generate threads for execution on the 3D / media subsystem 2015. The generated threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 2015.

[0273] In some embodiments, the 3D / media subsystem 2015 includes logic for executing threads generated by the 3D pipeline 2012 and the media pipeline 2016. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 2015, which includes thread dispatch logic for arbitrating various requests and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2015 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data between threads and storing output data.

[0274] 3D / Media Processing

[0275] Figure 21 is a block diagram of a graphics processing engine 2110 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2110 is Figure 20 a version of the GPE 2010 shown in Figure 21 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these. For example, illustrated Figure 203D pipeline 2012 and media pipeline 2016. The media pipeline 2016 is optional in some embodiments of the GPE 2110 and may not be explicitly included within the GPE 2110. For example and in at least one embodiment, a separate media and / or image processor is coupled to the GPE 2110.

[0276] In some embodiments, the GPE 2110 is coupled to or includes a command streamer 2103 that provides a command stream to the 3D pipeline 2012 and / or the media pipeline 2016. In some embodiments, the command streamer 2103 is coupled to a memory, which may be a system memory, or one or more caches of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 2103 receives commands from the memory and sends these commands to the 3D pipeline 2012 and / or the media pipeline 2016. The commands are instructions fetched from a ring buffer storing commands for the 3D pipeline 2012 and the media pipeline 2016. In one embodiment, additionally, the ring buffer may further include a batch command buffer storing multiple batches of multiple commands. Commands for the 3D pipeline 2012 may also include references to data stored in the memory, such as but not limited to vertex and geometry data for the 3D pipeline 2012 and / or image data and memory objects for the media pipeline 2016. The 3D pipeline 2012 and the media pipeline 2016 process commands and data by executing operations via logic within each pipeline or by dispatching one or more execution threads to the graphics core array 2114.

[0277] In various embodiments, the 3D pipeline 2012 may execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2114. The graphics core array 2114 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution units) within the graphics core array 2114 includes support for various 3D API shader languages and may execute multiple simultaneously executing threads associated with multiple shaders.

[0278] In some embodiments, the graphics core array 2114 further includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution units further include general-purpose logic programmable to perform parallel general-purpose computing operations in addition to graphics processing operations. The general-purpose logic may be associated with Figure 18 the (multiple) processor cores 1807 or as Figure 19The general logic within cores 1902A - 1902N performs processing operations either in parallel or in combination.

[0279] Output data generated by threads executing on the graphics core array 2114 can output data to memory in the unified return buffer (URB) 2118. The URB 2118 can store data for multiple threads. In some embodiments, the URB 2118 can be used to send data between different threads executing on the graphics core array 2114. In some embodiments, the URB 2118 can additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic 2120.

[0280] In some embodiments, the graphics core array 2114 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of the GPE 2110. In one embodiment, the execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0281] The graphics core array 2114 is coupled to the shared function logic 2120, which includes multiple resources shared among the graphics cores within the graphics core array. The shared functions within the shared function logic 2120 are hardware logic units that provide dedicated supplementary functions to the graphics core array 2114. In various embodiments, the shared function logic 2120 includes, but is not limited to, sampler 2121, math 2122, and inter - thread communication (ITC) 2123 logic. Additionally, some embodiments implement one or more caches 2125 within the shared function logic 2120. The shared function is implemented when the demand for a given dedicated function is not sufficient to be included within the graphics core array 2114. Instead, a single instantiation of the dedicated function is implemented as an independent entity within the shared function logic 2120 and shared among the execution resources within the graphics core array 2114. The exact set of functions shared among and included within the graphics core array 2114 varies between embodiments.

[0282] Figure 22 is a block diagram of another embodiment of the graphics processor 2200. Figure 22 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these.

[0283] In some embodiments, graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In some embodiments, ring interconnect 2202 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system.

[0284] In some embodiments, graphics processor 2200 receives batches of commands via ring interconnect 2202. The incoming commands are interpreted by command streamer 2203 in pipeline front end 2204. In some embodiments, graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via (multiple) graphics cores 2280A-2280N. For 3D geometry processing commands, command streamer 2203 supplies the commands to geometry pipeline 2236. For at least some media processing commands, command streamer 2203 supplies the commands to video front end 2234, which is coupled to media engine 2237. In some embodiments, media engine 2237 includes a video quality engine (VQE) 2230 for video and image post-processing and a multi-format encoding / decoding (MFX) 2233 engine for providing hardware-accelerated encoding and decoding of media data. In some embodiments, each of geometry pipeline 2236 and media engine 2237 generates execution threads for thread execution resources provided by at least one of graphics cores 2280A.

[0285] In some embodiments, the graphics processor 2200 includes scalable thread execution resources represented by modular cores 2280A - 2280N (sometimes referred to as core slices), each of which has a plurality of sub - cores 2250A - 2250N, 2260A - 2260N (sometimes referred to as core sub - slices). In some embodiments, the graphics processor 2200 can have any number of graphics cores 2280A - 2280N. In some embodiments, the graphics processor 2200 includes a graphics core 2280A that has at least a first sub - core 2250A and a second core sub - core 2260A. In other embodiments, the graphics processor is a low - power processor having a single sub - core (e.g., 2250A). In some embodiments, the graphics processor 2200 includes a plurality of graphics cores 2280A - 2280N, each of which includes a set of first sub - cores 2250A - 2250N and a set of second sub - cores 2260A - 2260N. Each sub - core in the set of first sub - cores 2250A - 2250N includes at least a first set of execution units 2252A - 2252N and media / texture samplers 2254A - 2254N. Each sub - core in the set of second sub - cores 2260A - 2260N includes at least a second set of execution units 2262A - 2262N and samplers 2264A - 2264N. In some embodiments, each sub - core 2250A - 2250N, 2260A - 2260N shares a set of shared resources 2270A - 2270N. In some embodiments, the shared resources include a shared cache memory and pixel operation logic. Other shared resources can also be included in various embodiments of the graphics processor.

[0286] Execution logic

[0287] Figure 23 Thread execution logic 2300 is illustrated, which includes an array of processing elements employed in some embodiments of the GPE. Figure 23 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these.

[0288] In some embodiments, the thread execution logic 2300 includes a pixel shader 2302, a thread dispatcher 2304, an instruction cache 2306, a scalable execution unit array including a plurality of execution units 2308A - 2308N, a sampler 2310, a data cache 2312, and a data port 2314. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, the thread execution logic 2300 includes one or more connections to memory (such as system memory or a cache) via the instruction cache 2306, the data port 2314, the sampler 2310, and one or more of the execution unit arrays 2308A - 2308N. In some embodiments, each execution unit (e.g., 2308A) is a separate vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, the execution unit array 2308A - 2308N includes any number of separate execution units.

[0289] In some embodiments, the execution unit array 2308A - 2308N is primarily used to execute "shader" programs. In some embodiments, the execution units in the array 2308A - 2308N execute an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal translation. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general - purpose processing (e.g., compute and media shaders).

[0290] Each execution unit in the execution unit array 2308A - 2308N operates on an array of data elements. The number of data elements is the "execution size", or the number of channels of an instruction. Execution channels are logical units for the execution of data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic - logic units (ALUs) or floating - point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2308A - 2308N support integer and floating - point data types.

[0291] The execution unit instruction set includes single instruction multiple data (SIMD) or single instruction multiple thread (SIMT) instructions. Various data elements can be stored in registers as compressed data types, and the execution unit processes the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (quad-word (QW) sized data elements), eight separate 32-bit compressed data elements (double-word (DW) sized data elements), sixteen separate 16-bit compressed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0292] One or more internal instruction caches (e.g., 2306) are included in the thread execution logic 2300 to cache the thread instructions of the execution unit. In some embodiments, one or more data caches (e.g., 2312) are included to cache thread data during thread execution. In some embodiments, a sampler 2310 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2310 includes specialized texture or media sampling functions to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0293] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2300 via the thread generation and dispatch logic. In some embodiments, the thread execution logic 2300 includes a local thread dispatcher 2304 that arbitrates the thread initiation requests from the graphics and media pipeline and instantiates the requested threads on one or more execution units 2308A - 2308N. For example, the geometry pipeline (e.g., Figure 22 2236) dispatches vertex processing, tessellation, or geometry processing threads to the thread execution logic 2300 ( Figure 23 ). In some embodiments, the thread dispatcher 2304 can also process runtime thread generation requests from an execution shader program.

[0294] Once a set of geometric objects has been processed and rasterized into pixel data, the pixel shader 2302 is invoked to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, the pixel shader 2302 computes values for various vertex attributes that are to be interpolated across the rasterized objects. In some embodiments, the pixel shader 2302 then executes a pixel shader program supplied by an application programming interface (API). To execute the pixel shader program, the pixel shader 2302 dispatches threads to execution units (e.g., 2308A) via a thread dispatcher 2304. In some embodiments, the pixel shader 2302 uses texture sampling logic in a sampler 2310 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and the input geometric data compute the pixel color data for each geometric fragment, or discard one or more pixels without further processing.

[0295] In some embodiments, the data port 2314 provides a memory access mechanism for the thread execution logic 2300 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 2314 includes or is coupled to one or more caches (e.g., the data cache 2312) to cache data via the data port for memory access.

[0296] Figure 24 is a block diagram illustrating a graphics processor instruction format 2400 according to some embodiments. In one or more embodiments, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid boxes illustrate components typically included in the execution unit instructions, while the dashed boxes include optional components or components only included in a subset of the instructions. In some embodiments, the described and illustrated instruction format 2400 is a macro-instruction because they are the instructions supplied to the execution unit, as contrasted with the micro-operations generated by instruction decoding once the instructions are processed.

[0297] In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format 2410. A 64-bit compressed instruction format 2430 may be used for some instructions based on selected instructions, instruction options, and the number of operands. The native 128-bit instruction format 2410 provides access to all instruction options, while some options and operations are restricted in the 64-bit instruction format 2430. The native instructions available in the 64-bit instruction format 2430 vary according to the embodiment. In some embodiments, a set of index values in an index field 2413 is used in part to compress the instructions. The execution unit hardware references a set of compression tables based on the index values and uses the compressed table output to reconstruct the native instructions in the 128-bit instruction format 2410.

[0298] For each format, instruction opcode 2412 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous addition operation across each color channel, which represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, instruction control field 2414 enables control of certain execution options such as channel selection (e.g., predication) and data channel order (e.g., shuffling). For 128-bit instruction 2410, execution size field 2416 limits the number of data channels that will be executed in parallel. In some embodiments, execution size field 2416 is not available for use in 64-bit compressed instruction format 2430.

[0299] Some execution unit instructions have up to three operands, including two source operands (src0 2420, src1 2422) and one destination 2418. In some embodiments, the execution unit supports dual-destination instructions, where one of these destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2424), where instruction opcode 2412 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0300] In some embodiments, 128-bit instruction format 2410 includes access / addressing mode information 2426, which, for example, specifies whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are provided directly by bits in instruction 2410.

[0301] In some embodiments, 128-bit instruction format 2410 includes an access / addressing mode field 2426, which specifies the addressing mode and / or access mode for the instruction. In one embodiment, the access mode defines the data access alignment for the instruction. Some embodiments support access modes, including 16-byte aligned access mode and 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, instruction 2410 may use byte-aligned addressing for source and destination operands, and when in a second mode, instruction 2410 may use 16-byte aligned addressing for all source and destination operands.

[0302] In one embodiment, the addressing mode portion of the access / addressing mode field 2426 determines whether the instruction is to use direct addressing or indirect addressing. When using the direct register addressing mode, the bits in the instruction 2410 directly provide the register addresses of one or more operands. When using the indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0303] In some embodiments, the instructions are grouped based on the opcode 2412 bit field to simplify opcode decoding 2440. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is only an example. In some embodiments, the move and logic opcode group 2442 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2442 share the five most significant bits (MSB), where the move (mov) instruction takes the form 0000xxxxb and the logic instruction takes the form 0001xxxxb. The flow control instruction group 2444 (e.g., call, jump (jmp)) includes instructions that take the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2446 includes a mix of instructions, including synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 2448 includes per-component arithmetic instructions (e.g., add, multiply (mul)) that take the form 0100xxxxb (e.g., 0x40). The parallel math group 2448 performs arithmetic operations in parallel across data channels. The vector math group 2450 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot product operations.

[0304] Graphics pipeline

[0305] Figure 25 is a block diagram of another embodiment of the graphics processor 2500. Figure 25 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these.

[0306] In some embodiments, the graphics processor 2500 includes a graphics pipeline 2520, a media pipeline 2530, a display engine 2540, thread execution logic 2550, and a render output pipeline 2570. In some embodiments, the graphics processor 2500 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued via a ring interconnect 2502 to the graphics processor 2500. In some embodiments, the ring interconnect 2502 couples the graphics processor 2500 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2502 are interpreted by a command streamer 2503, which supplies instructions to individual components of the graphics pipeline 2520 or the media pipeline 2530.

[0307] In some embodiments, the command streamer 2503 directs the operation of a vertex fetcher 2505, which reads vertex data from memory and executes vertex processing commands provided by the command streamer 2503. In some embodiments, the vertex fetcher 2505 provides vertex data to a vertex shader 2507, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 2505 and the vertex shader 2507 execute vertex processing instructions by dispatching execution threads to execution units 2552A, 2552B via a thread dispatcher 2531.

[0308] In some embodiments, the execution units 2552A, 2552B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, the execution units 2552A, 2552B have attached L1 caches 2551 that are dedicated to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0309] In some embodiments, the graphics pipeline 2520 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2511 configures the tessellation operation. A programmable domain shader 2517 provides backend evaluation of the tessellation output. The tessellator 2513 operates in the direction of the hull shader 2511 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2520. In some embodiments, if tessellation is not used, the tessellation components 2511, 2513, 2517 can be bypassed.

[0310] In some embodiments, a complete geometric object can be processed by the geometry shader 2519 via one or more threads dispatched to execution units 2552A, 2552B, or can proceed directly to the clipper 2529. In some embodiments, the geometry shader operates on the entire geometric object (as opposed to vertices or vertex patches in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2519 receives input from the vertex shader 2507. In some embodiments, the geometry shader 2519 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0311] Before rasterization, the clipper 2529 processes vertex data. The clipper 2529 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterization and depth test component 2573 in the render output pipeline 2570 dispatches pixel shaders to convert geometric objects into their per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2550. In some embodiments, an application can bypass rasterization and access the un-rasterized vertex data via the outflow unit 2523.

[0312] The graphics processor 2500 has an interconnect bus, an interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between the major components of the processor. In some embodiments, the execution units 2552A, 2552B and the associated cache(s) 2551, texture and media sampler 2554, and texture / sampler cache 2558 are interconnected via a data port 2556 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, each of the sampler 2554, caches 2551, 2558, and execution units 2552A, 2552B has a separate memory access path.

[0313] In some embodiments, the rendering output pipeline 2570 includes a rasterization and depth testing component 2573 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rendering output pipeline 2570 includes a windower / shader unit for performing fixed-function triangle and line rasterization. Associated render cache 2578 and depth cache 2579 are also available in some embodiments. The pixel operations component 2577 performs pixel-based operations on the data, although in some instances, pixel operations associated with 2D operations (e.g., bit blit image transfer with blending) are performed by the 2D engine 2541 or by the display controller 2543 using overlapping display planes at display time. In some embodiments, a shared L3 cache 2575 is available to all graphics components, allowing data to be shared without using the main system memory.

[0314] In some embodiments, the graphics processor media pipeline 2530 includes a media engine 2537 and a video front end 2534. In some embodiments, the video front end 2534 receives pipeline commands from the command streamer 2503. In some embodiments, the media pipeline 2530 includes a separate command streamer. In some embodiments, the video front end 2534 processes media commands before sending the commands to the media engine 2537. In some embodiments, the media engine 2537 includes a thread generation function for generating threads for dispatch to thread execution logic 2550 via a thread dispatcher 2531.

[0315] In some embodiments, the graphics processor 2500 includes a display engine 2540. In some embodiments, the display engine 2540 is external to the processor 2500 and is coupled to the graphics processor via a ring interconnect 2502, or some other interconnect bus or fabric. In some embodiments, the display engine 2540 includes a 2D engine 2541 and a display controller 2543. In some embodiments, the display engine 2540 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2543 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0316] In some embodiments, the graphics pipeline 2520 and the media pipeline 2530 may be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any one application programming interface (API). In some embodiments, the driver software of the graphics processor converts API calls dedicated to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct3D library from Microsoft Corporation, or support may be provided for both OpenGL and D3D. Support may also be provided for the open source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a mapping can be made from the pipelines of the future APIs to the pipelines of the graphics processor.

[0317] Graphics pipeline programming

[0318] Figure 26A is a block diagram illustrating a graphics processor command format 2600 according to some embodiments. Figure 26B is a block diagram illustrating a graphics processor command sequence 2610 according to an embodiment. Figure 26A The solid boxes in illustrate components that are typically included in a graphics command, while the dashed boxes include optional components or components that are only included in a subset of the graphics commands. Figure 26A An exemplary graphics processor command format 2600 includes a target client 2602 for identifying the command, a command operation code (opcode) 2604, and a data field for the relevant data 2606 of the command. Some commands also include a sub-opcode 2605 and a command size 2608.

[0319] In some embodiments, the client 2602 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser examines the client field of each command to coordinate further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once the command is received by the client unit, the client unit reads the opcode 2604 and the sub-opcode 2605 (if present) to determine the operation to be performed. The client unit uses the information in the data field 2606 to execute the command. For some commands, an explicit command size 2608 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands based on the command opcode. In some embodiments, commands are aligned by multiples of a double word.

[0320] Figure 26B The process flow diagram therein shows an exemplary graphics processor command sequence 2610. In some embodiments, software or firmware of a data processing system characterized by an embodiment of the graphics processor uses a version of the shown command sequence to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for illustrative purposes only, as the embodiments are not limited to these particular commands or this command sequence. Also, the commands may be issued as a batch of commands in a command sequence such that the graphics processor will process the command sequence in at least a partially concurrent manner.

[0321] In some embodiments, the graphics processor command sequence 2610 may begin with a pipeline dump flush command 2612 to cause any active graphics pipeline to complete the current outstanding commands for that pipeline. In some embodiments, the 3D pipeline 2622 and the media pipeline 2624 do not operate concurrently. A pipeline dump flush is performed to cause the active graphics pipeline to complete any outstanding commands. In response to the pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engine has completed the outstanding operations and invalidated the associated read caches. Optionally, any data marked as 'dirty' in the render cache may be flushed to memory. In some embodiments, the pipeline flush command 2612 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0322] In some embodiments, a pipeline select command 2613 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 2613 is only required once within an execution context before issuing pipeline commands, unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 2612 is required immediately before a pipeline switch via the pipeline select command 2613.

[0323] In some embodiments, a pipeline control command 2614 configures the graphics pipeline for operation and programs the 3D pipeline 2622 and the media pipeline 2624. In some embodiments, the pipeline control command 2614 configures the pipeline state of the active pipeline. In one embodiment, the pipeline control command 2614 is used for pipeline synchronization and for clearing data from one or more caches within the active pipeline before processing a batch of commands.

[0324] In some embodiments, the command to return buffer state 2616 is used to configure a set of return buffers for the corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers, which write intermediate data into the one or more return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring the return buffer state 2616 includes selecting the size and number of return buffers for a set of pipeline operations.

[0325] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on the pipeline determination 2620, the command sequence is customized to the 3D pipeline 2622 starting with the 3D pipeline state 2630 or the media pipeline 2624 starting at the media pipeline state 2640.

[0326] Commands for the 3D pipeline state 2630 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, the 3D pipeline state 2630 commands can also selectively disable or bypass specific pipeline elements if those elements will not be used.

[0327] In some embodiments, the 3D primitive 2632 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2632 commands are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 2632 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 2632 commands are used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 2622 dispatches shader execution threads to the graphics processor execution units.

[0328] In some embodiments, the 3D pipeline 2622 is triggered via the execution of a 2634 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometric processing on 3D primitives. Once the operations are completed, the resulting geometric objects are rasterized, and the pixel engine colors the resulting pixels. For those operations, additional commands for controlling pixel coloring and pixel backend operations may also be included.

[0329] In some embodiments, when a media operation is executed, the graphics processor command sequence 2610 follows the media pipeline 2624 path. Generally, the specific uses and ways of programming the media pipeline 2624 depend on the media or computing operations to be executed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and the resources provided by one or more general-purpose processing cores can be used, either wholly or in part, to perform media decoding. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to execute SIMD vector operations using a compute shader program that is not explicitly related to rendering graphics primitives.

[0330] In some embodiments, the media pipeline 2624 is configured in a manner similar to the 3D pipeline 2622. A set of commands for configuring the media pipeline state 2640 is dispatched or placed into the command queue before the media object commands 2642. In some embodiments, the commands for the media pipeline state 2640 include data for configuring the media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands for the media pipeline state 2640 also support the use of one or more pointers to "indirect" state elements that point to a batch of state settings.

[0331] In some embodiments, the media object command 2642 supplies a pointer to a media object for media pipeline processing. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing the media object command 2642. Once the pipeline states are configured and the media object command 2642 is queued, the media pipeline 2624 is triggered via an execute command 2644 or an equivalent execution event (e.g., a register write). The output from the media pipeline 2624 can then be post-processed by operations provided by the 3D pipeline 2622 or the media pipeline 2624. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0332] Graphics software architecture

[0333] Figure 27 FIG. illustrates an exemplary graphics software architecture for a data processing system 2700 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2710, an operating system 2720, and at least one processor 2730. In some embodiments, the processor 2730 includes a graphics processor 2732 and one or more general-purpose processor cores 2734. The graphics application 2710 and the operating system 2720 each execute in the system memory 2750 of the data processing system.

[0334] In some embodiments, the 3D graphics application 2710 includes one or more shader programs that include shader instructions 2712. The shader language instructions may be in a high-level shader language such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2714 that are in a machine language suitable for execution by the general-purpose processor core(s) 2734. The application also includes a graphics object 2716 defined by vertex data.

[0335] In some embodiments, the operating system 2720 is the Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system using a Linux kernel variant. The operating system 2720 may support a graphics API 2722, such as the Direct3D API or the OpenGL API. When the Direct3D API is in use, the operating system 2720 uses a front-end shader compiler 2724 to compile any shader instructions 2712 in HLSL into a lower-level shader language. The compilation may be just-in-time (JIT) compilation, or the application may perform shader pre-compilation. In some embodiments, during compilation of the 3D graphics application 2710, high-level shaders are compiled into low-level shaders.

[0336] In some embodiments, the user-mode graphics driver 2726 includes a back-end shader compiler 2727 for converting the shader instructions 2712 into a hardware-specific representation. When the OpenGL API is in use, the shader instructions 2712 in the GLSL high-level language are passed to the user-mode graphics driver 2726 for compilation. In some embodiments, the user-mode graphics driver 2726 uses operating system kernel-mode functions 2728 to communicate with the kernel-mode graphics driver 2729. In some embodiments, the kernel-mode graphics driver 2729 communicates with the graphics processor 2732 to dispatch commands and instructions.

[0337] IP core implementation

[0338] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions representing various logic within the processor. When read by the machine, the instructions may cause the machine to fabricate logic for performing the techniques described herein. Such a representation (referred to as an “IP core”) is a reusable unit of the logic of an integrated circuit that may be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities that load the hardware model on a manufacturing machine for fabricating the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

[0339] Figure 28FIG. is a block diagram illustrating an IP core development system 2800 that can be used to fabricate an integrated circuit for performing operations according to an embodiment. The IP core development system 2800 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., a SOC integrated circuit). A design facility 2830 can generate a software simulation 2810 of an IP core design using a high-level programming language (e.g., C / C++). The software simulation 2810 can be used to design, test, and verify the behavior of the IP core using a simulation model 2812. The simulation model 2812 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 2815 can then be created or synthesized based on the simulation model 2812. The RTL design 2815 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers (including the associated logic performed using the modeled digital signals). In addition to the RTL design 2815, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0340] The RTL design 2815 or equivalent can be further synthesized by the design facility into a hardware model 2820, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. A non-volatile memory 2840 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 2865. Alternatively, the IP core design can be transmitted (e.g., via the Internet) through a wired connection 2850 or a wireless connection 2860. The manufacturing facility 2865 can then fabricate an integrated circuit that is at least partially based on the IP core design. The fabricated integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0341] Exemplary system-on-chip integrated circuit

[0342] Figures 29 - 31 FIG. illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0343] Figure 29FIG. is a block diagram illustrating an exemplary system-on-chip integrated circuit 2900 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 2900 includes one or more application processors 2905 (e.g., CPUs), at least one graphics processor 2910, and may additionally include an image processor 2915 and / or a video processor 2920, any of which may be a modular IP core from the same or multiple different design facilities. The integrated circuit 2900 includes peripheral or bus logic including a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2935, and an I 2 S / I 2 C controller 2940. Additionally, the integrated circuit may also include a display device 2945 coupled to one or more of a high definition multimedia interface (HDMI) controller 2950 and a mobile industry processor interface (MIPI) display interface 2955. Storage may be provided by a flash memory subsystem 2960 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2965 to access SDRAM or SRAM memory devices. Additionally, some integrated circuits also include an embedded security engine 2970.

[0344] Figure 30 FIG. is a block diagram illustrating an exemplary graphics processor 3010 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3010 may be Figure 29 a variant of the graphics processor 2910. The graphics processor 3010 includes a vertex processor 3005 and one or more fragment processors 3015A - 3015N (e.g., 3015A, 3015B, 3015C, 3015D to 3015N - 1, and 3015N). The graphics processor 3010 can execute different shader programs via separate logic such that the vertex processor 3005 is optimized to perform operations of a vertex shader program, while the one or more fragment processors 3015A - 3015N perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. The vertex processor 3005 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. The (multiple) fragment processors 3015A - 3015N use the primitives and vertex data generated by the vertex processor 3005 to produce a frame buffer that is displayed on a display device. In one embodiment, the (multiple) fragment processors 3015A - 3015N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0345] In addition, the graphics processor 3010 further includes one or more memory management units (MMUs) 3020A - 3020B, (multiple) caches 3025A - 3025B, and (multiple) circuit interconnections 3030A - 3030B. One or more MMUs 3020A - 3020B provide virtual - to - physical address mapping for the graphics processor 3010, including for the vertex processor 3005 and / or (multiple) fragment processors 3015A - 3015N. Besides the vertex or image / texture data stored in one or more caches 3025A - 3025B, the virtual - to - physical address mapping can also reference vertex or image / texture data stored in the memory. In one embodiment, one or more MMUs 3020A - 3020B can be synchronized with one or more other MMUs within the system, including one or more MMUs associated with Figure 29 one or more application processors 2905, image processors 2915, and / or video processors 2920 of Figure 29 , such that each processor 2905 - 2920 can participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnections 3030A - 3030B enable the graphics processor 3010 to interact with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0346] Figure 31 FIG. is a block diagram of an additional exemplary graphics processor 3110 of a system - on - a - chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3110 can be Figure 29 a variant of the graphics processor 2910 of Figure 29 . The graphics processor 3110 includes Figure 30 one or more MMUs 3020A - 3020B, (multiple) caches 3025A - 3025B, and (multiple) circuit interconnections 3030A - 3030B of the integrated circuit 3000 of Figure 30 .

[0347] The graphics processor 3110 includes one or more shader cores 3115A - 3115N (e.g., 3115A, 3115B, 3115C, 3115D, 3115E, 3115F to 3015N - 1 and 3015N), and the one or more shader cores provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present can vary between embodiments and implementations. Additionally, the graphics processor 3110 further includes an inter - core task manager 3105, which acts as a thread dispatcher for dispatching execution threads to the one or more shader cores 3115A - 3115N. The graphics processor 3110 further includes a tiling unit 3118 for accelerating tiled operations for tile - based rendering, where the rendering operations of a scene are subdivided in image space. Tile - based rendering can be used to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0348] References to "one embodiment", "an embodiment", "example embodiments", "various embodiments", etc., indicate that the (s) embodiment(s) so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Moreover, some embodiments may have some, all, or none of the features described for other embodiments.

[0349] In the foregoing specification, embodiments have been described with reference to their specific exemplary embodiments. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the appended claims. The specification and drawings are accordingly to be regarded in an illustrative rather than a restrictive sense.

[0350] In the following description and claims, the term "coupled" and its derivatives may be used. "Coupled" is used to indicate that two or more elements cooperate or interact with each other, but they may or may not have intervening physical or electrical components between them.

[0351] As used in the claims, unless otherwise specified, use of the ordinal adjectives "first", "second", "third", etc., to describe a common element merely indicates that different instances of like elements are being referred to and is not intended to mean that the elements so described must be in a given sequence in time, in space, in ranking, or in any other way.

[0352] The following clauses and / or examples relate to additional embodiments or examples. Details in the examples may be used anywhere in one or more embodiments. The various features of different embodiments or examples may be combined with some of the included features and other excluded features in various ways to suit a variety of different applications. Examples may include subjects such as a method, components for performing actions of the method, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of the method, or a device or system for facilitating hybrid communication, according to the embodiments and examples described herein.

[0353] Some embodiments relate to Example 1, which includes an apparatus for facilitating hybrid processing of a workload associated with a graphics processor, the apparatus including: detection / observation logic to detect a workload of the graphics processor; and status query / notification logic to check a status of a shared functional unit (SFU) associated with the graphics processor to determine a distribution of the workload between the SFU and an execution unit (EU) associated with the graphics processor.

[0354] Example 2 includes the subject matter of Example 1, wherein the status query / notification logic is to facilitate placement of a status query message by the EU to a message entity to check the status of the SFU, wherein the message entity includes a message gateway.

[0355] Example 3 includes the subject matter of Examples 1-2, wherein the status query / notification logic is further to facilitate replay by the message entity of a status notification message indicating the status of the SFU, wherein the status includes idle or busy.

[0356] Example 4 includes the subject matter of Examples 1-3, further including decision / execution logic that, if the status indicates the SFU is idle, is to facilitate processing of one or more of the workload by the SFU.

[0357] Example 5 includes the subject matter of Examples 1-4, wherein if the status indicates the SFU is busy, the decision / execution logic is further to direct one or more of the workload to the EU for processing.

[0358] Example 6 includes the subject matter of Examples 1-5, further including message logic to generate a message to be transmitted to a message register file, wherein the message logic is further to deliver the message to the SFU via the message register file, and wherein the message logic is further to facilitate processing of the message by the SFU, wherein the message includes a workload or a request for processing a workload.

[0359] Example 7 includes the subject matter of Examples 1-6, wherein the graphics processor and the application processor are co-located on a common semiconductor package.

[0360] Some embodiments pertain to Example 8, which includes a method for facilitating hybrid processing of a workload associated with a graphics processor, the method including: detecting a workload of a graphics processor of a computing device; and checking a state of a shared functional unit (SFU) associated with the graphics processor to determine a distribution of the workload between the SFU and an execution unit (EU) associated with the graphics processor.

[0361] Example 9 includes the subject matter of Example 8, further including facilitating the EU to place a status query message to a message entity to check the state of the SFU, wherein the message entity includes a message gateway.

[0362] Example 10 includes the subject matter of Examples 8-9, further including facilitating the message entity to replay a status notification message indicating the state of the SFU, wherein the state includes idle or busy.

[0363] Example 11 includes the subject matter of Examples 8-10, further including if the state indicates the SFU is idle, facilitating the SFU to process one or more of the workload.

[0364] Example 12 includes the subject matter of Examples 8-11, further including if the state indicates the SFU is busy, directing one or more of the workload to the EU for processing.

[0365] Example 13 includes the subject matter of Examples 8-12, further including generating a message to be transmitted to a message register file; delivering the message to the SFU via the message register file; and facilitating the SFU to process the message, wherein the message includes a workload or a request to process a workload.

[0366] Example 14 includes the subject matter of Examples 8-13, wherein the graphics processor and the application processor are co-located on a common semiconductor package.

[0367] Some embodiments pertain to Example 15, which includes a graphics processing system, the graphics processing system including a computing device having a memory coupled to a processor, the processor to: detect a workload of a graphics processor of the computing device; and check a state of a shared functional unit (SFU) associated with the graphics processor to determine a distribution of the workload between the SFU and an execution unit (EU) associated with the graphics processor.

[0368] Example 16 includes the subject matter of Example 15, wherein the processor is further to facilitate the EU to place a status query message to a message entity to check the status of the SFU, and the message entity includes a message gateway.

[0369] Example 17 includes the subject matter of Examples 15 - 16, wherein the processor is further to facilitate the message entity to replay a status notification message indicating the status of the SFU, and the status includes idle or busy.

[0370] Example 18 includes the subject matter of Examples 15 - 17, wherein if the status indicates that the SFU is idle, the processor is further to facilitate the SFU to process one or more of the workloads.

[0371] Example 19 includes the subject matter of Examples 15 - 18, wherein if the status indicates that the SFU is busy, the processor is further to direct one or more of the workloads to the EU for processing.

[0372] Example 20 includes the subject matter of Examples 15 - 19, wherein the processor is further to: generate a message to be transmitted to a message register file; deliver the message to the SFU via the message register file; and facilitate the SFU to process the message, and the message includes a workload or a request for processing a workload.

[0373] Example 21 includes the subject matter of Examples 15 - 20, wherein the graphics processor and the application processor are located on a common semiconductor package.

[0374] Example 22 includes at least one non - transitory or tangible machine - readable medium, which includes a plurality of instructions that, when executed on a computing device, are to implement or perform the method claimed in any one of the claims or Examples 8 - 14.

[0375] Example 23 includes at least one machine - readable medium, which includes a plurality of instructions that, when executed on a computing device, are to implement or perform the method claimed in any one of the claims or Examples 8 - 14.

[0376] Example 24 includes a system, which includes means for implementing or performing the method claimed in any one of the claims or Examples 8 - 14.

[0377] Example 25 includes a device, which includes components for performing the method claimed in any one of the claims or Examples 8 - 14.

[0378] Example 26 includes a computing device arranged to implement or perform a method as claimed in any one of the claims or Examples 8 - 14.

[0379] Example 27 includes a communication device arranged to implement or perform a method as claimed in any one of the claims or Examples 8 - 14.

[0380] Example 28 includes at least one machine - readable medium including a plurality of instructions which, when executed on a computing device, are to implement or perform a method as claimed in any of the preceding claims or implement an apparatus as claimed in any of the preceding claims.

[0381] Example 29 includes at least one non - transitory or tangible machine - readable medium including a plurality of instructions which, when executed on a computing device, are to implement or perform a method as claimed in any of the preceding claims or implement an apparatus as claimed in any of the preceding claims.

[0382] Example 30 includes a system including means for implementing or performing a method as claimed in any of the preceding claims or implementing an apparatus as claimed in any of the preceding claims.

[0383] Example 31 includes an apparatus including components for performing a method as claimed in any of the preceding claims.

[0384] Example 32 includes a computing device arranged to implement or perform a method as claimed in any of the preceding claims or implement an apparatus as claimed in any of the preceding claims.

[0385] Example 33 includes a communication device arranged to implement or perform a method as claimed in any of the preceding claims or implement an apparatus as claimed in any of the preceding claims.

[0386] The accompanying drawings and the foregoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements can be combined well into a single functional element. Alternatively, certain elements can be broken down into multiple functional elements. Elements from one embodiment can be added to another embodiment. For example, the order of the processes described herein can be changed and is not limited to the manner described herein. In addition, the actions of any flowchart do not need to be implemented in the order shown; nor do all actions necessarily need to be performed. Moreover, those actions that do not depend on other actions can be performed in parallel with the other actions. The scope of the embodiments is in no way limited by these specific examples. Many variations (whether explicitly given in the specification, such as differences in structure, size, and material use) are possible. The scope of the embodiments is at least as wide as that given by the appended claims.

Claims

1. An apparatus for facilitating hybrid processing of a workload, the apparatus comprising: one or more processors, which are to: detect a workload of a graphics processor, the graphics processor including a shared functional pipeline and programmable execution units (EUs), wherein the shared functional pipeline includes at least one hardware unit configured to provide a dedicated function to complement the functions of the EUs, the hardware unit hereinafter referred to as a shared functional unit (SFU); and facilitate an execution unit (EU) to place a status query message to a message entity to check a status of a shared functional unit (SFU) associated with the graphics processor to determine a distribution of the workload between the SFU and an execution unit (EU) associated with the graphics processor, wherein the message entity includes a message gateway, and wherein the hybrid processing of the workload is at least based on an agnostic algorithm to dynamically achieve workload balance between the SFU and the EU; if the status indicates that the SFU is idle, facilitate the SFU to process one or more of the workload; and if the status indicates that the SFU is busy, direct one or more of the workload to the EU for processing to reduce stalling of the EU.

2. The apparatus according to claim 1, wherein the one or more processors are further to facilitate the message entity to replay a status notification message indicating the status of the SFU, wherein the status includes idle or busy.

3. The apparatus according to claim 1, wherein the one or more processors are further to generate a message to be transmitted to a message register file, and deliver the message to the SFU via the message register file, and facilitate the SFU to process the message, wherein the message includes a workload or a request for processing a workload.

4. The apparatus according to claim 1, wherein the graphics processor is co-located with an application processor on a common semiconductor package.

5. A method for facilitating hybrid processing of a workload, the method comprising: detecting a workload of a graphics processor of a computing device, the graphics processor including a shared functional pipeline and programmable execution units (EUs), wherein the shared functional pipeline includes at least one hardware unit configured to provide a dedicated function to complement the functions of the EUs, the hardware unit hereinafter referred to as a shared functional unit (SFU); facilitating an execution unit (EU) to place a status query message to a message entity to check a status of a shared functional unit (SFU) associated with the graphics processor to determine a distribution of the workload between the SFU and an execution unit (EU) associated with the graphics processor, wherein the message entity includes a message gateway, and wherein the hybrid processing of the workload is at least based on an agnostic algorithm to dynamically achieve workload balance between the SFU and the EU; if the status indicates that the SFU is idle, facilitating the SFU to process one or more of the workload; and If the state indicates that the SFU is busy, direct one or more of the workloads to the EU for processing to reduce EU stalls.

6. The method of claim 5, further comprising facilitating a status notification message from the message entity that indicates the state of the SFU, where the state includes idle or busy.

7. The method of claim 5, further comprising: generating a message to be transmitted to a message register file; delivering the message to the SFU via the message register file; and facilitating the SFU to process the message, where the message includes a workload or a request to process a workload.

8. The method of claim 5, where the graphics processor and the application processor are co-located on a common semiconductor package.

9. At least one machine-readable medium that includes multiple instructions that, when executed on a computing device, implement or perform the method claimed in any one of claims 5-8.

10. A system that includes means for implementing or performing the method claimed in any one of claims or examples 5-8.

11. An apparatus that includes components for performing the method claimed in any one of claims or examples 5-8.

12. A computing device that is arranged to implement or perform the method claimed in any one of claims or examples 5-8.

13. A communication device that is arranged to implement or perform the method claimed in any one of claims or examples 5-8.

14. An apparatus for facilitating hybrid processing of a workload, the apparatus comprising: means for detecting a workload of a graphics processor of a computing device, the graphics processor including a shared functional pipeline and programmable execution units (EUs), where the shared functional pipeline includes at least one hardware unit configured to provide a specialized function to complement the function of the EUs, the hardware unit hereinafter referred to as a shared function unit (SFU); means for facilitating an execution unit (EU) to place a status query message with a message entity to check the state of a shared function unit (SFU) associated with the graphics processor to determine the distribution of the workload between the SFU and the execution units (EUs) associated with the graphics processor, where the message entity includes a message gateway, and where the hybrid processing of the workload is at least based on an agnostic algorithm to dynamically achieve workload balance between the SFU and the EU; means for facilitating the SFU to process one or more of the workloads if the state indicates that the SFU is idle; and means for directing one or more of the workloads to the EU for processing to reduce EU stalls if the state indicates that the SFU is busy.

15. The apparatus according to claim 14, further comprising means for facilitating a status notification message for the message entity replay indicating the status of the SFU, wherein the status includes idle or busy.

16. The apparatus according to claim 14, further comprising: means for generating a message to be transmitted to a message register file; means for delivering the message to the SFU via the message register file; and means for facilitating the SFU to process the message, wherein the message includes a workload or a request for processing a workload.

17. The apparatus according to claim 14, wherein the graphics processor and the application processor are co-located on a common semiconductor package.

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