Metal chemical vapor deposition method for producing wraparound contacts and resulting structures

Abstract

Metal chemical vapor deposition methods for making wraparound contacts, and semiconductor structures having wraparound metal contacts are described. In an example, an integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is above the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-planar topography. A metal contact material is directly on the portion of the semiconductor feature. The metal contact material is conformal to the non-planar topography of the portion of the semiconductor feature. The metal contact material has a total atomic composition that includes 95% or more of a single metal species.

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of integrated circuit structures, and in particular metal chemical vapor deposition methods for manufacturing wraparound contacts, and semiconductor structures having wraparound metal contacts. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the evolving semiconductor industry. Scaling to smaller and smaller features enables increased density of functional units on the limited real estate of a semiconductor chip.

[0003] For example, shrinking the size of transistors allows an increased number of memories or logic devices to be incorporated on a chip, thereby being suitable for manufacturing products with increased capacity. However, the drive for increasingly more capacity is not without problems. The necessity for optimizing the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, as device size continues to shrink, multi-gate transistors such as tri-gate transistors have become more common. In conventional processes, tri-gate transistors are generally manufactured on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure. However, scaling multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits shrinks and as the absolute number of basic building blocks manufactured in a given area increases, the constraints on the semiconductor processes used to manufacture these building blocks have become overwhelming.

[0004] Integrated circuits typically include conductive microelectronic structures, which are known in the art as through-holes, for electrically connecting metal lines or other interconnections above the through-holes to metal lines or other interconnections below the through-holes. Through-holes are typically formed by photolithography. Representatively, a photoresist layer can be spin-coated on a dielectric layer, and the photoresist layer can be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer can be developed to form an opening in the photoresist layer. Next, an opening for a through-hole can be etched in the dielectric layer using the opening in the photoresist layer as an etching mask. The opening is preferably used as a through-hole opening. Finally, the through-hole opening can be filled with one or more metals or other conductive materials to form a through-hole.

[0005] Variability in conventional and prior art manufacturing processes may limit the possibility of further extending them into the 10 nm or sub-10 nm range, for example. Therefore, manufacturing the functional components required for future technology nodes may require the introduction of new methodologies or integration of new technologies in or instead of current manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A cross-sectional view of a semiconductor fin having a conductive contact formed thereon by sputtering deposition is illustrated.

[0007] Figure 1B Illustrated is a cross-sectional view of a semiconductor fin having a conductive contact formed thereon by chemical vapor deposition (CVD) according to an embodiment of the present disclosure.

[0008] Figure 2A A cross-sectional view of a semiconductor device having a conductive contact on a source or drain region according to an embodiment of the present disclosure is illustrated.

[0009] Figure 2B A cross-sectional view of another semiconductor device having a conductive portion on an elevated source or drain region according to an embodiment of the present disclosure is illustrated.

[0010] Figure 3 Illustrated is a plan view of a plurality of gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure.

[0011] Figures 4A-4C FIG. 1 illustrates a flowchart for various operations in a method of fabricating an integrated circuit structure according to an embodiment of the present disclosure. Figure 3 A cross-sectional view taken along the a-a' axis.

[0012] Figure 5 FIG. 1 illustrates an integrated circuit structure according to an embodiment of the present disclosure. Figure 3 Cross-sectional view taken along the b-b' axis.

[0013] Figure 6 Illustrated are plan views and corresponding cross-sectional views of metallization layers of an integrated circuit structure according to an embodiment of the present disclosure.

[0014] Fig. 7A Illustrated is a cross-sectional view of a non-planar semiconductor device having a CVD-deposited layer as a work function layer for a gate electrode according to an embodiment of the present disclosure.

[0015] Figure 7B The diagram shows an embodiment according to the present disclosure. Fig. 7A A plan view of a semiconductor device taken along the a-a' axis.

[0016] Figure 8 A computing device according to one implementation of an embodiment of the present disclosure is illustrated.

[0017] Fig. 9 is an insert that implements one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] A metal chemical vapor deposition method for manufacturing a wraparound contact portion, and an integrated circuit structure including a semiconductor structure having a wraparound metal contact portion are described. In the following description, numerous specific details, such as specific materials and tool operating systems, are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other examples, well-known features, such as single or dual damascene processes, are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. In addition, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, and then, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be interpreted as implying that these operations must be order-dependent. In particular, these operations do not need to be performed in the order presented.

[0019] Certain terminology may also be used in the following description for reference purposes only, and thus the certain terminology is not intended to be limiting. For example, terms such as "upper," "lower," "above," "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," and "side" describe the orientation and / or position of parts of a component within an arbitrary but consistent reference frame made clear by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0020] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0021] The embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring on the wafer, such as one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in BEOL.

[0022] The embodiments described below may be applicable to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, although exemplary processing schemes may be described using FEOL processing scenarios, such methods may also be applicable to BEOL processing. Likewise, although exemplary processing schemes may be described using BEOL processing scenarios, such methods may also be applicable to FEOL processing.

[0023] One or more embodiments described herein relate to using metal chemical vapor deposition for wraparound semiconductor contacts. Embodiments may be applicable to or include one or more of: chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

[0024] Particular embodiments may include fabricating a titanium or similar metal layer that provides conformal source / drain contacts using low temperature (e.g., less than 500 degrees Celsius, or in the range of 400-500 degrees Celsius) chemical vapor deposition of the contact metal. Implementation of such conformal source / drain contacts may improve three-dimensional (3D) transistor complementary metal oxide semiconductor (CMOS) performance.

[0025] To provide context, conventional metal to semiconductor contact layers are deposited using sputtering. Sputtering is a line of sight process and may not be well suited for 3D transistor fabrication. Known sputtering solutions have poor or incomplete metal-semiconductor junctions on device contact surfaces that have an angle of incidence relative to the deposition.

[0026] According to one or more embodiments of the present disclosure, a low temperature chemical vapor deposition process is implemented for making contact metals, thereby providing conformality in three dimensions and maximizing the metal semiconductor junction contact area. The resulting larger contact area can reduce the resistance of the junction. Embodiments may include deposition on a semiconductor surface with a non-planar topography, where the topography of an area refers to the surface shape and features themselves, and the non-planar topography includes non-planar surface shapes and features or portions of surface shapes and features, i.e., non-completely planar surface shapes and features.

[0027] Embodiments described herein may include the manufacture of wraparound contact structures. In one such embodiment, the use of pure metals is described, which are conformally deposited onto transistor source-drain contacts by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or plasma enhanced atomic layer deposition. Such conformal deposition can be used to increase the available area of ​​metal semiconductor contacts and reduce resistance, thereby improving the performance of transistor devices. In an embodiment, a relatively low deposition temperature results in a minimized resistance of the junction per unit area.

[0028] Figure 1A A cross-sectional view of a semiconductor fin having a conductive contact formed thereon by sputtering deposition is illustrated.

[0029] refer to Figure 1A , a sputtered contact 104 is formed on a semiconductor feature 102, such as a semiconductor fin, formed above a substrate 100. The sputtered contact includes a portion 104A covering a lower planar surface, a sidewall portion 104B covering a non-planar surface, and a portion 104C covering an upper planar surface. The thickness X of the portion 104B covering the non-planar surface is 1 Substantially greater than the thickness Y of the portion 104C covering the upper flat surface 1 Thinner, and generally thinner than portion 104A covering the lower planar surface.

[0030] Figure 1B Illustrated is a cross-sectional view of a semiconductor fin having a conductive contact formed thereon by chemical vapor deposition (CVD) according to an embodiment of the present disclosure.

[0031] refer to Figure 1B, a chemical vapor deposition (CVD) contact 154 is formed on a semiconductor feature 152, such as a semiconductor fin, formed above a substrate 150. The CVD contact includes a portion 154A covering a lower planar surface, a sidewall portion 154B covering a non-planar surface, and a portion 154C covering an upper planar surface. The thickness X of the portion 154B covering the non-planar surface is 2 The thickness Y of the portion 154C covering the upper flat surface is 2 Substantially the same, and substantially the same as portion 154A covering the lower planar surface.

[0032] It will be appreciated that various integrated circuit structures can be manufactured using an integration scheme involving a metal layer deposition process as described herein. According to an embodiment of the present disclosure, a method of manufacturing an integrated circuit structure includes providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, the substrate having features thereon. The method also includes subjecting titanium tetrachloride (TiCl 4 ) and hydrogen (H 2 ) reacts to form a titanium (Ti) layer on the features of the substrate. In one embodiment, the reaction is performed at a temperature in the range of 400-500 degrees Celsius, at a pressure in the range of 0.2-2 Torr, and at an RF frequency of approximately 400 kHz or approximately 13.56 MHz.

[0033] In an embodiment, the titanium layer has a total atomic composition including 98% or greater titanium and 0.5-2% chlorine. In an alternative embodiment, a similar process is used to make a high purity metal layer of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) or vanadium (V). In an embodiment, there is a relatively small film thickness variation, for example, in one embodiment, all coverage is greater than 50% and nominally 70% or greater (i.e., 30% or less thickness variation). In an embodiment, the thickness is measurably thicker on silicon (Si) or silicon germanium (SiGe) compared to other surfaces because Si or SiGe reacts during deposition and accelerates the uptake of Ti. In an embodiment, the film composition includes approximately 0.5% Cl (or less than 1%) as an impurity, with substantially no other observed impurities. In an embodiment, the deposition process enables metal coverage on non-line-of-sight surfaces, such as surfaces hidden by the sputtering deposition line of sight. The embodiments described herein can be implemented to improve transistor device drive by reducing the external resistance of the current driven through the source and drain contacts.

[0034] According to an embodiment of the present disclosure, the substrate features source / drain contact trenches that expose the semiconductor source / drain structure. The titanium layer (or other high purity metal layer) is a conductive contact layer for the semiconductor source / drain structure. An exemplary embodiment of such an implementation is described below with reference to Figure 2A , 2B , 3, 4A-4C and 5 are described in association.

[0035] According to another embodiment of the present disclosure, the substrate features conductive line trenches in the back-end-of-line (BEOL) metallization layer. The titanium layer (or other high purity metal layer) is a barrier layer for the conductive lines. An exemplary embodiment of such an implementation is described below with reference to Figure 6 Described in association.

[0036] According to another embodiment of the present disclosure, the substrate is characterized by a gate trench of a semiconductor device. The titanium layer (or other high purity metal layer) is a work function layer of a metal gate electrode of the semiconductor device. An exemplary embodiment of such an implementation is described below with reference to Fig. 7A and 7B Described in association.

[0037] As illustrated by various embodiments described below, an integrated circuit structure can include a semiconductor feature above a substrate. A dielectric layer is above the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-planar topography. A metal contact material is directly on the portion of the semiconductor feature. The metal contact material is conformal to the non-planar topography of the portion of the semiconductor feature. In one such embodiment, the metal contact material has a total atomic composition that includes 95% or greater of a single metal species.

[0038] In an embodiment, the metal contact material has a total atomic composition including 98% or greater titanium. In one such embodiment, the total atomic composition of the metal contact material further includes 0.5-2% chlorine. In an embodiment, the metal contact material has a thickness variation of 30% or less along the non-planar topography of the portion of the semiconductor feature. In an embodiment, the non-planar topography of the portion of the semiconductor feature includes an elevated central portion and lower side portions. In an embodiment, the non-planar topography of the portion of the semiconductor feature includes a saddle-shaped portion.

[0039] In an embodiment, the semiconductor feature comprises silicon. In one such embodiment, the semiconductor feature further comprises germanium. In an embodiment, the metal contact material further follows the sidewalls of the trench in the dielectric layer. In one such embodiment, the thickness of the metal contact material along the sidewalls of the trench decreases from the portion of the semiconductor feature to a position above the portion of the semiconductor feature. In an embodiment, the conductive fill material is on the metal contact material within the trench.

[0040] Figure 2A A cross-sectional view of a semiconductor device having a conductive contact on a source or drain region according to an embodiment of the present disclosure is illustrated.

[0041] refer to Figure 2A , the semiconductor structure 200 includes a gate structure 202 over a substrate 204. The gate structure 202 includes a gate dielectric layer 202A, a work function layer 202B, and a gate filler 202C. A source region 208 and a drain region 210 are on opposite sides of the gate structure 202. A source or drain contact 212 is electrically connected to the source region 208 and the drain region 210 and is spaced apart from the gate structure 202 by one or both of an interlayer dielectric layer 214 or a gate dielectric spacer 216. The source region 208 and the drain region 210 are regions of the substrate 204.

[0042] In an embodiment, the source or drain contact 212 includes a high purity metal layer 212A such as described above and a conductive trench filling material 212B. In one embodiment, the high purity metal layer 212A has a total atomic composition including 98% or greater titanium. In one such embodiment, the total atomic composition of the high purity metal layer 212A further includes 0.5-2% chlorine. In an embodiment, the high purity metal layer 212A has a thickness variation of 30% or less. In an embodiment, the conductive trench filling material 212B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0043] Figure 2B A cross-sectional view of another semiconductor device having a conductive portion on an elevated source or drain region according to an embodiment of the present disclosure is illustrated.

[0044] refer to Figure 2B, semiconductor structure 250 includes a gate structure 252 above substrate 254. Gate structure 252 includes a gate dielectric layer 252A, a work function layer 252B, and a gate filler 252C. Source region 258 and drain region 260 are on opposite sides of gate structure 252. Source or drain contacts 262 are electrically connected to source region 258 and drain region 260 and are spaced apart from gate structure 252 by one or both of interlayer dielectric layer 264 or gate dielectric spacer 266. Source region 258 and drain region 260 are epitaxial and / or embedded material regions formed in the etched regions of substrate 254. As depicted, in an embodiment, source region 258 and drain region 260 are elevated source and drain regions. In a specific such embodiment, the elevated source and drain regions are elevated silicon source and drain regions or elevated silicon germanium source and drain regions.

[0045] In an embodiment, the source or drain contact 262 includes a high purity metal layer 262A such as described above and a conductive trench filling material 262B. In one embodiment, the high purity metal layer 262A has a total atomic composition including 98% or greater titanium. In one such embodiment, the total atomic composition of the high purity metal layer 262A further includes 0.5-2% chlorine. In an embodiment, the high purity metal layer 262A has a thickness variation of 30% or less. In an embodiment, the conductive trench filling material 262B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0046] Therefore, in the embodiments, reference is made to Figure 2A and 2B , the integrated circuit structure includes a feature having a surface (a source or drain contact trench exposing a semiconductor source or drain structure). A high purity metal layer 212A or 262A is on the surface of the source or drain contact trench. It will be appreciated that the contact formation process may involve consumption of the exposed silicon or germanium or silicon germanium material of the source or drain region. Such consumption may degrade device performance. In contrast, according to an embodiment of the present disclosure, the surface (249 or 299) of the semiconductor source (208 or 258) or drain (210 or 260) structure is not eroded or consumed, or is substantially not eroded or consumed below the source or drain contact trench. In one such embodiment, no consumption or erosion is caused by low temperature deposition of the high purity metal contact layer.

[0047] Figure 3 Illustrated is a plan view of a plurality of gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure.

[0048] refer to Figure 3, a plurality of active gate lines 304 are formed over the plurality of semiconductor fins 300. Dummy gate lines 306 are at the ends of the plurality of semiconductor fins 300. The spaces 308 between the gate lines 304 / 306 are where trench contacts can be formed as conductive contacts to source / drain regions, such as source / drain regions 351, 352, 353, and 354.

[0049] In an embodiment, the pattern of the multiple gate lines 304 / 306 and / or the pattern of the multiple semiconductor fins 300 are described as a grating structure. In an embodiment, the term "grating" for the pattern of the multiple semiconductor fins 300 and / or the multiple gate lines 304 / 306 is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not directly achievable by conventional lithography. For example, a pattern based on conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask, as known in the art. Even further, the original pitch can be divided into four equal parts by a second round of spacer mask patterning. Therefore, the grating pattern described herein can have a pattern of the multiple semiconductor fins 300 spaced at a constant pitch and having a constant width and / or the multiple gate lines 304 / 306. The pattern can be manufactured by halving the pitch or by quartering the pitch or other pitch division methods.

[0050] Figures 4A-4C FIG. 1 illustrates a flowchart for various operations in a method of fabricating an integrated circuit structure according to an embodiment of the present disclosure. Figure 3 A cross-sectional view taken along the a-a' axis.

[0051] refer to Figure 4A , a plurality of active gate lines 404 are formed over semiconductor fins 402 formed over substrate 400. Dummy gate lines 406 are at the ends of semiconductor fins 402. Dielectric layers 410 are between active gate lines 404, between dummy gate lines 406 and active gate lines 404, and outside dummy gate lines 406. Embedded source / drain structures 408 are in semiconductor fins 402, the semiconductor fins 402 being between active gate lines 404 and between dummy gate lines 406 and active gate lines 404. Active gate lines 404 include gate dielectric layers 412, work function gate electrode portions 414, and fill gate electrode portions 416, and dielectric capping layers 418. Dielectric spacers 420 line the sidewalls of active gate lines 404 and dummy gate lines 406.

[0052] refer to Figure 4B, portions of the dielectric layer 410 between the active gate lines 404 and between the dummy gate line 406 and the active gate line 404 are removed to provide openings 430 in locations where trench contacts are to be formed. Removing portions of the dielectric layer 410 between the active gate lines 404 and between the dummy gate line 406 and the active gate line 404 may result in erosion of the embedded source / drain structure 408, thereby providing an eroded embedded source / drain structure 432, which may have an upper saddle-shaped morphology, such as Figure 4B As depicted in .

[0053] refer to Figure 4C , trench contacts 434 are formed in the openings 430 between the active gate lines 404 and between the dummy gate lines 406 and the active gate lines 404. Each of the trench contacts 434 may include a metal contact layer 436 and a conductive filling material 438.

[0054] Figure 5 FIG. 1 illustrates an integrated circuit structure according to an embodiment of the present disclosure. Figure 3 Cross-sectional view taken along the b-b' axis.

[0055] refer to Figure 5 , a fin 502 is depicted above a substrate 504. A lower portion of the fin 502 is surrounded by a trench isolation material 504. An upper portion of the fin 502 has been removed to enable growth of an embedded source and drain structure 506. A trench contact 508 is formed in an opening in a dielectric layer 510 that exposes the embedded source and drain structure 506. The trench contact includes a metal contact layer 512 and a conductive fill material 514. It will be appreciated that, according to an embodiment, the metal contact layer 512 extends to the top of the trench contact 508, as shown in FIG. Figure 5 However, in another embodiment, the metal contact layer 512 does not extend to the top of the trench contact 508, and is slightly recessed within the trench contact 508, for example, similar to Figure 4C 4. A depiction of metal contact layer 436 in FIG.

[0056] Therefore, the common reference Figure 3 , 4A-4C and 5, according to an embodiment of the present disclosure, an integrated circuit structure includes a semiconductor fin (300, 402, 502) above a substrate (400, 500). The semiconductor fin (300, 402, 502) has a top and a sidewall. A gate electrode (304, 404) is above the top and adjacent to a sidewall of a portion of the semiconductor fin (300, 402, 502). The gate electrode (304, 404) defines a channel region in the semiconductor fin (300, 402, 502). A first semiconductor source / drain structure (351, 432, 506) has a non-planar morphology at a first end of the channel region at a first side of the gate electrode (304, 404). The second semiconductor source / drain structure (352, 432, 506) is at a second end of the channel region at a second side of the gate electrode (304, 404), the second end being opposite to the first end, and the second side being opposite to the first side. The second semiconductor source / drain structure (352, 432, 506) has a non-planar morphology. The metal contact material (436, 512) is directly on the first semiconductor source / drain structure (351, 432, 506) and directly on the second semiconductor source / drain structure (352, 432, 506). The metal contact material (436, 512) conforms to the non-planar morphology of the first semiconductor source / drain structure (351, 432, 506) and conforms to the non-planar morphology of the second semiconductor source / drain structure (352, 432, 506).

[0057] In an embodiment, the metal contact material (436, 512) has a total atomic composition comprising 95% or greater of a single metal species. In one such embodiment, the metal contact material (436, 512) has a total atomic composition comprising 98% or greater of titanium. In a particular such embodiment, the total atomic composition of the metal contact material (436, 512) further comprises 0.5-2% chlorine. In an embodiment, the metal contact material (436, 512) has a thickness variation of 30% or less along the non-planar topography of the first semiconductor source / drain structure (351, 432, 506) and along the non-planar topography of the second semiconductor source / drain structure (352, 432, 506).

[0058] In an embodiment, the non-planar topography of the first semiconductor source / drain structure (351, 432, 506) and the non-planar topography of the second semiconductor source / drain structure (352, 432, 506) both include an elevated central portion and lower side portions, for example, as in Figure 5In an embodiment, the non-planar topography of the first semiconductor source / drain structure (351, 432, 506) and the non-planar topography of the second semiconductor source / drain structure (352, 432, 506) both include a saddle-shaped portion, for example, as in Figure 4C As depicted in .

[0059] In an embodiment, the first semiconductor source / drain structure (351, 432, 506) and the second semiconductor source / drain structure (352, 432, 506) both include silicon. In an embodiment, the first semiconductor source / drain structure (351, 432, 506) and the second semiconductor source / drain structure (352, 432, 506) both further include germanium, for example in the form of silicon germanium.

[0060] In an embodiment, the metal contact material (436, 512) directly on the first semiconductor source / drain structure (351, 432, 506) is also along the sidewalls of a trench in the dielectric layer (420, 510) above the first semiconductor source / drain structure (351, 432, 506), the trench exposing a portion of the first semiconductor source / drain structure (351, 432, 506). In one such embodiment, the thickness of the metal contact material (436) along the sidewalls of the trench decreases from 436A at the first semiconductor source / drain structure (432) to a location (436B) above the first semiconductor source / drain structure (432), an example of which is shown in FIG. Figure 4C In an embodiment, the conductive fill material (438, 514) is on the metal contact material (436, 512) within the trench, as shown in Figure 4C and 5 As depicted in .

[0061] In an embodiment, the integrated circuit structure further comprises a second semiconductor fin (e.g. Figure 3The upper fin 300, 402, 502 of the second semiconductor fin has a top and a sidewall. The gate electrode (304, 404) is also above the top and adjacent to the sidewall of a portion of the second semiconductor fin, the gate electrode defining a channel region in the second semiconductor fin. The third semiconductor source / drain structure (353, 432, 506) is at a first end of the channel region of the second semiconductor fin at a first side of the gate electrode (304, 404), the third semiconductor source / drain structure having a non-flat morphology. The fourth semiconductor source / drain structure (354, 432, 506) is at a second end of the channel region of the second semiconductor fin at a second side of the gate electrode (304, 404), the second end being opposite to the first end, the fourth semiconductor source / drain structure (354, 432, 506) having a non-flat morphology. The metal contact material (436, 512) is directly on the third semiconductor source / drain structure (353, 432, 506) and directly on the fourth semiconductor source / drain structure (354, 432, 506), and the metal contact material (436, 512) conforms to the non-planar morphology of the third semiconductor source / drain structure (353, 432, 506) and conforms to the non-planar morphology of the fourth semiconductor source / drain structure (354, 432, 506). In an embodiment, the metal contact material (436, 512) is continuous between the first semiconductor source / drain structure (351, 432, left side 506) and the third semiconductor source / drain structure (353, 432, right side 506), and is continuous between the second semiconductor source / drain structure (352) and the fourth semiconductor source / drain structure (354).

[0062] Figure 6 Illustrated are plan views and corresponding cross-sectional views of metallization layers of an integrated circuit structure according to an embodiment of the present disclosure.

[0063] refer to Figure 6 , the metallization layer 600 includes a pattern of conductive lines 602 and interlayer dielectric (ILD) lines 604. The metallization layer 600 may be patterned in a grid-like pattern having conductive lines 602 that are spaced at a constant pitch and have a constant width, such as in Figure 6 Although not shown, the conductive line 602 may have interruptions (ie, cuts or plugs) at various locations along the line. Some of the conductive lines may be associated with vias below, such as line 602' shown in a cross-sectional view as an example.

[0064] In an embodiment, the term "grid" for conductive lines 602 and ILD lines 604 is used herein to refer to a close pitch grid structure. In one such embodiment, the close pitch is not directly achievable by conventional photolithography. For example, a pattern based on conventional photolithography can be formed first, but the pitch can be halved by patterning using a spacer mask, as known in the art. Even further, the original pitch can be divided into four equal parts by a second round of spacer mask patterning. Therefore, the grid-like pattern described herein can have conductive lines 602 and / or ILD lines 604 that are spaced at a constant pitch and have a constant width. The pattern can be manufactured by halving the pitch or by quartering the pitch or other pitch division methods.

[0065] In an embodiment, conductive lines 602 (and possibly the via structures below) are composed of one or more metals or other conductive structures. Conductive lines 602 are sometimes also referred to in the art as traces, conductors, wires, metals, interconnects, or simply interconnects. In a specific embodiment, each of conductive lines 602 includes a barrier layer 612 and a conductive fill material 610.

[0066] In an embodiment, barrier layer 612 is a high purity metal layer, such as described above. In one embodiment, high purity metal barrier layer 612 has a total atomic composition including 98% or greater titanium. In one such embodiment, the total atomic composition of high purity metal barrier layer 612 further includes 0.5-2% chlorine. In an embodiment, high purity metal barrier layer 612 has a thickness variation of 30% or less. In an embodiment, conductive fill material 610 is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof.

[0067] Thus, in an embodiment, the integrated circuit structure includes a feature (a conductive line trench of a back-end-of-line (BEOL) metallization layer) having a surface. A high purity metal barrier layer 612 is on the surface of the conductive line trench. In one such embodiment, the high purity metal barrier layer 612 is a barrier layer for the conductive line 602.

[0068] In an embodiment, the ILD line 604 is composed of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO 2 )), doped silicon oxide, fluorinated silicon oxide, carbon-doped silicon oxide, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0069] will understand that Figure 6 The layers and materials described in association are typically formed on or above an underlying semiconductor substrate or structure of an integrated circuit, such as an underlying device (multi) layer. In an embodiment, the underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate generally includes a wafer or other component of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon, and silicon on insulator (SOI), as well as similar substrates formed from other semiconductor materials. The semiconductor substrate generally includes transistors, integrated circuits, etc., depending on the stage of manufacturing. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials typically found in semiconductor substrates. In addition, although not depicted, Figure 6 The structure depicted in can be fabricated on an underlying lower level back-end-of-line (BEOL) interconnect layer.

[0070] One or more embodiments described herein relate to manufacturing semiconductor devices, such as metal oxide semiconductor (MOS) devices. As an example, Fig. 7A Illustrated is a cross-sectional view of a non-planar semiconductor device having a CVD-deposited layer as a work function layer for a gate electrode according to an embodiment of the present disclosure. Figure 7B The diagram shows an embodiment according to the present disclosure. Fig. 7A A plan view of a semiconductor device taken along the a-a' axis.

[0071] refer to Fig. 7A , semiconductor structure or device 700 includes a non-planar active region (e.g., a fin structure, the fin structure including a protruding fin portion 704 and a sub-fin region 705), which is formed from a substrate 702 and within an isolation region 706. A gate line 708 is disposed over the protruding portion 704 of the non-planar active region, and over a portion of the isolation region 706. As shown, the gate line 708 includes a gate electrode 750 / 799 and a gate dielectric layer 752. In one embodiment, the gate line 708 may also include a dielectric cap layer 754. The gate contact 714, and the overlying gate contact via 716 are also seen from this perspective, along with the overlying metal interconnect 760, all of which are disposed in an interlayer dielectric stack or layer 770. Also seen from Fig. 7A From the perspective of FIG. 7 , the gate contact 714 is disposed above the isolation region 706 in one embodiment, but not above the non-planar active region.

[0072] According to an embodiment of the present disclosure, the layer 799 of the gate electrode 750 / 799 is a high purity metal layer, such as described above. In one embodiment, the high purity metal layer 799 is in the gate trench and on or above the gate dielectric layer 752. In one such embodiment, the high purity metal layer 799 is a work function layer of a metal gate electrode of a transistor 700 of an integrated circuit structure. In a specific embodiment, the transistor 700 is an N-type (NMOS) transistor, and the high purity metal layer 799 has an N-type work function. In another specific embodiment, the transistor 700 is a P-type (PMOS) transistor, and the high purity metal layer 799 has a P-type work function.

[0073] Thus, in an embodiment, the semiconductor structure or device 700 has a feature (gate line 708) with a surface (gate dielectric layer 752). A CVD deposited work function setting layer 799 (layer 799 of gate electrode 750 / 799) is formed on or adjacent to the gate dielectric layer 752. In one embodiment, the CVD deposited work function setting layer 799 has a total atomic composition including 98% or greater titanium. In one such embodiment, the total atomic composition of the CVD deposited work function setting layer 799 further includes 0.5-2% chlorine. In an embodiment, the CVD deposited work function setting layer 799 has a thickness variation of 30% or less.

[0074] refer to Figure 7B , the gate line 708 is shown as being disposed above the protruding fin portion 704. From this perspective, the source and drain regions 704A and 704B of the protruding fin portion 704 can be seen. In one embodiment, the source or drain regions 704A and 704B are doped portions of the original material of the protruding fin portion 704. In another embodiment, the material of the protruding fin portion 704 is removed and replaced with another semiconductor material, for example by epitaxial deposition. In either case, the source and drain regions 704A and 704B can extend below the height of the dielectric layer 706, i.e., into the sub-fin region 705.

[0075] In an embodiment, the semiconductor structure or device 700 is a non-planar device, such as, but not limited to, a fin-type FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode and gate electrode material of the gate line 708 surround at least the top surface and a pair of sidewalls of the three-dimensional body.

[0076] The substrate 702 may be composed of a semiconductor material that can undergo a manufacturing process and in which charge can migrate. In an embodiment, the substrate 702 is a bulk substrate composed of a crystalline silicon, silicon / germanium or germanium layer, which is doped with charge carriers such as but not limited to phosphorus, arsenic, antimony, boron, gallium or a combination thereof to form an active region 704. In one embodiment, the concentration of silicon atoms in the bulk substrate 702 is greater than 97%. In another embodiment, the bulk substrate 702 is composed of an epitaxial layer grown on top of a different crystalline substrate, such as a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate 702 may alternatively be composed of a III-V group material. In an embodiment, the bulk substrate 702 is composed of a III-V material, such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate 702 is composed of III-V materials and the charge carrier dopant impurity atoms are those such as, but not limited to, magnesium, beryllium, zinc, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0077] The isolation region 706 may be composed of a material suitable for ultimately electrically isolating or contributing to isolating a portion of the permanent gate structure from the underlying bulk substrate or isolating an active region formed within the underlying bulk substrate, such as an isolation fin active region. For example, in one embodiment, the isolation region 706 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0078] In an embodiment, the gate dielectric layer 752 is composed of a high-K material. For example, in one embodiment, the gate dielectric layer 752 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a layer of natural oxide formed by the top layers of the substrate 702. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion, the lower portion being composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 752 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

[0079] In an embodiment, the layer 750 of the gate electrode 750 / 799 is composed of a non-work function setting conductive fill material formed above the work function setting layer 799 deposited by CVD. In one such embodiment, the conductive fill material 750 includes a material such as, but not limited to, tungsten (W), aluminum (Al), or copper (Cu). In one embodiment, one or more conductive barrier layers (such as titanium nitride or tantalum nitride) are between the layers 750 and 799 of the gate electrode. In some implementations, the gate electrode may include a "U" shaped structure, the "U" shaped structure including a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In another implementation of the present disclosure, the gate electrode may include a combination of a U-shaped structure and a planar, non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers.

[0080] In an embodiment, the dielectric cap layer 754 and / or the dielectric spacer associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating the permanent gate structure from an adjacent or overlying conductive contact, such as a self-aligned contact, or contributing to its isolation. For example, in one embodiment, the dielectric cap layer 754 and / or the dielectric spacer are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0081] The gate contact 714, the overlying gate contact via 716, and / or the overlying metal interconnect 760 may be composed of a conductive material. In an embodiment, one or more of the contact, interconnect, or via is composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy, or a metal-semiconductor alloy (e.g., such as a silicide material). In a specific embodiment, one or more of the gate contact 714, the overlying gate contact via 716, or the overlying metal interconnect 760 includes a barrier layer and a conductive filling material. In one such embodiment, the barrier layer is a high-purity metal layer, such as described above. In an embodiment, the high-purity metal barrier layer has a total atomic composition including 98% or more of titanium. In an embodiment, the total atomic composition of the high-purity metal barrier layer further includes 0.5-2% of chlorine. In an embodiment, the high-purity metal barrier layer has a thickness variation of 30% or less. In an embodiment, the conductive filling material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof.

[0082] In an embodiment (although not shown), providing structure 700 involves the formation of a contact pattern that is substantially perfectly aligned with an existing gate pattern while eliminating the use of a lithography step with an extremely tight alignment budget. In one such embodiment, the method enables the use of an inherently highly selective wet etch (e.g., relative to a conventionally implemented dry or plasma etch) to generate a contact opening. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for an otherwise critical lithography operation for generating a contact pattern as used in conventional methods. In an embodiment, a trench contact grid is not patterned separately, but instead is formed between multiple (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0083] Additionally, the gate stack structure 708 may be fabricated by a replacement gate process. In such an approach, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, as opposed to being completed from an earlier process. In an embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is formed using a process comprising SF 6 In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etching process including aqueous NH 4 OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etch including aqueous phosphoric acid.

[0084] In an embodiment, one or more methods described herein essentially contemplate dummy and replacement gate processes that combine dummy and replacement contact processes to achieve structure 700. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than approximately 600 degrees Celsius, such as after forming the gate dielectric layer. The annealing is performed prior to forming the permanent contact.

[0085] Reference again Fig. 7A, the arrangement of the semiconductor structure or device 700 places the gate contact above the isolation region. Such an arrangement may be considered an inefficient use of layout space in some applications. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region. Typically, before forming a gate contact structure (such as a via) above the active portion of the gate and in the same layer as the trench contact via (e.g., in addition to), one or more embodiments of the present disclosure include first using a trench contact process aligned with the gate. Such a process may be implemented to form a trench contact structure for semiconductor structure manufacturing, such as for integrated circuit manufacturing. In an embodiment, the trench contact pattern is formed to align with an existing gate pattern. In contrast, conventional methods typically involve an additional lithography process with a close alignment of the lithographic contact pattern with the existing gate pattern, which is combined with selective contact etching. For example, a conventional process may include patterning of multiple (gate) grids, separate patterning of contact features.

[0086] In a particular embodiment, each of the trench contacts comprises a barrier layer and a conductive fill material. In one such embodiment, the barrier layer is a high purity metal layer, such as described above. In an embodiment, the high purity metal barrier layer has a total atomic composition comprising 98% or greater titanium. In an embodiment, the total atomic composition of the high purity metal barrier layer further comprises 0.5-2% chlorine. In an embodiment, the high purity metal barrier layer has a thickness variation of 30% or less. In an embodiment, the conductive fill material is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof.

[0087] It will be appreciated that not all aspects of the above process need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, a dummy gate need not have been formed before a gate contact is made over the active portion of the gate stack. The above gate stack may actually be a permanent gate stack as initially formed. Moreover, the processes described herein may be used to manufacture one or more semiconductor devices. The semiconductor device may be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Moreover, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for manufacturing semiconductor devices at a technology node of 10 nanometers (10nm) or less.

[0088] In an embodiment, as also used throughout this description, lithography operations are performed by using 193nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, and / or electron beam direct write (EBDW) lithography, etc. Positive photoresist or negative photoresist may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating type layer is a silicon ARC layer.

[0089] The embodiments disclosed herein can be used to manufacture a variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptops, servers), cellular phones, personal electronic devices, and the like. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, and the like via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0090] Figure 8 A computing device 800 according to one implementation of the present disclosure is illustrated. The computing device 800 houses a board 802. The board 802 may include a plurality of components, including, but not limited to, a processor 804 and at least one communication chip 806. The processor 804 is physically and electrically coupled to the board 802. In some implementations, the at least one communication chip 806 is also physically and electrically coupled to the board 802. In other implementations, the communication chip 806 is part of the processor 804.

[0091] Depending on its application, the computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard drives, compact disks (CDs), digital versatile disks (DVDs)), etc.).

[0092] The communication chip 806 enables wireless communication for transferring data to and from the computing device 800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which can transmit data by using modulated electromagnetic radiation, through non-solid media. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not contain. The communication chip 806 can implement any of a plurality of wireless standards or protocols including but not limited to the following: Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing device 800 may include a plurality of communication chips 806. For example, the first communication chip 806 may be dedicated to shorter range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 806 may be dedicated to longer range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0093] The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the present disclosure, the integrated circuit die of the processor includes one or more structures fabricated to include CVD-deposited metal films according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0094] The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. According to another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes one or more structures fabricated to include CVD-deposited metal films according to implementations of embodiments of the disclosure.

[0095] In further implementations, another component housed within computing device 800 may include an integrated circuit die including one or more structures fabricated to include CVD-deposited metal films according to implementations of embodiments of the present disclosure.

[0096] In various implementations, computing device 800 may be a laptop, a netbook, a notebook, an ultrabook, a smart phone, a tablet device, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other implementations, computing device 800 may be any other electronic device that processes data.

[0097] Fig. 9 An interposer 900 including one or more embodiments of the present disclosure is illustrated. Interposer 900 is an intermediate substrate for bridging a first substrate 902 to a second substrate 904. The first substrate 902 may be, for example, an integrated circuit die. The second substrate 904 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 900 is to spread connections to a wider pitch, or to reroute connections to different connections. For example, interposer 900 may couple an integrated circuit die to a ball grid array (BGA) 906, which may then be coupled to a second substrate 904. In some embodiments, the first and second substrates 902 / 904 are attached to opposite sides of interposer 900. In other embodiments, the first and second substrates 902 / 904 are attached to the same side of interposer 900. And in further embodiments, three or more substrates are interconnected by interposer 900.

[0098] The insert 900 may be formed of epoxy, fiberglass reinforced epoxy, ceramic material, or polymer material, such as polyimide. In other implementations, the insert may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0099] The insert 900 may include metal interconnects 908 and vias 910, including but not limited to through silicon vias (TSVs) 912. The insert 900 may further include embedded devices 914, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the insert 900. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used in the manufacture of the insert 900.

[0100] Thus, embodiments described herein include metal chemical vapor deposition methods for fabricating wraparound contacts, and integrated circuit structures including semiconductor structures having wraparound metal contacts.

[0101] The above description of the illustrated implementations of the embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific implementations and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as will be recognized by those skilled in the relevant art.

[0102] In view of the above detailed description, these modifications may be made to the present disclosure. The terms used in the appended claims should not be interpreted as limiting the present disclosure to the specific implementations disclosed in the specification and claims. On the contrary, the scope of the present disclosure will be determined entirely by the appended claims, which will be interpreted according to the established principles of claim interpretation.

[0103] Example Embodiment 1: An integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is above the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-planar topography. A metal contact material is directly on the portion of the semiconductor feature. The metal contact material is conformal to the non-planar topography of the portion of the semiconductor feature. The metal contact material has a total atomic composition including 95% or greater of a single metal species.

[0104] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the metal contact material has a total atomic composition comprising 98% or greater titanium.

[0105] Example Embodiment 3: The integrated circuit structure of Example Embodiment 1 or 2, wherein the total atomic composition of the metal contact material further comprises 0.5-2% chlorine.

[0106] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, 2, or 3, wherein the metal contact material has a thickness variation of 30% or less along the non-planar topography of the portion of the semiconductor feature.

[0107] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3, or 4, wherein the non-planar topography of the portion of the semiconductor feature includes an elevated central portion and lower side portions.

[0108] Example Embodiment 6: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, or 5, wherein the non-planar topography of the portion of the semiconductor feature includes a saddle-shaped portion.

[0109] Example Embodiment 7: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, or 6, wherein the semiconductor feature comprises silicon.

[0110] Example Embodiment 8: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, 6, or 7, wherein the semiconductor feature further comprises germanium.

[0111] Example embodiment 9: An integrated circuit structure of example embodiments 1, 2, 3, 4, 5, 6, 7 or 8, wherein the metal contact material is further along the sidewalls of the trench in the dielectric layer, and wherein the thickness of the metal contact material along the sidewalls of the trench thins from the portion of the semiconductor feature to a position above the portion of the semiconductor feature.

[0112] Example Embodiment 10: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, 6, 7, 8, or 9, further comprising a conductive fill material on the metal contact material within the trench.

[0113] Example embodiment 11: An integrated circuit structure, comprising a semiconductor fin above a substrate, the semiconductor fin having a top and a sidewall. A gate electrode is above the top and adjacent to the sidewall of a portion of the semiconductor fin, the gate electrode defining a channel region in the semiconductor fin. A first semiconductor source / drain structure is at a first end of the channel region at a first side of the gate electrode, the first semiconductor source / drain structure having a non-flat morphology. A second semiconductor source / drain structure is at a second end of the channel region at a second side of the gate electrode, the second end being opposite to the first end, the second side being opposite to the first side, the second semiconductor source / drain structure having a non-flat morphology. A metal contact material is directly on the first semiconductor source / drain structure and directly on the second semiconductor source / drain structure. The metal contact material is conformal to the non-flat morphology of the first semiconductor source / drain structure and conformal to the non-flat morphology of the second semiconductor source / drain structure. The metal contact material has a total atomic composition including 95% or more of a single metal species.

[0114] Example Embodiment 12: The integrated circuit structure of Example Embodiment 11, wherein the metal contact material has a total atomic composition comprising 98% or greater titanium.

[0115] Example Embodiment 13: The integrated circuit structure of Example Embodiment 11 or 12, wherein the total atomic composition of the metal contact material further comprises 0.5-2% chlorine.

[0116] Example Embodiment 14: The integrated circuit structure of Example Embodiment 11, 12 or 13, wherein the metal contact material has a non-planar topography along the first semiconductor source / drain structure and a thickness variation of 30% or less of the non-planar topography along the second semiconductor source / drain structure.

[0117] Example Embodiment 15: The integrated circuit structure of Example Embodiment 11, 12, 13 or 14, wherein the non-planar topography of the first semiconductor source / drain structure and the non-planar topography of the second semiconductor source / drain structure both include an elevated central portion and lower side portions.

[0118] Example Embodiment 16: The integrated circuit structure of Example Embodiment 11, 12, 13, 14 or 15, wherein both the non-planar topography of the first semiconductor source / drain structure and the non-planar topography of the second semiconductor source / drain structure include saddle-shaped portions.

[0119] Example Embodiment 17: The integrated circuit structure of Example Embodiment 11, 12, 13, 14, 15, or 16, wherein both the first semiconductor source / drain structure and the second semiconductor source / drain structure comprise silicon.

[0120] Example Embodiment 18: The integrated circuit structure of Example Embodiment 11, 12, 13, 14, 15, 16, or 17, wherein both the first semiconductor source / drain structure and the second semiconductor source / drain structure further comprise germanium.

[0121] Example embodiment 19: An integrated circuit structure of example embodiments 11, 12, 13, 14, 15, 16, 17 or 18, wherein the metal contact material directly on the first semiconductor source / drain structure is also along the sidewalls of a trench in the dielectric layer above the first semiconductor source / drain structure, the trench exposing a portion of the first semiconductor source / drain structure, and wherein the thickness of the metal contact material along the sidewalls of the trench thins from the first semiconductor source / drain structure to a position above the first semiconductor source / drain structure.

[0122] Example Embodiment 20: The integrated circuit structure of Example Embodiment 19, further comprising a conductive fill material on the metal contact material within the trench.

[0123] Example embodiment 21: The integrated circuit structure of example embodiments 11, 12, 13, 14, 15, 16, 17, 18, 19 or 20, wherein the integrated circuit structure further includes a second semiconductor fin having a top and sidewalls, wherein the gate electrode is further above the top and adjacent to the sidewalls of a portion of the second semiconductor fin, the gate electrode defining a channel region in the second semiconductor fin. A third semiconductor source / drain structure is at a first end of the channel region of the second semiconductor fin at a first side of the gate electrode, the third semiconductor source / drain structure having a non-planar morphology. A fourth semiconductor source / drain structure is at a second end of the channel region of the second semiconductor fin at a second side of the gate electrode, the second end being opposite to the first end, the fourth semiconductor source / drain structure having a non-planar morphology. The metal contact material is directly on the third semiconductor source / drain structure and directly on the fourth semiconductor source / drain structure, the metal contact material being conformal to the non-planar morphology of the third semiconductor source / drain structure and conformal to the non-planar morphology of the fourth semiconductor source / drain structure. The metal contact material is continuous between the first semiconductor source / drain structure and the third semiconductor source / drain structure, and is continuous between the second semiconductor source / drain structure and the fourth semiconductor source / drain structure.

[0124] Example Embodiment 22: A method of manufacturing an integrated circuit structure includes providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, the substrate having features thereon. The method also includes subjecting titanium tetrachloride (TiCl 4 ) and hydrogen (H 2 ) to form a titanium layer on the features of the substrate. The reaction is performed at a temperature in the range of 400-500 degrees Celsius, at a pressure in the range of 0.2-2 Torr, and at an RF frequency of approximately 400 kHz or approximately 13.56 MHz. The titanium layer has a total atomic composition including 98% or greater titanium and 0.5-2% chlorine.

[0125] Example Embodiment 23: The method of Example Embodiment 22, wherein the feature is a source / drain contact trench exposing a semiconductor source / drain structure, and wherein the titanium layer is a conductive contact layer for the semiconductor source / drain structure.

[0126] Example Embodiment 24: The method of Example Embodiment 22, wherein the feature is a conductive line trench of a back end of line (BEOL) metallization layer, and wherein the titanium layer is a barrier layer for the conductive line.

[0127] Example Embodiment 25: The method of Example Embodiment 22, wherein the feature is a gate trench of a semiconductor device, and wherein the titanium layer is a work function layer of a metal gate electrode of the semiconductor device.

Claims

1. An integrated circuit structure, comprising: a semiconductor feature over a substrate; a dielectric layer over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-planar topography; as well as A metal contact material is directly on the portion of the semiconductor feature, the metal contact material conforming to the non-planar topography of the portion of the semiconductor feature, and the metal contact material has an overall atomic composition comprising 95% or greater of a single metallic species.

2. The integrated circuit structure of claim 1, wherein the metal contact material has an overall atomic composition comprising 98% or greater titanium.

3. The integrated circuit structure of claim 2, wherein the total atomic composition of the metal contact material further comprises 0.5-2% chlorine.

4. The integrated circuit structure of claim 1 wherein the metal contact material has a thickness variation of 30% or less along the non-planar topography of the portion of the semiconductor feature.

5. The integrated circuit structure of claim 1, wherein the non-planar topography of the portion of the semiconductor feature comprises an elevated central portion and lower side portions.

6. The integrated circuit structure of claim 1 wherein the non-planar topography of the portion of the semiconductor feature comprises a saddle-shaped portion.

7. The integrated circuit structure of claim 1 wherein the semiconductor feature comprises silicon.

8. The integrated circuit structure of claim 7 wherein the semiconductor feature further comprises germanium.

9. The integrated circuit structure of claim 1 , wherein the metal contact material is further along a sidewall of a trench in the dielectric layer, and wherein a thickness of the metal contact material along the sidewall of the trench decreases from the portion of the semiconductor feature to a position above the portion of the semiconductor feature.

10. The integrated circuit structure of claim 9, further comprising: A conductive fill material is over the metal contact material within the trench.

11. An integrated circuit structure comprising: a semiconductor fin over the substrate, the semiconductor fin having a top and sidewalls; a gate electrode over the top portion and adjacent to a sidewall of a portion of the semiconductor fin, the gate electrode defining a channel region in the semiconductor fin; a first semiconductor source / drain structure at a first end of the channel region at a first side of the gate electrode, the first semiconductor source / drain structure having a non-planar topography; a second semiconductor source / drain structure at a second end of the channel region at a second side of the gate electrode, the second end being opposite to the first end, the second side being opposite to the first side, the second semiconductor source / drain structure having a non-planar morphology; as well as A metal contact material directly on the first semiconductor source / drain structure and directly on the second semiconductor source / drain structure, wherein the metal contact material is conformal to the non-planar morphology of the first semiconductor source / drain structure and is conformal to the non-planar morphology of the second semiconductor source / drain structure, and the metal contact material has a total atomic composition including 95% or greater of a single metal species.

12. The integrated circuit structure of claim 11 wherein the metal contact material has an overall atomic composition comprising 98% or greater titanium.

13. The integrated circuit structure of claim 12, wherein the total atomic composition of the metal contact material further comprises 0.5-2% chlorine.

14. The integrated circuit structure of claim 11, wherein the metal contact material has a non-planar topography along the first semiconductor source / drain structure and a thickness variation of 30% or less along the non-planar topography of the second semiconductor source / drain structure.

15. The integrated circuit structure of claim 11, wherein the non-planar topography of the first semiconductor source / drain structure and the non-planar topography of the second semiconductor source / drain structure both include an elevated central portion and lower side portions.

16. The integrated circuit structure of claim 11, wherein both the non-planar topography of the first semiconductor source / drain structure and the non-planar topography of the second semiconductor source / drain structure include saddle-shaped portions.

17. The integrated circuit structure of claim 11, wherein both the first semiconductor source / drain structure and the second semiconductor source / drain structure comprise silicon.

18. The integrated circuit structure of claim 17, wherein both the first semiconductor source / drain structure and the second semiconductor source / drain structure further comprise germanium.

19. An integrated circuit structure according to claim 11, wherein the metal contact material directly on the first semiconductor source / drain structure is further along the sidewalls of a trench in the dielectric layer above the first semiconductor source / drain structure, the trench exposing a portion of the first semiconductor source / drain structure, and wherein the thickness of the metal contact material along the sidewalls of the trench thins from the first semiconductor source / drain structure to a position above the first semiconductor source / drain structure.

20. The integrated circuit structure of claim 19, further comprising: A conductive fill material is over the metal contact material within the trench.

21. The integrated circuit structure of claim 11, further comprising: a second semiconductor fin having a top and sidewalls, wherein the gate electrode is further over the top and adjacent to the sidewalls of a portion of the second semiconductor fin, the gate electrode defining a channel region in the second semiconductor fin; a third semiconductor source / drain structure at a first end of a channel region of a second semiconductor fin at a first side of the gate electrode, the third semiconductor source / drain structure having a non-planar topography; as well as A fourth semiconductor source / drain structure at a second end of a channel region of a second semiconductor fin at a second side of a gate electrode, the second end being opposite to the first end, the fourth semiconductor source / drain structure having a non-planar morphology, wherein the metal contact material is directly on the third semiconductor source / drain structure and directly on the fourth semiconductor source / drain structure, the metal contact material is conformal to the non-planar morphology of the third semiconductor source / drain structure and is conformal to the non-planar morphology of the fourth semiconductor source / drain structure, and the metal contact material is continuous between the first semiconductor source / drain structure and the third semiconductor source / drain structure, and is continuous between the second semiconductor source / drain structure and the fourth semiconductor source / drain structure.

22. A method of manufacturing an integrated circuit structure, the method comprising: providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, the substrate having a semiconductor feature thereon, the semiconductor feature having a portion with a non-planar topography; as well as Titanium tetrachloride (TiCl4) and hydrogen (H2) are reacted to form a titanium layer on and conformally with the non-planar topography of the semiconductor feature, wherein the reaction is performed at a temperature in the range of 400-500 degrees Celsius, at a pressure in the range of 0.2-2 Torr, and at an RF frequency of approximately 400 kHz or approximately 13.56 MHz, and wherein the titanium layer has a total atomic composition comprising 98% or greater titanium and 0.5-2% chlorine.

23. The method of claim 22, wherein the semiconductor feature is a semiconductor source / drain structure, and wherein the titanium layer is a conductive contact layer for the semiconductor source / drain structure.

24. The method of claim 22, wherein the non-planar topography of the portion of the semiconductor feature comprises an elevated central portion and lower side portions.

25. The method of claim 22, wherein the non-planar topography of the portion of the semiconductor feature comprises a saddle-shaped portion.

26. A computer readable medium having stored thereon instructions which, when executed, cause a computing device to perform the method of any one of claims 22 to 25.

27. An apparatus for manufacturing an integrated circuit structure, the apparatus comprising: Means for providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, the substrate having a semiconductor feature thereon, the semiconductor feature having a portion with a non-planar topography; as well as Means for reacting titanium tetrachloride (TiCl4) and hydrogen (H2) to form a titanium layer on and conformally with the non-planar topography of the semiconductor feature, wherein the reaction is performed at a temperature in the range of 400-500 degrees Celsius, at a pressure in the range of 0.2-2 Torr, and at an RF frequency of approximately 400 kHz or approximately 13.56 MHz, and wherein the titanium layer has a total atomic composition comprising 98% or greater titanium and 0.5-2% chlorine.

28. The device of claim 27, wherein the semiconductor feature is a semiconductor source / drain structure, and wherein the titanium layer is a conductive contact layer for the semiconductor source / drain structure.

29. The apparatus of claim 27, wherein the non-planar topography of the portion of the semiconductor feature comprises an elevated central portion and lower side portions.

30. The apparatus of claim 27, wherein the non-planar topography of the portion of the semiconductor feature comprises a saddle-shaped portion.

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