Memory device including multiple latches and system on chip including the device

Abstract

The memory device includes: a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows; a first trigger configured to output first data to a first latch arranged in the first column among the plurality of latches based on a clock; and a second trigger configured to output second data to a second latch arranged in the second column among the plurality of latches based on a clock. The first trigger is also configured to block the output of the first data to the first latch during a lock period in which the first latch and the second latch maintain output regardless of input, and the second trigger is also configured to block the output of the second data to the second latch during the lock period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application Nos. 10-2018-0039997 and 10-2018-0122034 filed on April 5, 2018 and October 12, 2018, respectively, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Apparatuses consistent with the embodiments relate to a memory device and a system on chip including the memory device, and more particularly, to a memory device for storing data through a shared latch and a plurality of latches connected to the shared latch, and a system on chip including the memory device. Background Art

[0004] With the development of mobile products such as tablet PCs or mobile phones, high performance of a computing system including component devices such as memory devices and SoCs may be required. The SoC includes a memory device for storing data therein. The memory device may include a plurality of latches arranged in columns and rows. The memory device may write data to the plurality of latches and read the written data. Since high performance and low power of the SoC may be required, the memory device included in the SoC may require high performance and low power. Summary of the invention

[0005] According to an embodiment, a memory device includes: a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, each latch of the plurality of latches being configured to store at least one bit of data; a first flip-flop configured to output first data to a first latch arranged in the first column among the plurality of latches based on a clock; and a second flip-flop configured to output second data to a second latch arranged in the second column among the plurality of latches based on a clock. The first flip-flop is further configured to block the output of the first data to the first latch during a lock period in which the first latch and the second latch maintain output regardless of input, and the second flip-flop is further configured to block the output of the second data to the second latch during the lock period.

[0006] According to an embodiment, a system on chip includes: a control processing unit (CPU) configured to write first data to a plurality of latches by accessing the plurality of latches; and a memory device configured to store the first data corresponding to the access of the CPU. The memory device includes: a plurality of latches arranged in a plurality of columns including a first column and in a plurality of rows, each of the plurality of latches being configured to store at least one bit of data; and a first blocking circuit configured to output at least some bits of the first data to a first latch arranged in the first column among the plurality of latches based on a clock, and to block a signal applied to the first latch arranged in the first column during a locking period in which the first latch arranged in the first column does not output data.

[0007] According to an embodiment, a memory device includes: a plurality of latches arranged in a plurality of columns and a plurality of rows, each latch in the plurality of latches being configured to store at least one bit of data; and a bitwise enabler configured to shield one or more latches arranged in at least some of the plurality of columns based on a plurality of bit enable signals. The one or more latches are configured to receive write data without storing the write data when shielded by the bitwise enabler. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a computing system according to an embodiment of the inventive concept.

[0009] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the inventive concept.

[0010] Figure 3 is a circuit diagram illustrating a memory device according to an embodiment of the inventive concept.

[0011] Figure 4 is a circuit diagram illustrating a memory device according to an embodiment of the inventive concept.

[0012] Figure 5 is a timing diagram illustrating the operation of a memory device according to an embodiment of the inventive concept.

[0013] Fig. 6A , Figure 6B and Figure 6C Operations of a memory device according to an embodiment of the inventive concept are illustrated.

[0014] Figure 7 is a circuit diagram illustrating a memory device according to an embodiment of the inventive concept.

[0015] Figure 8 is a circuit diagram illustrating a memory device according to an embodiment of the inventive concept.

[0016] Fig. 9is a block diagram illustrating a memory device according to an embodiment of the inventive concept.

[0017] Fig. 10A is a block diagram illustrating a memory device according to an embodiment of the inventive concept.

[0018] Fig. 10B is a block diagram illustrating a memory device according to an embodiment of the inventive concept.

[0019] Fig. 10C is a block diagram illustrating a memory device according to an embodiment of the inventive concept.

[0020] Fig.11 is a circuit diagram illustrating a memory device according to an embodiment of the inventive concept.

[0021] Fig.12 is a circuit diagram illustrating a memory device according to an embodiment of the inventive concept.

[0022] Fig.13 is a circuit diagram illustrating a memory device according to an embodiment of the inventive concept.

[0023] Fig.14 is a block diagram illustrating an interface used in a computing system according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0024] The inventive concept provides a memory device capable of minimizing power consumption by including a shared latch, and a system on chip including the memory device.

[0025] The inventive concept also provides a memory device capable of selectively writing data bits by including a masking circuit for masking the plurality of latches per column when writing data into the plurality of latches, and a system on chip including the memory device.

[0026] Figure 1 is a block diagram illustrating a computing system according to an embodiment of the inventive concept.

[0027] refer to Figure 1 , the system on chip 1 may include a memory device 10, a CPU 11, a bus 12, and a plurality of functional blocks 13_1 and 13_2. The system on chip 1 may be applied to a smart phone, a tablet personal computer (PC), a digital camera, a mobile device, a set-top box, a smart card system, a server system, and various electronic devices. The system on chip 1 may include a plurality of components on one chip. For example, the system on chip 1 may include a device controller for controlling component devices such as the memory device 10, the plurality of functional blocks 13_1 and 13_2. According to an embodiment, the system on chip 1 may be implemented as an application processor.

[0028] The CPU 11 may control operations of the memory device 10 and the plurality of function blocks 13_1 and 13_2 connected via the bus 12. For example, the CPU 11 may write or read data by accessing the memory device 10.

[0029] The memory device 10 may store instructions, data or program codes for the operation of the system on chip 1. In an embodiment, the memory device 10 may include a plurality of latches, and data may be written to the plurality of latches. The memory device 10 may be a latch-based memory.

[0030] The plurality of functional blocks 13_1 and 13_2 may perform various functions supported by the system on chip 1. For example, the plurality of functional blocks 13_1 and 13_2 may include a modem, a memory controller, an input / output device, a display device, a digital signal processor (DSP), a universal serial bus (USB) controller, a peripheral component interconnect (PCI) interface, and the like.

[0031] The memory device 10 according to an embodiment of the inventive concept may include a blocking circuit shared by a plurality of latches. The blocking circuit may block signal transmission to the plurality of latches during a period in which the plurality of latches are locked, thereby reducing power consumed by the memory device 10.

[0032] Figure 2 is a block diagram illustrating a memory device 10 according to an embodiment of the inventive concept.

[0033] refer to Figure 2 , the memory device 10 may include a memory cell array 110 , a clock gating circuit 120 , a row decoder 130 , a blocking circuit 140 , a write enabler 150 , and a column decoder 160 .

[0034] The memory cell array 110 may include a plurality of memory cells arranged in rows and columns. In an embodiment, the plurality of memory cells may be a plurality of latches. The memory cell array 110 may store write data Data_w based on a clock Clk. The plurality of latches may be connected to a row decoder 130 and a clock gating circuit 120 along a row direction, and may be connected to a blocking circuit 140 and a column decoder 160 along a column direction.

[0035] The row decoder 130 may receive the row address Addr_R and may output a row enable signal En_Row generated by decoding the row address Addr_R to the clock gating circuit 120. The clock gating circuit 120 may output a clock Clk to a corresponding row of the memory cell array 110 based on the row enable signal En_Row.

[0036] The write enabler 150 may output a clock Clk to the clock gating circuit 120 and the blocking circuit 140 based on the write enable signal En_w. The blocking circuit 140 may receive the write data Data_w, and may output the write data Data_w to the memory cell array 110 based on the clock Clk. The blocking circuit 140 may be connected to a plurality of latches arranged along a column direction, and may block the output of the write data Data_w in a locking period in which the plurality of latches arranged along a column direction are locked.

[0037] The column decoder 160 may receive the column address Addr_C and output a column enable signal En_Col generated by decoding the received column address Addr_C to the memory cell array 110. The memory cell array 110 may output data of a corresponding column based on the column enable signal En_Col.

[0038] The memory device 10 according to an embodiment of the inventive concept may include a blocking circuit 140 that blocks data output to the memory cell array 110 during a period in which the memory cell array 110 may not store data, thereby preventing unnecessary power consumption and improving performance.

[0039] Figure 3 1 is a circuit diagram showing a memory device 10 according to an embodiment of the inventive concept. Figure 2 and Figure 3 Redundant description between .

[0040] refer to Figure 3 , the memory device 10 may include a memory cell array 110, a clock gating circuit 120, a row decoder 130, a first blocking circuit 140_1, a second blocking circuit 140_2, a write enabler 150, and a column decoder 160. Figure 2 The row decoder 130 , the write enabler 150 , and the column decoder 160 are described, and thus descriptions thereof will be omitted.

[0041] The memory cell array 110 may include a first latch L1 to a sixth latch L6. The first latch L1 to the third latch L3 (first latch) may be arranged in a first column C1. The fourth latch L4 to the sixth latch L6 (second latch) may be arranged in a second column C2. An embodiment including six latches L1 to L6 in the memory cell array 110 is described below, but this is only an embodiment. The memory cell array 110 may include six latches, more or less.

[0042] The clock gating circuit 120 may include first to third clock gates CG1 to CG3. The first clock gate CG1 may be connected to a first latch L1 and a fourth latch L4 (third latch) arranged in a first row of the memory cell array 110. The second clock gate CG2 may be connected to a second latch L2 and a fifth latch L5 (fourth latch) arranged in a second row of the memory cell array 110. The third clock gate CG3 may be connected to a third latch L3 and a sixth latch L6 arranged in a third row of the memory cell array 110.

[0043] The first clock gate CG1 may output the clock Clk received from the write enabler 150 to the first latch L1 and the fourth latch L4 based on the first row enable signal En_Row1 received from the row decoder 130. The second clock gate CG2 may output the clock Clk received from the write enabler 150 to the second latch L2 and the fifth latch L5 based on the second row enable signal En_Row2 received from the row decoder 130. The third clock gate CG3 may output the clock Clk received from the write enabler 150 to the third latch L3 and the sixth latch L6 based on the third row enable signal En_Row3 received from the row decoder 130.

[0044] The first blocking circuit 140_1 may include a first flip-flop FF1. The second blocking circuit 140_2 may include a second flip-flop FF2. The first flip-flop FF1 may receive a first write data bit WD1, and output the first write data bit WD1 to the first latch L1 to the third latch L3 corresponding to the edge of the clock Clk received from the write enabler 150. The first latch L1 to the third latch L3 may store the first write data bit WD1 based on the clock Clk of the clock gating circuit 120. The second flip-flop FF2 may receive a second write data bit WD2, and output the second write data bit WD2 to the fourth latch L4 to the sixth latch L6 corresponding to the edge of the clock Clk received from the write enabler 150. The fourth latch L4 to the sixth latch L6 may store the second write data bit WD2 based on the clock Clk of the clock gating circuit 120.

[0045] According to an embodiment conceived in the present invention, the blocking circuits 140_1 and 140_2 may respectively include a first trigger FF1 and a second trigger FF2, which may not output data for the first latch L1 to the sixth latch L6 during the locking time period in which the first latch L1 to the sixth latch L6 are locked, and uniformly maintain the output, thereby preventing power consumption according to the output of the first write data bit WD1 and the second write data bit WD2.

[0046] The column decoder 160 may output a first column selection signal Sel_C1 to the first multiplexer MUX1 based on the column address Addr_C, so the first multiplexer MUX1 may output data stored in any one of the first latch L1 to the third latch L3 as the first read data bit RD1. The column decoder 160 may also output a second column selection signal Sel_C2 to the second multiplexer MUX2 based on the column address Addr_C, so the second multiplexer MUX2 may output data stored in any one of the fourth latch L4 to the sixth latch L6 as the second read data bit RD2.

[0047] Figure 4 1 is a circuit diagram showing a memory device 10a according to an embodiment of the inventive concept. Figure 3 and Figure 4 Redundant description between .

[0048] refer to Figure 4 , the memory device 10a may include a memory cell array 110, a clock gating circuit 120, a row decoder 130, a first blocking circuit 140_1a, a second blocking circuit 140_2a, a write enabler 150, and a column decoder 160. Figure 3 The memory cell array 110 , the clock gating circuit 120 , the row decoder 130 , the write enabler 150 , and the column decoder 160 are described, and thus a description thereof will be omitted.

[0049] The first blocking circuit 140_1a may include a first shared latch SL1 and a second shared latch SL2. The second blocking circuit 140_2a may include a third shared latch SL3 and a fourth shared latch SL4. The first shared latch SL1 and the second shared latch SL2 and the first latch L1 to the third latch L3 may operate in different phases of the clock Clk. For example, the first shared latch SL1 may be in a pass state in the first phase of the clock Clk, and may be in a locked state in the second phase of the clock Clk. On the other hand, the second shared latch SL2 and the first latch L1 to the third latch L3 may be in a locked state in the first phase of the clock Clk, and may be in a pass state in the second phase of the clock Clk.

[0050] The third shared latch SL3 and the fourth shared latch SL4 and the fourth latch L4 to the sixth latch L6 can operate in different phases of the clock Clk. For example, the third shared latch SL3 can be in a pass state in the first phase of the clock Clk, and can be in a locked state in the second phase of the clock Clk. On the other hand, the second shared latch SL2 and the first latch L1 to the third latch L3 can be in a locked state in the first phase of the clock Clk, and can be in a pass state in the second phase of the clock Clk.

[0051] The lock state may refer to a state in which data stored in the latch is not output to the output terminal Q, and the pass state may refer to a state in which data stored in the latch is output to the output terminal Q. Alternatively, the lock state may refer to a state in which an output signal is maintained at a previous level regardless of an input signal, and the pass state may refer to a state in which an output signal is changed or maintained based on an input signal.

[0052] The memory device 10a according to an embodiment conceived in the present invention may include shared latches SL2 and SL4 in a locked state, which are in the same phase as the multiple latches L1 to L6 included in the memory cell array 110, thereby blocking signal transmission to the memory cell array 110 during a locking period in which the multiple latches L1 to L6 are in the locked state, and thus preventing power consumption due to unnecessary signal transmission.

[0053] Figure 5 is a timing diagram illustrating the operation of a memory device according to an embodiment of the inventive concept. More specifically, Figure 5 is a timing diagram illustrating operations of latches L1 to L3 included in a first column of a memory cell array and shared latches SL1 and SL2 connected to the latches L1 to L3 .

[0054] refer to Figure 4 and Figure 5 , when the write enable signal En_W transitions to the first phase (eg, logic high) from the first time point t1 , the clock Clk may be output to the first shared latch SL1 , the second shared latch SL2 , and the first to third latches L1 to L3 .

[0055] Because the clock Clk is in the first phase (eg, logic high) from the second time point t2 to the third time point t3 , the first shared latch SL1 may be in a lock state, and the second shared latch SL2 and the first to third latches L1 to L3 may be in a pass state.

[0056] Because the clock Clk is in the second phase (eg, logic low) from the third time point t3 to the fourth time point t4 , the first shared latch SL1 may be in a pass state, and the second shared latch SL2 and the first to third latches L1 to L3 may be in a lock state.

[0057] Because the clock Clk is in the first phase (eg, logic high) at the fourth to fifth time points t4 to t5 , the first shared latch SL1 may be in a lock state, and the second shared latch SL2 and the first to third latches L1 to L3 may be in a pass state.

[0058] Fig. 6A , Figure 6B and Figure 6C The operation of the memory device according to the embodiment of the present invention is shown. More specifically, Fig. 6A shows the memory device in Figure 4 Operations at the second time point t2 and the third time point t3 in . Figure 6B Shows Figure 4 Operation of the memory device in at a third time point t3 and a fourth time point t4. Figure 6C Shows Figure 4 Operation of the memory device in at a fourth time point t4 and a fifth time point t5.

[0059] refer to Figure 4 and Fig. 6A , when the first shared latch SL1 is in the locked state at the second time point t2 and the third time point t3, the first write data bit WD1 may be stored in the first shared latch SL1 and may not be transmitted to the second shared latch SL2.

[0060] refer to Figure 4 and Figure 6B , when the first shared latch SL1 is converted to the pass state at the third time point t3 and the fourth time point t4, the first write data bit WD1 stored in the first shared latch SL1 may be transferred to the second shared latch SL2, and the second shared latch SL2 may store the first write data bit WD1.

[0061] refer to Figure 4 and Figure 6C , when the second shared latch SL2 is converted to the pass state at the fourth time point t4 and the fifth time point t5, the first write data bit WD1 stored in the second shared latch SL2 can be transmitted to the first latch L1 to the third latch L3, and the first latch L1 to the third latch L3 can store the first write data bit WD1.

[0062] According to an embodiment of the inventive concept, since signals transmitted to the plurality of latches L1 to L3 at the third time point t3 and the fourth time point t4 may be blocked by the second shared latch SL2 , unnecessary signals may be prevented from being transmitted, thereby reducing power consumption.

[0063] Figure 7 1 is a circuit diagram showing a memory device 10b according to an embodiment of the inventive concept. Figure 3 and Figure 7 Redundant description between .

[0064] refer to Figure 7 , the memory device 10b may include a memory cell array 110, a clock gating circuit 120b, a row decoder 130, blocking circuits 140_1 and 140_2, and a write enabler 150. Figure 3 The memory cell array 110 , the row decoder 130 , the blocking circuits 140_1 and 140_2 , and the write enabler 150 are described, and thus a description thereof will be omitted.

[0065] The clock gating circuit 120 b may include a first row AND gate RA1 , a second row AND gate RA2 , a third row AND gate RA3 , a first row latch RL1 , a second row latch RL2 , and a third row latch RL3 .

[0066] The first row latch RL1 may output a first row enable signal En_Row1 to the first row AND gate RA1 based on the clock Clk received from the write enabler 150. The first row AND gate RA1 may be connected to the latches L1 and L4 arranged in the first row, and may output a first signal Sig1 generated by an AND operation of the clock Clk received from the write enabler 150 and the first row enable signal En_Row1 received from the first row latch RL1 to the latches L1 and L4 arranged in the first row. As a result, when there is the first row enable signal En_Row1, the first row latch RL1 and the first row AND gate RA1 may output the clock Clk as the first signal Sig1 to the latches L1 and L4 arranged in the first row.

[0067] The second row latch RL2 may output the second row enable signal En_Row2 to the second row AND gate RA2 based on the clock Clk received from the write enabler 150. The second row AND gate RA2 may be connected to the latches L2 and L5 arranged in the second row, and may output the second signal Sig2 generated by the AND operation of the clock Clk received from the write enabler 150 and the second row enable signal En_Row2 received from the second row latch RL2 to the latches L2 and L5 arranged in the second row. As a result, when there is the second row enable signal En_Row2, the second row latch RL2 and the second row AND gate RA2 may output the clock Clk as the second signal Sig2 to the latches L2 and L5 arranged in the second row.

[0068] The third row latch RL3 may output the third row enable signal En_Row3 to the third row AND gate RA3 based on the clock Clk received from the write enabler 150. The third row AND gate RA3 may be connected to the latches L3 and L6 arranged in the third row, and may output the third signal Sig3 generated by the AND operation of the clock Clk received from the write enabler 150 and the third row enable signal En_Row3 received from the third row latch RL3 to the latches L3 and L6 arranged in the third row. As a result, when there is the third row enable signal En_Row3, the third row latch RL3 and the third row AND gate RA3 may output the clock Clk as the third signal Sig3 to the latches L3 and L6 arranged in the third row.

[0069] In an embodiment, the first to third row latches RL1 to RL3 and the first to sixth latches L1 to L6 of the memory cell array 110 may operate in different phases of the clock Clk.

[0070] Figure 8 1 is a circuit diagram showing a memory device 10c according to an embodiment of the inventive concept. Figure 7 and Figure 8 Redundant description between .

[0071] refer to Figure 8 , the memory device 10c may include a memory cell array 110, a clock gating circuit 120c, a gating latch GL, a row decoder 130, blocking circuits 140_1 and 140_2, and a write enabler 150. Figure 3 The memory cell array 110 , the row decoder 130 , the blocking circuits 140_1 and 140_2 , and the write enabler 150 are described, and thus a description thereof will be omitted.

[0072] The gating latch GL may receive the row address Addr_R and output the row address Addr_R to the row decoder 130 based on the clock Clk received from the write enabler 150. In an embodiment, the gating latch GL and the first to sixth latches L1 to L6 included in the memory cell array 110 may operate in different phases of the clock Clk.

[0073] The row decoder 130 may output any one or any combination of the first row enable signals En_Row1 to the third row enable signals En_Row3 generated by decoding the row address Addr_R to the first row AND gates RA1 to the third row AND gates RA3, respectively. The first row AND gates RA1 to the third row AND gates RA3 may output first signals Sig1 to third signals Sig3 generated based on the first row enable signals En_Row1 to the third row enable signals En_Row3 to the memory cell array 110, respectively.

[0074] Fig. 9 1 is a block diagram showing a memory device 10d according to an embodiment of the inventive concept. Figure 2 and Fig. 9 Redundant description between .

[0075] refer to Fig. 9 , the memory device 10d may include a memory cell array 110, a clock gating circuit 120, a row decoder 130, a blocking circuit 140, a write enabler 150, a column decoder 160, and a bitwise enabler 170. Figure 2 The memory cell array 110 , the clock gating circuit 120 , the row decoder 130 , the blocking circuit 140 , the write enabler 150 , and the column decoder 160 are described, and thus descriptions thereof are omitted.

[0076] The bitwise enabler 170 may include at least one mask circuit 171 connected to a row of the memory cell array 110. The at least one mask circuit 171 may be externally (eg, Figure 1 The CPU 11 receives the bitwise enable signal En_BW and generates a mask signal Sig_M based on the bitwise enable signal En_BW. At least one latch included in the memory cell array 110 may be masked corresponding to the mask signal Sig_M. The masked latch may be prevented from writing data. In an embodiment, the mask signal Sig_M may be generated for each data bit.

[0077] The memory device 10d according to an embodiment of the present invention can perform data writing only on multiple latches that are not masked after performing masking on each bit, thereby preventing unnecessary data writing operations, thereby reducing the power consumption of the memory device 10d and improving the data writing performance of the memory device 10d.

[0078] Fig. 10A is a block diagram illustrating a memory device 10 e according to an embodiment of the inventive concept.

[0079] refer to Fig. 10A , the memory device 10e may include first to fourth masking circuits 171e to 174e and first to twelfth latches L1 to L12. The first to twelfth latches L1 to L12 may constitute a memory cell array arranged in rows and columns.

[0080] The first shielding circuit 171e may be connected to the latches L1, L2, and L3 arranged in the first column, and may output the first shielding signal Sig_M1 to the latches L1, L2, and L3 arranged in the first column based on the first bitwise enable signal En_BW1. The second shielding circuit 172e may be connected to the latches L4, L5, and L6 arranged in the second column, and may output the second shielding signal Sig_M2 to the latches L4, L5, and L6 arranged in the second column based on the second bitwise enable signal En_BW2. The third shielding circuit 173e may be connected to the latches L7, L8, and L9 arranged in the third column, and may output the third shielding signal Sig_M3 to the latches L7, L8, and L9 arranged in the third column based on the third bitwise enable signal En_BW3. The fourth masking circuit 174 e may be connected to the latches L10 , L11 , and L12 arranged in a fourth column, and may output a fourth masking signal Sig_M4 to the latches L10 , L11 , and L12 arranged in the fourth column based on the fourth bitwise enable signal En_BW4 .

[0081] In an embodiment, the data written to the memory device 10e may include 4 bits. The first bit D1_1, D1_2, and D1_3 of the data may be written to latches L1, L2, and L3 arranged in the first column. The second bit D2_1, D2_2, and D2_3 of the data may be written to latches L4, L5, and L6 arranged in the second column. In addition, the third bit D3_1, D3_2, and D3_3 of the data may be written to latches L7, L8, and L9 arranged in the third column. The fourth bit D4_1, D4_2, and D4_3 of the data may be written to latches L10, L11, and L12 arranged in the fourth column.

[0082] exist Fig. 10AIn the example of , when "1" is output as the first bitwise enable signal En_BW1, the second bitwise enable signal En_BW2, and the fourth bitwise enable signal En_BW4, data may be written to latches L1, L2, L3, and L4, L5, L6, L10, L11, L12 arranged in the second and fourth columns. On the other hand, when "0" is output as the third bitwise enable signal En_BW3, latches L7, L8, and L9 arranged in the third column may be masked, data may not be written, and existing data may be retained.

[0083] The memory device 10 e according to an embodiment of the inventive concept may prevent unnecessary write operations by shielding latches arranged in at least one column.

[0084] Fig. 10B 1 is a block diagram showing a memory device 10f according to an embodiment of the inventive concept. In detail, Fig. 10B An embodiment that performs 2-bit masking can be shown. Fig. 10A and Fig. 10B Redundant description between .

[0085] refer to Fig. 10B , the memory device 10f may include first to fourth masking circuits 171f to 174f and first to twelfth latches L1 to L12. The first to twelfth latches L1 to L12 may constitute a memory cell array arranged in rows and columns.

[0086] The first shielding circuit 171f and the second shielding circuit 172f can shield the latches L1, L2 and L3 arranged in the first column or the latches L4, L5 and L6 arranged in the second column based on the first bitwise enable signal En_BW1. The third shielding circuit 173f and the fourth shielding circuit 174f can shield the latches L7, L8 and L9 arranged in the third column or the latches L10, L11 and L12 arranged in the fourth column based on the second bitwise enable signal En_BW2.

[0087] exist Fig. 10B In the example of , when "1" is output as the first bitwise enable signal En_BW1, data writing may be performed on latches L1, L2, L3, L4, L5, and L6 arranged in the first and second columns. On the other hand, when "0" is output as the second bitwise enable signal En_BW2, masking may be performed on latches L7, L8, L9, L10, L11, and L12 arranged in the third and fourth columns, data writing may not be performed, and existing data may be retained.

[0088] Fig. 10BAn embodiment in which masking is performed for every two bits is shown, but this is only one embodiment. The technical concept of the inventive concept can also be applied to an embodiment in which masking is performed for more than or less than 2 bits.

[0089] Fig. 10C is a block diagram illustrating a memory device 10g according to an embodiment of the inventive concept. Fig. 10C Latches arranged in multiple columns connected to one shielding circuit may be shown. Fig. 10B and Fig. 10C Redundant description between .

[0090] refer to Fig. 10C , the memory device 10g may include a first masking circuit 171g, a second masking circuit 173g, and first to twelfth latches L1 to L12.

[0091] The first shielding circuit 171g can shield the latches L1, L2, L3, L4, L5 and L6 arranged in the first and second columns based on the first bitwise enable signal En_BW1. The second shielding circuit 173g can shield the latches L7, L8, L9, L10, L11 and L12 arranged in the third and fourth columns based on the second bitwise enable signal En_BW2.

[0092] exist Fig. 10C In the example of , when "1" is output as the first bitwise enable signal En_BW1, data writing may be performed on the latches L1, L2, L3, L4, L5, and L6 arranged in the first and second columns. On the other hand, when "0" is output as the second bitwise enable signal En_BW2, the second shielding circuit 173g may shield the latches L7, L8, L9, L10, L11, and L12 arranged in the third and fourth columns, data writing may not be performed on the latches L7, L8, L9, L10, L11, and L12 arranged in the third and fourth columns, and the existing data may be retained.

[0093] Fig. 10C An embodiment in which masking is performed every two bits is shown, which is only one embodiment. More than two columns may be connected to one masking circuit 171g or 173g to perform masking using more than 2 bits.

[0094] Fig.11 1 is a circuit diagram showing a memory device 10h according to an embodiment of the inventive concept. Figure 3 and Fig.11 Redundant description between .

[0095] refer to Fig.11, the memory device 10h may include a plurality of latches L1 to L6, a clock gating circuit 120, a row decoder 130, a first blocking circuit 140_1, a second blocking circuit 140_2, a write enabler 150, a column decoder 160, a first masking circuit 171h and a second masking circuit 172h. Figure 3 The plurality of latches L1 to L6 , the clock gating circuit 120 , the row decoder 130 , the first blocking circuit 140_1 , the second blocking circuit 140_2 , the write enabler 150 , and the column decoder 160 are described, and thus a description thereof will be omitted.

[0096] The first shielding circuit 171h may include a first shielding latch ML1 and first to third shielding AND gates MA1 to MA3. The second shielding circuit 172h may include a second shielding latch ML2 and fourth to sixth shielding AND gates MA4 to MA6.

[0097] The first shielding latch ML1 can receive the first bitwise enable signal En_BW1, and can output the first shielding signal Sig_M1 generated based on the clock Clk to the first shielding AND gate MA1 to the third shielding AND gate MA3. In an embodiment, the first shielding latch ML1 and the first latch L1 to the sixth latch L6 can operate in different phases of the clock Clk.

[0098] Only when the first shielding signal Sig_M1 is "1", the first shielding AND gate MA1 to the third shielding AND gate MA3 can output the clock Clk received from the first clock gate CG1 to the third clock gate CG3. As a result, when the first shielding signal Sig_M1 output from the first shielding latch ML1 is "0", the clock signal CLK output to the latches L1, L2 and L3 included in the first column C1 can be blocked by the first shielding AND gate MA1 to the third shielding AND gate MA3, and therefore, data may not be written to the latches L1, L2, L3 included in the first column C1.

[0099] The second shielding latch ML2 can receive the second bitwise enable signal En_BW2, and can output the second shielding signal Sig_M1 generated based on the clock Clk to the fourth shielding AND gate MA4 to the sixth shielding AND gate MA6. In an embodiment, the second shielding latch ML2 and the first latch L1 to the sixth latch L6 can operate in different phases of the clock Clk.

[0100] Only when the second shielding signal Sig_M2 is "1", the fourth shielding "AND" gate MA4 to the sixth shielding "AND" gate MA6 can output the clock Clk received from the first clock gate CG1 to the third clock gate CG3. As a result, when the second shielding signal Sig_M2 output from the second shielding latch ML2 is "0", the clock signal CLK output to the latches L4, L5 and L6 included in the second column C2 can be blocked by the fourth shielding "AND" gate MA4 to the sixth shielding "AND" gate MA6, and therefore, data may not be written to the latches L4, L5 and L6 included in the first column C2.

[0101] Fig.12 1 is a circuit diagram showing a memory device 10i according to an embodiment of the inventive concept. Figure 8 , Fig.11 and Fig.12 Redundant description between .

[0102] refer to Fig.12 , the memory device 10i may include a plurality of latches L1 to L6, a clock gating circuit 120i, a row decoder 130, a first blocking circuit 140_1, a second blocking circuit 140_2, a write enabler 150, a column decoder 160, a first masking circuit 171i, a second masking circuit 172i, and a gated latch GL. Fig.11 etc. describe the plurality of latches L1 to L6, the row decoder 130, the first blocking circuit 140_1, the second blocking circuit 140_2, the write enabler 150, the column decoder 160, the first masking circuit 171i, and the second masking circuit 172i, and thus a description thereof will be omitted.

[0103] The gated latch GL may output the row address Addr_R to the row decoder 130 based on the clock Clk. The row decoder 130 may output any one or any combination of first to third row enable signals En_Row1 to En_Row3 generated by decoding the row address Addr_R to first to third row AND gates RA1 to RA3.

[0104] The first row AND gate RA1 to the third row AND gate RA3 can output the clock Clk received from the write enabler 150 to the first shielded AND gate MA1 to the sixth shielded AND gate MA6 based on the first row enable signal En_Row1 to the third row enable signal En_Row3. The first shielded AND gate MA1 to the sixth shielded AND gate MA6 can output the clock Clk to the first latch L1 to the sixth latch L6 based on the shielding signals Sig_M1 and Sig_M2.

[0105] Fig.131 is a circuit diagram showing a memory device 10j according to an embodiment of the inventive concept. Fig.11 and Fig.13 Redundant description between .

[0106] refer to Fig.13 , the memory device 10j may include a plurality of latches L1 to L6, a row decoder 130, a first blocking circuit 140_1, a second blocking circuit 140_2, a write enabler 150, a column decoder 160, a first shielding clock gate MCG1, a second shielding clock gate MCG2, a first shielding circuit 171j, a second shielding circuit 172j, and a gated latch GL. Fig.11 and Fig.12 etc. describe the plurality of latches L1 to L6 , the row decoder 130 , the first blocking circuit 140_1 , the second blocking circuit 140_2 , the write enabler 150 , the column decoder 160 , and the gated latch GL, and thus a description thereof will be omitted.

[0107] The first masking clock gate MCG1 may receive the clock Clk from the write enabler 150 and output the clock Clk to the first blocking circuit 140_1 and the first masking circuit 171j based on the first bitwise enable signal En_BW1. The first blocking circuit 140_1 may output the first write data bit WD1 to the latches L1, L2 and L3 arranged in the first column C1 based on the clock Clk.

[0108] The first shielding circuit 171j may include first to third shielding AND gates MA1 to MA3. The first to third shielding AND gates MA1 to MA3 may output the clock Clk received from the first shielding clock gate MCG1 to the first to third latches L1 to L3 based on the first to third row enable signals En_Row1 to En_Row3.

[0109] The second masking clock gate MCG2 may receive the clock Clk from the write enabler 150 and may output the clock Clk to the second blocking circuit 140_2 and the second masking circuit 172j based on the second bitwise enable signal En_BW2. The first blocking circuit 140_1 may output the second write data bit WD2 to the latches L4, L5 and L6 arranged in the second column C2 based on the clock Clk.

[0110] The second shielding circuit 172j may include fourth to sixth shielding AND gates MA4 to MA6. The fourth to sixth shielding AND gates MA4 to MA6 may output the clock Clk received from the second shielding clock gate MCG2 to the fourth to sixth latches L4 to L6 based on the fourth to sixth row enable signals En_Row4 to En_Row6.

[0111] The masked clock gates MCG1 and MCG2 according to an embodiment of the inventive concept may control the blocking circuits 140_1 and 140_2 and the masking circuits 171 j and 172 j based on the bitwise enable signals En_BW1 and En_BW2 , and thus data writing may be performed for each bit.

[0112] Fig.14 is a block diagram illustrating interfaces used in the computing system 1000 according to an embodiment of the inventive concept.

[0113] refer to Fig.14 , the computing system 1000 may be implemented as a data processing device capable of using or supporting a MIPI interface, and may include an application processor (AP) 1600, an image sensor 1620, a display 1630, etc. A camera serial interface (CSI) host 1602 of the AP 1600 may perform serial communication with a CSI device 1621 of the image sensor 1620 through CSI. In an embodiment, the CSI host 1602 may include a deserializer DES, and the CSI device 1621 may include a serializer SER.

[0114] A display serial interface (DSI) host 1602 of the AP 1600 may perform serial communication with a DSI device 1631 of the display 1630 via the DSI. In an embodiment, the DSI host 1601 may include a serializer SER, and the DSI device 1631 may include a deserializer DES. The computing system 1000 may further include a radio frequency (RF) chip 1640 capable of communicating with the AP 1600. The PHY 1603 of the AP 1600 and the PHY 1641 of the RF chip 1640 may perform data transmission and reception according to a mobile industry processor interface (MIPI) DigRF 1642. In addition, the AP 1600 may further include a memory device 1604. The memory device 1604 may include a blocking circuit to block signal transmission for multiple latches during a locking period in which the multiple latches are not operating, as described above with reference to Figures 1 to 13 In addition, the memory device 1604 may include a masking circuit to control the plurality of latches so that some data bits are not written.

[0115] The computing system 1000 may further include a global positioning system (GPS), a storage device 1650, a microphone 1660, a dynamic random access memory (DRAM) 1670, and a speaker 1680. In addition, the computing system 1000 may perform communication using ultra-wideband (UWB) 1693, wireless local area network (WLAN) 1692, and world-wide interoperability for microwave access (WIMAX) 1691. However, the structure and interface of the computing system 1000 are not limited thereto.

[0116] While the inventive concept has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A memory device, comprising: a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, each latch of the plurality of latches being configured to store at least one bit of data; a first flip-flop configured to output first data to a first latch arranged in the first column among the plurality of latches based on a clock; as well as a second flip-flop configured to output second data to a second latch arranged in the second column among the plurality of latches based on the clock; The first trigger is further configured to block the output of the first data to the first latch during a locking period in which the first latch and the second latch maintain output regardless of input, and The second trigger is further configured to block output of the second data to the second latch during the locking period.

2. The memory device according to claim 1, wherein: The first trigger comprises: a first shared latch configured to output the received first data based on a first phase of the clock; and a second shared latch configured to output the first data received from the first shared latch to the first latch based on a second phase of the clock, The plurality of latches are configured to output first data received from the second shared latch based on the second phase.

3. The memory device according to claim 1, further comprising: a write enabler configured to output the clock to the first flip-flop and the second flip-flop based on a write enable signal; as well as The column decoder is configured to control reading data from the plurality of latches by decoding a column address.

4. The memory device according to claim 1, wherein: The plurality of rows include a first row and a second row, Wherein, the memory device further includes: a row decoder configured to generate a row enable signal by decoding a row address; a first clock gate configured to output the clock to a third latch arranged in the first row among the plurality of latches based on the row enable signal received from the row decoder; and a second clock gate configured to output the clock to a fourth latch arranged in the second row among the plurality of latches based on the row enable signal received from the row decoder, and Wherein, each of the first clock gate and the second clock gate comprises a latch and an AND gate.

5. The memory device according to claim 1, wherein: The plurality of rows include a first row and a second row, Wherein, the memory device further includes: a first gating latch configured to output a row address based on the clock; a row decoder configured to generate a row enable signal by decoding the row address received from the first gating latch; a first row AND gate configured to generate a first signal based on a first AND operation of the clock and the row enable signal received from the row decoder, and output the first signal to a third latch arranged in the first row among the plurality of latches; and The second row AND gate is configured to generate a second signal based on a second AND operation of the clock and the row enable signal received from the row decoder, and output the second signal to a fourth latch arranged in the second row among the plurality of latches.

6. The memory device of claim 1 , further comprising: a first masking circuit configured to mask the first latch arranged in the first column based on a first bit enable signal; as well as a second masking circuit configured to mask the second latch arranged in the second column based on a second bit enable signal, wherein each latch of the first latches is further configured to, when masked by the first masking circuit, receive the first data from the first flip-flop without storing the first data, and Each latch of the second latches is further configured to, when masked by the second masking circuit, receive the second data from the second flip-flop without storing the second data.

7. The memory device of claim 6, further comprising: a row decoder configured to generate a row enable signal by decoding a row address; as well as a plurality of row AND gates, each of the plurality of row AND gates being configured to output a clock for a corresponding row of the plurality of rows based on an AND operation of a latch clock and the row enable signal received from the row decoder, Wherein, the first shielding circuit comprises: A first masking latch configured to output a first bit enable signal based on the clock; and a plurality of first shielded AND gates, each of the plurality of first shielded AND gates being configured to output the first bit enable signal received from the first shielded latch to the first latch arranged in the first column based on the latch clocks respectively received from the plurality of row AND gates.

8. The memory device of claim 6, further comprising: a row decoder configured to generate a row enable signal by decoding a row address; as well as a first shielded clock gate configured to output a first shielded clock based on the first bit enable signal; Wherein, the first shielding circuit includes a plurality of first shielding AND gates, each of the plurality of first shielding AND gates being configured to output a latch clock to the first latch arranged in the first column based on the first shielding clock and the row enable signal received from the row decoder.

9. The memory device of claim 8, further comprising a second masked clock gate configured to output a second masked clock based on the second bit enable signal, in, The first flip-flop is further configured to receive the first masked clock from the first masked clock gate, and The second flip-flop is further configured to receive the second shielded clock from the second shielded clock gate.

10. A system on chip, comprising: a central processing unit CPU configured to write first data into the plurality of latches by accessing the plurality of latches; as well as a memory device configured to store the first data in response to access by the CPU, Wherein, the memory device comprises: The plurality of latches are arranged in a plurality of columns including a first column and in a plurality of rows, each latch of the plurality of latches being configured to store at least one bit of data; and The first blocking circuit is configured as follows: outputting at least some bits of first data to first latches arranged in the first column among the plurality of latches based on a clock; and In a lock period in which the first latches arranged in the first column do not output data, signals applied to the first latches arranged in the first column are blocked.

11. The system on chip according to claim 10, wherein: The first blocking circuit comprises: a first shared latch configured to output the received first data based on a first phase of the clock; and a second shared latch configured to output the first data received from the first shared latch to the first latch based on a second phase of the clock, The plurality of latches are configured to output first data received from the second shared latch based on the second phase.

12. The system on chip according to claim 10, wherein: The memory device further comprises: The second blocking circuit is configured as follows: outputting at least some bits of second data to second latches arranged in a second column among the plurality of latches based on the clock; and In a lock period in which the second latches arranged in the second column do not output data, signals applied to the second latches arranged in the second column are blocked.

13. The system on chip according to claim 12, wherein: The plurality of rows include a first row and a second row, Wherein, the system on chip further includes: a row decoder configured to generate a row enable signal by decoding a row address; a first clock gate configured to output the clock to a third latch arranged in the first row among the plurality of latches based on the row enable signal received from the row decoder; and a second clock gate configured to output the clock to a fourth latch arranged in the second row among the plurality of latches based on the row enable signal received from the row decoder, and Wherein, each of the first clock gate and the second clock gate comprises a latch and an AND gate.

14. The system on chip according to claim 12, wherein: The plurality of rows include a first row and a second row, Wherein, the system on chip further includes: a first gating latch configured to output a row address based on the clock; a row decoder configured to generate a row enable signal by decoding the row address received from the first gating latch; a first row AND gate configured to generate a first signal based on a first AND operation of the clock and the row enable signal received from the row decoder, and output the first signal to a third latch arranged in the first row among the plurality of latches; and The second row AND gate is configured to generate a second signal based on a second AND operation of the clock and the row enable signal received from the row decoder, and output the second signal to a fourth latch arranged in the second row among the plurality of latches.

15. The system on chip according to claim 12, further comprising: a first masking circuit configured to mask the first latch arranged in the first column based on a first bit enable signal; as well as a second masking circuit configured to mask the second latch arranged in the second column based on a second bit enable signal, wherein each latch of the first latches is further configured to, when masked by the first masking circuit, receive the first data from the first blocking circuit without storing the first data, and Each latch of the second latches is further configured to, when masked by the second masking circuit, receive the second data from the second blocking circuit without storing the second data.

16. A memory device comprising: a plurality of latches arranged in a plurality of columns and a plurality of rows, each latch of the plurality of latches being configured to store at least one bit of data; a bitwise enabler configured to mask one or more latches arranged in at least some of the plurality of columns based on a plurality of bit enable signals; as well as a row decoder configured to generate a row enable signal by decoding a row address, wherein the one or more latches are configured to receive write data without storing the write data when masked by the bitwise enabler, The bitwise enabler includes a first masking circuit configured to mask a first latch arranged in a first column among the plurality of latches based on a first bit enable signal, The memory device further comprises a first shielded clock gate, wherein the first shielded clock gate is configured to output a first shielded clock based on the first bit enable signal, and Wherein, the first shielding circuit includes a plurality of first shielding AND gates, each of the plurality of first shielding AND gates being configured to output a latch clock to the first latch arranged in the first column based on the first shielding clock and the row enable signal received from the row decoder.

17. The memory device of claim 16, further comprising: a plurality of row AND gates, each of the plurality of row AND gates being configured to output a latch clock for a corresponding row of the plurality of rows based on an AND operation of the first masked clock and the row enable signal received from the row decoder, Wherein, the first shielding circuit comprises: a first shielding latch configured to output a first bit enable signal based on the latch clock; and Wherein, each of the plurality of first shielded AND gates is further configured to output the first bit enable signal received from the first shielded latch to the first latch arranged in the first column based on the latch clocks respectively received from the plurality of row AND gates.

18. The memory device of claim 16, further comprising: a first flip-flop configured to output first data to the first latch arranged in the first column based on an edge of the first masked clock; as well as The second flip-flop is configured to output second data to a second latch arranged in a second column among the plurality of latches based on an edge of the second masked clock.

19. The memory device of claim 18, wherein: The bitwise enabler further includes a second masking circuit configured to mask the second latch arranged in the second column based on a second bit enable signal, The memory device further includes a second shielded clock gate, wherein the second shielded clock gate is configured to output the second shielded clock based on the second bit enable signal. wherein the first trigger is further configured to receive the first shielded clock from the first shielded clock gate, and The second flip-flop is further configured to receive the second shielded clock from the second shielded clock gate.

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