Semiconductor device and method for forming semiconductor device

Abstract

A semiconductor device, which includes a contact metallization layer disposed on a semiconductor substrate, an inorganic passivation structure disposed on the semiconductor substrate, and an organic passivation layer. The organic passivation layer located between the contact metallization layer and the inorganic passivation structure is vertically located closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

Description

Technical Field

[0001] Examples relate to a passivation concept for semiconductor devices and, in particular, to semiconductor devices and methods for forming semiconductor devices. Background Art

[0002] Semiconductor devices can experience very high electric fields at the surface of the edge termination region such that passivation using materials including good breakdown resistance may be required. Solutions using organic passivation are vulnerable to moisture collection and may cause corrosion. Solutions using inorganic passivation may be vulnerable to thermo-mechanical stress. In this context, cracks may occur if the inorganic passivation is in contact with the metallization layer and the arrangement is exposed to thermo-mechanical stress.

[0003] Thus, passivation taking into account high electric fields, humidity, and mechanical stress is important for the breakdown behavior and long-term reliability of semiconductor devices. Summary of the Invention

[0004] There is a need to provide a concept for passivation of semiconductor devices that allows for improved robustness and / or reliability of semiconductor devices.

[0005] This need can be met by the subject matter of the claims.

[0006] Examples relate to a semiconductor device that includes a contact metallization layer disposed on a semiconductor substrate, an inorganic passivation structure disposed on the semiconductor substrate, and an organic passivation layer. A portion of the organic passivation layer that is laterally located between the contact metallization layer and the inorganic passivation structure is vertically located closer to the semiconductor substrate than a portion of the organic passivation layer that is located on top of the inorganic passivation structure.

[0007] Other examples relate to a method of forming a semiconductor device. The method includes forming a contact metallization layer on a semiconductor substrate and forming an inorganic passivation structure on the semiconductor substrate. In addition, the method includes forming an organic passivation layer. A portion of the organic passivation layer that is laterally located between the contact metallization layer and the inorganic passivation structure is vertically located closer to the semiconductor substrate than a portion of the organic passivation layer that is located on top of the inorganic passivation structure. Brief Description of the Drawings

[0008] Some examples of the apparatus and / or method will be described below only by way of example and with reference to the drawings, in which

[0009] Figure 1 A schematic cross-section of a portion of a semiconductor device is shown;

[0010] Figure 2 A schematic cross-section of a portion of a semiconductor device is shown;

[0011] Figure 3 A flowchart showing a method for forming a semiconductor device is presented;

[0012] Figure 4 A schematic cross-section of a semiconductor device after depositing a contact metallization layer is presented;

[0013] Figure 5 A schematic cross-section of a semiconductor device after depositing an inorganic passivation structure is presented Figure 4 is presented;

[0014] Figure 6A -F presents a schematic cross-section of a part of a silicon carbide diode device including a TiAl3 buffer sublayer;

[0015] Figure 7A -C presents a schematic cross-section of a part of a silicon carbide device including an intermediate oxide layer;

[0016] Figure 8A -C presents a schematic cross-section of a part of a second silicon carbide device including an intermediate oxide layer; and

[0017] Figure 9 presents a schematic cross-section of a part of a third silicon carbide device including an intermediate oxide layer. DETAILED DESCRIPTION

[0018] Various examples will now be described more fully with reference to the accompanying drawings in which some examples are illustrated. In the figures, the thickness of lines, layers, and / or regions may be exaggerated for clarity.

[0019] Accordingly, while other examples can have various modifications and alternative forms, some specific examples are shown in the drawings and will subsequently be described in detail. However, this detailed description does not limit additional examples to the specific forms described. Additional examples may cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure. Throughout the description of the figures, the same numbers indicate the same or similar elements, and when such same or similar elements are compared to each other, they may be implemented identically or in a modified form while providing the same or similar functions.

[0020] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled or connected or coupled via one or more intervening elements. If two elements A and B are combined using "or", it is to be understood that all possible combinations are disclosed, namely only A, only B, and A and B. An alternative term for the same combination is "at least one of A and B". This also applies to combinations of more than two elements.

[0021] The terms used herein for the purpose of describing particular examples are not intended to limit additional examples. Whenever the singular forms such as "a", "an", and "the" are used and only a single element is neither explicitly nor implicitly defined as mandatory, additional examples may also implement the same functionality using multiple elements. Similarly, when a functionality is subsequently described as being implemented using multiple elements, additional examples may implement the same functionality using a single element or processing entity. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components, and / or any group thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning in the field to which the examples belong.

[0023] Figure 1 A block diagram showing a cross-section of a semiconductor device 100 according to an embodiment. The semiconductor device 100 includes a contact metallization layer 120, an inorganic passivation structure 130, and an organic passivation layer 140 disposed on a semiconductor substrate 110. A (first) portion of the organic passivation layer 140 is laterally located between the contact metallization layer 120 and the inorganic passivation structure 130, and a (second) portion of the organic passivation layer 140 is located on top of the inorganic passivation structure 130. The first portion of the organic passivation layer is vertically located closer to the semiconductor substrate 110 than the second portion of the organic passivation layer. In addition, a third portion of the organic passivation layer 140 is located on top of the contact metallization layer 120.

[0024] The layout can be selected such that a sufficiently large gap can be achieved between the contact metallization layer 120 and the inorganic passivation structure 130. Due to the gap between the contact metallization layer 120 and the inorganic passivation structure 130, the portion of the organic passivation layer 140 within the gap between the contact metallization layer 120 and the inorganic passivation structure 130 is closer to the semiconductor substrate 110 than the portion of the organic passivation layer 140 formed on top of the inorganic passivation structure 130. Due to the gap between the contact metallization layer 120 and the inorganic passivation structure 130, damage during the manufacture or operation of the semiconductor device can be reduced or avoided. Conversely, if the inorganic passivation layer 130 is directed above the contact metallization layer 120 or in contact with the contact metallization layer 120, cracks, for example, caused by varying temperatures, are more likely to occur. However, if the inorganic passivation structure 130 is selected such that there is a gap between the inorganic passivation structure 130 and the contact metallization layer 120, the stress in the layer stack on the semiconductor substrate can be reduced. In this way, the robustness and / or reliability of the semiconductor device can be improved.

[0025] The contact metallization layer 120 and the inorganic passivation structure 130 can be spaced apart from each other such that the lateral gap between the contact metallization layer 120 and the inorganic passivation structure 130 is at least partially filled with the organic passivation layer 140. The lateral distance d1 between the contact metallization layer 120 and the inorganic passivation structure 130 can be greater than the vertical thickness t1 of the contact metallization layer 120 (or greater than twice the vertical thickness t1 of the contact metallization layer 120, or greater than three times the vertical thickness t1 of the contact metallization layer 120). Additionally or alternatively, the lateral distance d1 between the contact metallization layer 120 and the inorganic passivation structure 130 can be less than the width w1 of the inorganic passivation structure 130 (or less than 50% of the width or less than 30% of the width). The width of the inorganic passivation structure 130 can be the smallest lateral dimension or the lateral dimension measured in a direction orthogonal to the edge of the semiconductor substrate 110 at the center of the edge. For example, the lateral distance between the inorganic passivation structure and the edge of the semiconductor substrate can be greater than 10 μm (or 20 μm or 50 μm). In this way, the semiconductor substrate 110 can be cut during the manufacture of the semiconductor device without cutting through the passivation structure, which may cause cracks or adhesion effects of the saw blade.

[0026] A first portion of the organic passivation layer 140 that is laterally located between the contact metallization layer 120 and the inorganic passivation structure 130 can be in contact with the semiconductor substrate 110, or one or more layers can be vertically located between the first portion and the semiconductor substrate 110. One or more optional layers can be vertically located between the first portion and the semiconductor substrate 110, and the one or more optional layers can include a thickness less than the thickness of the inorganic passivation structure 130.

[0027] The organic passivation layer 140 can be formed after the contact metallization layer 120 such that a third portion of the organic passivation layer 140 is located on top of the contact metallization layer 120. For example, the contact metallization layer 120 is vertically located closer to the semiconductor substrate 110 than the third portion of the organic passivation layer 140. For example, no portion of the organic passivation layer 140 is located below the contact metallization layer 120. The organic passivation layer 140 can extend from the second portion to the third portion, where the first portion is laterally located between the second portion and the third portion of the organic passivation layer 140. The organic passivation layer 140 can be fabricated or manufactured in a single manufacturing process (e.g., by deposition) that is not interrupted by the formation of another layer. For example, the entire organic passivation layer 140 can be formed after the formation of the contact metallization layer 120.

[0028] The thickness of the inorganic passivation structure 130 can be greater than 500 nm (or greater than 750 nm or greater than 1 μm) and / or less than 6 μm (or less than 3 μm or less than 1 μm). The inorganic passivation structure can be a single layer or can include two or more sub-layers. For example, the inorganic passivation structure 130 can be or can include an oxide layer (such as a silicon dioxide layer, an undoped silica glass (USG) layer, or a borophosphosilicate glass (BPSG) layer), which can include a thickness greater than 300 nm (or greater than 500 nm or greater than 750 nm) and / or less than 5 μm (or less than 3 μm or less than 1 μm). Optionally or additionally, the inorganic passivation structure 130 can be or can include a nitride layer (such as a silicon nitride layer), which can include a thickness greater than 400 nm (or greater than 500 nm or greater than 600 nm) and / or less than 800 nm (or less than 700 nm or less than 600 nm).

[0029] By selecting an appropriate thickness and / or material of the inorganic passivation structure 130, the semiconductor device can be configured such that in the blocking state of the electrical structure (such as a diode structure or a transistor structure) formed at the semiconductor substrate 110, the electric field at the surface of the inorganic passivation structure 130 (such as the interface between the inorganic passivation structure and the organic passivation layer) can be greater than 500 kV / cm (or greater than 600 kV / cm or greater than 800 kV / cm).

[0030] The thickness of the organic passivation layer 140 can be selected such that it can compensate for or absorb thermal stress without causing crack formation, and / or the electric field at the surface of the organic passivation layer 140 can be below a threshold value. The thickness and / or material of the organic passivation structure 140 can be configured such that in the blocking state of the electrical structure formed at the semiconductor substrate 110, the electric field at the surface of the organic passivation layer 140 (such as the interface between the organic passivation layer and the molding compound) can be below 500 kV / cm (or below 400 kV / cm or below 300 kV / cm). The organic passivation layer 140 can be a single layer or can include two or more sub-layers. For example, the organic passivation layer 140 can be a polyimide layer. The organic passivation layer 140 can have a thickness greater than 1 μm (or greater than 3 μm or greater than 5 μm) and / or less than 50 μm (or less than 30 μm or less than 15 μm).

[0031] The contact metallization layer 120 can be a single layer or can include two or more sub-layers. The contact metallization layer 120 can include a metal layer. For example, the contact metallization layer 120 can include copper (Cu) or aluminum (Al), or can include an alloy of aluminum and copper (such as AlCu or AlCuSi). The contact metallization layer 120 can include a thickness greater than 2 μm (or greater than 3 μm or greater than 4 μm) and / or less than 20 μm (or less than 10 μm or less than 6 μm).

[0032] Optionally, the semiconductor device 100 may further include a barrier layer to prevent atoms of the contact metallization layer 120 from diffusing into the semiconductor substrate 110. The barrier layer may include a first portion vertically disposed between the contact metallization layer 120 and the semiconductor substrate 110. Further, the first portion of the barrier layer may be in contact with the contact metallization layer 120 and the semiconductor substrate 110. The barrier layer may include a second portion disposed between the inorganic passivation structure 130 and the semiconductor substrate 110. For example, the second portion of the barrier layer may be in contact with the inorganic passivation structure 130 and the semiconductor substrate 110. The barrier layer may extend at least from the first portion of the barrier layer to the second portion of the barrier layer. In this way, during the construction of the inorganic passivation structure 130, the barrier layer may be used as an etch stop layer. The barrier layer may be or may include a titanium (Ti) layer, a titanium nitride (TiN) layer, and / or a tantalum (Ta) layer. The barrier layer may have a thickness greater than 100 nm (or greater than 150 nm or greater than 200 nm) and less than 300 nm (or less than 250 nm or less than 200 nm).

[0033] The barrier layer may include: a first sub-layer (e.g., a barrier sub-layer), which is also referred to as a Schottky barrier; and a second sub-layer (e.g., a buffer sub-layer), such as an etchant barrier and / or buffer. The first sub-layer may be in contact with the semiconductor substrate and may prevent atoms (e.g., metal atoms such as aluminum or copper) from a layer above the first sub-layer from diffusing into the semiconductor substrate. The second sub-layer may be in contact with the first sub-layer and the contact metallization layer 120. The second sub-layer may prevent particles (e.g., those described with respect to the passivation structure) used in the etching process from penetrating the first sub-layer by absorbing and / or capturing the etching particles. The first sub-layer may include titanium (e.g., a titanium layer), and the second sub-layer may include a titanium-aluminum alloy (e.g., a TiAl3 layer) or titanium nitride (e.g., a TiN layer).

[0034] Reference Figure 2 -6 discusses some examples related to the diode structure in more detail.

[0035] Some examples relate to transistor structures (e.g., insulated-gate field-effect transistors (IGFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or insulated-gate bipolar transistors (IGBTs)) as shown in FIGS. 7a-8. In some examples where the semiconductor device is a MOSFET (or IGFET or IGBT), the MOSFET may further include an intermediate oxide layer (e.g., a silicon dioxide layer). For example, the intermediate oxide layer may be directly disposed on the semiconductor substrate (in contact with the semiconductor substrate). The intermediate oxide layer may include a first sub-layer that is part of the gate oxide layer and a second sub-layer that is an interlayer dielectric layer formed on the gate oxide layer.

[0036] For example, a first lateral portion of the intermediate oxide layer can be disposed vertically between the contact metallization layer and the semiconductor substrate, and a second lateral portion of the intermediate oxide layer can be disposed vertically between the inorganic passivation structure and the semiconductor substrate. The intermediate oxide layer can extend at least from the first portion to the second portion.

[0037] For example, the inorganic passivation structure 130 can include a nitride layer (such as a silicon nitride layer). A first portion of the organic passivation layer 140 (such as the portion that is laterally located between the inorganic passivation structure 130 and the contact metallization layer 120) can be vertically located closer to the intermediate oxide layer 731 than a second portion of the organic passivation layer 140 (such as the portion located on the inorganic passivation structure 130). In this example, the intermediate oxide layer can be used as an etch stop layer for fabricating the nitride layer. An example is discussed in more detail with respect to FIG. 7.

[0038] Alternatively, a first portion of the barrier layer can be disposed vertically between the intermediate oxide layer and the contact metallization layer, and a second portion of the barrier layer can be disposed vertically between the inorganic passivation structure and the intermediate oxide layer. In this example, the inorganic passivation structure 130 can include a silicon oxide layer, such as but not limited to an undoped silicate glass layer, a borophosphosilicate glass, a phosphosilicate glass, and a borosilicate glass and / or a silicon nitride layer. The silicon oxide layer can be disposed vertically between the silicon nitride layer and the intermediate oxide layer. The barrier layer can be used as an etch stop layer for fabricating the silicon oxide layer and the silicon nitride layer. An example is discussed in more detail with respect to FIG. 8.

[0039] Optionally, the semiconductor device 100 can further include an adhesion layer, for example, to increase the adhesion of the organic passivation layer 140 on top of the inorganic passivation structure 130 and / or the contact metallization layer 120. The adhesion layer can include a first portion disposed between the contact metallization layer 120 and the organic passivation layer 140. For example, the first portion of the adhesion layer can be in contact with the contact metallization layer 120 and the organic passivation layer 140. The adhesion layer can include a second portion disposed between the inorganic passivation structure 130 and the organic passivation layer 140. For example, the second portion of the adhesion layer can be in contact with the inorganic passivation structure 130 and the organic passivation layer 140. The adhesion layer can extend at least from the first portion to the second portion such that the adhesion layer can also improve the adhesion of the organic passivation layer 140 in the gap between the contact metallization layer 120 and the inorganic passivation layer 130. The adhesion layer can have a thickness greater than 10 nm (or greater than 20 nm or greater than 30 nm) and less than 100 nm (or less than 60 nm or less than 40 nm). For example, the adhesion layer can be a silicon nitride layer.

[0040] Optionally, a bonding wire or solder material (such as solder balls, solder bumps, or already soldered material) can be in contact with the contact metallization layer 120. Optionally, the semiconductor device 100 can further include a molding compound structure in contact with the organic passivation layer 140. For example, after forming the organic passivation structure and after bonding the bonding wire to the contact metallization layer 120 or soldering the solder structure to the contact metallization layer 120 to connect the semiconductor substrate to the lead frame or package carrier of the semiconductor device 100, a molding compound is formed on the semiconductor substrate of the semiconductor device 100. The molding compound can be an epoxy-based molding compound or a soft molding compound.

[0041] For example, one or more electrical structures can be implemented at the semiconductor substrate 100. The electrical structure can be a diode structure (such as a vertical diode structure) or a transistor structure (such as a vertical transistor structure), such as for example a MOSFET or an IGBT. For example, the electrical structure can be a vertical transistor structure or a vertical diode structure having a lightly doped drift region.

[0042] For example, the semiconductor device 100 can include a drift region of the electrical structure, which includes a dopant of a first conductivity type. The semiconductor device 100 can include an edge termination region, which includes a dopant of a second conductivity type. The edge termination region can laterally extend at least partially under the inorganic passivation structure 130 from the contact region towards the edge of the semiconductor substrate 110. The edge termination region can be ohmically connected to the contact metallization layer 120 through the contact region. If there is an ohmic path or connection between two structures, the two structures can be ohmically connected. The contact region can be a highly doped portion of the edge termination region or a highly doped portion of the doped region of the electrical structure (such as the anode or cathode region of the diode structure or the source region or body region of the transistor structure) to achieve an ohmic contact to the wiring structure connected to the contact metallization layer 120 or the contact metallization layer 120.

[0043] The edge termination region can be selected such that the lateral distance between the inorganic passivation structure 130 and the edge of the semiconductor substrate 110 is smaller than the lateral distance between the edge termination doped region and the edge of the semiconductor substrate 110 (such as more than 1μm, more than 5μm, or more than 10μm smaller than the lateral distance between the edge termination doped region and the edge of the semiconductor substrate 110). Thus, the edge termination region can be completely covered by the inorganic passivation structure 130, or can be covered at least at the portion located near the edge of the semiconductor substrate 110. In this way, corrosion of the edge termination region can be prevented by the coverage of the inorganic passivation structure 130.

[0044] The edge termination region can be a depletable doped region including an average doping concentration such that if a maximum blocking voltage is applied to the semiconductor device 100 during normal operation of the semiconductor device 100, the lightly p-doped edge termination region is depletable.

[0045] The drift region includes dopants of a first conductivity type, which can be p-doped (e.g., caused by incorporation of aluminum ions or boron ions) or n-doped (e.g., caused by incorporation of nitrogen ions, phosphorus ions, or arsenic ions). Thus, the second conductivity type indicates the opposite type, n-doped or p-doped. In other words, the first conductivity type can indicate n-doping and the second conductivity type can indicate p-doping, or vice versa.

[0046] The edge termination region of the semiconductor device 100 and / or the doped body region and / or the doped source region of the transistor structure and / or the doped anode region and / or the doped cathode region of the diode structure can be located on the front side or the front surface of the semiconductor substrate 100. The doped drain region or the doped emitter or collector region of the transistor structure can be located on the back side or the back surface of the semiconductor substrate 100.

[0047] The front side or the front surface of the semiconductor substrate 110 can be the semiconductor surface of the semiconductor substrate 110 facing a metal layer, an insulating layer, or a passivation layer on top of the semiconductor surface. Compared to a substantially vertical edge of the semiconductor substrate 100 (e.g., created by separating the semiconductor substrate from others), the front surface of the semiconductor substrate 110 can be a substantially horizontally extending surface. The front surface of the semiconductor substrate 110 can be a substantially uniform plane (e.g., ignoring the non-uniformity of the semiconductor structure due to the manufacturing process or trenches). The front surface of the semiconductor substrate 110 can be the surface of the semiconductor substrate 110 used to form more complex structures (e.g., gates, source regions, and / or body regions of transistors, wiring layer stacks) than those at the back side of the semiconductor substrate 110.

[0048] The lateral direction or the lateral extension can be oriented substantially parallel to the front surface, and the vertical direction or the vertical extension can be oriented substantially orthogonal to the front surface. For example, the vertical direction and the vertical dimension or thickness of a layer can be measured orthogonal to the front surface of the semiconductor substrate, and the lateral direction and the lateral dimension can be measured parallel to the front surface of the semiconductor substrate.

[0049] For example, the semiconductor substrate 110 can be a wide-bandgap semiconductor substrate, whose bandgap is greater than that of silicon (1.1 eV). For example, the semiconductor substrate 110 can be a semiconductor substrate based on silicon carbide (SiC), or a semiconductor substrate based on gallium arsenide (GaAs), or a semiconductor substrate based on gallium nitride (GaN). The semiconductor substrate 110 can be a semiconductor wafer or a semiconductor die. Although the silicon carbide substrate is discussed in conjunction with the drawings and embodiments, it should be understood that these embodiments are not intended to be limited to SiC substrates, and other substrates (such as GaAs or GaN-based substrates) are also possible.

[0050] The transistor structure of the semiconductor device 100 (such as IGFET, MOSFET or IGBT) can be a vertical transistor structure that conducts current between the front surface and the back surface of the semiconductor substrate. For example, the transistor arrangement of the semiconductor device can include a plurality of doped source regions connected to the source wiring structure, a plurality of gate electrodes or a gate electrode grid connected to the gate wiring structure, and a backside drain metallization.

[0051] The transistor structure can be a transistor cell of a plurality of transistor cells of the transistor arrangement. For example, the transistor cell can include one or more source regions (such as distributed or positioned along the gate), at least one body region, and a gate (such as a trench gate located in a gate trench extending into the semiconductor substrate). Further, the transistor cells of the plurality of transistor cells can share a common (shared) drift region and / or a common drain region (such as the transistor cell is a MOSFET cell) or a common collector region (such as the transistor cell is an IGBT cell).

[0052] The semiconductor substrate can include a unit region (or active region) laterally surrounded by an edge termination region. The unit region can be a region of the semiconductor substrate that is used to conduct more than 90% of the current passing through the semiconductor substrate in the on-state or conducting state of the transistor arrangement (or the entire semiconductor device). For example, the unit region can be a region that includes all the source regions of the transistor arrangement or all the source regions of all the transistor structures of the semiconductor device. The edge termination region can be located between the edge of the semiconductor substrate and the unit region to support or block or reduce or dissipate the maximum voltage applied between the front surface and the back surface of the semiconductor substrate in the unit region in the lateral direction towards the edge of the semiconductor substrate.

[0053] The semiconductor device 100 can be a power semiconductor device. The semiconductor device can also include an electrical structure formed at a semiconductor substrate 110 (such as a transistor structure and / or a diode structure), which has a breakdown voltage or blocking voltage of more than 10V (such as a breakdown voltage of 10V, 20V, or 50V), a breakdown voltage or blocking voltage of more than 100V (such as a breakdown voltage of 200V, 300V, 400V, or 500V), or a breakdown voltage or blocking voltage of more than 500V (such as a breakdown voltage of 600V, 700V, 800V, or 1000V), or a breakdown voltage or blocking voltage of more than 1000V (such as a breakdown voltage of 1200V, 1500V, 1700V, 2000V, 3300V, or 6500V).

[0054] The organic passivation layer 140 can continuously cover the inorganic passivation layer 130 and at least a portion of the contact metallization layer 120.

[0055] More details and aspects are mentioned in connection with the examples described above or below. The semiconductor device can include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more of the examples described below (such as Figure 2-9 ).

[0056] Figure 2 A schematic cross-section of a semiconductor device 200 according to an embodiment is shown. The implementation of the semiconductor device 200 can be similar to the implementation described in connection with Figure 1 . The organic passivation layer 140 (such as a polyimide layer) is located within 300 nm of the semiconductor substrate in the gap between the contact metallization layer 120 (such as an AlCu alloy layer) and the inorganic passivation structure 130. The barrier layer 250 (such as a Ti layer) and the silicon nitride adhesion layer 260 are vertically located between the organic passivation layer 140 and the semiconductor substrate. The inorganic passivation structure 130 includes two layers: a silicon oxide layer 231 and a silicon nitride layer 232. Although the silicon oxide layer 231 is represented by a USG layer in the Figure 2 image, it should be understood that the silicon oxide layer 231 can alternatively include other silicon oxide layers, such as BPSG, BSG, and / or PSG. The organic passivation layer 140 extends laterally from a point between the edge 202 of the semiconductor device 200 and the edge of the inorganic passivation structure 130 to the contact metallization layer 120.

[0057] The barrier layer 250 has a first portion located between the semiconductor substrate and the contact metallization layer 120. The barrier layer 250 has a second portion located between the semiconductor substrate and the silicon oxide layer 231. The barrier layer 250 extends continuously from the first portion to the second portion. The barrier layer 250 has a third portion located between the adhesion layer 260 and the semiconductor substrate in the gap between the contact metallization layer 120 and the inorganic passivation structure 130.

[0058] The adhesion layer 260 has a first portion located between the organic passivation layer 140 and the contact metallization layer 120. The adhesion layer 260 has a second portion located between the organic passivation layer 140 and the silicon nitride layer 232. The adhesion layer 260 extends continuously from the first portion to the second portion. The adhesion layer 260 has a third portion located between the organic passivation layer 140 and the barrier layer 250 in the gap between the contact metallization layer 120 and the inorganic passivation structure 130.

[0059] In this example, the semiconductor device is a SiC diode. The semiconductor substrate includes a drift layer or doped drift region 211, a doped field stop region or buffer region 212, and a doped substrate region 213 that forms the n-doped cathode region of the SiC diode. The buffer region includes an average doping concentration that is higher than the average doping concentration of the drift region, and the substrate region includes an average doping concentration that is higher than the average doping concentration of the buffer region. Additionally, the semiconductor substrate includes a highly p-doped anode region 214 located at the front surface 201 of the semiconductor substrate. The highly p-doped anode region 214 can be an undepletable doped region that includes an average doping concentration such that if a maximum blocking voltage is applied to the semiconductor device 200 during normal operation of the semiconductor device 200, the anode region 214 is undepletable.

[0060] Furthermore, the semiconductor substrate includes a lightly p-doped edge termination region 215 that extends at least partially beneath the inorganic passivation structure 130. The lateral distance d2 from the inorganic passivation structure 130 to the edge 202 is less than the lateral distance d3 from the edge termination region 215 to the edge 202 of the semiconductor device 200. The lightly p-doped edge termination region 215 can be a depletable region that includes an average doping concentration such that if a maximum blocking voltage is applied to the semiconductor device 200 during normal operation of the semiconductor device 200, the lightly p-doped edge termination region 215 is depletable. The lightly p-doped edge termination region 215 is connected to the contact metallization layer 120 through the highly p-doped anode region 214.

[0061] More details and aspects of the semiconductor device 200 are mentioned in connection with the proposed concept or one or more of the examples described above. The semiconductor device 200 can include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more of the examples described above (e.g., Figure 1 ) or below (e.g., Figure 3-9 ).

[0062] Figure 3FIG. 0 shows a flow chart of a method 300 for forming a semiconductor device according to an embodiment. The method 300 includes forming 310 a contact metallization layer on a semiconductor substrate, forming 320 an inorganic passivation structure on the semiconductor substrate, and forming 330 an organic passivation layer. A first portion of the organic passivation layer that is laterally located between the contact metallization layer and the inorganic passivation structure is vertically located closer to the semiconductor substrate than a second portion of the organic passivation layer that is located on top of the inorganic passivation structure. In addition, a third portion of the organic passivation layer is located on top of the contact metallization layer.

[0063] The layout can be selected such that a sufficiently large distance can be achieved between the contact metallization layer and the inorganic passivation structure. Due to the distance between the contact metallization layer and the inorganic passivation structure, damage during the manufacture or operation of the semiconductor device can be reduced or avoided. In this way, the robustness and / or reliability of the semiconductor device can be improved.

[0064] More details and aspects of the method 300 are referred to in connection with the proposed concept or one or more of the examples described above. The method 300 can include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more of the examples described above (e.g., Figure 1-2 ) or below (e.g., Figure 4-9 ).

[0065] Figure 4 and Figure 5 show a schematic cross-section of a SiC diode at different stages of manufacture. Figure 4 and Figure 5 The SiC diode shown in can be manufactured similarly to the method described in connection with Figure 3 .

[0066] Figure 4 show a schematic cross-section of a SiC diode after forming a doped region (e.g., buffer region 212, drift region 211, anode region 214, and doped edge termination region 215) of a diode structure in a semiconductor substrate of a semiconductor device to be formed. In addition, a titanium barrier layer 250 in contact with the semiconductor substrate is formed and constructed. Figure 4 show a SiC diode after deposition and construction of a front-side metallization (e.g., an AlCu layer).

[0067] Figure 5 show a schematic cross-section of a SiC diode after deposition and construction of an inorganic passivation layer (e.g., a silicon oxide layer and a silicon nitride layer). During the construction of the inorganic passivation layer, the Ti barrier layer 250 is used as an etch stop between the front-side metallization and the edge of the constructed inorganic passivation layer.

[0068] As an example, Figure 2A SiC diode can be shown after forming (e.g., depositing and structuring) an organic passivation and opening (structuring) an optional silicon nitride adhesion layer 260.

[0069] After depositing and structuring the front-side metal (e.g., Figure 4 ), a passivated inorganic layer stack is deposited. For example, the inorganic layer stack can include a silicon oxide / silicon nitride stack whose silicon oxide thickness is measured so that the charge at the silicon oxide / silicon nitride interface may not affect the blocking behavior of the component (e.g., the charge ratio and field distribution in the edge termination). BPSG / silicon nitride, silicon oxide / BPSG / silicon nitride, or similar layer structures are also conceivable. After generating a resist mask, an inorganic passivation structure is structured in a subsequent process using a plasma etching process, and the resist mask is removed (e.g., Figure 5 ). Optionally, a thin adhesion layer (e.g., a thin silicon nitride layer) can be deposited, and a photosensitive organic passivation can be deposited in a subsequent process, which is structured and then cured using a lithography step. This organic passivation layer now serves as an etch mask for structuring the adhesion layer (optionally) in order to open the front-side metal in the area of the bonding pads. In Figure 2 the possible results are shown.

[0070] As described in connection with Figure 2 , 4 and 5, passivation can be generated after the AlCu / Ti process block, where the layout can be selected to ensure a sufficiently large distance between the AlCu edge and the passivation. By reducing the thickness of the inorganic passivation structure, stress-induced crack formation can be prevented. However, in order for the electric field strength to continue to be compatible with the molding compound, an organic passivation that also absorbs part of the mechanical stress is additionally deposited.

[0071] For example, the amount of the electric field strength at the interface between the inorganic passivation and the organic passivation generated by the thickness of the inorganic passivation can be > 500 kV / cm. Then, the size of the organic passivation can be determined in such a way that the amount of the electric field strength at the surface of the organic passivation representing the interface with the molding compound is greatly reduced in order to prevent degradation of the molding compound and / or flashover at the interface. Furthermore, the thickness of the organic passivation can be selected so that the force generated by thermal expansion does not cause crack formation in itself or in subsequent layers.

[0072] In this context, a sufficient gap can be achieved between the edge of the front-side metallization (positive electrode, e.g., Al-based) and the inorganic passivation. For example, if the inorganic hard passivation is guided over the metal and if this arrangement is exposed to thermomechanical stress, cracks may occur in the passivation due to the plastic deformation of Al(SiCu).

[0073] If inorganic hard passivation is now selected such that only the edge termination is covered, the surface covered by the inorganic hard passivation is thus reduced, and in this way a reduction of the stress in the SiC oxide nitride layer structure can be achieved.

[0074] In this case, to improve the adhesion of the organic passivation to the front side metal, a thin adhesion layer can be provided, which partially covers both the front side metal and the inorganic passivation, either partially or completely.

[0075] Mentioned in connection with the proposed concept or one or more of the examples described above or below Figure 4 and Figure 5 more details and aspects of the method shown in. The method can include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more of the examples described above (e.g. Figure 1-3 ) or below (e.g. Figures 6 - 9).

[0076] For example, if the contact metallization layer is formed before the inorganic passivation structure, the inorganic passivation structure is deposited on a surface with a high topology. On the other hand, if the inorganic passivation structure is formed before the contact metallization layer, during the construction of the inorganic passivation structure, the barrier layer, the sub - layers of the barrier layer, or the ohmic contact layer that can achieve an ohmic or Schottky contact between the contact metallization layer and the semiconductor substrate may be damaged.

[0077] For example, for a SiC Schottky diode, if dry chemical patterning of the dielectric passivation occurs between the fabrication of the Schottky metallization (e.g. Ti in the example of Figure 6) and the fabrication of the pad / contact metallization (AlCu in the example of Figure 6), the Schottky metal (e.g. also referred to as Schottky metallization, Schottky barrier, or Schottky layer) may deteriorate. The Schottky metallization can be uncovered and exposed to the effects of dry chemical etching. Unprotected Ti may deteriorate, and thus the Schottky interface may be affected. Therefore, it may be necessary to protect the Schottky metallization during dry chemical patterning.

[0078] In some examples, an edge termination for semiconductor elements with a high electric field strength at the edge can be introduced, which decisively improves the robustness against moisture by supplementing a pure organic passivation layer with dielectric passivation. The dielectric passivation can be used to protect the edge termination (e.g. the edge termination of a SiC diode) from moisture / humidity. With this form of passivation, the inorganic passivation can be patterned via an imide, which means that a porous inorganic oxide / nitride passivation is located above the AlCu metallization (see Figure 2 , 4 and 5). This can be a possible solution for encapsulations including soft molds, in which no mechanical stress may occur between the semiconductor device and the mold material.

[0079] For other packages (molded or plastic packages) where mechanical stress occurs between the die material, passivation, and Al-based front-end material, especially due to temperature increase, this method may not work. The stress caused by thermal variations leads to mechanical stress cracks in the inorganic passivation structure. Moisture-robust components are required because the so-called "hard mold" or "molding compound" may provide insufficient moisture protection. For diodes with imide passivation that only includes a uniformly doped junction termination edge (JTE), oxidation of the outer region of the JTE due to high humidity can be detected. For some but not all applications (such as automotive applications), the remaining blocking capacity of the device may be sufficient.

[0080] In some examples, after fabricating the front-side metallization via an additional mask (such as Ti Schottky and AlCu pads, see Figure 2 , 4 and 5), the inorganic passivation of the plastic package can be patterned. Thus, the passivation is spatially separated from the AlCu edge, and no cracks are formed in the package due to thermal stress. In this case, the Ti Schottky metal can be protected from the dry chemical etching of the AlCu metallization. However, in this case, the passivation is deposited via the AlCu edge and is also etched in this region. This can be up to 5 microns of AlCu thickness. However, the thicker the front-side metallization, the more critical this becomes because the resist must be guided to the edge; as the AlCu thickness increases, the resist thickness also increases. To improve the i 2 T performance (a measure of the surge current intensity) of the diode or the short-circuit performance of the MOSFET, a larger heat sink can be provided by increasing the thickness of the metallization. The thicker the AlCu metallization, the more difficult it is to process the dielectric passivation in this step.

[0081] High topologies can be avoided by creating a dielectric passivation between the Schottky metallization and the pad metallization. Figure 6A-6F An example of a Schottky SiC diode is shown in

[0082] In some methods, silicon nitride / silicon oxide (SiNx / SiOx) passivation can be used in the edge region. In these cases, the passivation can be formed before depositing the Ti-Al(Cu) metallization or between the Ti and AlCu process blocks. The passivation can be in contact with the metallization, which may lead to adhesion problems or, in the case of thermal stress, cracks in the passivation.

[0083] The degradation of the Schottky contact can be improved by providing a buffer layer above the Ti layer, which can absorb the effects of any process steps between the Schottky and the pad metallization (e.g., dry etching processes). For several reasons, the TiAl3 layer can play a role in this regard: 1) Since Ti can be used as the Schottky metal for the diodes produced, Al can be deposited in situ with appropriate tools. Thus, the SiC-Ti interface can be the same as that of the products produced. 2) During the temper action, the formation of TiAl3 can be set very precisely, forming a strong adhesion between the Ti and TiAl3 layers in the case of a smooth and uninterrupted transition. 3) The formation of TiAl3 serves as an etch stop for the AlCu etch. Thus, no undercut will be produced under the passivation (see Figure 6E ). A sufficient distance (e.g., 3 - 5 microns) can be maintained between the AlCu and the passivation.

[0084] To keep the electric field strength compatible with the die material, an additional organic passivation can be used, which encapsulates the complete inorganic (silicon oxide - silicon nitride) passivation and also absorbs part of the mechanical stress. Thus, due to the thickness of the inorganic passivation, the amount of the electric field strength at the interface between the inorganic passivation and the organic passivation can be > 500 kV / cm. The size of the organic passivation can be determined such that at its surface representing the interface with the die material, the amount of the electric field strength can be reduced so that the degradation of the die material and / or rollover within it can be excluded. The thickness of the organic passivation can range from 5 microns (e.g., for 650 V devices) to 20 microns (e.g., for 2 kV devices).

[0085] For example, a TiAl3 layer can be used, which acts as both a buffer layer and an etch stop layer. The TiAl3 can be produced by a temper action according to the Ti - Al layer sequence. The ratio of these layers can be selected such that the Ti layer forming the Schottky barrier remains all the way to the semiconductor body and a TiAl3 layer is formed above the Ti layer. The TiAl3 layer can be used as a buffer layer for the remaining materials from dry chemical etching (e.g., fluorine). This may not refer to the contaminants (e.g., polymers) located on top of the TiAl3. Thus, the Ti Schottky metallization can be protected from being affected. The TiAl3 layer can also be used as an etch stop layer in the wet chemical patterning of the AlCu metallization. Thus, under - etching of the dielectric passivation cannot be caused.

[0086] Some examples relate to the implementation of a TiAl3 buffer layer for protecting the Ti Schottky layer of a SiC diode used in subsequent dry chemical etching processes during the manufacture of moisture - robust and thermally - robust SiC devices.

[0087] Figure 6A-6FA schematic cross-section of a portion of a SiC diode including a TiAl3 barrier sub-layer is shown. For example, the implementation of the SiC diode can be similar to, for example, the semiconductor device described with respect to Figure 1 and / or Figure 2 as described.

[0088] Figure 6A A schematic cross-section of a portion of the SiC diode after deposition of titanium and aluminum metallization is shown. For example, a first barrier sub-layer 651 is deposited on a semiconductor substrate 110, and an intermediate barrier layer 653 is deposited on the first sub-layer 651. The first sub-layer 651 is a Ti layer, and the intermediate layer 653 is an Al layer. The first barrier sub-layer 651 and the intermediate layer 653 can be deposited with a selected Ti-Al thickness ratio such that after tempering (see Figure 6C ), the remaining Ti and the resulting TiAl3 layer are thick enough to avoid cracking due to stress. For example, a ratio of Ti to Al of 2 to 1 (or 1.5 to 1 or 3 to 1) can be deposited (e.g., a 180 nm Ti layer and a 90 nm Al layer).

[0089] Figure 6B These two layers are shown after the first sub-layer 651 and the intermediate layer 653 are constructed.

[0090] Figure 6C The SiC diode after tempering and formation of the TiAl3 layer is shown. By appropriately adjusting the time, temperature, and / or pressure, the Ti layer and the Al layer can be tempered to cause the intermediate layer 653 to react with the first barrier sub-layer 651 and convert from Al to a second barrier sub-layer 652 including a TiAl alloy layer (e.g., a TiAl3 layer). After tempering, assuming an initial 180 nm Ti and 90 nm Al layer, this may result in approximately a 120 nm TiAl3 layer serving as a buffer layer to absorb the bonding from the dry etching process, and a 150 nm Ti layer serving as the Schottky metal / interface for the resulting diode. For example, rapid thermal processing can be used for TiAl3 formation.

[0091] Figure 6D The SiC diode after deposition and construction of a silicon nitride-silicon oxide passivation of an inorganic passivation structure is shown. The inorganic passivation structure 130 includes a silicon oxide layer 231 that is at least 500 nm (or at least 800 nm or at least 1000 nm) thick and a silicon nitride layer 232 that is at least 200 nm (or at least 300 nm or at least 400 nm) thick. To construct the inorganic passivation structure, a photomask layer can be formed and lithography can be performed. Then, the inorganic passivation structure can be etched by a dry etching process. After that, the resist and / or polymer can be removed.

[0092] The inorganic passivation structure can be deposited and patterned on the first sub-layer 651 without degrading the Schottky interface of the first sub-layer 651 because the second sub-layer 652 protects the first sub-layer 651 from the dry etching process. In this way, it is possible to form the inorganic passivation structure before forming the metallization layer.

[0093] Figure 6E A SiC diode is shown after the deposition and patterning of an AlCu pad metallization (e.g., contact metallization layer 120). The AlCu front-side metallization can be deposited, and an etch mask can be formed by lithography. The contact metallization layer 120 can be patterned by wet chemical etching, which can remove the AlCu layer but not the TiAl3 layer. Thus, under-etching of the inorganic passivation structure (e.g., silicon oxide layer 231) does not occur. As in other examples discussed herein, a gap d1 is maintained between the AlCu layer and the passivation to avoid passivation cracks during thermo-mechanical stress.

[0094] Figure 6F A SiC diode is shown after the etching of the imide passivation (to achieve an organic passivation layer) and the adhesion layer passivation. An adhesion layer 260 (e.g., having a thickness of 40 nm) is deposited after the formation of the contact metallization layer 120, and an organic passivation layer 140 (e.g., an imide layer with a thickness of 5 μm) is deposited on the adhesion layer 260. Then the organic layer passivation layer 140 and the adhesion layer 260 are constructed and the surface is cleaned.

[0095] More details and aspects are mentioned in connection with the proposed concept or one or more of the examples described above or below. The method can include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more of the examples described above (e.g., Figure 1-5 ) or below (e.g., FIGS. 7-9).

[0096] Some examples relate to a semiconductor device including a barrier layer that includes a first sub-layer and a second sub-layer. The first sub-layer can be a TiAl alloy layer, and the second sub-layer can be a Ti layer. Additionally, the semiconductor device includes a contact metallization layer containing aluminum (e.g., AlCu, AlSiCu, or AlSi). At least a portion of the barrier layer can be located between the semiconductor substrate of the semiconductor device and the contact metallization layer. Additionally, at least a portion of the first sub-layer of the barrier layer contacts the second sub-layer and contacts the contact metallization layer.

[0097] More details and aspects are mentioned in connection with the proposed concept or one or more of the examples described above or below.

[0098] Some examples relate to methods for forming semiconductor devices, which include forming a barrier layer including a first sub-layer and a second sub-layer. The first sub-layer may be a Ti layer and the second sub-layer may be a TiAl alloy layer. In addition, the method includes forming a contact metallization layer including aluminum (such as AlCu, AlSiCu, or AlSi). At least a portion of the barrier layer may be located between the semiconductor substrate of the semiconductor device and the contact metallization layer. In addition, at least a portion of the second sub-layer of the barrier layer contacts the first sub-layer and contacts the contact metallization layer.

[0099] For example, an inorganic passivation structure may be formed before the contact metallization layer. In this way, deposition of the inorganic passivation structure on a surface with a high topology due to the contact metallization layer can be avoided.

[0100] The TiAl alloy layer may be a TiAl3 layer. The TiAl3 layer may be formed to have a thickness of at least 80 nm (or at least 100 nm) and / or at most 400 nm (or at most 300 nm or at most 200 nm). The TiAl3 layer may be formed by applying at least 1 h (or at least 5 h) and / or at most 20 h (or at most 15 h) at a temperature of at least 300 °C (or at least 350 °C, such as 400 °C).

[0101] More details and aspects are mentioned in connection with the concepts presented or one or more of the examples described above or below.

[0102] High humidity may cause problems of edge degradation of SiC MOSFETs. In some cases, it may be necessary to protect the semiconductor body from moisture.

[0103] Some methods may use SiNx / SiOx passivation in the edge region. In these methods, passivation may be achieved before depositing Ti-Al(Cu) metallization or between the Ti and AlCu process blocks. The passivation may contact the metallization, which may cause adhesion problems or, in the case of thermomechanical stress, cause cracks in the passivation. In some methods, compared with SiC MOSFETs, the processing of SiC diodes and thus also the cross-section may deviate. In addition, these methods may include uniformly doped edge termination, and the p-in-p termination does not reduce the field in the edge.

[0104] The problem of moisture-permeable edge passivation of SiC MOSFETs can be solved by fabricating passivation after the AlCu / Ti-TiN process block. The layout can be chosen such that a sufficiently large distance is established between the AlCu edge and the passivation, but the edge termination of the MOSFET can be completely covered by dielectric passivation. Compared to diodes, the processing and thus also the cross-section can be different because the edge region may be covered by a gate oxide (GOX) and / or an interlayer dielectric (ILD). Therefore, it may no longer be necessary to deposit an oxide / nitride passivation (as in the case of diodes). Instead, the ILD+GOX can be used as a silicon oxide layer, and only a nitride layer can be used. Regarding the function of the layers: The silicon nitride layer can be used as the actual moisture barrier, and the silicon oxide layer can be used as an adhesion layer to SiC. They can be chosen thick enough to minimize the effect of variations at the silicon oxide-silicon nitride interface on the charge balance in the edge. Since the inorganic silicon oxide-silicon nitride passivation layer may not be stretchable across the AlCu metallization, and the MOSFET can be mounted in a soft die module, the thickness can be reduced accordingly and an oxide thickness of at least 300 nm (or 400 nm or 500 nm) and at most 1000 nm (or 800 nm or 500 nm) may be sufficient.

[0105] To keep the electric field strength compatible with the die material, additional organic passivation can be used, which encapsulates the complete silicon oxide-silicon nitride passivation and also absorbs part of the mechanical stress. Thus, for example, due to the thickness of the inorganic passivation, the amount of electric field strength at the interface between the inorganic passivation and the organic passivation can be >500 kV / cm. The size of the organic passivation can be determined such that at its surface representing the interface with the die material, the amount of electric field strength can be reduced so that degradation of the die material and / or flipping within it can be excluded. The thickness of the organic passivation can in turn be chosen such that the forces caused by thermal expansion do not result in the formation of cracks in the same or subsequent layers.

[0106] If an inorganic hard passivation is chosen such that only the edge termination is covered, the area covered by the inorganic hard passivation can be reduced, and thus a reduction in voltage in the SiC oxide / nitride layer setup can be obtained. In this case, to ensure the adhesion of the organic passivation to the front-side metal, a thin adhesive layer can be used, which covers both the front-side metal under the imide and also the inorganic passivation.

[0107] An edge structure for SiC MOSFETs can be introduced. Passivation can be selected such that GOX and ILD are combined with an additional deposited silicon oxide / silicon nitride layer to form dielectric passivation for the moisture barrier. In some examples, the silicon oxide layer can be optional (not mandatory). To reduce or eliminate crack formation in the inorganic passivation, the distance between the AlCu edge and the silicon oxide - silicon nitride passivation can be large enough. To further reduce the electric field in the passivation, imide passivation can be used. A thin silicon nitride adhesion layer can be used to improve its adhesion.

[0108] With this combination of inorganic and organic layers, both the mechanical requirements of the packaging form and the hard mold can be met, as well as the moisture robustness requirements for modern semiconductor devices and their fields of use.

[0109] This passivation can be used independently of the actual edge structure within the semiconductor. Thus, for example, for JTE, where p - doping is uniformly guided around the device in an annular structure, and for the so - called p - in - p JTE, where the field strength can be significantly reduced at the edge of the device, both in the semiconductor and in the passivation region above the semiconductor body.

[0110] Some examples relate to a manufacturing method for a moisture - robust and thermally stable junction - terminated p - in - p edge for SiC - MOSFETs. Some examples of SiC - MOSFETs including an intermediate oxide layer (e.g., including an ILD + GOX layer) are described below. In the example shown in FIG. 7, only a silicon nitride layer (as an inorganic passivation structure) is deposited on the ILD + GOX. In the example shown in FIG. 8, there is an optional thin silicon oxide layer. In Figure 9 the example shown, the barrier layer extends across the edge termination region.

[0111] Figure 7A -C shows a schematic cross - section of a part of a SiC MOSFET including an intermediate oxide layer and a p - in - p edge termination structure. For example, the implementation of a SiC MOSFET can be similar to the implementation of semiconductor devices described in conjunction with Figure 1 、 2 and / or 6a - 6f.

[0112] Figure 7A Shows a schematic cross - section of a SiC MOSFET through the deposition and patterning of front - side metallization (e.g., after wet etching of AlCu and dry etching of Ti / TiN). The SiC MOSFET includes a SiC substrate 110, a contact metallization layer 120 (e.g., an AlCu layer with a thickness of 5μm), a barrier layer 250, an intermediate oxide layer 731, and an ohmic contact layer 770.

[0113] In this example, the stack layer 250 may include a Ti layer and / or a TiN layer. A first lateral portion of the stack layer 250 may be in vertical contact with the contact metallization layer 120 on one side and in vertical contact with the ohmic contact layer 770 on the opposite side. A second lateral portion of the stack layer 250 may be in vertical contact with the contact metallization layer 120 on one side and in vertical contact with the intermediate oxide layer 731 on the opposite side.

[0114] The ohmic contact layer 770 may include a nickel-aluminum (NiAl) alloy layer. The ohmic contact layer 770 may have a thickness of at least 20 nm and at most 60 nm. The ohmic contact layer 770 may be in vertical contact with the stack sub-layer 250 on one side and in vertical contact with the SiC substrate 110 on the opposite side.

[0115] The intermediate oxide layer 731 may include an ILD layer and a GOX layer. The intermediate oxide layer 731 may be formed before the contact metallization layer 120. At least a portion of the intermediate oxide layer 731 may be vertically located between the contact metallization layer 120 (and / or the stack layer 250) and the SiC substrate 110.

[0116] Figure 7B A schematic cross-section of a SiC MOSFET after deposition and patterning of an inorganic passivation nitride layer (e.g., after deposition, etching, resist removal, and surface cleaning of a 400-nm-thick silicon nitride) is shown. The silicon nitride layer 232 may be deposited on the intermediate oxide layer 731. The silicon nitride layer 232 may be patterned via a resist mask such that the intermediate oxide layer 731 laterally located between the contact metallization layer 120 (e.g., the AlCu edge) and the inorganic passivation structure (e.g., the silicon nitride layer 232) is not removed or etched. In other words, the intermediate oxide layer 731 may be used as an etch stop for the construction of the silicon nitride layer 232.

[0117] Figure 7C A schematic cross-section of a SiC MOSFET after completion of organic passivation, opening of the silicon nitride adhesion layer 260, and etching of ILD+GOX in the edge region (e.g., after deposition of a 40-nm-thick adhesion layer 260 HSP and an imide process block) is shown. A portion of the organic passivation layer 140 may be disposed in the gap laterally between the contact metallization layer 120 and the silicon nitride layer 232 (e.g., similar to those shown in Figure 1 and 2 ). The distance d4 from the lateral edge of the silicon nitride layer 232 to the edge of the SiC MOSFET may be greater than the distance d5 from the lateral edge of the intermediate oxide layer 731 to the edge of the SiC MOSFET.

[0118] In the deposition and patterning of the front-side metal (see Figure 7A), a silicon nitride layer 232 is deposited. Subsequently, it is patterned through a resist mask. For example, the etching process is selective such that the ILD + GOX is not etched between the passivation and the AlCu edge. After removing the resist mask and cleaning the surface (see Figure 7B ), the deposition of the adhesive layer 260 (40 nm silicon nitride) can be performed, and then the fabrication of the imide passivation can be carried out. Subsequently, the adhesive layer 260 can be opened through an imide mask, and finally, the ILD+GOX in the outer edge region can be etched (see Figure 7C ). After cleaning the surface, the front-side process can be completed.

[0119] More details and aspects are mentioned in connection with the proposed concept or one or more of the examples described above or below. The SiC MOSFET can include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more of the examples described above (e.g., Figure 1 -6) or below (e.g., FIGS. 8-9).

[0120] Figure 8A -C shows a schematic cross-section of a portion of a SiC MOSFET including an intermediate oxide layer and a p-in-p edge termination structure. For example, the implementation of the SiC MOSFET can be similar to that of the semiconductor device described in connection with Figure 1 , 2 , 6A-6F and / or 7A-7C.

[0121] Figure 8A shows a schematic cross-section of the SiC MOSFET after deposition and patterning on the front side (e.g., after wet AlCu and dry Ti / TiN etching with an additional mask). Compared with Figure 7A , the Ti / TiN layer is patterned through an additional mask such that the Ti / TiN layer can extend further along the intermediate oxide layer 731 than the contact metallization layer 120. Therefore, the Ti / TiN layer 250 can be used as an etch stop for subsequent silicon nitride / silicon oxide etching.

[0122] In other words, the barrier layer 250 can extend laterally beyond the contact metallization layer 120. This portion of the barrier layer 250 (e.g., the portion that does not contact the contact metallization layer 120) can act as an etch stop during the subsequent etching of the silicon nitride layer 232 / silicon oxide layer 231 (e.g., the inorganic passivation structure).

[0123] Figure 8BShows a schematic cross-section of a SiC MOSFET after deposition and patterning of an inorganic passivation layer (e.g., after passivation etching, resist removal, and surface cleaning). Compared with FIG. 7, the inorganic passivation structure 130 of FIG. 8 further includes a silicon oxide layer 231. As Figure 8B shown, the intermediate oxide layer 731 (ILD and GOX layers) has been etched at the edges (together with the silicon nitride layer and the silicon oxide layer of the inorganic passivation structure). The intermediate oxide layer 731 below the Ti / TiN barrier layer 250 located in the gap is not etched because the Ti / TiN barrier layer 250 acts as an etch stop in this region. For example, the Ti / TiN barrier layer 250 is thick enough so that it is not consumed during the etching of the oxide.

[0124] Figure 8C Shows a schematic cross-section of a SiC MOSFET after completion of organic silicon passivation and opening of the silicon nitride adhesion layer 260. The oxide layer has been etched, so only the adhesion layer 260 (at the edge of the SiC substrate) needs to be removed.

[0125] The SiC MOSFET includes a semiconductor substrate 110, a contact metallization layer 120, a silicon nitride layer 232 and a silicon oxide layer 231 (e.g., the inorganic passivation structure 130), an intermediate oxide layer 731, a barrier layer 250, an organic passivation structure 140 (e.g., imide), an adhesion layer 260, and an ohmic contact layer 770. The distance d5 from the side edge of the intermediate oxide layer 731 to the edge of the SiC MOSFET can be equal to the distance d4 from the lateral edge of the inorganic passivation structure (from the edge of the silicon nitride layer 232 / silicon oxide layer 231) to the edge of the SiC MOSFET.

[0126] In Figure 8A-8C the example shown, a silicon oxide / silicon nitride stack is used to implement a moisture barrier. In this way, the distance of the silicon oxide - silicon nitride interface from the edge termination of the device can be increased, and thus the influence of the boundary layer charge can be further reduced.

[0127] In this example, the Ti / TiN barrier layer 250 is patterned via an additional mask. After depositing the silicon oxide / silicon nitride and fabricating a resist mask, in subsequent steps, the inorganic passivation can be patterned by means of a plasma etching step and the resist can be removed again (see Figure 8B ). Here, the Ti / TiN layer in the gap between the passivation and AlCu can be used as an etch stop layer. In the next process, the deposition of the adhesive layer 260 (e.g., 40 nm silicon nitride) is performed again and then imide passivation is fabricated. Subsequently, the adhesion layer 260 is opened via an imide mask. Contrary to the example of Figure 7A-7C , it may not be necessary to etch the GOX + ILD again.

[0128] More details and aspects are mentioned in connection with the proposed concepts or one or more of the examples described above or below. The SiC MOSFET may include one or more additional optional features corresponding to one or more aspects of the proposed concepts or one or more of the examples described above (e.g., Figure 1 -7) or below (e.g., Figure 9 ).

[0129] Figure 9 A schematic cross-section of a portion of another SiC MOSFET including an intermediate oxide layer 731 is shown. Figure 9 The cross-section shown in Figure 8A-8C shows a schematic process flow for forming the SiC MOSFET. For example, the implementation of the SiC MOSFET may be similar to that of the SiC device described in connection with

[0130] Figure 9 The example shown in Figure 8A-8C differs from the example in

[0131] in the structure of the barrier layer 250. The barrier layer 250 of the SiC MOSFET differs from the barrier layer 250 of the SiC MOSFET in its lateral extent. That is, the barrier layer 250 of the SiC MOSFET extends at least towards the edge region of the device in a p-ring structure that terminates at the p in p edge, while the barrier layer 250 of the SiC MOSFET shown in FIG. 8 does not extend laterally beyond the outermost p-ring structure of the SiC substrate.

[0132] After forming the SiC substrate including doped regions and the intermediate oxide layer 731 for implementing transistor cells and edge termination, a Ti / TiN layer (e.g., the barrier layer 250) is deposited. A photolithographic mask is provided on the Ti / TiN layer. Dry etching of the Ti / TiN layer is performed, thereby removing the Ti / TiN other than that covered by the mask.

[0133] More details and aspects are mentioned in connection with the proposed concepts or one or more of the examples described above or below. The SiC MOSFET may include one or more additional optional features corresponding to one or more aspects of the proposed concepts or one or more of the examples described above (e.g., Figure 1-8) or one or more additional optional features of one or more of the examples described below.

[0134] Some embodiments relate to moisture-robust device passivation with good thermal performance. A passivation structure including both an organic layer and an inorganic layer can meet both the mechanical requirements of a package type with a hard mold and the requirements of the robustness specified for modern semiconductor devices and their applications in terms of moisture.

[0135] Some other concepts introduce edge termination for semiconductor devices with high electric field strength at the edges, which significantly improves the robustness against moisture in the absence of any organic passivation layer. This may be feasible only for package forms with a soft mold, in which no mechanical stress occurs between the semiconductor and the molding compound. For other packages where mechanical stress occurs between the molding compound and the passivation, especially due to temperature rise, this may not be a solution. However, these package forms also require moisture-resistant components because the so-called "hard cast" or "molding compound" does not provide sufficient moisture protection.

[0136] There are some concepts that use SiNx / SiOx passivation in the edge region, where, in all cases, the passivation is achieved before the deposition of the Ti-Al(Cu) metallization or between the Ti and AlCu process blocks. That is, the passivation and the metallization are in contact, which may cause difficulties or, in the case of TC stress, cracks in the passivation.

[0137] Aspects and features mentioned and described in conjunction with one or more of the accompanying drawings and the previously detailed examples can also be combined with one or more of the other examples in order to replace the same features of the other examples or to introduce the aspect and feature additionally into the other examples.

[0138] When a computer program is executed on a computer or a processor, an example can further be or relate to a computer program having program code for performing one or more of the methods described above. The steps, operations, or processes of the various methods described above can be executed by a programmed computer or processor. An example can also cover program storage devices such as digital data storage media, which are machine, processor, or computer-readable and encode machine-executable, processor-executable, or computer-executable instruction programs. The instructions execute or cause the execution of some or all of the actions of the methods described above. The program storage device can, for example, include or be a digital memory, a magnetic storage medium such as disks and tapes, a hard disk drive, or an optically readable digital data storage medium. Further examples can also cover a computer, a processor, or a control unit programmed to perform the actions of the methods described above or a (field) programmable logic array ((F)PLA) or a (field) programmable gate array ((F)PGA) programmed to perform the actions of the methods described above.

[0139] The description and drawings merely illustrate the principles of the present disclosure. In addition, all examples described herein are mainly intended to be clearly for educational purposes only, to help the reader understand the principles of the present disclosure and the concepts contributed by the inventor(s) to advance the field. All statements of the principles, aspects and examples of the present disclosure described herein, as well as their specific examples, are intended to cover their equivalents.

[0140] For example, a block diagram may illustrate a high-level circuit diagram implementing the principles of the present disclosure. Similarly, a flowchart, a process diagram, a state transition diagram, pseudocode, etc. may represent various processes, operations or steps, which may be represented, for example, substantially in a computer-readable medium and thus executed by a computer or a processor, whether or not such a computer or processor is explicitly shown. The methods disclosed in the description or claims may be implemented by an apparatus having means for performing each of the corresponding actions of these methods.

[0141] It should be understood that unless otherwise specified explicitly or implicitly for technical reasons, the disclosure of multiple actions, processes, operations, steps or functions in the description or claims may not be construed as being in a particular order. Thus, the disclosure of multiple actions or functions does not limit these actions or functions to a particular order, unless these actions or functions are not interchangeable due to technical reasons. In addition, in some examples, a single action, function, process, operation or step may respectively include or may be divided into multiple sub-actions, functions, processes, operations or steps. Such sub-actions may be included and may be part of the disclosure of that single action, unless explicitly excluded.

[0142] In addition, the following claims are hereby incorporated into the detailed description, where each claim may stand alone as a separate example. Although each claim may stand alone as a separate example, note that although a dependent claim may refer to a particular combination with one or more other claims in the claims, other examples may also include combinations of the subject matter of the dependent claim with each other dependent claim or the independent claim. Such combinations are explicitly set forth herein unless stated not to be intended for a particular combination. In addition, even if the claim is not directly dependent on an independent claim, the features of the claim that refers to any other independent claim are also intended to be included.

Claims

1. A semiconductor device (100, 200), comprising: A contact metallization layer (120) disposed on a semiconductor substrate (110); An inorganic passivation structure (130) disposed on the semiconductor substrate (110); And An organic passivation layer (140), wherein a first portion of the organic passivation layer (140) is laterally located between the contact metallization layer (120) and the inorganic passivation structure (130), and a second portion of the organic passivation layer (140) is located on top of the inorganic passivation structure (130), and wherein the first portion of the organic passivation layer is vertically located closer to the semiconductor substrate (110) than the second portion of the organic passivation layer, and wherein a third portion of the organic passivation layer is located on top of the contact metallization layer (120); Wherein the inorganic passivation structure (130) comprises a continuous layer that contacts the semiconductor substrate (110), or only an electrically insulating layer is located between the continuous layer and the semiconductor substrate (110), Wherein the contact metallization layer comprises a first edge side extending from the upper surface of the contact metallization layer towards the semiconductor substrate, Wherein the inorganic passivation structure comprises a second edge side extending from the upper surface of the inorganic passivation structure towards the semiconductor substrate, Wherein the first edge side and the second edge side define a lateral gap between the inorganic passivation structure and the contact metallization layer, Wherein the first portion of the organic passivation layer extends into the lateral gap, and Wherein the second edge side is the surface of the inorganic passivation material closest to the contact metallization layer.

2. The semiconductor device according to claim 1, wherein the thickness of the inorganic passivation structure (130) is at least 500 nm.

3. The semiconductor device according to any one of the preceding claims 1-2, wherein the inorganic passivation structure (130) comprises at least a silicon oxide layer (231) having a thickness of at least 300 nm and at most 5 μm.

4. The semiconductor device according to any one of the preceding claims 1-2, wherein the inorganic passivation structure (130) comprises at least a nitride layer (232) having a thickness of at least 300 nm and at most 900 nm.

5. The semiconductor device according to any one of the preceding claims 1-2, wherein the lateral distance (d1) between the inorganic passivation structure (130) and the contact metallization layer (120) is greater than the thickness (t1) of the contact metallization layer (120).

6. The semiconductor device according to any one of the preceding claims 1-2, wherein the lateral distance (d1) between the inorganic passivation structure (130) and the contact metallization layer (120) is less than the width (w1) of the inorganic passivation structure (130).

7. The semiconductor device according to any one of the preceding claims 1-2, wherein the lateral distance (d2) between the inorganic passivation structure (130) and the edge (202) of the semiconductor substrate (110) is at least 10 μm.

8. The semiconductor device according to one of the preceding claims 1-2, wherein the thickness and / or material of the inorganic passivation structure (130) is configured such that the electric field at the surface of the inorganic passivation structure (130) is at least 500 kV / cm in the blocking state of the electrical structure formed at the semiconductor substrate (110).

9. The semiconductor device according to one of the preceding claims 1-2, wherein the organic passivation layer (140) is a polyimide layer having a thickness of at least 1 μm and at most 50 μm.

10. The semiconductor device according to one of the preceding claims 1-2, wherein the thickness and / or material of the organic passivation structure (140) is configured such that the electric field at the surface of the organic passivation layer (140) is at most 500 kV / cm in the blocking state of the electrical structure formed at the semiconductor substrate (110).

11. The semiconductor device according to one of the preceding claims 1-2, further comprising a barrier layer (250), wherein a first portion of the barrier layer (250) is disposed between the contact metallization layer (120) and the semiconductor substrate (110), wherein a second portion of the barrier layer (250) is disposed between the inorganic passivation structure (130) and the semiconductor substrate (110), and wherein the barrier layer (250) extends at least from the first portion of the barrier layer (250) to the second portion of the barrier layer (250).

12. The semiconductor device according to claim 11, wherein the barrier layer (250) comprises a first sub-layer (651) and a second sub-layer (652), wherein the first sub-layer comprises titanium, and wherein the second sub-layer comprises a titanium-aluminum alloy.

13. The semiconductor device according to claim 11 or 12, wherein the first portion of the barrier layer (250) is disposed vertically between the intermediate oxide layer (731) and the contact metallization layer (120), and the second portion of the barrier layer (250) is disposed vertically between the inorganic passivation structure (130) and the intermediate oxide layer (731).

14. The semiconductor device according to one of the preceding claims 1-2, further comprising an adhesion layer (260), wherein a first portion of the adhesion layer (260) is disposed between the contact metallization layer (120) and the organic passivation layer (140), wherein a second portion of the adhesion layer (260) is disposed between the inorganic passivation structure (130) and the organic passivation layer (140), and wherein the adhesion layer (260) extends at least from the first portion of the adhesion layer (260) to the second portion of the adhesion layer (260).

15. The semiconductor device according to claim 14, wherein the adhesion layer (260) has a thickness of at most 100 nm and at least 10 nm.

16. The semiconductor device according to one of the preceding claims 1-2, further comprising a molding compound structure in contact with the organic passivation layer (140).

17. A semiconductor device according to one of the preceding claims 1-2, wherein the semiconductor substrate (110) includes a drift region (211) of an electrical structure, the drift region (211) including a dopant of a first conductivity type, wherein the semiconductor substrate (110) includes an edge termination region (215), the edge termination region (215) including a dopant of a second conductivity type, wherein the edge termination region (215) extends laterally at least partially under the inorganic passivation structure (130) from the contact region towards the edge (202) of the semiconductor substrate (110), and wherein the edge termination region (215) is ohmically connected to the contact metallization layer (120).

18. The semiconductor device according to claim 17, wherein a lateral distance (d2) between the inorganic passivation structure (130) and the edge (202) of the semiconductor substrate (110) is less than a lateral distance (d3) between the edge termination region (215) and the edge (202) of the semiconductor substrate (110).

19. A semiconductor device according to one of the preceding claims 1-2, wherein a bonding wire or a solder structure is in contact with the contact metallization layer (120).

20. A semiconductor device according to one of the preceding claims 1-2, wherein the semiconductor substrate (110) is a semiconductor substrate of a wide bandgap material.

21. A semiconductor device according to one of the preceding claims 1-2, further comprising an electrical structure formed at the semiconductor substrate (110) and having a breakdown voltage of at least 100V.

22. A semiconductor device according to one of the preceding claims 1-2, wherein the organic passivation layer (140) continuously covers the inorganic passivation layer (130) and at least some portions of the contact metallization layer (120).

23. A semiconductor device according to one of the preceding claims 1-2, further comprising an intermediate oxide layer (731), wherein a first portion of the intermediate oxide layer (731) is vertically disposed between the contact metallization layer (120) and the semiconductor substrate (110), wherein a second portion of the intermediate oxide layer (731) is vertically disposed between the inorganic passivation structure (130) and the semiconductor substrate (110), and wherein the intermediate oxide layer (731) extends at least from the first portion to the second portion.

24. The semiconductor device according to claim 23, wherein the inorganic passivation structure (130) includes a nitride layer (232), and wherein a first portion of the organic passivation layer (140) is vertically located closer to the intermediate oxide layer (731) than a second portion of the organic passivation layer (140).

25. The semiconductor device according to claim 23, wherein the inorganic passivation structure (130) includes a silicon oxide layer (231) and a silicon nitride layer (232), and wherein the silicon oxide layer (231) is vertically disposed between the silicon nitride layer (232) and the intermediate oxide layer (731).

26. A semiconductor device, comprising: A stack layer (250) comprising a first sub-layer (651) and a second sub-layer (652), wherein the first sub-layer (651) is a titanium layer and the second sub-layer (652) is a titanium-aluminum alloy layer; and A contact metallization layer (120) containing aluminum, where at least a portion of the first sub-layer (651) contacts the semiconductor substrate of the semiconductor device and is located between the contact metallization layer (120) and the semiconductor substrate (110) of the semiconductor device, and at least a portion of the second sub-layer (652) of the stack layer (250) contacts the first sub-layer (651) and contacts the contact metallization layer (120), where a portion of the stack layer extends laterally beyond the edge side of the contact metallization layer, and where the semiconductor device further includes a layer stack directly disposed on the portion of the stack layer, the layer stack including an adhesion layer directly contacting the portion of the stack layer and an organic passivation layer directly contacting the adhesion layer.

27. A method for forming a semiconductor device, comprising: Forming a stack layer (250) including a first sub-layer (651) and a second sub-layer (652), wherein the first sub-layer (651) is a titanium layer and the second sub-layer (652) is a titanium-aluminum alloy layer; and Forming a contact metallization layer (120) containing aluminum, where at least a portion of the first sub-layer (651) contacts the semiconductor substrate of the semiconductor device and is located between the contact metallization layer (120) and the semiconductor substrate (110) of the semiconductor device, and at least a portion of the second sub-layer (652) of the stack layer (250) contacts the first sub-layer (651) and contacts the contact metallization layer (120), where a portion of the stack layer extends laterally beyond the edge side of the contact metallization layer, and where the semiconductor device further includes a layer stack directly disposed on the portion of the stack layer, the layer stack including an adhesion layer directly contacting the portion of the stack layer and an organic passivation layer directly contacting the adhesion layer.

28. The method according to claim 27, wherein an inorganic passivation structure (130) is formed before the contact metallization layer (120).

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