Semiconductor package and method for manufacturing semiconductor package

Abstract

An embodiment of the present invention relates to a device with a pad pattern, which includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extension portions extending through the peripheral portion.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor package and a method for manufacturing the semiconductor package. Background Art

[0002] In general, a semiconductor die can be connected to other devices external to the semiconductor die by a type of package utilizing solder bumps. The solder bumps can be formed by initially forming an underbump metallization layer in contact with the conductive portion of the semiconductor die, and then placing conductive features and solder onto the underbump metallization. A reflow operation can then be performed to shape the solder into a desired shape. The solder can then be placed in physical contact with an external device, and another reflow operation can be performed to engage the solder with the external device. In this manner, a physical and electrical connection can be formed between the semiconductor die and an external device, such as a printed circuit board, another semiconductor die, or the like.

[0003] Different materials used to form the semiconductor die (such as dielectric materials, metallization materials, etch stop layer materials, barrier layer materials, and other materials) may each have a unique coefficient of thermal expansion that is different from another material. This type of mismatch in coefficient of thermal expansion causes each of the materials to expand in a different manner when the semiconductor die is heated during later processing, testing, or use. Thus, at high temperatures, there is a mismatch in coefficient of thermal expansion that causes stresses to form between the different materials and, thus, between different portions of the semiconductor die. These stresses can cause delamination to occur between the various material layers. This delamination can damage the semiconductor die during the manufacturing process or during its intended use. Summary of the invention

[0004] The present invention is directed to a device, a semiconductor package, and a method of manufacturing a semiconductor package that can reduce or de-concentrate stress on the sidewalls of a pad pattern caused during thermal cycles of testing, manufacturing, and operation, thereby resulting in a higher yield and more reliable device.

[0005] According to some embodiments of the present disclosure, a device includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extension portions extending through the peripheral portion.

[0006] According to some embodiments of the present disclosure, a semiconductor package includes an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulation material. The redistribution structure extends over the encapsulated semiconductor device and is electrically connected to the semiconductor device. The redistribution structure includes a dielectric layer, a pad pattern, and a plurality of dielectric plugs. The pad pattern is disposed on the dielectric layer, wherein the pad pattern includes at least one pad portion embedded in the dielectric layer, and a lower surface of the pad pattern is substantially coplanar with a lower surface of the dielectric layer away from the encapsulated semiconductor device. A plurality of dielectric plugs extend through the pad pattern and surround the pad portion.

[0007] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor package includes the following steps. A redistribution structure is formed on a carrier, wherein forming the redistribution structure on the carrier includes the following steps: forming a first dielectric layer on the carrier, wherein the first dielectric layer includes a pad opening; forming a pad pattern on the first dielectric layer, wherein the pad pattern extends into the pad opening and includes a plurality of holes; and forming a second dielectric layer on the pad pattern, wherein the second dielectric layer fills the holes. An encapsulated semiconductor device is formed on the redistribution structure. The carrier is removed to reveal a lower surface of the pad pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figures 1 to 10 Cross-sectional views illustrating intermediate stages in the fabrication of semiconductor package structures according to some exemplary embodiments of the present disclosure.

[0010] Fig.11 A top view illustrating a pad pattern of a semiconductor package according to some exemplary embodiments of the present disclosure.

[0011] Fig.12 A cross-sectional view illustrating a portion of a redistribution structure of a semiconductor package according to some exemplary embodiments of the present disclosure.

[0012] Fig.13 A cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0013] Fig.14 illustrate Fig.13 A top view of a pad pattern of a semiconductor package in FIG.

[0014] Fig.15 A cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0015] Fig.16 illustrate Fig.15 A top view of a pad pattern of a semiconductor package in FIG.

[0016] Fig.17 A cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0017] Fig.18 illustrate Fig.17 A top view of a pad pattern of a semiconductor package in FIG.

[0018] Fig.19 A cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0019] Fig. 20 illustrate Fig.19 A top view of a pad pattern of a semiconductor package in FIG.

[0020] Description of Figure Numbers

[0021] 100, 100a, 100b, 100c, 100d: semiconductor packaging;

[0022] 110, 110a, 110b, 110c, 110d: rewiring structure;

[0023] 112, 112b, 112c: a first dielectric layer;

[0024] 114, 114a, 114b, 114c, 114d: pad patterns;

[0025] 116: a second dielectric layer;

[0026] 120, 120': semiconductor device;

[0027] 121, 140: substrate;

[0028] 122: contact pad;

[0029] 123: electrical terminal;

[0030] 124, 170: bottom filling glue;

[0031] 125, 125': encapsulated semiconductor device;

[0032] 126, 162: welding materials;

[0033] 130, 130': encapsulating material;

[0034] 142: conductive bonding member;

[0035] 150: electrical connector;

[0036] 160: Passive device;

[0037] 200, 300: carrier;

[0038] 210: adhesive layer;

[0039] 1121, 1121b, 1121c, 1121d: pad openings;

[0040] 1141, 1141a, 1141b, 1141c, 1141d: pad part;

[0041] 1142, 1142a, 1142c, 1142d: peripheral part;

[0042] 1143, 1143a, 1143b, 1143c, 1143d: holes;

[0043] 1144, 1144b: connecting part;

[0044] 1145c, 1145d: incision;

[0045] 1146d: pad notch;

[0046] 1161: Dielectric plug;

[0047] S1: Side wall. DETAILED DESCRIPTION

[0048] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0049] Additionally, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0050] In addition, for ease of description, terms such as "first", "second", "third", "fourth", etc. may be used herein to describe one or more similar or different elements or features as illustrated in the figures, and may be used interchangeably depending on the order of existence or the context of description.

[0051] Figures 1 to 10 Cross-sectional views illustrating intermediate stages in the fabrication of semiconductor package structures according to some exemplary embodiments of the present disclosure.

[0052] It should be noted that the present disclosure will be described with reference to some embodiments in a specific context, namely an integrated fan-out packaging structure and a method for manufacturing the same. However, the concepts in the present disclosure may also be applied to other semiconductor packages or circuits. According to various embodiments, a device (e.g., a rewiring structure) applicable to a semiconductor package, a semiconductor package structure, and a method for forming a semiconductor package are provided. According to some embodiments, intermediate stages of forming a semiconductor package are described, and variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, similar reference numerals are used to represent similar elements.

[0053] In some embodiments, a semiconductor package (such as shown in FIG. Fig.10 The intermediate stages of the semiconductor package 100 in FIG. 1 are described as follows. Figure 1 , a carrier 200 is provided, and an adhesive layer 210 may be disposed on the carrier 200. In some embodiments, the carrier 200 may include a silicon-based material such as glass, ceramic, or silicon oxide, or other materials such as aluminum oxide, a combination of any of these materials, or the like. The carrier 200 is planar so as to accommodate, for example, a semiconductor device 120 (not shown). Figure 1 But refer to below Figure 5B and Figure 7The present invention relates to the attachment of semiconductor devices to carrier 200 (illustrated and discussed in detail). Adhesive layer 210 may be placed on carrier 200 to assist in the adhesion of an overlying structure (e.g., redistribution structure 110). In one embodiment, adhesive layer 210 may include UV glue that reduces or loses its adhesive properties when exposed to UV light. However, other types of adhesives may also be used, such as pressure-sensitive adhesives, radiation-curable adhesives, light to heat conversion release coatings (LTHC), epoxies, combinations of these adhesives, or the like. Adhesive layer 210 may be placed on carrier 200 in a semi-liquid or gel form that is easily deformable under pressure.

[0054] In some embodiments, a redistribution structure (such as shown in Figure 5 The redistribution structure 110 in the embodiment may be formed on the carrier 200 or on the adhesive layer 210 (if present). The formation of the redistribution structure 110 includes the following steps. Figure 1 , the redistribution structure 110 can be formed by initially forming a first dielectric layer 112 on the carrier 200 or on the adhesive layer 210 (if present). In one embodiment, the first dielectric layer 112 can be polybenzoxazole (PBO), but any suitable material, such as polyimide or a polyimide derivative, can be used instead. The first dielectric layer 112 can be placed using, for example, a spin coating process, but any suitable method and thickness can be used instead. In some embodiments, the first dielectric layer 112 includes a pad opening 1121. The pad opening 1121 can be formed by the first dielectric layer 112 by removing a portion of the first dielectric layer 112 to expose at least a portion of the underlying carrier 200 or the adhesive layer 210 (if present). In some embodiments, the pad opening 1121 can be formed using a suitable photolithography mask and etching process, but any suitable process can be used.

[0055] refer to Figure 2, a pad pattern 114 is formed on the first dielectric layer 112. In some embodiments, the pad pattern 114 is embedded in the pad opening 1121 of the first dielectric layer 112. In other words, the pad pattern 114 extends into the pad opening 1121 and includes a plurality of holes 1143 extending through the pad pattern 114. In some embodiments, the holes 1143 may be configured in the form of a mesh (e.g., a mesh hole). In some embodiments, the pad pattern 114 may be one of the patterns of a redistribution circuit layer formed on the first dielectric layer 112, and the redistribution circuit layer may include more than one pad pattern 114. In one embodiment of forming the redistribution circuit layer using a seed layer, a patterned photoresist, and a plating process, the holes 1143 may be formed simply by not removing the photoresist in those areas where the holes 1143 are needed. In this way, the holes 1143 within the pad pattern 114 are formed together with the rest of the redistribution circuit layer, and no additional process steps are used.

[0056] For example, the pad pattern 114 may be formed by initially forming a seed layer (not shown) by a suitable formation process such as CVD or sputtering. In some embodiments, the seed layer may include Cu, Ti / Cu, TiW / Cu, Ti, CrCu, Ni, Pd, or the like, and may be deposited over the first dielectric layer 112 by, for example, sputtering. A photoresist (also not shown) may be formed to cover a portion of the metal layer 114, and the photoresist may then be patterned to expose those portions of the metal layer 114 where at least one pad portion 1141 and the peripheral portion 1142 are required to be located. Once the photoresist has been formed and patterned, a conductive material such as copper may be formed on the seed layer by a deposition process such as plating. However, when the materials and methods discussed are suitable for forming conductive materials, these materials are merely exemplary. Any other suitable material such as AlCu or Au and any other suitable formation process such as CVD or PVD may alternatively be used to form the pad pattern 114. Once the conductive material has been formed, the patterned photoresist can be removed by a suitable removal process, such as ashing. In addition, after removing the patterned photoresist, the conductive material can be used as a mask to remove those portions of the seed layer covered by the patterned photoresist, such as by a suitable etching process. However, the processes described above are for illustration only. Any suitable process for forming the pad pattern 114 can be used.

[0057] In another embodiment, the pad pattern 114 on the first dielectric layer 112 may be formed as a solid material, and the hole 1143 may be formed after the formation of the remaining portion of the pad pattern 114. In this embodiment, a photoresist mask and etching process may be used, wherein after the pad pattern 114 has been formed, a photoresist is placed over the pad pattern 114 and patterned, and one or more etching processes are used to remove those portions of the pad pattern 114 where the hole 1143 is desired. Any suitable process may be used to form the hole 1143.

[0058] Fig.11 A top view illustrating a pad pattern of a semiconductor package according to some exemplary embodiments of the present disclosure. Fig.12 A cross-sectional view of a portion of a rewiring structure of a semiconductor package according to some exemplary embodiments of the present disclosure is illustrated. Fig.11 and Fig.12 And reference Figure 2 In some embodiments, the hole 1143 surrounds (eg, surrounds) the pad opening 1121 (shown in FIG. Figure 1 1141 and the peripheral portion 1142. The pad portion 1141 extends into the pad opening 1121, and the peripheral portion 1142 surrounds the pad portion 1141. In some embodiments, the hole 1143 is disposed on the peripheral portion 1142 and extends through the peripheral portion 1142, such as Fig.11 and Fig.12 Therefore, the pad portion 1141 is positioned at the pad opening 1121, and because the pad portion 1141 and the first dielectric layer 112 are both formed on the carrier 200 or the adhesive layer 210 (if present) having a planar top surface, the lower surface of the pad portion 1141 is substantially coplanar with the lower surface of the first dielectric layer 112.

[0059] refer to Figure 3, the second dielectric layer 116 is formed on the pad pattern 114, and the second dielectric layer 116 fills the hole 1143 to form a plurality of dielectric plugs 1161 extending through the pad pattern 114. That is, the second dielectric layer 116 includes a plurality of extension portions 1161 (i.e., dielectric plugs 1161) extending through the peripheral portion 1142. In other words, the hole 1143 is filled with the dielectric material of the second dielectric layer 116. In some embodiments, the dielectric plug 1161 surrounds the pad opening 1121 and extends through the peripheral portion 1142. In some embodiments, the peripheral portion 1142 is disposed on the upper surface of the first dielectric layer 112. The pad portion 1141 is connected to the peripheral portion 1142 and extends from the upper surface of the first dielectric layer 112 to the lower surface of the first dielectric layer 112. In some embodiments, the pad portion 1141 and the peripheral portion 1142 are formed integrally. That is, the pad portion 1141 is directly connected to the peripheral portion 1142 without any borderline therebetween.

[0060] With this arrangement, the pad pattern 114 is fabricated with a hole 1143 passing through the peripheral portion 1142 to reduce the possibility of damage along the sidewalls (eg, as shown in FIG. 1 ) of the pad pattern 114 during thermal cycle testing, further processing, or operation. Fig.12 In other words, by forming the pad portion 114 with the hole 1143 (i.e., the dielectric plug 1161 / extension portion), the pad portion 114 is better able to withstand stresses associated with semiconductor manufacturing, testing, and operating processes. In addition, the hole 1143 can be used to reduce or eliminate delamination or peeling that may occur along the sidewall of the pad portion 114. Such reduction or prevention of delamination and peeling will help prevent defects and increase the overall yield of the manufacturing process of the semiconductor package (e.g., semiconductor package 100). It should be noted that the arrangement of the pad pattern 114 with the hole 1143 can also be applied to any other layer of the rewiring structure 110.

[0061] In some embodiments, the total layout area of ​​the hole 1143 may be approximately 3% to approximately 60% of the total layout area of ​​the pad portion 1141 and the peripheral portion 1142. As used herein, the term "layout area" refers to the total layout area of ​​the hole 1143 from a top view (e.g., Fig.11 , Fig.14 , Fig.16 as well as Fig. 20The area occupied by the structure of interest (e.g., hole 1143, pad portion 1141, and / or peripheral portion 1142) from the top view shown in FIG. 1144. For hole 1143, the term "layout area" may be the cross-sectional area of ​​hole 1143. In some embodiments, because the thickness of hole 1143 and pad pattern 114 is substantially the same or at least similar, the sum of the volume of hole 1143 is substantially 3% to 60% of the sum of the volume of pad portion 1141 and peripheral portion 1142. At this ratio, hole 1143 can reduce the high sidewall peeling stress of pad pattern 114 and increase the contact area between pad pattern 114 and dielectric layer 112, dielectric layer 114, which reduces the risk of delamination of pad pattern 114. In some embodiments, each of holes 1143 (i.e., dielectric plug 1161 / extension portion) may be square, rectangular, circular, elliptical, triangular, or irregular in shape. Any suitable shape may be used to reduce the sidewall peeling stress of the pad pattern 114 .

[0062] In one embodiment, the pad opening 1121 is circular in shape. In such an embodiment, the holes 1143 may be arranged adjacent to the outer circumference (e.g., the peripheral portion 1142) of the pad pattern 114 and configured as a portion of a non-continuous circle. In addition, to ensure that the peripheral portion 1142 remains physically and electrically connected to the pad portion 1141, the connecting portion 1144 of the peripheral portion 1142 separates the holes 1143 from each other.

[0063] Reference Figure 4 , after the second dielectric layer 116 is formed, one or more rewiring circuit layers and one or more dielectric layers may be alternately formed on the carrier 200 so that the rewiring structure 110 is formed on the carrier 200. In some embodiments, the rewiring structure 110 may be formed by the following operations: continuously depositing a conductive layer; patterning the conductive layer to form a rewiring circuit; partially covering the rewiring circuit; and filling the gaps between the rewiring circuits with a dielectric layer, etc. The material of the rewiring circuit (including the pad pattern 114) may include a metal or a metal alloy, including aluminum, copper, tungsten and / or alloys thereof. The dielectric layer (including the dielectric layer 112, the dielectric layer 116) may be formed of a dielectric material, such as an oxide, a nitride, a carbide, a carbonitride, a combination thereof and / or multiple layers thereof. However, the number of dielectric layers and the number of rewiring circuit layers are not limited in the present disclosure.

[0064] In some embodiments, an encapsulated semiconductor device (eg, as shown in FIG. Figure 5B The encapsulated semiconductor device 125' is shown in Figure 7In some embodiments, encapsulated semiconductor device 125' / encapsulated semiconductor device 125 may be a reconstituted wafer including a plurality of semiconductor devices 120 encapsulated by encapsulation material 130. With this arrangement, a plurality of semiconductor packages may be formed simultaneously for batch production. For the sake of brevity and clarity, Figures 1 to 10 The manufacturing process of one of the semiconductor packages (such as semiconductor package 100) is described in FIG. Figure 5 1 and 2, one of the semiconductor devices 120 disposed on the redistribution structure 110 is illustrated. The formation of the encapsulated semiconductor device 125' / encapsulated semiconductor device 125 can be described as follows.

[0065] Optionally, a plurality of through holes (not shown) may be provided on the carrier 200, and the through holes may surround at least one device region where the semiconductor device 120 / semiconductor device 120' is to be provided. In the present embodiment, the through holes are formed on the redistribution structure 110 positioned on the carrier 200 and electrically connected to the redistribution structure, but the present disclosure is not limited thereto. In other embodiments, the through holes may be pre-formed and then placed on the carrier 200.

[0066] Reference Figure 5 In some embodiments, at least one semiconductor device 120' (one semiconductor device 120' is illustrated, but not limited thereto) may be disposed on the carrier 200 and within or between the through holes (if any). Figure 5 , the semiconductor package 100 may include one semiconductor device 120'. In other embodiments, the semiconductor package 100 may include more than one semiconductor device as a group, and the through hole may surround the group of semiconductor devices. In some embodiments, the semiconductor device 120' is electrically connected to the redistribution structure 110. In one embodiment, the semiconductor device 120' may be mounted on the redistribution structure 110 using, for example, surface mounting technology through a variety of electrical terminals 123 such as conductive bumps and a variety of solder materials 126, but any suitable mounting method may be used instead.

[0067] In some embodiments, the semiconductor device 120' may be a logic device die including logic circuits therein. In some exemplary embodiments, the semiconductor device 120' is a die designed for mobile applications and may include, for example, a power management integrated circuit (PMIC) die and a transceiver (TRX) die. It should be noted that more or fewer semiconductor devices 120' may be placed above the rewiring structure 110 and flush with each other.

[0068] In some exemplary embodiments, each of the semiconductor devices 120' may include a substrate 121, a plurality of active devices (not shown), and a plurality of contact pads 122. The contact pads 122 (e.g., copper pads) may be formed on an active surface (e.g., a lower surface) of the semiconductor device 120' and electrically coupled to the contact pads 122 on the substrate 121. The substrate 121 may include an active layer of a doped or undoped bulk silicon or silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a semiconductor material layer such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that may be used include multi-layer substrates, gradient substrates, or hybrid orientation substrates. In some embodiments, the semiconductor device 120' may be a die that may contain a plurality of transistors and other active and passive devices that perform a variety of electrical functions. Active devices may be formed in or on substrate 121 using any suitable method.

[0069] In some embodiments, a material such as a polymer is then applied between the semiconductor device 120' and the rewiring structure 110 as an underfill 124. The underfill 124 is typically a polymer, such as an epoxy. As heat is applied to the semiconductor device 120' and / or the rewiring structure 110, capillary action can be used to cause the underfill 124 to flow between the semiconductor device 120' and the rewiring structure 110. When formed from a material such as a polymer epoxy, the underfill 124 is then typically cured, thereby hardening the polymer. The cured underfill 124 surrounds the electrical terminal 123 and is used to protect the electrical terminal 123 and the connection between the semiconductor device 120' and the rewiring structure 110, as well as to support the semiconductor device 120' on the rewiring structure 110.

[0070] Reference Figure 5AIn some embodiments, the semiconductor device 120' and the through-hole (if any) on the redistribution structure 110 are encapsulated by the encapsulation material 130'. In other words, the encapsulation material 130' is formed on the redistribution structure 110 to encapsulate the semiconductor device 120' and the through-hole (if any). In some embodiments, the encapsulation material 130' is in contact with the redistribution structure 110. The encapsulation material 130' may include a molding compound resin, such as polyimide, PPS, PEEK, PES, a heat-resistant crystalline resin, a combination of these resins, or the like. The encapsulation of the semiconductor device 120' and the through-hole (if any) may be performed in a molding device (not shown). The encapsulation material 130' may be placed in a mold cavity of the molding device, or may be injected into the mold cavity through an injection port.

[0071] Once the encapsulation material 130' is placed into the mold cavity so that the encapsulation material 130' encapsulates the semiconductor device 120' and the through-holes (if present), the encapsulation material 130' can be cured to harden the encapsulation material 130' for optimal protection. In addition, an initiator and / or a catalyst can be included in the encapsulation material 130' to better control the curing process. In some embodiments, the top surface of the encapsulation material 130' can be higher than the back surface of the semiconductor device 120'. That is, the encapsulation material 130' covers the back surface of the semiconductor device 120'.

[0072] Reference Figure 5B , a thinning process may be performed on the encapsulation material 130' to expose or thin the back surface of the semiconductor device 120'. The thinning process may be, for example, a mechanical grinding or CMP process, in which chemical etchants and abrasives are used to react the encapsulation material 130' with the semiconductor device 120' and grind away the encapsulation material and the semiconductor device. The resulting structure is shown in Figure 5B After the thinning process is performed, Figure 5B As shown in , the back surface of the semiconductor device 120 is substantially flush with the upper surface of the encapsulation material 130. However, while the CMP process described above is presented as an illustrative embodiment, it is not intended to be limiting. Any other suitable removal process may be used alternatively to thin the encapsulation material 130 and the semiconductor device 120. For example, a series of chemical etches may be used alternatively. This process and any other suitable process may be used alternatively to thin the encapsulation material 130 and the semiconductor device 120, and all such processes are fully included within the scope of the embodiments.

[0073] Therefore, it will include Figure 5BThe resulting structure of the semiconductor device 120, the through-via (if present), and the encapsulation material 130 shown in is referred to as an encapsulated semiconductor device 125', which may have a wafer form in the process. Therefore, in the encapsulated semiconductor device 125', the semiconductor device 120 is disposed on the die region of the rewiring structure 110, the through-via (if present) extends through the encapsulated semiconductor device 125' outside the die region, and the encapsulation material 130 encapsulates the semiconductor device 120 and the through-via (if present). In other words, the encapsulation material 130 encapsulates the semiconductor device 120 therein, and the through-via (if present) extends through the encapsulation material 130.

[0074] Reference Figure 6 Alternatively, before the encapsulation material 130 is formed on the redistribution structure 110, the substrate 140 is mounted on the semiconductor device 120 by a plurality of conductive bonding members 142 disposed around the semiconductor device 120. In other words, in an alternative embodiment, Figure 5 Follow the steps shown in the following order: Figure 6 Steps shown instead of execution Figure 5A and Figure 5B The steps shown. The substrate 140 can be mounted on the rewiring structure 110 by surface mounting technology. In some embodiments, the substrate 140 can be, for example, a doped or undoped silicon substrate, or an active layer of a silicon-on-insulator (SOI) substrate, and can act as an insert used as an intermediate substrate. However, the substrate 140 can alternatively be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that can provide suitable protection and / or interconnection functions. These materials and any other suitable materials can alternatively be used for the substrate 140. In other embodiments, the substrate 140 can be a semiconductor device, a semiconductor package, a heat sink, or any combination thereof. The conductive bonding member 142 connected to the rewiring structure 110 can be, for example, a solder ball formed by reflow. However, a copper column or a gold column can also be used as a conductive bonding member 142 by reflowing with a soldering material.

[0075] Reference Figure 7 In the embodiment of the present invention, the encapsulation material 130 encapsulates the semiconductor device 120 and the conductive bonding member 142, and fills the gap between the semiconductor device 120 and the substrate 140. The encapsulation material 130 may include a molding compound resin, such as polyimide, PPS, PEEK, PES, a heat-resistant crystalline resin, a combination of these resins, or the like. In some embodiments, the encapsulation material 130 may be an underfill, which is typically a polymer, such as an epoxy resin.

[0076] Throughout this description, we will include Figure 7The resulting structure of the semiconductor device 120, substrate 140, conductive bonding member 142, and encapsulation material 130 shown in the figure is referred to as an encapsulated semiconductor device 125, which may have a wafer form in the process. Therefore, in the encapsulated semiconductor device 125, the semiconductor device 120 is mounted on the rewiring structure 110, and the substrate 140 is mounted above the semiconductor device 120 through the conductive bonding member 142. The encapsulation material 130 encapsulates the semiconductor device 120 and the conductive bonding member 142, and fills the gap between the semiconductor device 120 and the substrate 140. The rewiring structure 110 is disposed above the encapsulated semiconductor device 125 and is electrically connected to the semiconductor device 120. Throughout the description, the semiconductor device 125 will be included as follows. Figure 7 The resulting structure of encapsulated semiconductor devices 125 and redistribution structure 110 shown in FIG. 1 is referred to as a reconstituted wafer.

[0077] In some embodiments, after the encapsulated semiconductor device 125 is formed on the redistribution structure 110, another carrier 300 may be disposed on the substrate 140. In other words, the carrier 300 and the carrier 200 are disposed on two opposite sides of the reconstructed wafer, respectively. In some embodiments, the reconstructed wafer with the carrier 200 may be flipped over and disposed on the carrier 300 by attaching the substrate 140 to the carrier 300. The carrier 300 carrying the reconstructed wafer with the carrier 200 may further include a frame structure (not shown), which may be a metal ring intended to provide support and stability to the structure during and after the sequential peeling process. In some embodiments, the reconstructed wafer with the carrier 200 is attached to the frame structure using, for example, UV tape, but any other suitable adhesive or attachment may be used instead.

[0078] Reference Figure 8 , removing (e.g., peeling off) the carrier 200 from the reconstituted wafer on the carrier 300. The carrier 200 may be peeled off using, for example, a thermal process to change the adhesive properties of the adhesive layer 210. In one embodiment, an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser is used to irradiate and heat the adhesive layer 210 until the adhesive layer 210 loses at least some of its adhesive properties. Once performed, then Figure 8 As shown in FIG. , the carrier 200 and the adhesive layer 210 can be physically separated and removed from the redistribution structure 110 of the reconstructed wafer.

[0079] After removing the carrier 200, the lower surface of the pad pattern 114 is exposed for subsequent electrical connection. In some embodiments, the lower surface of the pad pattern 114 is substantially coplanar with the lower surface of the dielectric layer 112. In such embodiments, the lower surface of the pad pattern 114 is the lower surface of the pad portion 1141, and the lower surface of the dielectric layer 112 is the surface away from the encapsulated semiconductor device 125.

[0080] Reference Fig. 9 ,like Fig. 9 As shown in , the resulting structure after removing the carrier 200 can then be flipped. Subsequently, at least one electronic component (eg, a plurality of electrical connectors 150 and / or at least one passive device 160) can be mounted on the pad portion 1141 (now Fig. 9 On the lower surface of the electrical connector 150 (facing upward). In some embodiments, the electrical connector 150 includes a solder bump. In some embodiments, the electrical connector 150 may further include a metal column. The passive device 160 may be an integrated passive device (IPD). In an embodiment of the present invention, the rewiring structure 110 includes a plurality of pad patterns 114. Some of the pad portions 1141 of the pad pattern 114 are mounted with the electrical connector 150, and at least one of the pad portions 1141 of the pad pattern 114 is mounted with the passive device 160. With this arrangement, the pad portion 1141 can act as an under bump metallurgy (UBM) layer, and thus an additional UBM layer can be omitted. In some embodiments, the formation of the electrical connector 150 may include placing a solder ball on the pad portion 1141, and then reflowing the solder ball. In an alternative embodiment, the formation of the electrical connector 150 may include performing a plating process to form a solder material on the pad portion 1141, and then reflowing the plated solder material. For example, the electrical connector 150 can be a contact bump, such as a microbump or a controlled collapse chip connection (C4) bump, and can include a material such as tin or other suitable materials such as silver or copper. In one embodiment in which the electrical connector 150 is a tin solder bump, the electrical connector 150 can be formed by initially forming a tin layer by any suitable method, such as evaporation, electroplating, printing, solder transfer, ball planting, etc. Once the tin layer has been formed on the structure, reflow can be performed to form the material into the desired bump shape. In some embodiments, the electrical connector 150 can be a metal column, and the formation of the metal column can include plating using a photoresist. The passive device 160 can be manufactured using standard wafer manufacturing techniques such as thin film processing and photolithography processing, and can be mounted on another pad portion 1141 by, for example, flip chip bonding.

[0081] Throughout this description, we will include Fig. 9 The resulting structure of the rewiring structure 110, encapsulated semiconductor device 125, substrate 140 (if present), and electronic components 150 / 160 shown in FIG. 1 is referred to as a semiconductor package, which may be in wafer form in the process.

[0082] Reference Fig.10 , peeling the carrier 300 from the substrate 140 of the semiconductor package. In one embodiment, the carrier 300 is peeled from the substrate 140 by, for example, irradiating the UV adhesive on the carrier 300 with UV radiation, and once the UV adhesive has lost or reduced its adhesiveness, the substrate 140 can be physically separated from the carrier 300.

[0083] In some embodiments, the semiconductor package is in the form of a wafer during the process. Therefore, once the carrier 300 is peeled off, a singulation process is performed on the semiconductor package in the form of a wafer to form a plurality of semiconductor packages 100. In one embodiment, the singulation process can be performed by using a saw blade (not shown) to cut through the semiconductor package in the form of a wafer, thereby separating one portion (for example, including a semiconductor device 120 and a substrate 140) from another portion to form a plurality of semiconductor packages 100. Fig.10 . However, as one of ordinary skill in the art will appreciate, using a saw blade to singulate the semiconductor packages 100 is merely an illustrative embodiment and is not intended to be limiting. Alternative methods for singulating the semiconductor packages 100 may alternatively be used, such as using one or more etches to separate the semiconductor packages 100. These methods and any other suitable methods may alternatively be used to singulate the semiconductor packages 100. In the present embodiment, each of the semiconductor packages 100 may be an integrated fan-out package.

[0084] Therefore, by forming the pad pattern 114 of the rewiring structure 110 of the semiconductor package 100 with the holes 1143 as described herein, a more reliable device can be obtained. Specifically, by forming the holes 1143 as described in any of the embodiments herein, the stress on the sidewalls of the pad pattern 114 caused during thermal cycles of the testing, manufacturing and operation processes can be reduced or made less concentrated. In this way, delamination, peeling and cracking that may otherwise be caused by these stresses can be reduced or eliminated, resulting in a greater yield and a more reliable device.

[0085] Fig.13 A cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. Fig.14 illustrate Fig.13 A top view of the pad pattern of the semiconductor package in FIG. Fig.13 and Fig.14 The pad pattern 114a of the semiconductor package 100a in the embodiment of the present invention contains the same Figure 2 , Fig.11 as well as Fig.12 The pad pattern 114 of the disclosed semiconductor package 100 has many features that are the same or similar. For the purpose of clarity and simplicity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals refer to the same or similar components. Fig.13 and Fig.14 The pad pattern 114a of the semiconductor package 100a is similar to that shown in FIG. Figure 2 , Fig.11 as well as Fig.12 The main differences between the pad patterns 114 of the semiconductor packages 100 in FIG. 1 and FIG. 2 are described as follows.

[0086] In some embodiments, the pad pattern 114a is rectangular in shape. For example, the pad portion 1141a and the peripheral portion 1142a of the pad pattern 114a are both rectangular in shape. In addition, each of the holes 1143a may be as shown in FIG. Fig.14 . In some alternative embodiments, hole 1143a may be in a different shape. Therefore, pad opening 1121 is a rectangular opening, and rectangular pad portion 1141a extends into rectangular pad opening 1121 to be coplanar with the lower surface of dielectric layer 112. Hole 1143a surrounds rectangular pad portion 1141a and is positioned within peripheral portion 1142a. In such an embodiment, passive device 160 may be directly mounted on rectangular pad portion 1141a by welding material 162. It should be noted that in the present embodiment, pad portion 1141a and peripheral portion 1142a are both rectangular in shape. However, in other embodiments, pad portion 1141a and peripheral portion 1142a may also be square, rectangular, circular, elliptical, triangular or irregular in shape. The present disclosure is not limited thereto. In some embodiments, the semiconductor package 100a may further include an underfill 170 that may surround the solder material 162 and fill the gap between the passive device 160 and the redistribution structure 110a, thereby enhancing the bonding strength, redistributing the thermal mismatch load, and protecting the solder connections.

[0087] Fig.15 A cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. Fig.16 illustrate Fig.15 A top view of the pad pattern of the semiconductor package in FIG. Fig.15 and Fig.16 The pad pattern 114b of the semiconductor package 100b contains the previously combined Fig.13 and Fig.14The pad pattern 114a of the disclosed semiconductor package 100a has many features that are the same or similar. For the purpose of clarity and simplicity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals refer to the same or similar components. Fig.15 and Fig.16 The pad pattern 114b of the semiconductor package 100b is similar to that shown in FIG. Fig.13 and Fig.14 The main differences between the pad patterns 114a of the semiconductor package 100a in FIG. 1 and FIG. 1 are described as follows.

[0088] In some embodiments, the at least one pad portion mentioned above may include a plurality of pad portions 1141b embedded in the first dielectric layer 112b. That is, the pad pattern 114b includes a plurality of (rectangular) pad portions 1141b, and the dielectric layer 112b includes a plurality of (rectangular) pad openings 1121b. The pad portions 1141b extend into the pad openings 1121b, respectively, and the (rectangular) holes 1143b (i.e., dielectric plugs / extensions) surround the periphery of the pad portions 1141b. In the present embodiment, no hole 1143b is provided between two adjacent pad portions 1141b to separate the pad portions 1141b. In other words, the pad pattern 114b further includes at least one connecting portion 1144b provided on the upper surface of the dielectric layer 112b. The connecting portion 1144b connects any two adjacent pad portions 1141b in the pad openings 1121b extending into the pad portions 1141b. As such, the pad portions 1141b are connected to each other through the connection portion 1144b and form a continuous metal block. In such an embodiment, the passive device 160 may be mounted on the pad portion 1141b by the soldering material 162. In some embodiments, the semiconductor package 100b may further include an underfill 170, which may surround the soldering material 162 and fill the gap between the passive device 160 and the redistribution structure 110b, thereby enhancing the bonding strength, redistributing the thermal mismatch loading, and protecting the solder connection.

[0089] Fig.17 A cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. Fig.18 illustrate Fig.17 A top view of the pad pattern of the semiconductor package in FIG. Fig.17 and Fig.18 The pad pattern 114c of the semiconductor package 100c contains the previously combined Fig.13 and Fig.14The pad pattern 114a of the disclosed semiconductor package 100a has many features that are the same or similar. For the purpose of clarity and simplicity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals refer to the same or similar components. Fig.17 and Fig.18 The pad pattern 114c of the semiconductor package 100c is similar to that shown in FIG. Fig.13 and Fig.14 The main differences between the pad patterns 114a of the semiconductor package 100a in FIG. 1 and FIG. 1 are described as follows.

[0090] In some embodiments, the at least one pad portion described above may include a plurality of pad portions 1141c embedded in the first dielectric layer 112c. That is, the pad pattern 114c includes a plurality of (rectangular) pad portions 1141c (illustrated as three but not limited thereto), and the dielectric layer 112c includes a plurality of (rectangular) pad openings 1121c (illustrated as three but not limited thereto). The pad portions 1141c extend into the pad openings 1121c, respectively, and the (rectangular) holes 1143c (i.e., dielectric plugs / extensions) surround each of the pad portions 1141c. In the present embodiment, some of the holes 1143c are disposed between two adjacent pad portions 1141c to separate the pad portions 1141c from each other. In other words, the peripheral portion 1142c surrounds each of the pad portions 1141c, so that the holes 1143c extending through the peripheral portion 1142c surround each of the pad portions 1141c accordingly. In addition, the peripheral portion 1142c may further include a plurality of cutouts 1145c disposed along an edge of the peripheral portion 1142c and positioned between any two adjacent pad portions 1141c. In such an embodiment, the passive device 160 may be mounted on the pad portion 1141c by the solder material 162. In some embodiments, the semiconductor package 100c may further include an underfill 170 that may surround the solder material 162 and fill a gap between the passive device 160 and the redistribution structure 110c, thereby enhancing the bonding strength, redistributing the thermal mismatch load, and protecting the solder connection.

[0091] Fig.19 A cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. Fig. 20 illustrate Fig.19 A top view of the pad pattern of the semiconductor package in FIG. Fig.19 and Fig. 20 The pad pattern 114d of the semiconductor package 100d contains the previously combined Fig.13 and Fig.14The pad pattern 114a of the disclosed semiconductor package 100a has many features that are the same or similar. For the purpose of clarity and simplicity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals refer to the same or similar components. Fig.19 and Fig. 20 The pad pattern 114d of the semiconductor package 100d is similar to that shown in FIG. Fig.13 and Fig.14 The main differences between the pad patterns 114a of the semiconductor package 100a in FIG. 1 and FIG. 1 are described as follows.

[0092] In some embodiments, the (rectangular) pad portion 1141d further includes a plurality of pad recesses 1146d (illustrated as three, but not limited thereto) extending through the pad portion 1141d and disposed in the (rectangular) pad opening 1121d. The hole 1143d surrounds the periphery of the pad portion 1141d. The pad portion 1141d extends into the pad opening 1121d and is divided into a plurality of connection portions by the pad recesses 1146d. In this embodiment, the (rectangular) hole 1143c surrounds the periphery of the pad portion 1141d. In addition, the peripheral portion 1142d may further include a plurality of cut-outs 1145d disposed along the edge of the peripheral portion 1142d and disposed corresponding to the pad recesses 1146d. In such an embodiment, the passive device 160 may be mounted on the connection portion of the pad portion 1141c defined by the pad recesses 1146d. In some embodiments, the semiconductor package 100d may further include an underfill 170 that may surround the solder material 162 and fill the gap between the passive device 160 and the redistribution structure 110d, thereby enhancing the bonding strength, redistributing the thermal mismatch load, and protecting the solder connections.

[0093] By forming a pad pattern with holes in different arrangements as described herein but not limited thereto, various ratios of the volume of the holes to the volume of the pad pattern can be designed or modified according to the actual needs of the product. In turn, a more reliable device can be obtained. Specifically, by forming holes as described in any of the embodiments herein, the stress on the sidewalls of the pad pattern caused during thermal cycles of the testing, manufacturing, and operating processes can be reduced or made less concentrated. In this way, delamination, peeling, and cracking that may otherwise be caused by these stresses can be weakened or eliminated, resulting in a greater yield and a more reliable device. In addition, the electronic device can be mounted on the pad portion without forming any UBM layer.

[0094] Based on the above discussion, it can be seen that the present disclosure provides various advantages. However, it should be understood that not all advantages must be discussed herein, other embodiments may provide different advantages, and specific advantages are not required for all embodiments.

[0095] According to some embodiments of the present disclosure, a device includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extension portions extending through the peripheral portion.

[0096] According to some embodiments of the present disclosure, the peripheral portion is disposed on an upper surface of the first dielectric layer, and the at least one pad portion is connected to the peripheral portion and extends from the upper surface to the lower surface of the first dielectric layer.

[0097] According to some embodiments of the present disclosure, the at least one pad portion is integrally formed with the peripheral portion.

[0098] According to some embodiments of the present disclosure, a sum of layout areas of the plurality of extension portions is 3% to 60% of a sum of layout areas of the at least one pad portion and the peripheral portion.

[0099] According to some embodiments of the present disclosure, the plurality of extension portions surround a periphery of the at least one pad portion.

[0100] According to some embodiments of the present disclosure, the at least one pad portion includes a plurality of pad portions embedded in the first dielectric layer, the peripheral portion surrounds the plurality of pad portions, and the plurality of extension portions surround each of the plurality of pad portions.

[0101] According to some embodiments of the present disclosure, the pad portion includes a plurality of pad recesses extending through the at least one pad portion, and the plurality of extension portions surround a periphery of the at least one pad portion.

[0102] According to some embodiments of the present disclosure, a semiconductor package includes an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulation material. The redistribution structure extends over the encapsulated semiconductor device and is electrically connected to the semiconductor device. The redistribution structure includes a dielectric layer, a pad pattern, and a plurality of dielectric plugs. The pad pattern is disposed on the dielectric layer, wherein the pad pattern includes at least one pad portion embedded in the dielectric layer, and a lower surface of the pad pattern is substantially coplanar with a lower surface of the dielectric layer away from the encapsulated semiconductor device. A plurality of dielectric plugs extend through the pad pattern and surround the pad portion.

[0103] According to some embodiments of the present disclosure, the pad pattern further includes a peripheral portion surrounding the at least one pad portion, and the plurality of dielectric plugs extend through the peripheral portion.

[0104] According to some embodiments of the present disclosure, the peripheral portion is disposed on the upper surface of the dielectric layer, the at least one pad portion extends from the upper surface of the dielectric layer to the lower surface, and the lower surface of the at least one pad portion is coplanar with the lower surface of the dielectric layer.

[0105] According to some embodiments of the present disclosure, the at least one pad portion includes a plurality of pad portions embedded in the dielectric layer, and the plurality of dielectric plugs surround peripheries of the plurality of pad portions.

[0106] According to some embodiments of the present disclosure, the at least one pad portion includes a plurality of pad portions, and the plurality of dielectric plugs surround each of the plurality of pad portions.

[0107] According to some embodiments of the present disclosure, the pad portion includes a plurality of pad recesses extending through the at least one pad portion, and the plurality of dielectric plugs surround a periphery of the at least one pad portion.

[0108] According to some embodiments of the present disclosure, the semiconductor package further includes an electronic component mounted on the lower surface of the pad pattern.

[0109] According to some embodiments of the present disclosure, the electronic component includes an electrical connector bump or a passive device.

[0110] According to some embodiments of the present disclosure, the encapsulated semiconductor device further includes: a plurality of conductive bonding members disposed around the semiconductor device; and a substrate disposed above the semiconductor device through the conductive bonding members, wherein the encapsulation material encapsulates the conductive bonding members.

[0111] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor package includes the following steps. A redistribution structure is formed on a carrier, wherein forming the redistribution structure on the carrier includes the following steps: forming a first dielectric layer on the carrier, wherein the first dielectric layer includes a pad opening; forming a pad pattern on the first dielectric layer, wherein the pad pattern extends into the pad opening and includes a plurality of holes; and forming a second dielectric layer on the pad pattern, wherein the second dielectric layer fills the holes. An encapsulated semiconductor device is formed on the redistribution structure. The carrier is removed to reveal a lower surface of the pad pattern.

[0112] According to some embodiments of the present disclosure, the method of manufacturing a semiconductor package further includes: mounting electronic components on the lower surface of the pad pattern.

[0113] According to some embodiments of the present disclosure, forming the encapsulated semiconductor device on the redistribution structure includes: disposing a semiconductor device on the redistribution structure; and forming an encapsulation material on the redistribution structure to encapsulate the semiconductor device.

[0114] According to some embodiments of the present disclosure, forming the encapsulated semiconductor device on the redistribution structure includes: before the encapsulation material is formed on the redistribution structure, mounting a substrate above the semiconductor device via a plurality of conductive bonding members, wherein the encapsulation material encapsulates the conductive bonding members.

[0115] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or obtaining the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: a first dielectric layer; A pad pattern is disposed on the first dielectric layer and comprises: at least one pad portion embedded in the first dielectric layer, wherein a lower surface of the at least one pad portion is coplanar with a lower surface of the first dielectric layer; and a peripheral portion surrounding the at least one pad portion and including a plurality of holes; a second dielectric layer disposed on the pad pattern, the plurality of holes being filled with portions of the second dielectric layer to form a plurality of extension portions extending through the peripheral portion; and An electrical connector bump is mounted on and in contact with the lower surface of the at least one pad portion. 2 . The semiconductor package according to claim 1 , wherein the peripheral portion is disposed on an upper surface of the first dielectric layer, and the at least one pad portion is connected to the peripheral portion and extends from the upper surface to the lower surface of the first dielectric layer. 3 . The semiconductor package according to claim 1 , wherein the at least one pad portion is integrally formed with the peripheral portion. 4 . The semiconductor package according to claim 1 , wherein a sum of layout areas of the plurality of extension portions is 3% to 60% of a sum of layout areas of the at least one pad portion and the peripheral portion. 5 . The semiconductor package according to claim 1 , wherein the plurality of extension portions surround a periphery of the at least one pad portion. 6 . The semiconductor package according to claim 1 , wherein the at least one pad portion comprises a plurality of pad portions embedded in the first dielectric layer, the peripheral portion surrounds the plurality of pad portions, and the plurality of extension portions surround each of the plurality of pad portions. 7 . The semiconductor package according to claim 1 , wherein the pad portion comprises a plurality of pad recesses extending through the at least one pad portion, and the plurality of extension portions surround a periphery of the at least one pad portion.

8. A semiconductor package, comprising: Encapsulated semiconductor devices, including semiconductor devices encapsulated by encapsulation materials; as well as a redistribution structure extending over the encapsulated semiconductor device and electrically connected to the semiconductor device, wherein the redistribution structure comprises: Dielectric layer; a pad pattern disposed on the dielectric layer and comprising a plurality of holes distributed in a peripheral portion of the pad pattern, wherein the pad pattern comprises at least one pad portion embedded in the dielectric layer, and a lower surface of the pad pattern is coplanar with a lower surface of the dielectric layer away from the encapsulated semiconductor device; and a second dielectric layer covering the peripheral portion of the pad pattern, wherein the plurality of holes are filled with portions of the second dielectric layer to form a plurality of dielectric plugs extending through the pad pattern and surrounding the at least one pad portion; and The electrical connector bump is mounted on the lower surface of the pad pattern and contacts the lower surface. 9 . The semiconductor package of claim 8 , wherein the pad pattern further includes a peripheral portion surrounding the at least one pad portion, and the plurality of dielectric plugs extend through the peripheral portion.

10. The semiconductor package of claim 9, wherein the peripheral portion is disposed on an upper surface of the dielectric layer, the at least one pad portion extends from the upper surface of the dielectric layer to the lower surface, and a lower surface of the at least one pad portion is coplanar with the lower surface of the dielectric layer. 11 . The semiconductor package according to claim 9 , wherein the at least one pad portion comprises a plurality of pad portions embedded in the dielectric layer, and the plurality of dielectric plugs surround peripheries of the plurality of pad portions. 12 . The semiconductor package of claim 9 , wherein the at least one pad portion comprises a plurality of pad portions, and the plurality of dielectric plugs surround each of the plurality of pad portions. 13 . The semiconductor package of claim 9 , wherein the pad portion comprises a plurality of pad recesses extending through the at least one pad portion, and the plurality of dielectric plugs surround a periphery of the at least one pad portion.

14. The semiconductor package of claim 8, wherein the encapsulated semiconductor device further comprises: A plurality of conductive bonding members are arranged around the semiconductor device; as well as A substrate is disposed above the semiconductor device and connected to the semiconductor device through the conductive bonding member, wherein the encapsulation material encapsulates the conductive bonding member.

15. A method for manufacturing a semiconductor package, comprising: A redistribution structure is formed on a carrier, wherein forming the redistribution structure on the carrier comprises: forming a first dielectric layer on the carrier, wherein the first dielectric layer includes a pad opening; forming a pad pattern on the first dielectric layer, wherein the pad pattern extends into the pad opening and includes a peripheral portion surrounding the pad opening and a plurality of holes distributed in the peripheral portion of the pad pattern; and forming a second dielectric layer on the pad pattern, wherein the second dielectric layer fills the plurality of holes; forming an encapsulated semiconductor device on the redistribution structure; and The carrier is removed to expose the lower surface of the pad pattern.

16. The method for manufacturing a semiconductor package according to claim 15, further comprising: Electronic components are mounted on the lower surface of the pad pattern.

17. The method of manufacturing a semiconductor package according to claim 15, wherein forming the encapsulated semiconductor device on the redistribution structure comprises: disposing a semiconductor device on the redistribution structure; as well as An encapsulation material is formed on the redistribution structure to encapsulate the semiconductor device.

18. The method of manufacturing a semiconductor package according to claim 17, wherein forming the encapsulated semiconductor device on the redistribution structure comprises: Before the encapsulation material is formed on the redistribution structure, a substrate is mounted above the semiconductor device via a plurality of conductive bonding members, wherein the encapsulation material encapsulates the conductive bonding members.

19. A semiconductor package, comprising: a first dielectric layer; A pad pattern is disposed on the first dielectric layer and includes a plurality of holes, and the plurality of holes are distributed in a peripheral portion of the pad pattern; a second dielectric layer covering the peripheral portion of the pad pattern, wherein the plurality of holes are filled with portions of the second dielectric layer, wherein a lower surface of the pad pattern is coplanar with a lower surface of the first dielectric layer; as well as The electrical connector bump is mounted on the lower surface of the pad pattern and contacts the lower surface. 20 . The semiconductor package of claim 19 , wherein the electrical connector bump and the second dielectric layer are disposed on opposite sides of the first dielectric layer. 21 . The semiconductor package according to claim 19 , wherein the pad pattern portion covers a portion of an upper surface of the first dielectric layer and extends into a pad opening defined by the first dielectric layer. 22 . The semiconductor package according to claim 19 , wherein the pad pattern is distributed in a bottom area of ​​a pad opening defined by the first dielectric layer, and the pad pattern covers a sidewall of the pad opening and a portion of an upper surface of the first dielectric layer.

23. The semiconductor package according to claim 19, wherein the pad pattern includes a pad portion distributed in a bottom area of ​​a pad opening defined by the first dielectric layer, the pad portion of the pad pattern covers a side wall of the pad opening and an outer portion of the pad portion covers a portion of an upper surface of the first dielectric layer. 24 . The semiconductor package according to claim 19 , wherein the second dielectric layer comprises a protruding portion covered by a pad portion of the pad pattern, and the protruding portion protrudes beyond the electrical connector bump.

25. A semiconductor package, comprising: A first dielectric layer including a pad opening; a pad pattern disposed on the first dielectric layer and extending into the pad opening of the first dielectric layer, wherein a lower surface of the pad pattern is coplanar with a lower surface of the first dielectric layer, and the pad pattern includes a plurality of holes extending through the pad pattern; a second dielectric layer disposed on the pad pattern and including a plurality of extension portions filling the plurality of holes of the pad pattern; as well as An electrical connector bump is on the lower surface of the pad pattern.

26. The semiconductor package according to claim 25, wherein the pad pattern comprises: a first portion formed in a bottom region of the pad opening and covering a sidewall of the pad opening; as well as The second portion covers a portion of the upper surface of the first dielectric layer. 27 . The semiconductor package according to claim 26 , wherein the plurality of holes of the pad pattern are distributed in a second portion of the pad pattern, and the plurality of extending portions of the second dielectric layer are in contact with the upper surface of the first dielectric layer. 28 . The semiconductor package of claim 27 , wherein the plurality of extended portions of the second dielectric layer surround a periphery of the first portion. 29 . The semiconductor package according to claim 27 , wherein the first portion includes a plurality of first portions, and the plurality of extending portions of the second dielectric layer surround each of the plurality of first portions. 30 . The semiconductor package according to claim 26 , wherein the plurality of holes of the pad pattern are distributed in the first portion of the pad pattern, and lower surfaces of the plurality of extension portions of the second dielectric layer are coplanar with the lower surface of the pad pattern. 31 . The semiconductor package according to claim 26 , wherein the second portion of the pad pattern surrounds the first portion of the pad pattern.

32. The semiconductor package according to claim 26, wherein the first portion and the second portion are integrally formed.

33. A semiconductor package, comprising: Rewiring structure, including: a first dielectric layer; a pad pattern, comprising a first portion buried in the first dielectric layer and a second portion connected to the first portion, wherein a lower surface of the first portion is coplanar with a lower surface of the first dielectric layer; and a plurality of dielectric plugs extending through the first portion and the second portion of the pad pattern; An electrical connector protrusion is on the lower surface of the first portion.

34. The semiconductor package of claim 33, wherein the second portion of the pad pattern surrounds the first portion of the pad pattern and is formed on an upper surface of the first dielectric layer, and the first portion of the pad pattern extends from the upper surface of the first dielectric layer to the lower surface of the first dielectric layer.

35. The semiconductor package according to claim 33, wherein the first portion and the second portion are integrally formed.

36. The semiconductor package according to claim 33, further comprising: A semiconductor device, on the rewiring structure: and An encapsulation material encapsulates the semiconductor device.

37. The semiconductor package according to claim 36, further comprising: A substrate is disposed above the semiconductor device, wherein the substrate is connected to the redistribution structure via a plurality of conductive bonding members disposed around the semiconductor device, and the encapsulation material encapsulates the plurality of conductive bonding members.

38. The semiconductor package of claim 36, wherein the semiconductor device is disposed on the redistribution structure via a plurality of electrical terminals between the semiconductor device and the redistribution structure.

39. The semiconductor package according to claim 38, further comprising: The bottom filling glue is disposed between the semiconductor device and the redistribution structure, wherein the bottom filling glue surrounds the plurality of electrical terminals.

40. A semiconductor package, comprising: Rewiring structure, including: A first dielectric layer including a pad opening; a pad pattern disposed on the first dielectric layer, wherein the pad pattern extends into the pad opening and includes a plurality of holes extending through the pad pattern; and a second dielectric layer on the pad pattern, wherein the second dielectric layer fills the plurality of holes; an encapsulated semiconductor device on the redistribution structure; and An electronic component is disposed on a lower surface of the pad pattern away from the encapsulated semiconductor device.

41. The semiconductor package according to claim 40, wherein the electronic component is in contact with the lower surface of the pad pattern.

42. The semiconductor package of claim 40, wherein the electronic component comprises a solder bump.

43. The semiconductor package according to claim 40, wherein the electronic component comprises a passive device and a solder disposed between the passive device and the pad pattern.

44. The semiconductor package according to claim 43, further comprising: The bottom filling glue is disposed between the passive device and the redistribution structure, wherein the bottom filling glue surrounds the solder.

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