Device, method and computer readable storage medium for amplifier compensation

Abstract

An apparatus, method, and computer-readable storage medium for amplifier compensation are provided. The apparatus includes a first amplifier, a second amplifier, and a compensation setting generator for generating a first amplifier compensation setting and a second amplifier compensation setting. A controller is operable to apply the first amplifier compensation setting to the first amplifier and the second amplifier compensation setting to the second amplifier. The controller is also operable to switch between generating updates to the first amplifier compensation setting and the second amplifier compensation setting.

Description

Technical Field

[0001] The present invention relates to an apparatus, a method and a computer-readable storage medium for amplifier compensation. Background Art

[0002] Conventional circuits may include one or more amplifiers for amplifying corresponding input signals. Typically, an amplifier is an electronic device for increasing the power or magnitude (time-varying voltage or current) of a signal. An amplifier typically uses power from a power supply to amplify the amplitude of a received signal to produce a corresponding amplified output signal. The amplified output signal may be used for any of a variety of purposes, such as driving an audio speaker, a display screen, etc.

[0003] One type of amplifier is an operational amplifier. An operational amplifier (or sometimes called an op-amp) is an integrated circuit (IC) that operates as a voltage amplifier. An op-amp has differential inputs. That is, an op-amp has two inputs of opposite polarity. In some cases, an op-amp has a single output and a very high gain, which means that the output signal is much higher than the input signal. External passive components such as resistors, capacitors, etc. can be coupled to the operational amplifier to control its behavior and provide the desired output.

[0004] One property of an operational amplifier is its input referred offset voltage, which can cause amplification errors if it is a high value. Ideally, the input referred offset voltage associated with an operational amplifier is zero.

[0005] In conventional power management IC designs, three common methods are used to correct the input-referred offset of the corresponding operational amplifier. For example, conventional methods include:

[0006] 1.) Use a large resistor chain and iDAC to minimize the input referred offset. The disadvantage of this approach is that it consumes a lot of space and the trimming process also increases the manufacturing cost.

[0007] 2.) Use an auxiliary amplifier to sense / correct the input reference offset voltage of the target amplifier. The disadvantage of this method is that each target amplifier requires an auxiliary amplifier, which leads to large space consumption and design complexity; in addition, since the auxiliary amplifier needs to operate between the automatic zero phase and the amplification phase, a dedicated clock circuit is required.

[0008] 3.) Using a chopping method, where the polarity of the input signal to the target amplifier needs to be constantly changed. The disadvantage of this method is the required polarity changes; this method also requires the design of filters to filter out switching noise. Summary of the invention

[0009] Embodiments herein include novel methods of improving the accuracy with which amplification is provided and reducing the effects of input referred offset voltage.

[0010] More specifically, embodiments herein include novel apparatus (eg, hardware, circuit, device, etc.) including: a first amplifier, a second amplifier, and a compensation setting generator for generating a first amplifier compensation setting and a second amplifier compensation setting.

[0011] The novel apparatus also includes a controller operable to apply (input) the generated first amplifier compensation setting to the first amplifier to provide compensation and to apply (input) the generated second amplifier compensation setting to the second amplifier to provide compensation.

[0012] According to further embodiments, the systems discussed herein include a first compensator (associated with a first amplifier) ​​and a second compensator (associated with a second amplifier). To provide compensation such as correction of an input-referred offset voltage associated with the first amplifier (such as a multi-stage amplifier including a transconductance input amplifier stage), the first compensator generates a first correction output based on a first compensation setting and applies the first correction output to the first amplifier. To provide compensation such as correction of an input-referred offset voltage associated with the second amplifier (such as a multi-stage amplifier including a transconductance input amplifier stage), the second compensator generates a second correction output based on a second compensation setting and applies the second correction output to the second amplifier.

[0013] To ensure more accurate amplification over time, the controller may be configured to switch between generating updates corresponding to first amplifier compensation settings applied to the first amplifier and second amplifier compensation settings applied to the second amplifier.

[0014] More specifically, according to further embodiments, the controller is operable to switch between controlling the compensation setting generator to generate updates to the first amplifier compensation setting and the second amplifier compensation setting in different time slots.

[0015] As previously described, the first amplifier compensation setting corrects the input (reference) offset voltage associated with the first amplifier. The second amplifier compensation setting corrects the input (reference) offset voltage associated with the second amplifier. Continuously updating the first amplifier compensation setting (value) and the second amplifier compensation setting (value), such as in different time slots, ensures more accurate compensation of the input reference offsets associated with the first amplifier and the second amplifier.

[0016] Note also that the compensation setting generator may be configured to generate the first amplifier compensation setting and the second amplifier compensation setting in any suitable manner and according to any suitable schedule. In one embodiment, the controller is operable to control the compensation setting generator to repeatedly generate and update the first amplifier compensation setting and the second amplifier compensation setting according to a periodic time slot schedule, thereby switching between generating updates to the first amplifier compensation setting and updating the second amplifier compensation setting.

[0017] A single compensation setting generator may be configured to generate any number of compensation settings for any number of amplifiers. The compensation setting generator may be configured to generate respective compensation settings in a periodic manner according to a time slot schedule such that each of the compensation settings is continuously updated over time.

[0018] The periodic schedule for repeatedly generating updates to the compensation settings may be implemented based on any suitable clock signal. In one embodiment, the controller controls the generation of the periodic time slot schedule based at least in part on a control output, such as a PWM (pulse width modulation) control signal of a power supply for controlling the generation of an output voltage from a corresponding power converter circuit of the power supply.

[0019] According to further embodiments, both the first amplifier and the second amplifier operate in a continuous amplification mode to amplify respective received signals to produce respective outputs when the compensation setting generator switches between generating the first amplifier compensation setting and the second amplifier compensation setting.

[0020] In yet other embodiments, the first amplifier is a first multi-stage amplifier including a corresponding first amplifier stage coupled to drive a corresponding second amplifier stage. The first compensator is operable to drive at least one node coupling the corresponding first amplifier stage in the first amplifier to the corresponding second amplifier stage in the first amplifier. The second amplifier is optionally a second multi-stage amplifier including a corresponding first amplifier stage coupled to drive a corresponding second amplifier stage in the second amplifier. The second compensator is operable to drive at least one node coupling the corresponding first amplifier stage in the second amplifier to the corresponding second amplifier stage.

[0021] Each of the first compensator and the second compensator can be of any suitable type. In one non-limiting example embodiment, the first compensator is a transconductance amplifier operable to output a current to at least one node coupling a corresponding first stage in the first amplifier to a corresponding second stage in the first amplifier. The second compensator is optionally a transconductance amplifier operable to output a current to at least one node coupling a corresponding first stage in the second amplifier to a second stage in the second amplifier.

[0022] In one non-limiting example implementation, to generate a first amplifier compensation setting and a second amplifier compensation setting, the controller is operable to: i) selectively couple an input of the first amplifier to a compensation setting generator to generate the first compensation setting, and ii) selectively couple an input of the second amplifier to the compensation setting generator to generate the second compensation setting. In the manner previously discussed, the generation of the amplifier compensation settings can be accomplished in different time slots.

[0023] According to further embodiments, when generating the first compensation setting, the controller is operable to: i) electrically decouple the compensation setting generator from the second amplifier, and ii) electrically couple the compensation setting generator to the input of the first amplifier.

[0024] When generating the second compensation setting, the controller is operable to: i) electrically decouple the compensation setting generator from the first amplifier, and ii) electrically couple the compensation setting generator to an input of the second amplifier.

[0025] The first compensator and the second compensator may be configured in any suitable manner to provide compensation. In one example embodiment, the first compensator includes: i) a first storage circuit for storing a first amplifier compensation setting, and ii) a first transconductance compensation amplifier for driving the first amplifier with a correction output having a magnitude dependent on the magnitude of the first amplifier compensation setting stored in the first storage circuit. The second compensator includes: i) a second storage circuit for storing a second amplifier compensation setting, and ii) a second transconductance compensation amplifier for driving the second amplifier with a correction output having a magnitude dependent on the magnitude of the second amplifier compensation setting stored in the second storage circuit.

[0026] The embodiments herein are more useful than conventional techniques. For example, some embodiments herein require only one offset correction circuit (compensation setting generator) to compensate for the input reference offset voltage associated with each of the multiple amplifiers. Therefore, one embodiment herein includes sharing one offset compensator between multiple target amplifiers, which will save valuable circuit board area and component cost. When implemented in a power management POL circuit, directly using the PWM signal (as an input to the controller) will also eliminate the need to design an oscillator circuit, which further improves the simplicity of design.

[0027] These and other more specific embodiments are disclosed in greater detail below.

[0028] Note that the techniques discussed herein may be implemented in any suitable environment, such as amplifier circuits, power supplies, multi-phase power supply applications, single-phase point-of-load (also known as POL) power supply applications, and the like.

[0029] It should also be noted that although the embodiments discussed herein may be applied to multi-phase power supply circuits, such as multi-phase power supply circuits implementing buck converters, DC-DC converter phases, the concepts disclosed herein may be advantageously applied to any other suitable topology as well as general power supply control applications.

[0030] Note also that the embodiments herein may include computer processor hardware (which executes corresponding switch instructions) to perform and / or support any or all of the method operations disclosed herein. In other words, one or more computerized devices or processors (computer processor hardware) may be programmed and / or configured to operate as described herein to perform different embodiments of the present invention.

[0031] Other embodiments herein include software programs for performing the steps and operations outlined above and disclosed in detail below.One such embodiment includes a computer program product with a non-transient computer storage medium (e.g., memory, disk, flash memory, ...), the non-transient computer storage medium includes computer program instructions and / or logic encoded thereon, and the computer program instructions and / or logic are programmed to perform any operation in the operation disclosed herein when executed in a computerized device with a processor and a corresponding memory.Such an arrangement is generally provided as software instructions, codes and / or other data (e.g., data structures) arranged or encoded on a computer-readable storage medium or a non-transient computer-readable medium, such as an optical medium (e.g., CD-ROM), a floppy disk or a hard disk or other media such as firmware or microcode in one or more ROM or RAM or PROM chips, an application-specific integrated circuit (ASIC), circuit logic, etc. Software or firmware or other such configurations can be installed on a corresponding controller circuit to enable the controller circuit (such as logic) to perform the technology described herein.

[0032] Thus, one embodiment of the present disclosure relates to a computer program product including a computer-readable medium having stored thereon instructions for supporting operations such as controlling one or more phases in a power supply. For example, in one embodiment, the instructions, when executed by computer processor hardware (one or more computer devices, control logic, digital circuits, etc.), cause the computer processor hardware to perform the following operations: generate a first amplifier compensation setting and a second amplifier compensation setting (during different time slots), the generated first amplifier compensation setting being used to correct an input offset voltage associated with a first amplifier, the generated second amplifier compensation setting being used to correct an input offset voltage associated with a second amplifier; apply / input the first compensation setting to a first compensator, the first compensator providing compensation to the first amplifier; apply / input the second compensation setting to a second compensator, the second compensator providing compensation to the second amplifier; and switch between updating the first compensation setting applied to the first amplifier and the second compensation setting applied to the second amplifier.

[0033] The order of operations is added for clarity. These operations may be performed in any suitable order.

[0034] It should be understood that the systems, methods, apparatuses, devices, logic, etc., as discussed herein may be implemented strictly as hardware (such as analog circuits, digital circuits, logic, etc.), as a hybrid of software and hardware, or solely as software, such as within a processor or within an operating system or within a software application.

[0035] Note that although each of the various features, techniques, configurations, etc. herein may be discussed in different places of the present disclosure, it is intended that, where appropriate, the various concepts may be optionally performed independently of one another or in combination with one another. Thus, one or more of the present inventions described herein may be embodied and observed in many different ways.

[0036] In addition, it is noted that this preliminary discussion of embodiments herein intentionally does not describe every embodiment and / or further novel aspect of the present disclosure or claimed invention. Instead, this brief description only provides general embodiments and corresponding novel points compared to conventional techniques. For additional details and / or possible viewpoints (arrangements) of the present invention, the reader is referred to the detailed description section of the present disclosure and the corresponding drawings discussed further below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects, features and advantages of the present invention will become apparent from the following more detailed description of the preferred embodiments herein as shown in the accompanying drawings, wherein like reference numerals refer to the same parts throughout the different drawings. The drawings are not necessarily drawn to scale, but emphasis is placed on illustrating the embodiments, principles, concepts, etc.

[0038] Figure 1 is an example diagram illustrating a compensation amplifier according to embodiments herein.

[0039] Figure 2 is an example diagram of an apparatus for providing amplifier compensation according to an embodiment of the present invention.

[0040] Figure 3 is an example timing diagram for controlling a corresponding compensation setting generator according to embodiments herein.

[0041] Figure 4 is an example diagram illustrating automatic zeroing (calibration) of a compensation setting generator according to embodiments herein.

[0042] Figure 5 is an example diagram illustrating generation of a second amplifier compensation setting according to embodiments herein.

[0043] Figure 6 is an example diagram illustrating automatic zeroing (calibration) of a compensation setting generator according to embodiments herein.

[0044] Figure 7 is an example diagram illustrating generation of a first amplifier compensation setting according to embodiments herein.

[0045] Figure 8 is an example diagram showing an amplifier and a compensator according to embodiments herein.

[0046] Fig. 9 is an example diagram illustrating a compensation setting generator according to embodiments herein.

[0047] Fig.10 is an example diagram illustrating computer processor hardware and related software instructions or logic circuits for performing methods according to embodiments herein.

[0048] Fig.11 is an example diagram illustrating a method according to an embodiment of the present invention.

[0049] Fig.12 is an example diagram illustrating a compensation amplifier according to embodiments herein.

[0050] Fig.13 is an example diagram illustrating a compensation amplifier according to embodiments herein. DETAILED DESCRIPTION

[0051] Now, more specifically, Figure 1 is an example diagram of a device 100 according to implementations herein.

[0052] As shown, apparatus 100 (which may be implemented in any suitable form, such as hardware, circuitry, devices, etc.) includes controller 140, compensation setting generator 110, compensator 121, compensator 122, amplifier 131, and amplifier 132. Thus, each of these resources may be implemented as hardware, circuitry, devices, etc.

[0053] In general, the controller 140 generates a control output 145 (one or more control signals) to control the compensation setting generator 110 and control the generation of the amplifier compensation setting 111 and the amplifier compensation setting 112. The first amplifier compensation setting 111 is generated to correct (or reduce) the effects of an input (reference) offset voltage associated with the first amplifier 131. The second amplifier compensation setting is generated to correct or reduce the effects of an input (reference) offset voltage associated with the second amplifier 132.

[0054] Thus, the first amplifier compensation setting 111 provides correction for the input offset voltage associated with the first amplifier 131 ; the second amplifier compensation setting 112 corrects the input offset voltage associated with the second amplifier.

[0055] During operation, as the name implies, the first compensator 121 provides compensation to the first amplifier 131 based on the amplifier compensation setting 111. The second compensator provides compensation to the second amplifier 132 based on the amplifier compensation setting 112.

[0056] The compensation setting generator 110 generates a first amplifier compensation setting 111 and a second amplifier compensation setting 112. The controller is operable to: i) apply (input) the first amplifier compensation setting 111 to the first compensator 121 and apply (input) the second amplifier compensation setting 112 to the second compensator 122.

[0057] To ensure more accurate amplification over time, the controller 140 is operable to repeatedly switch between generating updates to the first amplifier compensation setting 111 input to the first compensator 121 and the second amplifier compensation setting 112 input to the second compensator 122 .

[0058] In one embodiment, the compensator 121 may include a storage circuit or a buffer for storing the generated first amplifier compensation setting 111 ; the compensator 122 may include a storage circuit or a buffer for storing the generated second amplifier compensation setting 112 .

[0059] To provide compensation, such as correcting an input-referred offset voltage associated with the first amplifier 131 , the first compensator 121 generates a first correction output 261 based on the first compensation setting 111 and applies (inputs) the first correction output 261 to the first amplifier 131 .

[0060] In a similar manner, to provide compensation, such as correcting an input-referred offset voltage associated with the second amplifier 132 , the second compensator 122 generates a second correction output 262 based on the second compensation setting 112 and applies (inputs) the correction output 262 to the second amplifier 132 .

[0061] In one embodiment, if Fig.12 As shown, compensator 121 is integrated or manufactured as a part of amplifier 131; compensator 122 is integrated or manufactured as a part of amplifier 132. In this case, via input from controller 140, compensation setting generator 110 is operable to apply first amplifier compensation setting 111 to first amplifier 131 to provide corresponding compensation; controller 140 is operable to apply second amplifier compensation setting 112 to second amplifier 132 to provide corresponding compensation.

[0062] According to another embodiment, Fig.13 As shown, compensator 121 is integrated or manufactured as part of compensation setting generator 110; in addition, compensator 122 is integrated or manufactured as part of compensation setting generator 110. In this case, via input from controller 140, compensation setting generator 110 is operable to apply correction output signal 261 to amplifier 131 to provide corresponding compensation; compensation setting generator 110 is operable to apply correction output signal 262 to amplifier 132 to provide corresponding compensation.

[0063] Reference again Figure 1 According to another embodiment, the controller 140 is operable to generate the amplifier compensation setting 111 and the amplifier compensation setting 112 in different time slots. In this case, the controller 140 switches between controlling the compensation setting generator 110 to generate updates to the first amplifier compensation setting 111 and the second amplifier compensation setting 112.

[0064] As further described herein, continuously updating the first amplifier compensation setting 111 (value) and the second amplifier compensation setting 112 (value) ensures more accurate compensation of the input-referenced offsets associated with the first amplifier 131 and the second amplifier 132. In other words, if the input-referenced offset voltage associated with the first amplifier 131 and / or the second amplifier 132 changes over time, continuous updating of the corresponding amplifier compensation setting 111 and the amplifier compensation setting 112 ensures constant correction and thus more accurate amplification of the input signal 181 to the output signal 191 (via the amplifier 131) and more accurate amplification of the input signal 182 to the output signal 192 (via the amplifier 132).

[0065] Figure 2 is an example diagram of an apparatus for providing amplifier compensation according to an embodiment of the present invention.

[0066] As previously described, the compensation setting generator 110 generates the first amplifier compensation setting 111 and the second amplifier compensation setting 112 .

[0067] In one embodiment, compensation setting generator 110 controlled by controller 140 includes offset compensator A4 (such as a linear differential amplifier), transconductance amplifier stage A5, and storage circuit (capacitors C3 and C4) to generate amplifier compensation setting 111 and amplifier compensation setting 112. In an alternative embodiment, the storage circuit is a digital buffer that stores a digital representation of the amplifier compensation setting associated with offset compensator A4.

[0068] As discussed further below, capacitor C3 and capacitor C4 of compensation setting generator 110 store amplifier compensation settings derived by transconductance amplifier stage A5 in compensation setting generator 110 during a so-called auto-zero phase of calibrating amplifier A4 in compensation setting generator 110. In this case, when generating a corresponding amplifier compensation setting 111 or amplifier compensation setting 112, transconductance amplifier stage A5 in compensation setting generator 110 is operable to generate and output a correction output 221 (such as differential output signals 221-1 and 221-2), the magnitude of which depends on the magnitude of the amplifier compensation setting (voltage) stored in capacitor C3 and capacitor C4 (storage circuit). The details of calibrating compensation setting generator 110 will be discussed below. Figure 3 , Figure 4 and Figure 6 Further discussion in.

[0069] like Figure 2As further shown in FIG. 1 , as a non-limiting example implementation, the first amplifier 131 is a first multi-stage amplifier that includes a respective first transconductance amplifier stage 222 ( A1 ) coupled to drive a respective second amplifier stage 223 ( A2 ).

[0070] In one embodiment, the first transconductance amplifier stage 222 in the amplifier 131 is a differential transconductance input amplifier stage. According to further embodiments, the gain of the first transconductance amplifier stage 222 in the amplifier 131 is significantly greater (such as more than 5 times or any other suitable multiple) than the gain of the transconductance amplifier A3. The gain of the first transconductance amplifier stage 232 (A6) in the amplifier 132 is significantly greater (such as more than 5 times or any other suitable multiple) than the gain of the transconductance amplifier A8.

[0071] Typically, each of the transconductance amplifiers discussed herein (such as amplifiers A1, A3, A5, A6, and A8) receives a differential input voltage. Based on the corresponding transconductance gain associated with the corresponding amplifier and the differential voltage input between the inverting input and the non-inverting input, the transconductance amplifier outputs a differential output current. The magnitude of the output current of the corresponding transconductance amplifier at each differential output terminal is equal in an ideal situation. However, the polarity of the output current is opposite. For example, the non-reverse current output from transconductance amplifier A3 is opposite to the reverse current output from transconductance amplifier A3. Each of the transconductance amplifiers operates in a similar manner.

[0072] As further described herein, the output 261 (such as a differential current) from amplifier A3 provides compensation to the output of transconductance amplifier A1 to correct the input reference offset associated with transconductance amplifier A1; the output current 262 (such as a differential current) from amplifier A8 provides compensation to the output of transconductance amplifier A6 to correct the input reference offset associated with transconductance amplifier A6.

[0073] The first compensator 121 includes a transconductance amplifier A3, which is capable of operating to drive a corresponding correction output 261 (such as a differential output current signal) to multiple nodes (such as node 231-1 and node 231-2), which couple the corresponding first transconductance amplifier stage 222 in the first amplifier 131 to the corresponding second amplifier stage 223 in the first amplifier 131.

[0074] The magnitude of the correction output 261 (one or more signals) output by transconductance amplifier A3 in compensator 121 depends on the magnitude of amplifier compensation setting 111 (voltage) generated by compensation setting generator 110 and stored in capacitors C1 and C2 (storage circuit).

[0075] As a further non-limiting example implementation, the second amplifier 132 is a second multi-stage amplifier that includes a respective first transconductance amplifier stage 232 ( A6 ) coupled to drive a respective second amplifier stage 233 ( A7 ).

[0076] In one embodiment, the first transconductance amplifier stage 232 in the amplifier 132 is a differential transconductance input amplifier stage. According to further embodiments, the gain of the first transconductance amplifier stage 232 in the amplifier 132 is significantly greater (such as more than 5 times) than the gain of the amplifier A8. The gain of the first transconductance amplifier stage 232 in the amplifier 132 is significantly greater (such as more than 5 times) than the gain of the transconductance amplifier A8.

[0077] The second compensator 122 includes a transconductance amplifier A8, which is capable of operating to drive a corresponding correction output 262 (one or more output current signals) to multiple nodes (such as node 241-1 and node 241-2), which couple the corresponding first amplifier stage 232 in the second amplifier 132 to the corresponding second amplifier stage 233 in the second amplifier 132.

[0078] The magnitude of the correction output 262 output by transconductance amplifier A8 in compensator 122 depends on the magnitude of amplifier compensation setting 112 (voltage) generated by compensation setting generator 110 and stored in capacitor C5 and capacitor C6 (storage circuit).

[0079] According to further embodiments, both first amplifier 131 and second amplifier 132 may be configured to operate in a continuous amplification mode to amplify corresponding received signals when compensation setting generator 110 switches between generating first amplifier compensation setting 111 and second amplifier compensation setting 112 to generate corresponding output signals.

[0080] like Figure 2As further shown in FIG. 1 , the compensation setting generator 110 further includes switches S11, S12, S13, S14, S21, S22, S23, S24, S31, S32, S33, and S34. The controller 140 controls the activation of the switch groups during different control phases. For example, switches S11, S12, S13, and S14 represent a first group of switches simultaneously controlled by the control output 322; switches S21, S22, S23, and S24 represent a second group of switches simultaneously controlled by the control output 323; switches S31, S32, S33, and S34 represent a third group of switches simultaneously controlled by the control output 321. Assume that the controller generates a switch control output 321 for activating a third group of switches including switches S31, S32, S33, and S34. As discussed in more detail below, activating switches S31 and S32 to an on state causes the reference voltage V ref Is input to the inverting output node and non-inverting output node of amplifier A4. V ref The magnitude of can be any suitable value. If amplifier A4 is an ideal operational amplifier, applying the same input voltage value to both the inverting and non-inverting phases will result in the same output voltage for voltage 210-1 and voltage 210-2. However, due to the input reference offset voltage associated with amplifier A4, the magnitudes of voltage 210-1 and voltage 210-2 are different.

[0081] In this example embodiment, during the activation of switches S31 and S32 to the on state, amplifier A4 generates a corresponding output voltage 210-1, which is delivered to the inverting input and storage circuit (capacitor C4) in transconductance amplifier A5 through switch S33 (also activated to the on state). Capacitor C4 stores the generated voltage 210-1. In addition, amplifier A4 generates a corresponding output voltage 210-2, which is delivered to the non-inverting input and storage circuit (capacitor C3) in transconductance amplifier A5 through switch S34 (activated to the on state). Capacitor C3 stores voltage 210-2.

[0082] Assume that the controller 140 generates the switch control output 322 for simultaneously activating the set of switches including the switch S11 , the switch S12 , the switch S13 , and the switch S14 to the on state.

[0083] In this case, the switch S11 is activated to the on state, so that the input signal 182-1 is input to the non-inverting node of the amplifier A4. The switch S12 is activated to the on state in phase Q2, so that the input signal 182-2 is input to the inverting node of the amplifier A4. Therefore, by activating the switch S11 and the switch S12 to the on state, the controller 140 can be operated to electrically couple the compensation setting generator 110 to the input terminal of the second amplifier 132.

[0084] In addition, during the activation of the first group of switches S11, S12, S13, and S14 to the on state, the amplifier A4 generates a corresponding output voltage 210-1, which is delivered to the non-inverting input and storage circuit (capacitor C5) of the transconductance amplifier A8 through the switch S13 (activated to the on state). The capacitor C5 stores the voltage 210-1. The amplifier A4 also generates a corresponding output voltage 210-2, which is delivered to the inverting input and storage circuit (capacitor C6) of the transconductance amplifier A8 through the switch S14 (activated to the on state). The capacitor C6 stores the voltage 210-2.

[0085] The previously stored voltages in capacitors C5 and C6 cause transconductance amplifier A8 to provide correction to voltages 210-1 and 210-2 generated by amplifier A4. Thus, when generating amplifier compensation setting 112 stored in capacitors C5 and C6, the previously stored voltages in capacitors C3 and C4 provide correction to amplifier A4.

[0086] Assume that the controller 140 generates the switch control output 323 for simultaneously activating the set of switches including the switch S21 , the switch S22 , the switch S23 , and the switch S24 to the on state.

[0087] Activating switch S21 to an on state in phase Q4 causes input signal 181-1 to be input to the non-inverting node in amplifier A4. Activating switch S22 to an on state causes input signal 181-2 to be input to the inverting node in amplifier A4. Thus, by activating switches S21 and S22, controller 140 is operable to electrically couple compensation setting generator 110 to an input terminal in first amplifier 131, and to electrically decouple compensation setting generator 110 from an input terminal in second amplifier 132 (by deactivating switches S11 and S12).

[0088] In this case, during the simultaneous activation of switches S21, S22, S23, and S24, amplifier A4 generates a corresponding output voltage 210-1, which is delivered to the inverting input and storage circuit (capacitor C2) in transconductance amplifier A3 through switch S23 (activated to the on state). Capacitor C2 stores voltage 210-1. Amplifier A4 also generates a corresponding output voltage 210-2, which is delivered to the non-inverting input and capacitor C1 in transconductance amplifier A3 through switch S24 (activated to the on state). Capacitor C1 stores voltage 210-2.

[0089] The previously stored voltages in capacitors C3 and C4 cause transconductance amplifier A5 to provide correction to voltages 210-1 and 210-2 generated by amplifier A4. Thus, when generating amplifier compensation setting 111 stored in capacitors C1 and C2, the previously stored voltages in capacitors C3 and C4 provide correction to amplifier A4.

[0090] Note that in one embodiment, Figure 2 The amplifiers A3 and A8 in the circuits C1 and C2, and the circuits C5 and C6 are respectively so-called "auxiliary stages", in particular auxiliary stages of the associated amplifiers 131, 132. In this case, such as Fig.12 As shown, auxiliary stages A3 and A8 and corresponding circuits C1 , C2 , C5 and C6 may be part of amplifier 131 for A3 and part of amplifier 132 for A8 . Alternatively, they may form part of compensation setting generator 110 .

[0091] Note that in one embodiment, Figure 2 Amplifier A3, amplifier A5 and amplifier A8 in FIG. 1 are so-called "auxiliary stages" associated with compensation setting generator 110. In this case, such as Fig.13 As shown, each of auxiliary stages A3 , A5 , and A8 and corresponding circuits C1 , C2 , C3 , C4 , C5 , and C6 may be part of compensation setting generator 110 .

[0092] Figure 3 is an example timing diagram for controlling a corresponding compensation setting generator according to embodiments herein.

[0093] As previously discussed, compensation setting generator 110 may be configured to generate first amplifier compensation setting 111 and second amplifier compensation setting 112 in any suitable manner and according to any suitable schedule.

[0094] In one embodiment, the controller 140 is operable to generate control outputs 145 (switch control outputs 321, 322, and 323) to control the compensation setting generator 110 to repeatedly generate and update the first amplifier compensation setting 111 (stored as a differential voltage in capacitor C1 and capacitor C2 in one embodiment) and the second amplifier compensation setting (stored as a differential voltage in capacitor C5 and capacitor C6 in one embodiment) according to a periodic time slot schedule 300 that switches between i) generating and applying updates to the first amplifier compensation setting 111 and ii) generating and applying updates to the second amplifier compensation setting 112.

[0095] The switch control output 321 in the timetable 300 controls the activation / deactivation of switches S31, S32, S33, and S34. A logic high of the switch control output 321 indicates when to activate these switches to the on state, while a logic low indicates when to deactivate the switches to the off state.

[0096] The switch control output 322 in the timetable 300 controls the activation / deactivation of switches S11, S12, S13, and S14. A logic high of the switch control output 322 indicates when to activate these switches to the on state, while a logic low indicates when to deactivate the switches to the off state.

[0097] The switch control output 323 in the timetable 300 controls the activation / deactivation of switches S21, S22, S23, and S24. A logic high of the switch control output 323 indicates when to activate these switches to the on state, while a logic low indicates when to deactivate the switches to the off state.

[0098] The periodic time slot schedule 300 may be implemented based on any suitable clock signal. In one embodiment, the controller 140 may be based at least in part on the control signal ( Figure 2 A clock signal 292 in the control circuit controls the generation of a periodic time slot schedule, and the control signal is such as a PWM (pulse width modulation) control signal of the power supply 260 for controlling the generation of the output voltage from the corresponding power converter circuit.

[0099] In this example embodiment, each calibration cycle includes four phases, namely phase Q1 , phase Q2 , phase Q3 , and phase Q4 .

[0100] In phase Q1, such as between time T1 and time T2 for cycle #1, the controller 140 generates the switch control output 321 as a high state for activating switches S31, S32, S33, and S34 to the on state. During phase Q1, the controller 140 generates the switch control output 322 as a low state for deactivating switches S11, S12, S13, and S14 to the off state. During phase Q1, the controller 140 generates the switch control output 323 as a low state for deactivating switches S21, S22, S23, and S24 to the off state. Note that the following Figure 4 The settings of the switches and circuit connections for phase Q1 are shown.

[0101] Reference again Figure 3 , in phase Q2, such as between time T2 and T3 for cycle #1, the controller 140 generates a switch control output 322 as a high state for activating switches S11, S12, S13, and S14 to the on state. During phase Q2, the controller 140 generates a switch control output 323 as a low state for deactivating switches S21, S22, S23, and S24 to the off state. During phase Q2, the controller 140 generates a switch control output 321 as a low state for deactivating switches S31, S32, S33, and S34 to the off state. Figure 5 The settings of the switches and circuit connections for phase Q2 are shown.

[0102] Reference again Figure 3 , in phase Q3, such as between time T3 and T4 for cycle #1, the controller 140 generates a switch control output 321 as a high state for activating switches S31, S32, S33, and S34 to the on state. During phase Q3, the controller 140 generates a switch control output 322 as a low state for deactivating switches S11, S12, S13, and S14 to the off state. During phase Q3, the controller 140 generates a switch control output 323 as a low state for deactivating switches S21, S22, S23, and S24 to the off state. Figure 6 The settings of the switches and circuit connections for phase Q3 are shown.

[0103] Reference again Figure 3, in phase Q4, such as between time T4 and T5 for cycle #1, the controller 140 generates a switch control output 323 as a high state for activating switches S21, S22, S23, and S24 to the on state. During phase Q4, the controller 140 generates a switch control output 322 as a low state for deactivating switches S11, S12, S13, and S14 to the off state. During phase Q4, the controller 140 generates a switch control output 321 as a low state for deactivating switches S31, S32, S33, and S34 to the off state. Figure 7 The switch and circuit connection settings for phase Q4 are shown.

[0104] Similar to cycle #1, the controller 140 repeats control for each of the multiple cycles (cycle #2, cycle #3, etc.) to continuously update the amplifier compensation setting 111 (stored in capacitors C1 and C2) and the amplifier compensation setting 112 (stored in capacitors C5 and C6) for each cycle. More specifically, the amplifier compensation setting 111 stored in the corresponding storage circuits such as capacitors C1 and capacitors C2 is updated in phase Q4 of each cycle; the amplifier compensation setting 112 stored in the storage circuits such as capacitors C5 and capacitors C6 is updated in phase Q2 of each cycle.

[0105] In one embodiment, even though the amplifier compensation settings are updated during different portions of each cycle, amplifiers 131 and 132 still provide uninterrupted amplification of input signals 181 and 182. Thus, in one embodiment, correction output 261 applied to amplifier 131 and correction output 262 applied to amplifier 132 are always updated to provide appropriate amplification of input signals 181 and 182 to generate corresponding output signals 191 and 192.

[0106] For three of the four phases in the corresponding cycle, the magnitude of the stored amplifier compensation setting is constant. During a phase, the corresponding amplifier compensation setting may be updated to a new value. For example, during phase Q1, phase Q2, and phase Q3, the current value of the amplifier compensation setting 111 stored in the storage circuit (such as capacitors C1 and C2) is used as a basis for providing a correction of the corresponding input reference offset associated with the first amplifier 131. The magnitude of the amplifier compensation setting 111 is updated in phase Q4. The amplifier 131 provides continuous amplification of the input 181 to the output 191 in each of the multiple phases Q1, Q2, Q3, and Q4.

[0107] During phases Q1, Q3, and Q4, the value of the amplifier compensation setting 112 stored in a storage circuit, such as capacitors C5 and C6, is used as a basis for providing a correction of a corresponding input-referred offset associated with the second amplifier 132. The magnitude of the amplifier compensation setting 112 is updated in phase Q2. The amplifier 131 provides continuous amplification of the input 182 to the output 192 in each of the plurality of phases Q1, Q2, Q3, and Q4.

[0108] Embodiments herein are more useful than conventional techniques. For example, certain embodiments herein require only one offset correction circuit, such as compensation setting generator 110, to compensate for input-referred offset voltages associated with amplifiers 131 and 132. Thus, one embodiment herein includes sharing one offset compensator between multiple target amplifiers, which saves valuable circuit board area and the cost of components otherwise required to provide compensation. When implemented in a power management POL circuit, directly using a PWM signal (such as an input from a power supply) eliminates the need to design a separate oscillator circuit, which further improves the simplicity of the corresponding amplifier circuit.

[0109] Figure 4 is an example diagram illustrating automatic zeroing (calibration) of a compensation setting generator according to embodiments herein.

[0110] As previously described, in phase Q1, such as between time T1 and T2 for cycle #1, the controller 140 generates the switch control output 321 as a high state for activating the group of switches S31, S32, S33, and S34 to the on state. During phase Q1, the controller 140 generates the switch control output 322 as a low state for deactivating the group of switches S11, S12, S13, and S14 to the off state. During phase Q1, the controller 140 generates the switch control output 323 in a low state for deactivating the group of switches S21, S22, S23, and S24 to the off state.

[0111] The switch S31 and the switch S32 are activated to the on state so that the reference voltage V ref Is input to the inverting output node and non-inverting output node of amplifier A4. V ref The magnitude of can be any suitable value. If amplifier A4 is an ideal operational amplifier, applying the same input voltage value to the inverting and non-inverting phases will result in the same output voltage for voltage 210-1 and voltage 210-2. However, due to the input reference offset voltage associated with amplifier A4, the magnitude of voltage 210-1 and voltage 210-2 are different.

[0112] In this example implementation, during phase Q1, amplifier A4 generates a corresponding output voltage 210-1, which is delivered to the inverting input terminal and storage circuit (capacitor C4) in transconductance amplifier A5 through switch S33 (also activated to the on state). Capacitor C4 stores the generated voltage 210-1.

[0113] Amplifier A4 generates a corresponding output voltage 210-2, which is delivered to the non-inverting input and storage circuit (capacitor C3) in transconductance amplifier A5 through switch S34 (activated to the on state). Capacitor C3 stores voltage 210-2.

[0114] These operations in phase Q1 provide automatic zeroing of amplifier A4 for subsequent use in phase Q2 for updating and generating amplifier compensation settings 112 stored in capacitors C5 and C6. In other words, the storage circuit (such as capacitors C3 and C4) stores compensation values ​​(such as one or more voltage values) that are used to correct the input-referred offset associated with amplifier A4 when amplifier A4 is subsequently used to generate amplifier compensation settings 112 in a subsequent phase Q2.

[0115] Figure 5 is an example diagram illustrating generation of a second amplifier compensation setting according to embodiments herein.

[0116] As previously described, in phase Q2, for example, between time T2 and T3 for cycle #1, the controller 140 generates a switch control output 322 as a high state for activating switches S11, S12, S13, and S14 to the on state. During phase Q2, the controller 140 generates a switch control output 323 as a low state for deactivating switches S21, S22, S23, and S24 to the off state. During phase Q2, the controller 140 generates a switch control output 321 as a low state for deactivating switches S31, S32, S33, and S34 to the off state.

[0117] Activating switch S11 to an on state in phase Q2 causes input signal 182-1 to be input to a non-inverting node in amplifier A4. Activating switch S12 to an on state in phase Q2 causes input signal 182-2 to be input to an inverting node in amplifier A4. Thus, in phase Q2, by activating switches S11 and S12, controller 140 is operable to electrically couple compensation setting generator 110 to an input of second amplifier 132 and electrically decouple compensation setting generator 110 from an input of first amplifier 131 (by deactivating switches S21 and S22).

[0118] In this case, during phase Q2, amplifier A4 generates a corresponding output voltage 210-1, which is delivered to the non-inverting input and storage circuit (capacitor C5) in transconductance amplifier A8 through switch S13 (activated to the on state). Capacitor C5 stores voltage 210-1. Amplifier A4 also generates a corresponding output voltage 210-2, which is delivered to the inverting input and storage circuit (capacitor C6) in transconductance amplifier A8 through switch S14 (activated to the on state). Capacitor C6 stores voltage 210-2.

[0119] The previously stored voltages in capacitors C5 and C6 cause transconductance amplifier A8 to provide correction to voltages 210-1 and 210-2 generated by amplifier A4. Thus, when amplifier compensation setting 112 stored in capacitors C5 and C6 is generated during phase Q2, the previously stored voltages in capacitors C3 and C4 provide correction to amplifier A4.

[0120] Figure 6 is an example diagram illustrating automatic zeroing (calibration) of a compensation setting generator according to embodiments herein.

[0121] As previously described, in phase Q3, such as between time T3 and T4 of cycle #1, the controller 140 generates a switch control output 321 as a high state for activating switches S31, S32, S33, and S34 to the on state. During phase Q3, the controller 140 generates a switch control output 322 as a low state for deactivating switches S11, S12, S13, and S14 to the off state. During phase Q3, the controller 140 generates a switch control output 323 as a low state for deactivating switches S21, S22, S23, and S24 to the off state.

[0122] The switch S31 and the switch S32 are activated to the on state so that the reference voltage V ref is input to the inverting output node and the non-inverting output node in amplifier A4. In this case, amplifier A4 generates a corresponding output voltage 210-1, which is delivered to the inverting input and storage circuit capacitor C4 in transconductance amplifier A5 through switch S33 (also activated to the on state). Capacitor C4 stores voltage 210-1.

[0123] Amplifier A4 generates a corresponding output voltage 210-2, which is delivered to the non-inverting input of transconductance amplifier A5 and storage circuit capacitor C3 through switch S34 (activated to the on state). Capacitor C3 stores voltage 210-2.

[0124] The operations in phase Q3 provide automatic zeroing of amplifier A4 for subsequent use in phase Q4 for updating and generating amplifier compensation settings 111 stored in capacitors C1 and C2. In other words, the storage circuit (such as capacitors C3 and C4) stores a compensation value (such as a voltage value) that is used to correct the input-referred offset associated with amplifier A4 when amplifier A4 is subsequently used to generate amplifier compensation settings 111 in a subsequent phase Q4.

[0125] Figure 7 is an example diagram illustrating generation of a first amplifier compensation setting according to embodiments herein.

[0126] In phase Q4, such as between time T4 and T5 of cycle #1, the controller 140 generates a switch control output 323 as a high state for activating switches S21, S22, S23, and S24 to the on state. During phase Q4, the controller 140 generates a switch control output 322 as a low state for deactivating switches S11, S12, S13, and S14 to the off state. During phase Q4, the controller 140 generates a switch control output 321 as a low state for deactivating switches S31, S32, S33, and S34 to the off state.

[0127] Activating switch S21 to an on state in phase Q4 causes input signal 181-1 to be input to a non-inverting node in amplifier A4. Activating switch S22 to an on state in phase Q4 causes input signal 181-2 to be input to an inverting node in amplifier A4. Thus, in phase Q4, by activating switches S21 and S22, controller 140 is operable to electrically couple compensation setting generator 110 to the input of first amplifier 131, and to electrically decouple compensation setting generator 110 from the input of second amplifier 132 (by deactivating switches S11 and S12).

[0128] In this case, during phase Q4, amplifier A4 generates a corresponding output voltage 210-1, which is delivered to the inverting input and storage circuit (capacitor C2) in transconductance amplifier A3 through switch S23 (activated to the on state). Capacitor C2 stores voltage 210-1.

[0129] Amplifier A4 also generates a corresponding output voltage 210-2, which is delivered to the non-inverting input of transconductance amplifier A3 and capacitor C1 through switch S24 (activated to the on state). Capacitor C1 stores voltage 210-2.

[0130] The previously stored voltages in capacitors C3 and C4 cause transconductance amplifier A5 to provide correction to voltages 210-1 and 210-2 generated by amplifier A4. Thus, when amplifier compensation setting 111 stored in capacitors C1 and C2 is generated during phase Q4, the previously stored voltages in capacitors C3 and C4 provide correction to amplifier A4.

[0131] Figure 8 is an example diagram showing a more specific implementation of an amplifier and a compensator according to embodiments herein.

[0132] As shown in this example embodiment, and as previously described, transconductance amplifier A3 provides correction to amplifier 131, which includes amplifier A1 and amplifier A2. Amplifier 132 may be configured to include similar circuitry.

[0133] Fig. 9 is an example diagram showing a more specific implementation of a compensation setting generator according to embodiments herein.

[0134] As shown in this example embodiment, and as previously described, transconductance amplifier A5 provides correction to amplifier A4 in compensation setting generator 110 .

[0135] Fig.10 is an example block diagram of a computer device for implementing any of the operations discussed herein according to embodiments herein.

[0136] As shown, the computer system 1000 of the present example (such as implemented by any one of one or more resources such as a controller 140, a compensation setting generator 110, a compensator 121, etc.) includes an interconnect 1011 that couples a computer-readable storage medium 1012 such as a non-transitory type of medium (or hardware storage medium) in which digital information can be stored and retrieved, a processor 1013 (e.g., computer processor hardware such as one or more processor devices), an I / O interface 1014, and a communication interface 1017.

[0137] I / O interface 1014 provides connection to any appropriate circuitry, such as each phase.

[0138] The computer-readable storage medium 1012 may be any hardware storage resource or device, such as a memory, an optical storage device, a hard drive, a floppy disk, etc. In one embodiment, the computer-readable storage medium 1012 stores instructions and / or data used by the control application 140-1 to perform any of the operations as described herein.

[0139] Furthermore, in this example embodiment, communication interface 1018 enables computer system 1000 and processor 1013 to communicate over resources such as network 193 to retrieve information from remote sources, as well as to communicate with other computers.

[0140] As shown, computer-readable storage medium 1012 is encoded with a control application 140-1 (eg, software, firmware, etc.) that is executed by processor 1013. Control application 140-1 may be configured to include instructions for implementing any of the operations discussed herein.

[0141] During operation of one embodiment, the processor 1013 accesses the computer-readable storage medium 1012 using the interconnect 1011 in order to launch, run, execute, interpret or otherwise perform instructions in the control application 140 - 1 stored on the computer-readable storage medium 1012 .

[0142] Execution of the control application 140-1 generates processing functionality, such as a control process 140-2 in the processor 1013. In other words, the control process 140-2 associated with the processor 1013 represents one or more aspects of executing the control application 140-1 within or on the processor 1013 in the computer system 1000.

[0143] According to various implementations, note that computer system 1000 may be a microcontroller device, logic, hardware processor, mixed analog / digital circuit, etc. configured to control power and perform any of the operations as described herein.

[0144] Now it will pass Fig.11 The functions supported by different resources are discussed with reference to the flowcharts in FIG. 1. Note that the steps in the flowcharts below may be performed in any suitable order.

[0145] Fig.11 is an example diagram illustrating a method according to an embodiment of the present invention.

[0146] In processing operation 1110, the controller 140 controls the compensation setting generator 110 to generate a first amplifier compensation setting 111 and a second amplifier compensation setting 112 (during different time slots). In one embodiment, the first amplifier compensation setting 111 is generated to correct the input offset voltage associated with the first amplifier 131; the second amplifier compensation setting 112 is generated to correct the input offset voltage associated with the second amplifier 132.

[0147] In process operation 1120 , the controller 140 applies the first amplifier compensation setting 111 to the first amplifier 131 .

[0148] In process operation 1130 , the controller 140 applies the second amplifier compensation setting 112 to the second amplifier 132 .

[0149] In processing operation 1140 , the controller 140 switches between updating the first compensation setting 111 applied to the first amplifier 131 and updating the second compensation setting 112 applied to the second amplifier 132 .

[0150] Note again that the techniques herein are well suited for circuit applications such as applications including multiple amplifiers. However, it should be noted that the embodiments herein are not limited to use in such applications, and the techniques discussed herein are also well suited for use in other applications.

[0151] Based on the description set forth herein, a large number of specific details have been set forth to provide a thorough understanding of the subject matter claimed for protection. However, it should be understood by those skilled in the art that the subject matter claimed for protection can be practiced without these specific details. In other cases, the methods, devices, systems, etc. that ordinary technicians should know are not described in detail, so as not to obscure the subject matter claimed for protection. Some parts of the detailed description have been presented with respect to the algorithm or symbolic representation of the operation performed on the data bit or binary digital signal stored in the computing system memory such as computer memory. These algorithm descriptions or representations are examples of the technology used by ordinary technicians in the field of data processing to convey the essence of their work to other technicians in the field. The algorithms described herein are generally considered to be self-consistent sequences of operations or similar processing that produce desired results. In this context, operation or processing involves physical manipulation of physical quantities. Generally, although not necessarily, these quantities can take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared or otherwise manipulated. Sometimes, mainly for public use reasons, it is convenient to refer to signals such as bits, data, values, elements, symbols, characters, terms, numbers, numerals, etc. However, it should be understood that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels. Unless otherwise expressly stated, it will be apparent from the following discussion that throughout this specification, discussions utilizing terms such as "processing," "computing," "calculating," "determining," and the like refer to the actions or processes of a computing platform such as a computer or similar electronic computing device that manipulates or transforms data represented as physical electronic or magnetic quantities in a memory, register, or other information storage device, transmission device, or display device of the computing platform.

[0152] Although the present invention has been specifically shown and described with reference to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various changes in form and detail may be made in the present invention without departing from the spirit and scope of the present application as defined by the appended claims. Such changes are intended to be encompassed by the scope of the present application. Therefore, the above description of the embodiments of the present application is not intended to be limiting. On the contrary, any limitation of the present invention is provided in the appended claims.

Claims

1. A device for amplifier compensation, comprising: First amplifier; A second amplifier; a controller to apply a first amplifier compensation setting to the first amplifier and a second amplifier compensation setting to the second amplifier and to switch between generating updates corresponding to the first amplifier compensation setting applied to the first amplifier and the second amplifier compensation setting applied to the second amplifier; and Compensation setting generator, wherein the controller is further configured to selectively couple an input of the first amplifier to the compensation setting generator to generate the first amplifier compensation setting, and selectively couple an input of the second amplifier to the compensation setting generator to generate the second amplifier compensation setting, wherein the first amplifier compensation setting is configured to correct an input offset voltage associated with the first amplifier, and Wherein the second amplifier compensation setting is configured to correct an input offset voltage associated with the second amplifier.

2. The device according to claim 1, wherein: The controller is operable to switch between controlling the compensation setting generator to generate updates to the first amplifier compensation setting and the second amplifier compensation setting in different time slots.

3. The device according to claim 1, wherein: Both the first amplifier and the second amplifier operate in a continuous amplification mode that amplifies respective received signals when the compensation setting generator generates the first amplifier compensation setting and the second amplifier compensation setting.

4. The apparatus according to claim 1, further comprising: a first compensator operable to provide a first compensation to the first amplifier based on the first amplifier compensation setting; a second compensator operable to provide a second compensation to the second amplifier based on the second amplifier compensation setting; wherein the first amplifier is a first multi-stage amplifier including a respective first amplifier stage coupled to drive a respective second amplifier stage, the first compensator being operable to drive at least one node coupling the respective first amplifier stage of the first amplifier to the respective second amplifier stage; and Wherein, the second amplifier is a second multi-stage amplifier including a corresponding first amplifier stage coupled to drive a corresponding second amplifier stage of the second amplifier, and the second compensator is operable to drive at least one node coupling the corresponding first amplifier stage of the second amplifier to the corresponding second amplifier stage.

5. The device according to claim 4, wherein: the first compensator being a transconductance amplifier operable to drive at least one node coupling a corresponding first amplifier stage of the first amplifier to a corresponding second amplifier stage of the first amplifier; as well as Wherein the second compensator is a transconductance amplifier operable to drive at least one node coupling the corresponding first amplifier stage of the second amplifier to the corresponding second amplifier stage of the second amplifier.

6. The device according to claim 1, wherein: The compensation setting generator is operable to repeatedly generate and update the first amplifier compensation setting and the second amplifier compensation setting according to a periodic time slot schedule.

7. The device according to claim 6, wherein: The periodic time slot schedule is implemented based at least in part on a control signal operable to control generation of an output voltage from the power converter.

8. The device according to claim 1, wherein: The controller is operable to electrically decouple the compensation setting generator from the second amplifier when generating the first amplifier compensation setting, and Wherein, when generating the second amplifier compensation setting, the controller is operable to electrically decouple the compensation setting generator from the first amplifier.

9. The apparatus according to claim 1, further comprising: a first compensator operable to provide a first compensation to the first amplifier based on the first amplifier compensation setting; a second compensator operable to provide a second compensation to the second amplifier based on the second amplifier compensation setting; wherein the first compensator comprises: i) a first storage circuit for storing the first amplifier compensation setting, and ii) a first transconductance compensation amplifier for driving the first amplifier with a correction signal having a magnitude that depends on the magnitude of the first amplifier compensation setting stored in the first storage circuit; and Wherein, the second compensator includes: i) a second storage circuit, the second storage circuit is used to store the second amplifier compensation setting, and ii) a second transconductance compensation amplifier, the second transconductance compensation amplifier is used to drive the second amplifier using a correction signal whose size depends on the size of the second amplifier compensation setting stored in the second storage circuit.

10. The device according to claim 9, wherein: The compensation setting generator includes an offset compensator, a transconductance amplifier stage and a third storage circuit, wherein the third storage circuit is operable to store a third amplifier compensation setting derived by a transconductance amplifier stage of the compensation setting generator, and Therein, the transconductance amplifier stage is operable to output a correction signal having a magnitude dependent upon a magnitude of a third amplifier compensation setting stored in the third storage circuit.

11. The device according to claim 1, further comprising: a first compensator operable to generate a first correction signal based on the first amplifier compensation setting, the first compensator providing an input offset voltage correction to the first amplifier via application of the first correction signal to the first amplifier; as well as A second compensator is operable to generate a second correction signal based on the second amplifier compensation setting, the second compensator providing an input offset voltage correction to the second amplifier via application of the second correction signal to the second amplifier.

12. A method for amplifier compensation, comprising: generating a first compensation setting by a compensation setting generator, and applying the first compensation setting to a first amplifier; generating a second compensation setting by the compensation setting generator and applying the second compensation setting to a second amplifier; as well as switching between updating a first compensation setting applied to the first amplifier and a second compensation setting applied to the second amplifier, wherein generating the first compensation setting comprises coupling an input terminal of the first amplifier to the compensation setting generator, wherein generating the second compensation setting comprises coupling an input terminal of the second amplifier to the compensation setting generator, wherein the first compensation setting is configured to correct an input offset voltage associated with the first amplifier, and Wherein the second compensation setting is configured to correct an input offset voltage associated with the second amplifier.

13. The method according to claim 12, further comprising: The first compensation setting and the second compensation setting are generated in different time slots.

14. The method according to claim 12, further comprising: The first amplifier and the second amplifier are operated in a continuous amplification mode to amplify respective received signals while repeatedly updating the first compensation setting and the second compensation setting.

15. The method according to claim 12, further comprising: driving, by a first compensator, at least one node coupling a first amplifier stage of the first amplifier to a second amplifier stage of the first amplifier to compensate the first amplifier; as well as At least one node coupling the first amplifier stage of the second amplifier to the second amplifier stage of the second amplifier is driven by a second compensator to compensate the second amplifier.

16. The method according to claim 12, further comprising: A first compensation setting applied to the first amplifier and a second compensation setting applied to the second amplifier are repeatedly generated and updated according to a periodic schedule.

17. The method according to claim 16, further comprising: The periodic schedule is implemented based at least in part on a control signal that controls generation of an output voltage from the power converter.

18. The method according to claim 12, further comprising: electrically decoupling a compensation setting generator from the second amplifier when generating the first compensation setting; as well as The compensation setting generator is electrically decoupled from the first amplifier when generating the second compensation setting.

19. The method according to claim 12, further comprising: storing the first compensation setting in a first storage circuit; inputting the first compensation setting in the first storage circuit into a first compensator, the first compensator driving the first amplifier with a correction signal having a magnitude that depends on the magnitude of the first compensation setting stored in the first storage circuit; storing the second compensation setting in a second storage circuit; as well as The second compensation setting in the second storage circuit is input into a second compensator, which drives the second amplifier with a correction signal whose magnitude depends on the magnitude of the second compensation setting stored in the second storage circuit.

20. The method of claim 12, further comprising: generating a first correction signal based on the first compensation setting, the first correction signal providing an input offset voltage correction to the first amplifier; as well as A second correction signal is generated based on the second compensation setting, the second correction signal providing an input offset voltage correction to the second amplifier.

21. A computer-readable storage medium storing instructions which, when executed by computer processor hardware, cause the computer processor hardware to implement the method according to any one of claims 12 to 20.

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