Semiconductor device package and method of manufacturing the same

Abstract

At least some embodiments of the present invention relate to semiconductor device packaging. The semiconductor device package includes: a first substrate having a first surface and a second surface opposite to the first surface; a second substrate adjacent to the first surface of the first substrate; and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. The surface of the encapsulant is coplanar with or protrudes beyond the second surface of the first substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device package comprising a first substrate, a second substrate, and an encapsulation. Background Technology

[0002] To improve the performance of semiconductor device packaging, electronic components or semiconductor devices can be mounted on both sides of a substrate. A frame plate that can surround some of the components or semiconductor devices is mounted on the substrate via connecting elements (e.g., solder bumps). Multi-side molding techniques can be used to encapsulate the components or semiconductor devices on both sides of the substrate. This multi-side molding technique may involve two molding operations. During the molding operations, the connecting elements used to attach the frame plate to the substrate may deform or be damaged, which can adversely affect the performance of the semiconductor device package. Summary of the Invention

[0003] In some embodiments, according to one aspect, a semiconductor device package includes: a first substrate having a first surface and a second surface opposite to the first surface; a second substrate adjacent to the first surface of the first substrate; and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. The surface of the encapsulant is coplanar with or protrudes beyond the second surface of the first substrate.

[0004] In some embodiments, according to another aspect, a semiconductor device package includes: a first substrate having a surface; a second substrate adjacent to the first substrate; an encapsulant encapsulating the second substrate; and a conductive layer disposed on the surfaces of the encapsulant and the first substrate. The first substrate includes a ground layer exposed from the surface. The first substrate defines a space. The second substrate covers the space. The encapsulant fills the space. The conductive layer is in contact with the ground layer.

[0005] In some embodiments, according to another aspect, a semiconductor device package includes: a first substrate defining a space; a second substrate adjacent to the first substrate and covering the space; a first electronic component; a second electronic component; and an encapsulator. The second substrate has a first surface, a second surface opposite to the first surface, and a third surface extending from the first surface to the second surface. The first electronic component is disposed on the first surface of the second substrate. The second electronic component is disposed on the second surface of the second substrate and in the space of the first substrate. The encapsulator has a surface and encapsulates the first substrate, the second substrate, the first electronic component, and the second electronic component. The third surface of the second substrate is offset from the surface of the encapsulator by a non-zero distance.

[0006] In some embodiments, according to another aspect, a method for manufacturing a semiconductor device package includes: providing a first substrate having a first surface and a second surface opposite to the first surface, the first substrate defining a plurality of spaces; disposing an adhesive layer on the second surface of the first substrate; providing a semiconductor device module on the first surface of the first substrate; and encapsulating the first substrate and the semiconductor device module with an encapsulant. Attached Figure Description

[0007] Figure 1 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present invention is provided.

[0008] Figure 2A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present invention is provided.

[0009] Figure 2B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present invention is provided.

[0010] Figure 2C A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present invention is provided.

[0011] Figure 3A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present invention is provided.

[0012] Figure 3B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present invention is provided.

[0013] Figure 4A A method for manufacturing a semiconductor device package according to some embodiments of the present invention is described.

[0014] Figure 4B A method for manufacturing a semiconductor device package according to some embodiments of the present invention is described.

[0015] Figure 4C A method for manufacturing a semiconductor device package according to some embodiments of the present invention is described.

[0016] Figure 4D A method for manufacturing a semiconductor device package according to some embodiments of the present invention is described.

[0017] Figure 5 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present invention is provided.

[0018] Figure 6A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present invention is provided.

[0019] Figure 6BA cross-sectional view illustrating a semiconductor device package according to some embodiments of the present invention is provided.

[0020] Figure 7 This illustrates a cross-sectional view of a comparative semiconductor device package.

[0021] Figure 8A Describe the method for manufacturing a comparative semiconductor device package.

[0022] Figure 8B Describe the method for manufacturing a comparative semiconductor device package.

[0023] Figure 8C Describe the method for manufacturing a comparative semiconductor device package.

[0024] Figure 8D Describe the method for manufacturing a comparative semiconductor device package. Detailed Implementation

[0025] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of the invention will be readily understood from the detailed description taken in conjunction with the accompanying drawings.

[0026] Spatial descriptions, such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc., are specified relative to a particular component or group of components or a plane of a component or group of components to orient one or more components as shown in the associated diagrams. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantages of the embodiments of the invention are that they do not deviate from such arrangements.

[0027] Figure 1 This is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present invention. The semiconductor device package 1 includes a substrate 10, a substrate 11, an encapsulation 12, a connection element 13, and electronic components (e.g., semiconductor devices) 14, 15, 16, and 17.

[0028] Substrate 11 has an upper surface 11u, an outer / lateral surface 11o, and a lower surface 11b. The outer surface 11o of substrate 11 extends from the upper surface 11u to the lower surface 11b. In some embodiments, substrate 11 may comprise a motherboard. Electronic components 14 and 15 are disposed on the upper surface 11u of substrate 11. Electronic components 16 and 17 are disposed on the lower surface 11b of substrate 11. Electronic components 14, 15, 16, or 17 may constitute at least a portion of a flip-chip package, a wire-bonded package, or both. Electronic components 14, 15, 16, and 17 may be passive devices (including, for example, capacitors) and / or active devices (including, for example, semiconductor dies).

[0029] Substrate 10 has an upper surface 10u, an outer / lateral surface 10o, and a lower surface 10b. The outer surface 10o of substrate 10 extends from the upper surface 10u to the lower surface 10b. The outer surface 10o of substrate 10 and the outer surface 11o of substrate 11 are coplanar. In some embodiments, substrate 10 may include a frame plate. Substrate 10 may include a dielectric layer 101. Substrate 10 may include a conductive pad surrounded by the dielectric layer 101. In some embodiments, the dielectric layer 101 may be a solder resist layer. The dielectric layer 101 may be omitted. Substrate 10 is adjacent to substrate 11. Substrate 10 is electrically connected to substrate 11 via a connection element 13. The connection element 13 may be a solder bump. Substrate 10 defines one space (or opening) or multiple spaces (or multiple openings). Electronic components 16 and 17 are at least partially disposed in the space of substrate 10. Substrate 11 covers the space.

[0030] Encapsulation 12 (which may contain a molding compound) has an upper surface 12u, an outer / lateral surface 12o, and a lower surface 12b. The outer surface 12o of encapsulation 12 may extend from the upper surface 12u to the lower surface 12b (e.g., it may extend around one side of substrate 11, not shown). Encapsulation 12 encapsulates substrates 10 and 11. Encapsulation 12 encapsulates electronic components 14, 15, 16, and 17. The outer surface 10o of substrate 10, the outer surface 11o of substrate 11, and the outer surface 12o of encapsulation 12 are coplanar. The lower surface 10b of substrate 10 and the lower surface 12b of encapsulation 12 are coplanar. The lower surface 10b of substrate 10 is exposed by encapsulation 12. In some embodiments, encapsulation 12 may completely encapsulate substrate 11. In such embodiments, the outer surface 11o of substrate 11 may be completely covered by encapsulation 12.

[0031] Figure 2A This is a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present invention. The semiconductor device package 2 includes a substrate 10, a substrate 11, an encapsulation 22, a connection element 13, and electronic components 14, 15, 16, and 17.

[0032] Substrate 11 has an upper surface 11u, an outer / lateral surface 11o, and a lower surface 11b. The outer surface 11o of substrate 11 extends from the upper surface 11u to the lower surface 11b. In some embodiments, substrate 11 includes a motherboard. Electronic components 14 and 15 are disposed on the upper surface 11u of substrate 11. Electronic components 16 and 17 are disposed on the lower surface 11b of substrate 11.

[0033] Substrate 10 has an upper surface 10u, an outer / lateral surface 10o, and a lower surface 10b. The outer surface 10o of substrate 10 extends from the upper surface 10u to the lower surface 10b. The outer surface 10o of substrate 10 and the outer surface 11o of substrate 11 are coplanar. Substrate 10 may include a dielectric layer 101. The dielectric layer 101 is adjacent to the lower surface 10b. Substrate 10 may include a conductive pad surrounded by the dielectric layer 101. In some embodiments, the dielectric layer 101 may be a solder resist layer. The dielectric layer 101 may be omitted. Substrate 10 is adjacent to substrate 11. Substrate 10 is electrically connected to substrate 11 via a connection element 13. Substrate 10 defines a space. Electronic components 16 and 17 are disposed in the space of substrate 10. Substrate 11 covers the space. Substrate 10 extends horizontally.

[0034] Encapsulation 22 has an upper surface 22u, an outer / lateral surface 22o, and a lower surface 22b. The outer surface 22o of encapsulation 22 may extend from the upper surface 22u to the lower surface 22b (e.g., it may extend around one side of substrate 11, not shown). Encapsulation 22 encapsulates substrates 10 and 11. Encapsulation 22 encapsulates electronic components 14, 15, 16, and 17. The outer surface 10o of substrate 10, the outer surface 11o of substrate 11, and the outer surface 22o of encapsulation 22 are coplanar. The lower surface 10b of substrate 10 is exposed by encapsulation 22. In some embodiments, encapsulation 22 may completely encapsulate substrate 11. In such embodiments, the outer surface 11o of substrate 11 may be completely covered by encapsulation 22.

[0035] Encapsulation 22 includes a portion 221. The portion 221 protrudes below (or beyond) the substrate 10. The portion 221 protrudes below the dielectric layer 101 of the substrate 10. The lower surface 22b of encapsulation 22 is the surface of the portion 221 and protrudes below the surface 10b of the substrate 10. Encapsulation 22 may substantially fill the space defined by the substrate 10.

[0036] Figure 2B This is a cross-sectional view of a semiconductor device package 2 comprising a substrate 10' and an encapsulation 22' according to some embodiments of the present invention, and shows... Figure 2A An enlarged view of the area defined by the dashed line.

[0037] The substrate 10' has an upper surface 10'u, an outer / lateral surface 10'o, and a lower surface 10'b. The substrate 10' includes a dielectric layer 101'. The dielectric layer 101' may be a solder resist layer. The substrate 10' defines a space. Electronic components 16 and 17 are disposed in the space of the substrate 10'.

[0038] The substrate 10' is slightly tilted (e.g., relative to the central portion of the semiconductor device package 2, and / or relative to a centrally positioned electronic component, such as electronic component 17). The central portion of the substrate 10' is higher than the peripheral portion of the substrate 10' (e.g., the central portion of the substrate 10' is closer to the substrate 11 than the peripheral portion of the substrate 10'). The inner lateral surface of the substrate 10' may be higher than the outer lateral surface 10'o, and the substrate 10' is encapsulated by an encapsulant 22'. The encapsulant 22' includes a portion 221' having a lower surface 22'b. The portion 221' protrudes below at least a portion of the substrate 10'. The portion 221' protrudes below at least a portion of the dielectric layer 101' of the substrate 10'. The lower surface 22'b of the portion 221' protrudes below at least a portion of the surface 10'b of the substrate 10'. The central portion of the lower surface 22'b may protrude further than the outer portion of the lower surface 22'b.

[0039] Figure 2C This is a cross-sectional view of a semiconductor device package 2 comprising a substrate 10″ and an encapsulation 22″ according to some embodiments of the present invention, and shows... Figure 2A An enlarged view of the area defined by the dashed line.

[0040] The substrate 10″ has an upper surface 10″u, an outer / lateral surface 10″o, and a lower surface 10″b. The substrate 10″ includes a dielectric layer 101″ and a conductive pad 102″. The dielectric layer 101″ may be a solder resist layer. The dielectric layer 101″ surrounds the conductive pad 102″. The substrate 10″ defines a space. Electronic components 16 and 17 are disposed within the space of the substrate 10″.

[0041] The substrate 10″ is slightly tilted (e.g., relative to the central portion of the semiconductor device package 2, and / or relative to a centrally positioned electronic component, such as electronic component 17). The central portion of the substrate 10″ is higher than the peripheral portion of the substrate 10″ (e.g., the central portion of the substrate 10″ is closer to the substrate 11 than the peripheral portion of the substrate 10″). The inner lateral surface of the substrate 10″ may be higher than the outer lateral surface 10″o, and the substrate 10″ is encapsulated by an encapsulant 22″. The encapsulant 22″ includes a portion 221″ having a lower surface 22″b. The portion 221″ protrudes below at least a portion of the substrate 10″. The portion 221″ protrudes below at least a portion of the dielectric layer 101″ of the substrate 10″. The lower surface 22″b of the portion 221″ protrudes below at least a portion of the surface 10″b of the substrate 10″. The portion 221″ covers a portion of the substrate 10″. The portion 221″ partially covers the lower surface 10″b of the substrate 10″. A portion 221″ partially covers a portion of the dielectric layer 101″. The portion 221″ on the substrate 10″ and the conductive pad 102″ are separated by a distance. In some embodiments (not shown), the central portion of the lower surface 22″b may protrude further than the outer portion of the lower surface 22″b.

[0042] Figure 3A This is a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present invention. The semiconductor device package 3 includes a substrate 30, a substrate 11, an encapsulation 32, a connection element 13, electronic components 14, 15, 16, 17, and a conductive layer 38.

[0043] Substrate 11 has an upper surface 11u, an outer / lateral surface 11o, and a lower surface 11b. The outer surface 11o of substrate 11 extends from the upper surface 11u to the lower surface 11b. In some embodiments, substrate 11 may include a motherboard. Electronic components 14 and 15 are disposed on the upper surface 11u of substrate 11. Electronic components 16 and 17 are disposed on the lower surface 11b of substrate 11.

[0044] Substrate 30 has an upper surface 30u, an outer / lateral surface 30o, and a lower surface 30b. The outer surface 30o of substrate 30 extends from the upper surface 30u to the lower surface 30b. The outer surface 30o of substrate 30 and the outer surface 11o of substrate 11 (generally parallel to each other) are offset from each other and are not coplanar. In some embodiments, substrate 30 may include a frame plate. Substrate 30 may include a dielectric layer 301, a conductive pad 302, and a conductive layer 303. In some embodiments, the conductive pad 302 may be replaced by a solder bump. The conductive pad 302 is surrounded by the dielectric layer 301. In some embodiments, the dielectric layer 301 may be a solder resist layer. The dielectric layer 301 may be omitted. The conductive layer 303 may be a ground layer. The conductive layer 303 is exposed from the outer surface 30o. Substrate 30 is adjacent to substrate 11. Substrate 30 is electrically connected to substrate 11 via a connection element 13. Substrate 30 defines a space. Electronic components 16 and 17 are disposed in the space of substrate 30. Substrate 11 covers the space.

[0045] Encapsulation 32 has an upper surface 32u, an outer / lateral surface 32o, and a lower surface 32b. Encapsulation 32 encapsulates substrates 30 and 11. Encapsulation 32 encapsulates electronic components 14, 15, 16, and 17. The outer surface 30o of substrate 30 and the outer surface 32o of encapsulation 32 are coplanar. The lower surface 30b of substrate 30 is exposed by encapsulation 32. Encapsulation 32 completely encapsulates substrate 11. The outer surface 11o of substrate 11 is completely covered by encapsulation 32. The outer surface 11o of substrate 11 and the outer surface 32o of encapsulation 32 are spaced apart by a non-zero distance. The outer surface 11o of substrate 11 and the outer surface 32o of encapsulation 32 (generally parallel to each other) are offset from each other and are not coplanar.

[0046] Encapsulation 32 includes a portion 321. The portion 321 protrudes below the substrate 30. The portion 321 protrudes below the dielectric layer 301 of the substrate 30. The lower surface 32b of the portion 321 protrudes below the surface 30b of the substrate 30.

[0047] A conductive layer 38 is disposed on the outer surface 30o of the encapsulant 32 and the substrate 30. The conductive layer 38 is in contact with the conductive layer 303. In some embodiments, the conductive layer 38 may be a shielding layer.

[0048] Figure 3B This is a cross-sectional view of a semiconductor device package 3' according to some embodiments of the present invention. The semiconductor device package 3' includes a substrate 30', a substrate 11, an encapsulation 32', a connection element 13, electronic components 14, 15, 16, 17, and a conductive layer 38'.

[0049] Substrate 11 has an upper surface 11u, an outer / lateral surface 11o, and a lower surface 11b. The outer surface 11o of substrate 11 extends from the upper surface 11u to the lower surface 11b. In some embodiments, substrate 11 may include a motherboard. Electronic components 14 and 15 are disposed on the upper surface 11u of substrate 11. Electronic components 16 and 17 are disposed on the lower surface 11b of substrate 11.

[0050] Substrate 30' has an upper surface 30'u, an outer / lateral surface 30'o, and a lower surface 30'b. The outer surface 30'o of substrate 30' and the outer surface 11o of substrate 11 are coplanar. In some embodiments, substrate 30 may include a frame plate. Substrate 30' may include a dielectric layer 301', a conductive pad 302', and a conductive layer 303'. The conductive pad 302' is surrounded by the dielectric layer 301'. In some embodiments, the dielectric layer 301' may be a solder resist layer. The dielectric layer 301' may be omitted. The conductive layer 303' may be a ground layer. The conductive layer 303' is exposed from the outer surface 30'o. Substrate 30' is adjacent to substrate 11. Substrate 30' is electrically connected to substrate 11 via a connection element 13. Substrate 30' defines a space. Electronic components 16 and 17 are disposed in the space of substrate 30'. Substrate 11 covers the space. In some embodiments, substrate 11 may include a ground layer exposed from the outer surface 11o of substrate 11. Conductive layer 38' may contact the ground layer of substrate 11 and may be electrically connected to connection element 13.

[0051] Encapsulation 32' has an upper surface 32'u, an outer / lateral surface 32'o, and a lower surface 32'b. Encapsulation 32' encapsulates substrate 30' and substrate 11. Encapsulation 32' encapsulates electronic components 14, 15, 16, and 17. The outer surface 30'o of substrate 30' and the outer surface 32'o of encapsulation 32' are coplanar. The lower surface 30'b of substrate 30' is exposed by encapsulation 32'.

[0052] Encapsulation 32' includes portion 321'. Portion 321' protrudes below substrate 30'. Portion 321' protrudes below dielectric layer 301' of substrate 30'. Lower surface 32'b of portion 321' protrudes below surface 30'b of substrate 30'.

[0053] A conductive layer 38' is disposed on the outer surface 30'o of the encapsulant 32' and the substrate 30'. The conductive layer 38' is in contact with the conductive layer 303'. The conductive layer 38' is in contact with the outer surface 11o of the substrate 11. In some embodiments, the conductive layer 38 may be a shielding layer.

[0054] Figures 4A to 4DSome embodiments of a method for manufacturing a semiconductor device package 1 according to some embodiments of the present invention are described. In some embodiments, a semiconductor device package 2 may be manufactured similarly by the described method.

[0055] See Figure 4A A method for manufacturing a semiconductor device package 1 includes providing a substrate 10 having an upper surface 10u, an outer / lateral surface 10o, and a lower surface 10b opposite to the surface 10u. The substrate 10 may include a frame plate. The substrate 10 includes a strip or a panel. The substrate 10 includes a dielectric layer 101. The substrate 10 may include a conductive pad surrounded by the dielectric layer 101. In some embodiments, the dielectric layer 101 may be a solder resist layer. A connection element 13″ is disposed on the upper surface 10u of the substrate 10. The connection element 13″ may include solder material.

[0056] An adhesive layer 100 is disposed on the lower surface 10b of the substrate 10. Individual semiconductor device modules 40 are disposed on the upper surface 10u of the substrate 10. The semiconductor device module 40 includes a substrate 11 and electronic components 14, 15, 16, and 17. The substrate 11 may include a motherboard. The substrate 11 has an upper surface 11u, an outer / lateral surface 11o, and a lower surface 11b. Electronic components 14 and 15 are disposed on the upper surface 11u of the substrate 11. Electronic components 16 and 17 are disposed on the lower surface 11b of the substrate 11. Connecting elements 13' are disposed on the semiconductor device module 40. Connecting elements 13' may contain solder material.

[0057] In some embodiments, the strips or panels of the semiconductor device module 40 are preprocessed through a single-splitting operation. The strips or panels of the semiconductor device module 40 are divided into multiple units.

[0058] See Figure 4B The semiconductor device module 40 is mounted on the substrate 10. The semiconductor device module 40 is electrically connected to the substrate 10 via a connection element 13 (e.g., a connection element formed by connection element 13' and connection element 13″).

[0059] See Figure 4C The substrate 10 and the semiconductor device module 40 are encapsulated in a single molding operation. The substrate 10 and the semiconductor device module 40 are encapsulated by an encapsulant 12. During this single molding operation, a carrier may be provided on an adhesive layer 100. The carrier covers the substrate 10, the adhesive layer 100, and the semiconductor device module 40. The carrier may be a mold. This single molding operation can significantly reduce the cost of semiconductor device packaging manufacturing and increase throughput (e.g., compared to processes involving more than a single molding operation).

[0060] See Figure 4DThe adhesive layer 100 is then removed. Subsequently, a separation operation is performed. During the separation operation, the substrate 10 and the encapsulation 12 may be sawn. In some embodiments, the substrate 11 of the semiconductor device module 40 is sawn during the separation operation.

[0061] Figure 5 This is a cross-sectional view of a semiconductor device package molded in a carrier 500 according to some embodiments of the present invention. The carrier 500 is provided on an adhesive layer 100. The carrier 500 covers the substrate 10, the adhesive layer 100, and the semiconductor device module 40. The carrier 500 may be a mold.

[0062] The carrier 500 includes portions 501 and 502. Portion 501 is pressed onto the substrate 10. Portion 502 is pressed onto the adhesive layer 100. The substrate 10, adhesive layer 100, and semiconductor device module 40 are disposed between portions 501 and 502. The adhesive layer 100 is disposed between the substrate 10 and portion 502. Portion 501 may not directly press or contact the semiconductor device module 40. Portion 501 may not directly press or contact the substrate 11 of the semiconductor device module 40. The substrate 10 and semiconductor device module 40 are encapsulated within the carrier 500. Because the carrier 500 is disposed on the adhesive layer 100, the carrier 500 can directly press the periphery of the substrate 10 (e.g., on the surface 10u of the substrate 10) and can avoid direct pressing or contact with the substrate 11. This helps ensure that the connecting element 13 does not deform during the molding operation.

[0063] Semiconductor device package 1 or 2 can be manufactured using carrier 500.

[0064] Figure 6A This is a cross-sectional view of a semiconductor device package molded in a carrier 500' according to some embodiments of the present invention. The carrier 500' is provided on an adhesive layer 100. The carrier 500' covers the substrate 10', the adhesive layer 100, and the semiconductor device module 40. The carrier 500' may be a mold.

[0065] The carrier 500' comprises a portion 501 and a portion 502'. The portion 502' includes a protrusion 502'a ( Figure 6B(As shown in the diagram). Part 501 is pressed onto substrate 10'. Part 502' is pressed onto substrate 10' (e.g., via adhesive layer 100). Substrate 10', adhesive layer 100, and semiconductor device module 40 are disposed between part 501 and part 502'. Adhesive layer 100 is disposed between substrate 10' and part 502'. Space 503 is defined by two adjacent portions of part 502'. Space 503 is defined by adhesive layer 100 and two adjacent portions of part 502'. Space 503 is located below substrate 10'. Protrusion 502'a is located below the inner periphery of substrate 10'. Protrusion 502'a correspondingly supports the inner peripheral portion of substrate 10'. Because the injection force of the molding operation can be extremely large, in some comparative embodiments, the injection encapsulant can flow or be pushed to and cover the lower surface 10'b of substrate 10' (which can cause disconnection problems). The design of carrier 500' helps prevent the encapsulated material from flowing or being pushed to the lower surface 10'b of substrate 10' and covers the lower surface 10'b.

[0066] Figure 6B This is a cross-sectional view of a carrier 500' according to some embodiments of the present invention, and shows... Figure 6A An enlarged view of the area demarcated by the dashed line. The protrusion 502'a of the carrier 500' supports the inner peripheral portion of the substrate 10', and may not fully support the central portion of the substrate 10'. Therefore, the substrate 10' may deform slightly during the molding operation. The substrate 10' may be slightly tilted. The central portion of the substrate 10' may be higher than the peripheral portion of the substrate 10'.

[0067] The surface 502'u of portion 502' and the lower surface of adhesive layer 100 are separated by a distance D1. Distance D1 ranges from approximately 0.01 mm to approximately 0.02 mm. The outer surface of protrusion 502'a and the inner surface of substrate 10' are offset by a distance D2. Distance D2 ranges from approximately 0.2 mm to approximately 0.25 mm.

[0068] Based on the design of carrier 500', it can be manufactured Figure 2B and Figure 2C Substrates 10' and 10″.

[0069] Figure 7 This is a cross-sectional view of a comparative semiconductor device package 6. The semiconductor device package 6 includes a substrate 60, a substrate 61, an encapsulation 62, a connecting element 63, and electronic components 14, 15, 16, and 17.

[0070] Substrate 61 has an upper surface 61u, an outer / lateral surface 61o, and a lower surface 61b. Substrate 11 contains a motherboard. Electronic components 14 and 15 are disposed on the upper surface 61u of substrate 61. Electronic components 16 and 17 are disposed on the lower surface 61b of substrate 61.

[0071] Substrate 60 has an upper surface 60u, an outer / lateral surface 60o, and a lower surface 60b. Substrate 60 may include a frame plate. Substrate 60 may include a solder mask and conductive pads. The conductive pads are surrounded by the solder mask. Substrate 60 is adjacent to substrate 61. Substrate 60 is electrically connected to substrate 61 via a connection element 63. The connection element 63 is a solder bump. Substrate 60 defines a space. Electronic components 16 and 17 are disposed in the space of substrate 60. Substrate 61 covers the space.

[0072] Encapsulation 62 has an upper surface 62u, an outer / lateral surface 62o, and a lower surface 62b. The encapsulation includes portions 621 and 622. Encapsulation 62 encapsulates substrates 60 and 61. Encapsulation 62 encapsulates electronic components 14, 15, 16, and 17. The lower surface 60b of substrate 10 is lower than the lower surface 62b of encapsulation 62. The lower surface 60b of substrate 60 is exposed by encapsulation 62. A portion of the inner peripheral surface of substrate 60 is exposed by encapsulation 62.

[0073] Figures 8A to 8D Some embodiments illustrating methods for manufacturing semiconductor device packages 6.

[0074] See Figure 8A A method for manufacturing a semiconductor device package 6 includes providing a substrate 61 having an upper surface 61u, an outer / lateral surface 61o, and a lower surface 61b opposite to surface 61u. The substrate 61 includes a strip or a panel. A substrate 60 is provided on the substrate 61. The substrate 60 has an upper surface 60u, an outer / lateral surface 60o, and a lower surface 60b opposite to surface 60u. The substrate 60 is mounted on the lower surface 61b of the substrate 61 via a connecting element 63. The substrate 60 includes a strip or a panel. Electronic components 16 and 17 are disposed on the lower surface 61b of the substrate 61.

[0075] See Figure 8B An adhesive layer 600 is provided on a substrate 60, and a first molding operation is subsequently performed. During the first molding operation, a mold can directly press the substrate 61 and the adhesive layer 600. The substrates 60 and 61, as well as electronic components 16 and 17, are encapsulated by an encapsulant 621. Because the mold will directly press the substrate 61 and the adhesive layer 600 during the first molding operation, the lower surface 60b of the substrate 60 and the lower surface of the encapsulant 621 are not coplanar.

[0076] Furthermore, since the substrate 61 is pressed by the mold, the connecting element 63 may deform due to the pressure from the mold. Deformation of the connecting element 63 may cause delamination between the connecting element 63 and the encapsulation 621.

[0077] See Figure 8C Electronic components 14 and 15 are disposed on the upper surface 61u of substrate 61. Adhesive layer 600 is removed.

[0078] See Figure 8D A second molding operation is then performed. Substrate 61 and electronic components 14 and 15 are encapsulated by encapsulant 622. Encapsulant 62, containing encapsulants 621 and 622, encapsulates substrate 60, substrate 61, and electronic components 14, 15, 16, and 17. Subsequently, a separation operation is performed. The lower surface 60b of substrate 10 is higher than the lower surface of encapsulant 62.

[0079] As used herein and unless otherwise defined, the terms “substantially,” “essentially,” “approximately,” and “about” are used to describe and account for minor variations. When used in conjunction with an event or situation, the terms may cover situations where the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with numerical values, the terms may cover a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” may mean that two surfaces are coplanar within a few micrometers, for example, within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm. For example, "essentially parallel" might refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "essentially perpendicular" might refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0080] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0081] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to transfer electric current. Conductive materials typically indicate those that exhibit very little or no resistance to current flow. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0082] Although the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Artistic representations of the invention may differ from actual devices due to manufacturing processes and tolerances. Other embodiments of the invention may exist that are not specifically described. This specification and the drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, the order and grouping of operations are not limiting unless specifically indicated herein.

Claims

1. A semiconductor device package comprising: A first substrate has a first surface and a second surface opposite to the first surface, the first substrate defining a space, the first substrate including a solder resist layer and a conductive pad surrounded by the solder resist layer, the solder resist layer being adjacent to the second surface, and a central portion of the first substrate being higher than a peripheral portion of the first substrate. A second substrate is adjacent to the first surface of the first substrate and covers the space; as well as An encapsulation that encapsulates a first substrate and a second substrate, the encapsulation comprising a portion having a lower surface that protrudes below at least a portion of the solder mask layer on the first substrate, the central portion of the lower surface of the encapsulation portion protruding further than the outer portion of the lower surface, the encapsulation portion partially covering a portion of the solder mask layer. The second substrate is completely encapsulated by the encapsulant.

2. The semiconductor device package of claim 1, wherein the second substrate has a first surface and a second surface opposite to the first surface of the second substrate, and the semiconductor device package further comprises: A first electronic component is disposed on the first surface of the second substrate; as well as A second electronic component is disposed on the second surface of the second substrate and in the space.

3. The semiconductor device package of claim 1, wherein the encapsulant directly contacts the outer surface of the second substrate.

4. The semiconductor device package of claim 3, wherein the first substrate has an outer surface and includes a ground layer exposed from the outer surface.

5. The semiconductor device package of claim 4, further comprising a conductive layer disposed on the outer surface of the encapsulant and the first substrate and in contact with the ground layer.

6. The semiconductor device package of claim 1, wherein the first substrate has an outer surface and includes a ground layer exposed from the outer surface.

7. The semiconductor device package of claim 6, further comprising a conductive layer disposed on the outer surface of the encapsulant and the first substrate and in contact with the ground layer.

8. The semiconductor device package of claim 1, wherein the portion of the encapsulation partially covers the second surface of the first substrate.

9. The semiconductor device package of claim 8, wherein the portion of the encapsulation and the conductive pad are separated by a non-zero distance.

10. The semiconductor device package of claim 9, wherein the central portion of the first substrate is closer to the second substrate than the peripheral portion of the first substrate.

11. A semiconductor device package comprising: A first substrate has a first surface and a second surface opposite to the first surface, and has a lateral surface and includes a ground layer exposed from the lateral surface. The first substrate defines a space. The first substrate includes a solder resist layer and a conductive pad surrounded by the solder resist layer, the solder resist layer being adjacent to the second surface. The central portion of the first substrate is higher than the peripheral portion of the first substrate. A second substrate is adjacent to the first substrate and covers the space; An encapsulation that encapsulates the second substrate and fills the space, the encapsulation comprising a portion having a lower surface that protrudes below at least a portion of the solder mask layer of the first substrate, the central portion of the lower surface of the portion of the encapsulation protruding further than the outer portion of the lower surface, the portion of the encapsulation partially covering a portion of the solder mask layer; as well as A conductive layer is disposed on the lateral surface of the encapsulation and the first substrate, the conductive layer being in contact with the ground layer. The outer surface of the second substrate is separated from the conductive layer by the encapsulant.

12. The semiconductor device package of claim 11, wherein the second substrate is completely encapsulated by the encapsulant.

13. The semiconductor device package of claim 11, wherein the second substrate has a lateral surface, and the lateral surface of the second substrate and the lateral surface of the first substrate are offset from each other.

14. The semiconductor device package of claim 11, further comprising: A first electronic component is disposed on the upper surface of the second substrate; as well as A second electronic component is disposed on the lower surface of the second substrate and in the space.

15. A semiconductor device package comprising: A first substrate has a first surface and a second surface opposite to the first surface, and defines a space. The first substrate includes a solder resist layer and a conductive pad surrounded by the solder resist layer. The solder resist layer is adjacent to the second surface of the first substrate. The central portion of the first substrate is higher than the peripheral portion of the first substrate. A second substrate is adjacent to the first substrate and covers the space, the second substrate having a first surface, a second surface opposite to the first surface, and a third surface extending from the first surface to the second surface; as well as A first electronic component is disposed on the first surface of the second substrate; A second electronic component is disposed on the second surface of the second substrate and in the space of the first substrate; as well as An encapsulation having a surface and encapsulating a first substrate, a second substrate, a first electronic component, and a second electronic component, the encapsulation including a portion having a lower surface that protrudes below at least a portion of the solder mask layer on the first substrate, the central portion of the lower surface of the encapsulation further protruding than the outer portion of the lower surface, the encapsulation partially covering a portion of the solder mask layer. The third surface of the second substrate is offset from the surface of the encapsulant by a non-zero distance, wherein the encapsulant contacts the third surface of the second substrate.

16. The semiconductor device package of claim 15, wherein the first substrate has a lateral surface and includes a ground layer exposed from the lateral surface of the first substrate, and the semiconductor device package further includes a conductive layer disposed on the encapsulation and the lateral surface of the first substrate and in contact with the ground layer.

17. A method for manufacturing a semiconductor device package, comprising: A first substrate is provided having a first surface and a second surface opposite to the first surface, the first substrate defining a space, wherein the first substrate includes a solder resist layer and a conductive pad surrounded by the solder resist layer, the solder resist layer being adjacent to the second surface; An adhesive layer is disposed on the second surface of the first substrate; A semiconductor device module is provided on the first surface of the first substrate, wherein the semiconductor device module includes: a second substrate having a first surface and a second surface opposite to the first surface of the second substrate; and a plurality of first electronic components disposed on the first surface of the second substrate; And a plurality of second electronic components disposed on the second surface of the second substrate; as well as The first substrate and the semiconductor device module are encapsulated using an encapsulant in a single molding operation, wherein the central portion of the first substrate is higher than the peripheral portion of the first substrate, the encapsulant includes a portion having a lower surface that protrudes below at least a portion of the solder resist layer of the first substrate, the central portion of the lower surface of the encapsulant further protruding than the outer portion of the lower surface, and the encapsulant partially covering a portion of the solder resist layer.

18. The method of claim 17, wherein the first substrate comprises a plurality of peripheral portions, and the method further comprises: A carrier is provided on the adhesive layer, wherein the carrier includes a plurality of protrusions supporting the plurality of peripheral portions of the first substrate.

19. The method of claim 17, wherein the encapsulation comprises providing a force on the first substrate, the peripheral portion of the first substrate being deformed by the force.

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