Electronic device with short circuit protection element, manufacturing method and design method

Abstract

The present disclosure relates to electronic devices, manufacturing methods, and design methods with short-circuit protection elements. For example, an electronic device includes: a control terminal extending on a first surface of a substrate; a first conductive terminal extending in the substrate at the first surface of the substrate; a first insulating layer sandwiched between the control terminal and the first conductive terminal; a conductive path that can be biased under a bias voltage; and a protection element coupled to the control terminal and the conductive path, the protection element forming an electrical connection between the control terminal and the conductive path, and configured to melt and thereby interrupt the electrical connection when there is a leakage current above a critical threshold between the control terminal and the first conductive terminal through the first insulating layer.

Description

Technical Field

[0001] The present disclosure relates to an electronic device (particularly a power MOSFET) provided with a protection element, a manufacturing method for the electronic device, and a method for designing the electronic device. Particularly, the protection element is a fuse. Background Art

[0002] A large number of scientific studies have shown that MOSFET devices made of silicon carbide (SiC) have good switching performance. From an industrial perspective, in addition to switching performance, SiC devices also have good structural strength, which is a desirable feature in power systems.

[0003] During the manufacturing steps and handling of SiC wafers, the interaction between mechanical devices and SiC wafers can lead to the release of debris due to the high hardness of SiC. As a result, these debris are permanently deposited on the surface of the wafer and form local defects, which can adversely affect the functionality of the final MOSFET device.

[0004] Regarding this, Figure 1A A transistor 1, specifically a vertical channel MOSFET, is shown in a side cross-sectional view, comprising: a SiC substrate 8; a gate region 4, for example made of polysilicon, arranged on a first surface of the substrate 8; a body region 5, extending in the substrate 8 at the first surface; a source region 6, extending in the body region 5 at the first surface of the substrate 8; and a drain region 7, extending on a second surface of the substrate 8 opposite to the first surface.

[0005] The transistor 1 has a debris particle 2 inserted between the gate region 4 and the source region 6. In addition, the gate oxide layer 10 extends between the substrate 8 and the gate region 4 on the source region 6. Specifically, the particle 2 extends through the entire thickness of the gate oxide layer 10, electrically connecting the source region 6 and the gate region 4 to each other. Thus, the particle 2 constitutes a point defect that short-circuits the gate region 4 and the source region 6.

[0006] Figure 1B yes Figure 1A The circuit representation of transistor 1.

[0007] In use, when the gate region 4 is biased at a voltage V GS When biased, particles 2 form a conductive path, allowing the current i SC Flows between the gate region 4 and the source region 6 (hereinafter also referred to as "short-circuit current"). SC In this case, transistor 1 fails.

[0008] Similar problems may arise in the case of defects originating from the manufacturing process of the gate oxide, thereby creating a leakage path due to a direct or tunneling connection between the gate region 4 and the source region 6 .

[0009] Commercial MOSFET devices are usually made of Figure 1A and Figure 1B The MOSFET device is composed of a plurality of transistors 1 of the type shown, which are connected in parallel and cooperate with each other to properly manage the current +6 generated by the specific application in which they are used. In the event of a failure of only one transistor 1 belonging to the MOSFET device, the entire MOSFET device must also be discarded, which increases the manufacturing costs. Summary of the invention

[0010] According to the present disclosure, there are provided an electronic device provided with a protection element, a power MOSFET device including a plurality of the electronic devices, a manufacturing method for the electronic device, and a method for designing the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a better understanding of the present disclosure, preferred embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0012] Figure 1A shows in cross-section a SiC MOSFET according to an embodiment of known type having a defect through the gate oxide resulting in a direct electrical connection between the gate terminal and the source terminal;

[0013] Figure 1B Shows Figure 1A Circuit diagram of MOSFET;

[0014] Figure 2 A circuit diagram showing a MOSFET provided with a fuse-type protection element according to one aspect of the present disclosure;

[0015] Figure 3 The top view shows the Figure 2 A layout of a portion of a MOSFET device of a plurality of MOSFETs;

[0016] Figure 4 According to one embodiment of the present disclosure, Figure 3 The section line IV-IV is taken Figure 3 A side cross-sectional view of a MOSFET device;

[0017] Figure 5 According to another embodiment of the present disclosure, Figure 3 The section line IV-IV is taken Figure 3 A side cross-sectional view of a MOSFET device; and

[0018] Figure 6 According to another embodiment of the present disclosure, Figure 3 The section line IV-IV is taken Figure 3A side cross-sectional view of a MOSFET device. DETAILED DESCRIPTION

[0019] Figure 2 FIG. 1 shows an equivalent circuit of a transistor 20 according to one aspect of the present disclosure, the transistor 20 being specifically a vertical channel MOSFET, more specifically a power MOSFET. Figure 1A and Figure 1B As briefly described, transistor 20 comprises a gate region 24 (forming a control terminal G) which, in use, may be coupled to a bias voltage V GS a generator 23; a source region 26 (forming a first conductive terminal S); and a drain region 27 (forming a second conductive terminal D).

[0020] Specifically, according to the present disclosure, the transistor includes a protection element 21 between a gate region 24 and a generator 23. More specifically, the protection element 21 is a fuse configured to be disconnected in the presence of a fault caused by, for example, Figure 1A The existence of point defects represented in the figure, the short-circuit current i caused by particle 2 SC (like Figure 1B The electrical connection between the generator 23 and the gate region 24 is interrupted when the generator 23 and the gate region 24 are interrupted.

[0021] Figure 3 A MOSFET device 30 according to the present disclosure is shown, which is composed of Figure 2 A plurality (two or more) of transistors 20 of the type shown are connected in parallel with one another. In the event of a failure of one of the transistors 20 belonging to the MOSFET device 30, the corresponding fuse 21 blows, causing a short-circuit current i to flow between the generator 23 and the source region 26 via the gate region 24 and the point defect 2. SC of interruption.

[0022] Figure 3 A portion of a MOSFET device 30 according to one embodiment of the present disclosure is shown in a three-axis Cartesian reference system X, Y, Z; specifically, the MOSFET device 30 is shown in a top view in plane XY, and only essential elements for understanding the present embodiment are shown.

[0023] The MOSFET device 30 includes an active region 32, a guard region 34, and a connection region 36. The guard region 34 is interposed between the active region 32 and the connection region 36.

[0024] In detail, the active area 32 comprises a plurality of gate regions 24 and a plurality of source regions 26 in the form of stripes, which extend in a known manner along respective main directions parallel to the axis Y. Each gate region 24 (particularly made of polysilicon) has a width d measured along the axis X. G, for example included between 1 μm and 3 μm.

[0025] The protection zone 34 includes a plurality of protection elements 21 (especially fuses), each of which is electrically connected to a corresponding gate zone 24. Figure 3 In the embodiment of the present invention, each fuse 21 has structural and electrical continuity with the corresponding gate region 24. In other words, the fuse 21 and the corresponding gate region 24 form an integral structure. According to one aspect of the present disclosure, the gate region 24 and the fuse 21 are both made of polysilicon.

[0026] Each fuse 21 has a substantially parallelepiped shape with a width d measured along the axis X. P , which is smaller than the corresponding width d of the gate region 24 coupled thereto. G For example, the width d P Included between 1μm and 3μm.

[0027] The connection region 36 is made of a conductive material (here, polysilicon), is electrically coupled to each fuse 21, and is also configured to be connected to the fuse 21 via metallization ( Figure 3 ) and is coupled to the generator 23 in a manner known per se.

[0028] Specifically, in the present embodiment, each fuse 21 has structural and electrical continuity with the connection region 36. In other words, the connection region 36, the plurality of fuses 21, and the plurality of gate regions 24 form an integral structure.

[0029] Figure 4 Shows Figure 3 MOSFET device 30 of the cross-sectional view; specifically, Figure 4 Shows Figure 3 A portion of the transistor 20 is taken along the cross-sectional line IV-IV.

[0030] In detail, transistor 20 comprises a substrate 48, in particular made of SiC, having a first surface 48a and a second surface 48b opposite each other. In particular, in the present embodiment, the term "substrate" contemplates a structural element that may include one or more epitaxial layers grown on a base substrate.

[0031] An insulating layer 52 (in particular a gate oxide) extends above the first surface 48a and is made of, for example, deposited silicon oxide (SiO2) and has a width measured along the axis Z and including and The thickness between.

[0032] On the insulating layer 52 , the gate region 24 extends at the active region 32 .

[0033] On the insulating layer 52, a field plate oxide layer 54 (particularly made of TEOS) extends at the protection zone 34 and to the connection zone 36. The field plate oxide layer 54 has a thickness measured along the axis Z, which, in the point corresponding to the protection zone 34, includes and The field plate oxide layer 54 has a thickness measured along the axis Z, which is included in the point corresponding to the connection area 36. and between.

[0034] On the field plate oxide layer 54, the fuse 21 (having a thickness h measured along the axis Z, including and In other words, the fuse 21 has a cross section measured in the plane XZ (ie, the bottom area of ​​the fuse 21) which is included in the 0.5 μm 2 and 1.5 μm 2 between.

[0035] According to the present embodiment, the fuse 21 has electrical and structural continuity with the gate region 24. In addition, the fuse 21 has electrical and structural continuity with the connection region 36.

[0036] On the gate region 24 and the fuse 21, another insulating layer 56 extends at the active region 32, the protection region 34 and the connection region 36. The further insulating layer 56 (particularly made of TEOS) has a thickness measured along the axis Z, which is comprised between and between.

[0037] A metallization layer 58 (particularly made of Al / Si / Cu) having a thickness measured along the axis Z comprised between 2.5 μm and 3.5 μm extends over the further insulating layer 56 at the active zone 32. The metallization layer 56 forms Figure 2 The first conduction terminal S of transistor 2.

[0038] Another metallization layer 60, in particular made of TEOS, has a width measured along the axis Z and including and The thickness is between 1000 and 2000 Å, which extends over the further insulating layer 56 at the connection region 36. The further metallization layer 60 is a field plate metallization layer.

[0039] A passivation layer 62 , for example made of polyamide, extends over the active region 32 , the protection region 34 and the connection region 36 , in particular over the metallization layer 58 , the further insulating layer 56 and the further metallization layer 60 .

[0040] An interface layer 64, specifically made of nickel silicide, extends on the second surface 48b. A metallization layer 66, for example, made of Ti / Ni / Au, extends on the interface layer 64. The metallization layer 66 forms Figure 2 The second conductive terminal D of the transistor 20.

[0041] Under normal operating conditions, i.e. without Figure 1A In the case of defects of the type described above, there is no leakage current between the gate region 24 and the source region 26, or in any case, the possible leakage current is about 10 nA (for a gate bias voltage V of ±20 V in the region GS ), so it can be ignored. On the contrary, in the presence of the above defects, there may be a current of milliampere level or slightly smaller (for example, higher than 0.8mA) (i.e., short-circuit current i SC ).

[0042] The applicant has found that in use when the short-circuit current i SC When the current (approximately 1 mA) flows through the fuse 21 for approximately 1 ms, the following formula is used to generate 10 4 Temperature change ΔT of K level:

[0043]

[0044] Where ρ is the resistivity of the fuse 21 (10 in the case of polysilicon). -4 Ω·cm), c is the specific heat (700 J / kg·keV in the case of polycrystalline silicon), and D is the material density of the fuse 21 (2330 kg / m in the case of polycrystalline silicon). 3 ), h is the thickness of the fuse 21 along the axis Z, and d P is the width of the fuse 21 along the axis X.

[0045] The Applicant has also discovered that, during the time interval considered, this temperature variation ΔT causes the fuse 21 to blow, thereby isolating the transistor 20 from the generator 23 ( Figure 2 ).

[0046] The fuse 21 is designed so that a short circuit current i SC In the case of interrupting the electrical connection between the connection area 36 (connected to the generator 23 in use) and the gate area 24, the short-circuit current i SC The value depends on the bias voltage V GS , and in each case is higher than the leakage current observed under normal operating conditions. Specifically, the fuse 21 is designed to be SC changes its physical state (for example, from solid to molten or from solid to gas).

[0047] Therefore, in general, the fuse 21 is designed to interrupt the electrical connection between the connection region 36 and the gate region 24 (e.g., by changing the physical state) in the presence of a current above a critical threshold, where the critical threshold is at least one order of magnitude higher than the leakage current under normal operating conditions (e.g., the critical threshold is equal to or higher than 50nA).

[0048] Figure 5 Shown as Figure 4 An alternative embodiment of the MOSFET device 30 Figure 3 MOSFET device 30 is a cross-sectional view taken along section line IV-IV. Figure 4 The corresponding components are shown in Figure 5 The same reference numerals are used in the drawings and will not be described further.

[0049] exist Figure 5 In the embodiment of FIG. 5 , each transistor 20 has an opening 70 through the insulating layer 56 at the protection zone 34 to reach the fuse 21 . The passivation layer 62 extends within the opening 70 to contact the fuse 21 .

[0050] In the present embodiment, since silicon oxide has a higher mechanical strength than polyamide, the passivation layer 62 allows absorbing and weakening the products generated by the melting of the fuse 21 in a more effective manner than the insulating layer 56 .

[0051] Figure 6 Shown as Figure 4 and Figure 5 An alternative embodiment of the MOSFET 30 Figure 3 MOSFET device 30 of the embodiment of the invention is a cross-sectional view taken along the cross-sectional line IV-IV. Figure 4 and Figure 5 The corresponding components are shown in Figure 6 The same reference numerals are used in the drawings and will not be described further.

[0052] exist Figure 6 In the embodiment of the present invention, the gate region 24 and the connection region 36 partially extend on the field plate oxide layer 54 at the protection zone 34 without direct electrical contact. More specifically, the respective portions of the gate region 24 and the connection region 36 extending at the protection zone 34 are electrically insulated and physically isolated by an insulating element 80 made of, for example, SiO2. In addition, the gate region 24 and the respective portions of the connection region 36 extending at the protection zone 34 are electrically coupled together by a conductive element 82 (particularly made of metal (e.g., Al / Si / Cu)), which extends through the insulating layer 56 to electrically contact the respective portions of the gate region 24 and the connection region 34 extending at the protection zone 34. The conductive element 82 is also covered by the passivation layer 62.

[0053] The conductive element 82 forms Figure 2 In one embodiment, the metal fuse 21 has a substantially parallelepiped shape with a thickness h measured along the Z axis and included between 2.5 μm and 3.5 μm and a width d measured along the X axis and included between 2.5 μm and 3.5 μm. P .

[0054] From examination of the characteristics of devices provided in accordance with the present disclosure, the advantages provided are apparent.

[0055] Specifically, in a MOSFET device formed by multiple transistors connected in parallel to each other and cooperating to properly manage the current required by the specific application in which they are used, in the event that only one transistor belonging to the MOSFET device fails, the functionality of the entire MOSFET device can be restored by disconnecting the single defective transistor, maintaining good electrical insulation characteristics and only a partial loss in the current capacity of the device.

[0056] Furthermore, in the event that the insulation between the gate and source terminals of one or more transistors of the MOSFET device degrades due to a leakage current greater than 0.8 mA, in use, the fuses corresponding to the one or more degraded transistors will blow, thereby automatically isolating them.

[0057] Finally, it is obvious that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of protection of the present disclosure.

[0058] For example, the present disclosure may be applied to a device having a substrate made of a material other than SiC, such as Si, GaN (gallium nitride), or glass.

[0059] In addition, the present disclosure also finds application in devices other than MOSFET, such as GaN power devices, LDMOS (laterally diffused MOS) transistors, VMOS (vertical MOS) transistors, DMOS (diffused MOS) transistors, CMOS (complementary MOS) transistors, or other integrated devices provided with a control terminal and at least one conductive terminal.

[0060] Furthermore, device 30 may include one or more transistors of the horizontal channel MOSFET type.

[0061] Furthermore, the device 30 may be formed of only one transistor 20. In this case, the blowing of the fuse 21 interrupts the operation of the entire device 30. This embodiment is useful in a case where the device 30 is integrated in a complex electronic system and is not important to the operation of the electronic system (for example, in the presence of redundancy), but a failure of the device 30 may jeopardize the operation of other elements of the electronic system.

[0062] In addition, Figure 4 and Figure 5 In the embodiment of the present invention, the fuse 21 may be made of a material different from the gate region 24 and / or the connection region 36, such as a metal or a conductive polymer, whose resistivity is less than 10Ω·cm.

[0063] Furthermore, the fuse 21 may have a geometric shape other than a parallelepiped shape, such as a cylindrical shape or a generally polyhedral shape.

[0064] According to a further embodiment, the protection element 21 is configured to be in a state where the physical state does not change but due to the presence of the short-circuit current i SC Failure of the protection element 21 (whether direct failure or failure indirectly caused by the presence of another element) interrupts the electrical connection between the connection region 36 and the gate region 24.

[0065] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the detailed description above. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents required by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. An electronic device comprising: A substrate having a first side and a second side, wherein the first side is opposite to the second side; a control terminal extending on the first surface of the substrate; a first conductive terminal extending in the substrate at the first side of the substrate; a first insulating layer, sandwiched between the control terminal and the first conductive terminal; a conductive path configured to be electrically coupled to a generator of a bias voltage; as well as A protection element is coupled to the control terminal and the conductive path, the protection element forms an electrical connection between the control terminal and the conductive path, and is configured to interrupt the electrical connection in response to a leakage current between the control terminal and the first conductive terminal through the first insulating layer being higher than a critical threshold. The electronic device according to claim 1 , wherein the protection element is a fuse. 3 . The electronic device according to claim 1 , wherein the protection element is made of a material having a resistivity of less than 10 Ω·cm, the material being selected from polysilicon, metal or conductive polymer. 4 . The electronic device according to claim 1 , wherein the protection element, the control terminal and the conductive path form a monolithic structure.

5. The electronic device according to claim 1, further comprising: a second insulating layer extending on the control terminal, the conductive path and the protection element and completely covering the protection element; as well as A passivation layer, made of a polymeric material, extends on the second insulating layer and has a mechanical resistance lower than that of the second insulating layer.

6. The electronic device according to claim 1, further comprising: a second insulating layer extending over the control terminal, the conductive path and the protection element; a passivation layer made of a polymeric material extending on said second insulating layer and having a mechanical resistance less than that of said second insulating layer; as well as An opening is formed through the thickness of the second insulating layer at the protection element, and the passivation layer and the protection element are in direct contact with each other. 7 . The electronic device according to claim 1 , wherein the protection element is made of metal and extends over the control terminal and over the conductive path, the control terminal and the conductive path being electrically coupled together only through the protection element. 8 . The electronic device according to claim 1 , wherein the protection element is configured to interrupt the electrical connection when the leakage current has a value higher than the critical threshold of 0.8 mA.

9. The electronic device according to claim 1, wherein the protection element has a shape selected from a parallelepiped, a cylinder, a 2 and 1.5 μm 2 The cross section between.

10. The electronic device of claim 1, wherein the device is a vertical conduction MOSFET and further comprising a second conductive terminal extending on the second face of the substrate. 11 . The electronic device of claim 10 , wherein the control terminal is a gate terminal, the first conductive terminal is a source terminal, and the second conductive terminal is a drain terminal.

12. The electronic device according to claim 1, wherein the control terminal is in a bar shape.

13. A power MOSFET device, comprising: A substrate having a first side and a second side, wherein the first side is opposite to the second side; A plurality of electronic devices, each electronic device comprising: a control terminal extending on the first surface of the substrate; a first conductive terminal extending in the substrate at the first side of the substrate; a first insulating layer, sandwiched between the control terminal and the first conductive terminal; a conductive path configured to be electrically coupled to a generator of a bias voltage; and A protection element is coupled to the control terminal and the conductive path, the protection element forms an electrical connection between the control terminal and the conductive path, and is configured to interrupt the electrical connection in response to a leakage current between the control terminal and the first conductive terminal through the first insulating layer being higher than a critical threshold.

14. The power MOSFET device of claim 13, wherein each electronic device comprises: a second insulating layer extending on the control terminal, the conductive path and the protection element and completely covering the protection element; as well as A passivation layer, made of a polymeric material, extends on the second insulating layer and has a mechanical resistance lower than that of the second insulating layer.

15. The power MOSFET device of claim 13, wherein each electronic device comprises: a second insulating layer extending over the control terminal, the conductive path and the protection element; a passivation layer made of a polymeric material extending on said second insulating layer and having a mechanical resistance less than that of said second insulating layer; as well as An opening is formed through the thickness of the second insulating layer at the protection element, and the passivation layer and the protection element are in direct contact with each other.

16. The power MOSFET device of claim 13, wherein the protection element is made of metal and extends over the control terminal and the conductive path, the control terminal and the conductive path being electrically coupled together exclusively through the protection element.

17. A method for manufacturing an electronic device, comprising: forming a first conductive terminal on the first surface of the substrate; forming a first insulating layer on the first surface of the substrate; forming a control terminal on the insulating layer; forming a conductive path on the insulating layer and adjacent to the control terminal, the conductive path being configured to be electrically coupled to a generator of a bias voltage; as well as A protection element is formed coupled to the control terminal and the conductive path, the protection element being configured to interrupt the electrical connection in response to a leakage current between the control terminal and the first conductive terminal through the first insulating layer being above a critical threshold in the presence of the bias voltage.

18. The method according to claim 17, further comprising: A second insulating layer is formed on the control terminal, the conductive path and the protection element, extending and completely covering the protection element; as well as A passivation layer made of a polymeric material is formed, the passivation layer extending on the second insulating layer and having a mechanical resistance lower than that of the second insulating layer.

19. A method for designing an electronic device, comprising: Designing a control terminal extending on the first surface of the substrate; Designing a first conductive terminal, wherein the first conductive terminal extends in the substrate at the first surface of the substrate; Designing a first insulating layer sandwiched between the control terminal and the first conductive terminal; designing a conductive path configured to be electrically coupled to a generator of a bias voltage; as well as Designing a protection element coupled to the control terminal and the conductive path includes sizing the protection element to interrupt the electrical connection when a leakage current above a critical threshold is set between the control terminal and the first conductive terminal through the first insulating layer in the presence of the bias voltage.

20. The method according to claim 19, further comprising: Designing a second insulating layer, wherein the second insulating layer extends on the control terminal, the conductive path and the protection element and completely covers the protection element; as well as A passivation layer made of a polymer material is provided which extends over the second insulating layer and has a mechanical resistance which is lower than the mechanical resistance of the second insulating layer.

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