Semiconductor devices

Abstract

The present invention provides a semiconductor device, which is a semiconductor device having a bootstrap diode and a current limiting resistor, and can suppress the reduction in the accuracy of the resistance value of the current limiting resistor. The current limiting resistor (2) is opposite to the p-type anode region (13) of the bootstrap diode (1) in the depth direction through an insulating film (15). The current limiting resistor (2) is composed of a polysilicon layer (21-24) as a polysilicon resistor and a polysilicon connection portion (20) as a connection portion with a limiting resistor electrode (17b). The polysilicon layer (21-24) is arranged at a position further outward than the polysilicon connection portion (20), and one end of each polysilicon layer is connected to the polysilicon connection portion (20), and the portion on the other end side is in contact with the anode electrode (17a) via a contact hole (18b). In addition, the polysilicon layer (21-24) is evenly arranged between the connection portion with the polysilicon connection portion (20) and the contact hole (18b).

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] In the past, it is known that a bootstrap circuit that generates a voltage higher than the internal power supply voltage VCC of the gate drive circuit is built into the gate drive circuit of a half-bridge circuit for power conversion such as an inverter circuit (for example, refer to the following patent documents 1 to 5). By providing a gate voltage that is boosted by the bootstrap circuit to a voltage higher than the drain voltage VDD of the switching power device of the upper bridge arm to the switching power device of the high potential side (high side: hereinafter referred to as the upper bridge arm) of the half-bridge circuit, the switching power device of the upper bridge arm is completely turned on. Fig.15 : is a circuit diagram showing an equivalent circuit of a part of components of a general bootstrap circuit.

[0003] like Fig.15 As shown, the bootstrap circuit 100 is composed of a bootstrap diode (BSD: Bootstrap Diode) 101, a bootstrap capacitor (BSC: Bootstrap Condenser) (not shown), and a current limiting resistor 102. The positive electrode of the bootstrap capacitor is connected to the cathode of the bootstrap diode 101, and the gate of the switching power device of the upper bridge arm (not shown) is connected to the negative electrode of the bootstrap capacitor. Between the anode of the bootstrap diode 101 and the internal power supply, the current limiting resistor 102 is connected to the bootstrap diode 101 in series.

[0004] For the bootstrap circuit 100, when the switch device of the upper arm of the half-bridge circuit is in the on state and the switch device of the low potential side (low side: hereinafter referred to as the lower arm) is in the off state, the bootstrap diode 101 is turned on, and the voltage obtained by subtracting the voltage drop of the current limiting resistor 102 and the bootstrap diode 101 from the internal power supply voltage VCC is charged to the bootstrap capacitor. At this time, the switch device of the upper arm is not turned on because the gate voltage is zero potential.

[0005] On the other hand, when the switch device of the upper bridge arm of the half-bridge circuit is in the off state and the switch device of the lower bridge arm is in the on state, the gate voltage of the switch device of the upper bridge arm becomes a voltage value obtained by adding the potential of the positive electrode of the bootstrap capacitor to the drain voltage VDD of the switch device of the upper bridge arm. As a result, the switch device of the upper bridge arm is completely turned on. Such an operation of the bootstrap circuit 100 is repeated at the cycle of the switching frequency input to the gate drive circuit.

[0006] The charge amount of the bootstrap capacitor is determined by the product (time constant) of the combined resistance value of the bootstrap diode 101 resistance value R101 and the current limiting resistor 102 resistance value R102 (= the resistance value R101 of the bootstrap diode 101 + the resistance value R102 of the current limiting resistor 102) and the capacity of the bootstrap capacitor. Therefore, a current limiting resistor 102 with high accuracy (small deviation) of the resistance value R102 is sought. Therefore, the current limiting resistor 102 uses a polysilicon (poly-Si) resistor that has no parasitic effects and can reduce the area of ​​the semiconductor substrate (semiconductor chip).

[0007] The polysilicon resistor that becomes the current limiting resistor 102 is arranged on the front side of the semiconductor substrate (semiconductor chip) through an interlayer insulating film, and is a polysilicon layer connected in series with the bootstrap diode 101 including a pn junction formed on the same semiconductor substrate. In addition, in the past, the current limiting resistor 102 used a polysilicon layer in a rectangular planar shape. The reason is that it is easy to calculate the sheet resistance from the aspect ratio (specifically, the volume) of the rectangular surface of the polysilicon layer, and it is easy to design the current limiting resistor 102 from the sheet resistance, so the current limiting resistor 102 can be correctly formed according to the desired resistance value R102 (for example, refer to the following patent document 6).

[0008] The structures of the bootstrap diode 101 and the current limiting resistor 102 of the conventional bootstrap circuit will be described. Fig.16 It is a plan view showing the structure of a bootstrap diode and a current limiting resistor of a conventional bootstrap circuit as viewed from the front side of a semiconductor substrate. Fig.17 It is shown Fig.16 A cross-sectional view of the cross-sectional structure at the cutting line AA-AA'. Fig.16 Equivalent to the following patent document 6 Figure 6 , Fig.17 Equivalent to the following patent document 6 Figure 7 .like Fig.16 , Fig.17 As shown, the bootstrap diode 101 and the current limiting resistor 102 of the bootstrap circuit 100 are disposed on the same semiconductor substrate 110 .

[0009] The bootstrap diode 101 is disposed in the diode region 121 and is composed of a p-type anode region 113 and an n-type - Type drift region 112 and n + The pn junction of the cathode region 111 is formed. + Type cathode region 111 and n - The semiconductor substrate 110 is formed by stacking the semiconductor layers of the n-type drift region 112. - The main surface on the side of the drift region 112 is taken as the front surface, and the n +The main surface on the side of the p-type cathode region 111 is the back surface. The p-type anode region 113 is selectively provided on the surface layer (n - The p-type anode region 113 has a substantially rectangular planar shape.

[0010] Inside the p-type anode region 113, p-type anode regions are selectively provided along the periphery of the p-type anode region 113. + Type anode contact region 114. + The p-type anode contact region 114 has a substantially U-shaped plane shape extending along three sides of the substantially rectangular plane shape of the p-type anode region 113, and surrounds the central portion (inner side) of the diode region 121. On the front surface of the semiconductor substrate 110, a polysilicon layer that functions as a current limiting resistor 102 (shaded portion) is provided via an oxide film 115. The current limiting resistor 102 is provided in the central portion of the diode region 121, and is opposed to the p-type anode region 113 in the depth direction.

[0011] The current limiting resistor 102 has a substantially rectangular planar shape. The current limiting resistor 102 is covered by an interlayer insulating film 116. On the interlayer insulating film 116, an anode electrode 117a and a limiting resistor electrode 117b are arranged separately from each other. + The contact hole 118a' of the contact portion (electrical contact portion) between the anode contact region 114 is provided to penetrate the interlayer insulating film 116 and the oxide film 115 in the depth direction. In addition, the interlayer insulating film 116 is provided with a contact hole 118a which is a contact portion between the anode electrode 117a and the current limiting resistor 102, and a contact hole 118b which is a contact portion between the limiting resistor electrode 117b and the current limiting resistor 102.

[0012] Anode electrode 117a and p + The anode contact region 114 has a substantially U-shaped planar shape and surrounds the current limiting resistor 102. The anode electrode 117a is connected to the p-type anode contact region 114 through a substantially U-shaped planar contact hole 118a'. + The entire surface of the anode contact region 114 is substantially in contact with the anode electrode 117a. In addition, the anode electrode 117a is in contact with the current limiting resistor 102 via the contact hole 118a. Fig.16 , the contact hole 118a and the contact hole 118a' are shown to be separately arranged. Fig.17 , it is shown that the contact hole 118a and the contact hole 118a' are connected to each other.

[0013] The contact hole 118a, which is the contact portion between the anode electrode 117a and the current-limiting resistor 102, and the contact hole 118b, which is the contact portion between the limiting resistor electrode 117b and the current-limiting resistor 102, are provided in a substantially straight line shape formed along a pair of opposite sides of the substantially rectangular plane shape of the current-limiting resistor 102. The contact hole 118a, which is the contact portion between the anode electrode 117a and the current-limiting resistor 102, is provided in a straight line portion (a straight line portion with other straight line portions connected at both ends) that does not have an open end 119a among the three straight line portions constituting the substantially U-shaped plane shape of the anode electrode 117a.

[0014] The limiting resistor electrode 117b has a substantially rectangular planar shape whose area is smaller than that of the current limiting resistor 102. The entire surface of the limiting resistor electrode 117b is opposed to the current limiting resistor 102 in the depth direction via the interlayer insulating film 116. The limiting resistor electrode 117b is in contact with the current limiting resistor 102 via the contact hole 118b. The limiting resistor electrode 117b is fixed to the internal power supply voltage VCC. The diode region 121 is surrounded by the edge termination region 122. Fig.16 In FIG. 1 , the limiting resistor electrode 117 b is represented by the sparsest dotted line, and the anode electrode 117 a is represented by a dotted line denser than the limiting resistor electrode 117 b. The contact holes 118 a and 118 b are represented by dotted lines denser than the anode electrode 117 a.

[0015] Prior art literature

[0016] Patent Literature

[0017] Patent Document 1: Japanese Patent No. 5473511

[0018] Patent Document 2: Japanese Patent No. 5754399

[0019] Patent Document 3: Japanese Patent No. 4397602

[0020] Patent Document 4: Japanese Patent No. 4610941

[0021] Patent Document 5: Japanese Patent No. 2898272

[0022] Patent Document 6: Japanese Patent Application Publication No. 2011-129628 Summary of the invention

[0023] Technical issues

[0024] However, in the conventional bootstrap circuit, the anode electrode 117a and the p +The portion 130 on the open end 119a side of the contact hole 118a' of the contact portion between the anode contact region 114 and the type is not opposite to the contact hole 118a which is the contact portion between the anode electrode 117a and the current limiting resistor 102 in the direction from the central portion side (inner side) of the diode region 121 toward the edge termination region 122 side (outer side). Therefore, the length of the current path (hole movement path) flowing from the current limiting resistor 102 into the bootstrap diode 101 is different within the surface of the front surface of the semiconductor substrate 110.

[0025] That is, from the anode electrode 117a and p + The length of the moving path of electrons flowing into the contact hole 118a which is the contact portion between the anode electrode 117a and the current limiting resistor 102 is different within the surface of the front surface of the semiconductor substrate 110. For example, from the contact portion between the anode electrode 117a and the p + The moving path 131 of electrons flowing into the contact hole 118a which is the contact portion between the anode electrode 117a and the current limiting resistor 102 becomes the longest from the open end 119a of the contact hole 118a' which is the contact portion between the anode contact region 114 and the type anode contact region 114.

[0026] Thus, the anode electrode 117a and the p + The electrons moving from the open end 119a side of the contact hole 118a' of the contact portion between the anode electrode 117a and the current limiting resistor 102 to the contact hole 118a which is the contact portion between the anode electrode 117a and the current limiting resistor 102 are concentrated at the end 132 of the contact hole 118a which is the contact portion between the anode electrode 117a and the current limiting resistor 102. Therefore, there is a problem that the local heat release at the end of the current limiting resistor 102 becomes larger than the heat release corresponding to the resistance value R102 based on the volume of the current limiting resistor 102, and the accuracy of the resistance value R102 of the current limiting resistor 102 is easily changed.

[0027] An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a semiconductor device including a bootstrap diode and a current limiting resistor constituting a bootstrap circuit, wherein a decrease in the accuracy of the resistance value of the current limiting resistor can be suppressed.

[0028] Technical Solution

[0029] In order to solve the above-mentioned problems and achieve the purpose of the present invention, the semiconductor device of the present invention has the following characteristics. A first semiconductor region of a second conductivity type is selectively provided on the surface layer of the front surface of a semiconductor substrate of a first conductivity type. The second semiconductor region of the first conductivity type is the portion of the semiconductor substrate other than the first semiconductor region. The bootstrap diode is formed by the pn junction of the first semiconductor region and the second semiconductor region. An insulating layer covers the front surface of the semiconductor substrate. A polycrystalline silicon layer is provided inside the insulating layer. The polycrystalline silicon layer is opposite to the first semiconductor region via the insulating layer. The first electrode is in electrical contact with the first semiconductor region and the polycrystalline silicon layer. The second electrode is in electrical contact with the polycrystalline silicon layer. The third electrode is provided on the back surface of the semiconductor substrate and is in contact with the second semiconductor region. The first contact portion between the first electrode and the first semiconductor region is configured as a ring surrounding the polycrystalline silicon layer. At a position further inside the ring of the first contact portion, the second contact portion between the first electrode and the polycrystalline silicon layer is uniformly arranged relative to the ring of the first contact portion. A third contact portion between the second electrode and the polysilicon layer is uniformly arranged with respect to the second contact portion at an inner side of the second contact portion.

[0030] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the polysilicon layer has a first polysilicon portion and a plurality of second polysilicon portions. The first polysilicon portion is in electrical contact with the second electrode via the third contact portion. The plurality of second polysilicon portions are arranged at a position further outward than the first polysilicon portion, and are connected to the first polysilicon portion at the inner end, respectively, and are in electrical contact with the first electrode at the outer end via the second contact portion. The plurality of second polysilicon portions are uniformly arranged relative to the third contact portion.

[0031] Furthermore, in the semiconductor device of the present invention, in the above invention, widths of the plurality of second polysilicon portions are constant from a connection portion with the first polysilicon portion to the second contact portion.

[0032] Furthermore, in the semiconductor device of the present invention, in the above invention, a plurality of the second polysilicon portions are connected in parallel between the third contact portion and the second contact portion.

[0033] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the first polysilicon portion has a circular planar shape. The plurality of second polysilicon portions extend outward in a spiral shape and surround the first polysilicon portion, wherein the spiral shape starts from the connection portion with the first polysilicon portion and ends at the second contact portion.

[0034] Furthermore, in the semiconductor device of the present invention, in the above invention, the second contact portion is arranged at an equal distance from the first contact portion.

[0035] Furthermore, in the semiconductor device of the present invention, in the above invention, the third contact portion is arranged at an equal distance from the second contact portion.

[0036] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the polysilicon layer has a circular planar shape, the second contact portion is configured in a ring shape with an equal distance from the first contact portion, and the third contact portion is configured in a ring shape with an equal distance from the second contact portion.

[0037] In the semiconductor device of the present invention, in the above invention, the polysilicon layer has a ring-shaped planar shape, and the third contact portion is located outside the inner periphery of the polysilicon layer.

[0038] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the polysilicon layer is divided into a plurality of sector-shaped planar shapes.

[0039] Furthermore, in the semiconductor device of the present invention, in the above invention, the surface area of ​​the polysilicon layer is 40% or more of the surface area of ​​the first semiconductor region.

[0040] Furthermore, in the semiconductor device of the present invention, in the above invention, a surface area of ​​the polysilicon layer is equal to a surface area of ​​the first semiconductor region.

[0041] According to the above invention, current can be uniformly passed through the polysilicon layer functioning as a current limiting resistor, so that there is no portion where electrons are locally concentrated in the current limiting resistor. Therefore, it is possible to suppress the heat generation of the current limiting resistor from being partially increased.

[0042] Technical Effects

[0043] According to the semiconductor device of the present invention, the semiconductor device includes a bootstrap diode and a current limiting resistor constituting a bootstrap circuit, and has an effect of being able to suppress a decrease in the accuracy of the resistance value of the current limiting resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a plan view showing the layout of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate.

[0045] Figure 2 It is shown in an enlarged manner Figure 1 Part of the floor plan.

[0046] Figure 3: is a circuit diagram showing an equivalent circuit of the semiconductor device according to the first embodiment.

[0047] Figure 4 It is shown Figure 1 Cross-sectional view of the cross-sectional structure at the cutting line AA'.

[0048] Figure 5 It is shown Figure 1 A cross-sectional view of another example of the cross-sectional structure at the cutting line AA'.

[0049] Figure 6 This is a plan view showing an example of the structure of a semiconductor device according to Embodiment 2.

[0050] Figure 7 It is shown in an enlarged manner Figure 6 Part of the floor plan.

[0051] Figure 8 : is a circuit diagram showing an equivalent circuit of the semiconductor device according to the second embodiment.

[0052] Fig. 9 This is a plan view showing the layout of the semiconductor device according to the third embodiment as viewed from the front side of the semiconductor substrate.

[0053] Fig.10 It is shown Fig. 9 Part of the floor plan.

[0054] Fig.11 This is a plan view showing the layout of the semiconductor device according to the third embodiment as viewed from the front side of the semiconductor substrate.

[0055] Fig.12 It is shown Fig.11 Part of the floor plan.

[0056] Fig.13 This is a plan view showing the layout of the semiconductor device according to the third embodiment as viewed from the front side of the semiconductor substrate.

[0057] Fig.14 It is shown Fig.13 Part of the floor plan.

[0058] Fig.15 : is a circuit diagram showing an equivalent circuit of a part of components of a general bootstrap circuit.

[0059] Fig.16 It is a plan view showing the structure of a bootstrap diode and a current limiting resistor of a conventional bootstrap circuit as viewed from the front side of a semiconductor substrate.

[0060] Fig.17 It is shown Fig.16A cross-sectional view of the cross-sectional structure at the cutting line AA-AA'.

[0061] Explanation of symbols

[0062] 1 Bootstrap diode

[0063] 2 Current limiting resistor

[0064] 10 Semiconductor substrate

[0065] 11 n + Cathode region

[0066] 12 n - Drift zone

[0067] 13 p-type anode region

[0068] 14 p + Anode contact area

[0069] 15 Insulation film

[0070] 16 Interlayer insulation film

[0071] 17a Anode electrode

[0072] 17b Limiting resistance electrode

[0073] 18a, 18b, 18b', 18c, 35a to 35f contact holes

[0074] 19 Passivation film

[0075] 20, 20' Polysilicon connection

[0076] 21~24,33a~33f,42,61~68,71,71',72~75 Polysilicon layer

[0077] 30 cathode electrode

[0078] 31 FLR

[0079] 32 p + Type contact area

[0080] 34 FP

[0081] 41 p-type channel stop region

[0082] 43 Channel stopper electrode

[0083] 51 Diode Area

[0084] 52 Edge terminal area

[0085] R1 is the resistance value of the bootstrap diode

[0086] R21~R24, R61~R68, Rn Resistance value of the polysilicon layer that functions as a polysilicon resistor

[0087] t1, t2 thickness of polysilicon layer

[0088] VCC Internal power supply voltage

[0089] VDD Drain Voltage

[0090] w1 The width of the polysilicon layer that functions as a polysilicon resistor

[0091] x1, x2 Shortest distance between contact holes DETAILED DESCRIPTION

[0092] The preferred embodiment of the semiconductor device of the present invention is described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, the layers and regions prefixed with n or p respectively indicate that electrons or holes are majority carriers. In addition, the + in n or p indicates that the impurity concentration is higher than the impurity concentration in the layer or region not marked with the symbol, and the - in n or p indicates that the impurity concentration is lower than the impurity concentration in the layer or region not marked with the symbol. It should be noted that in the following description of the embodiment and the accompanying drawings, the same symbols are marked for the same structure, and repeated descriptions are omitted.

[0093] The structure of the semiconductor device according to the first embodiment will be described. Figure 1 This is a plan view showing the layout of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate. Figure 2 It is shown in an enlarged manner Figure 1 A part of the floor plan. Figure 2 In the figure, the enlarged Figure 1 part of the current limiting resistor 2. Figure 1 , Figure 2 In the embodiment, the insulating film 15 and the interlayer insulating film 16 (see Figure 4 ) Illustration omitted. Figure 3 is a circuit diagram showing an equivalent circuit of the semiconductor device according to Embodiment 1. Figure 3 In Figure 1 Equivalent circuit of bootstrap diode 1 and current limiting resistor 2. Figure 4 It is shown Figure 1 Cross-sectional view of the cross-sectional structure at the cutting line AA'. Figure 5 It is shown Figure 1 A cross-sectional view of another example of the cross-sectional structure at the cutting line AA'.

[0094] exist Figure 1 , Figure 2The semiconductor device of the first embodiment shown in FIG. 1 includes components of a bootstrap circuit, namely, a bootstrap diode (BSD) 1 and a current limiting resistor 2 (see FIG. 2 ) on the same semiconductor substrate (semiconductor chip). Figure 3 , Figure 4 The bootstrap circuit is built into a gate drive circuit of a half-bridge circuit for power conversion, such as an inverter circuit, and has a function of boosting an internal power supply voltage VCC of the gate drive circuit to a voltage higher than a drain voltage VDD of a switching device on a high potential side (upper bridge arm) of the half-bridge circuit, thereby generating a gate voltage supplied to the switching device of the upper bridge arm.

[0095] The bootstrap circuit is composed of a bootstrap diode 1, a current limiting resistor 2, and a bootstrap capacitor (BSC) (not shown). The charge amount of the bootstrap capacitor (i.e., the voltage of the bootstrap capacitor) is determined by the combined resistance value of the bootstrap diode 1 and the current limiting resistor 2. The bootstrap diode 1 is composed of a p-type anode region 13 (see Figure 4 ) and n - The drift region 12 and the n + Type cathode region 11 (refer to Figure 4 ) is formed. The p-type anode region 13 is arranged on the entire front surface of the semiconductor substrate 10 in the diode region. The diode region is a region where the bootstrap diode 1 is arranged.

[0096] Although not shown in the figure, the p-type anode region 13 has a circular planar shape, for example. + The p-type anode contact region 14 is arranged in a substantially annular shape along the outer periphery of the p-type anode region 13. + The anode contact region 14 is in contact with the anode electrode 17a described later via the contact hole 18a. The contact hole 18a is arranged along the p + The contact hole 18a is formed into a substantially annular shape by forming a positive electrode contact region 14. The diameter of the contact hole 18a is larger than the inner diameter of the anode electrode 17a and smaller than the outer diameter of the anode electrode 17a.

[0097] On the front surface of the semiconductor substrate 10, a polysilicon (poly-Si) resistor serving as a current limiting resistor 2 is arranged with an insulating film 15 interposed therebetween. The insulating film 15 is provided on, for example, the entire front surface of the semiconductor substrate and has a contact hole. The insulating film 15 may be, for example, an oxide film, a nitride film, or a laminated film thereof. The current limiting resistor 2 is opposed to the p-type anode region 13 in the depth direction with the insulating film 15 interposed therebetween. In addition, the current limiting resistor 2 is covered by an interlayer insulating film 16 and is opposed to the anode electrode 17a and the limiting resistor electrode 17b described later in the depth direction with the interlayer insulating film 16 interposed therebetween.

[0098] The current limiting resistor 2 has a structure in which a polysilicon layer is divided into a plurality of layers, so that when a current flows from the limiting resistor electrode 17b through the current limiting resistor 2 to the p-type anode region 13 of the bootstrap diode 1 (hole movement), a plurality of current paths are formed in parallel between the limiting resistor electrode 17b and the p-type anode region 13 of the bootstrap diode 1. Specifically, the current limiting resistor 2 is composed of a plurality of (four in this case) polysilicon layers 21 to 24 functioning as polysilicon resistors, and a polysilicon layer (hereinafter referred to as a polysilicon connection portion) 20 electrically connecting these polysilicon layers 21 to 24 to the limiting resistor electrode 17b.

[0099] The polysilicon connection portion 20, the polysilicon layers 21 to 24, and the polysilicon layers 33a to 33f and 42 described later can be formed by, for example, patterning the entire polysilicon layer stacked on the surface of the insulating film 15 into a predetermined pattern. Figure 1 , Figure 2 In the figure, multiple polysilicon layers that can be formed in the same process are indicated by hatching (in Figure 6 , Figure 7 The same is true in Chinese).

[0100] The polysilicon connection portion 20 is arranged, for example, in the central part of the chip. In addition, the polysilicon connection portion 20 has a planar shape, for example, a circle. The polysilicon connection portion 20 contacts the limiting resistance electrode 17b via the contact hole 18c. The diameter of the polysilicon connection portion 20 is smaller than the diameter of the limiting resistance electrode 17b. The contact hole 18c, which becomes the contact portion (electrical contact portion) between the limiting resistance electrode 17b and the polysilicon connection portion 20, is located at a position further inside than the contact hole 18b described later, and is uniformly arranged at an equal distance x1 from the contact hole 18b. Specifically, the contact hole 18c is arranged in a ring shape, for example, along the outer periphery of the polysilicon connection portion 20. The diameter of the contact hole 18c is smaller than the diameter of the polysilicon connection portion 20.

[0101] The multiple polysilicon layers 21 to 24 all have substantially the same planar shape and are arranged separately from each other. One end of each of the multiple polysilicon layers 21 to 24 is connected to the periphery of the polysilicon connection portion 20. The respective connection portions of the multiple polysilicon layers 21 to 24 and the polysilicon connection portion 20 only need to be uniformly arranged along the periphery of the polysilicon connection portion 20, and various changes can be made according to the resistance value of the polysilicon layers 21 to 24. The portion of the polysilicon connection portion 20 that is further outside (on the chip end side) than the contact hole 18c functions as a polysilicon resistor together with the polysilicon layers 21 to 24.

[0102] Each of the plurality of polysilicon layers 21 to 24 has a planar shape that extends outwardly along the periphery of the polysilicon connection portion 20 in a spiral shape starting from a connection portion with the polysilicon connection portion 20 and ending at a contact hole 18b described later (at a point between 1 and 24). Figure 1 , Figure 2 The figure shows three swirls). The polysilicon connection portion 20 is surrounded by a plurality of polysilicon layers 21 to 24 in an annular shape. The planar shape of the polysilicon layers 21 to 24 can be a curve shape that smoothly continues from the connection portion with the polysilicon connection portion 20 toward the outside, or can be a Figure 1 , Figure 2 As shown, a plurality of arc (curve)-shaped polysilicon layers having different diameters are connected together from the connection portion with the polysilicon connection portion 20 toward the outside to form a lightning shape having a partially bent portion.

[0103] The larger the surface area of ​​the polysilicon layers 21 to 24 is set, the higher the heat dissipation of the polysilicon layers 21 to 24 is, so it is preferred. The sum of the total surface area of ​​the plurality of polysilicon layers 21 to 24 and the surface area of ​​the polysilicon connection portion 20 (i.e., the surface area of ​​the current limiting resistor 2) can be set, for example, to be more than 40% of the surface area of ​​the p-type anode region 13, preferably substantially equal to the surface area of ​​the p-type anode region 13. The closer the surface area of ​​the current limiting resistor 2 is set to be to the surface area of ​​the p-type anode region 13, the more the heat dissipation of the current limiting resistor 2 can be improved.

[0104] Each of the multiple polysilicon layers 21 to 24 is in contact with the anode electrode 17a at a portion on the other end side via the contact hole 18b. Each contact hole 18b that becomes a contact portion between the anode electrode 17a and the polysilicon layers 21 to 24 is located further inside than the contact hole 18a and is evenly arranged at an equal distance x2 from the contact hole 18a. Specifically, each contact hole 18b is arranged at equal intervals along the inner periphery of the anode electrode 17a, for example.

[0105] In all polysilicon layers 21 to 24, the length of the current path from the contact hole 18c that becomes the contact portion between the limiting resistor electrode 17b and the polysilicon connecting portion 20 to the contact hole 18b that becomes the contact portion between the anode electrode 17a and the other end of each polysilicon layer 21 to 24 is equal to the shortest distance x1. The resistance values ​​R21 to R24 of the polysilicon layers 21 to 24 are respectively determined by the length of the current path and the width w1 described later. The resistance values ​​R21 to R24 of the polysilicon layers 21 to 24 are, for example, several Ω to several hundred Ω. In addition, in all polysilicon layers 21 to 24, the length of the current path from the contact hole 18c that becomes the contact portion between the anode electrode 17a and the other end of each polysilicon layer 21 to 24 to the contact hole 18b that becomes the contact portion between the anode electrode 17a and the p +The shortest distance x2 from the contact portion between the anode contact regions 14 to the contact hole 18a is equal.

[0106] That is, the layout of the contact portion for extracting current from the limiting resistor electrode 17b to the current limiting resistor 2 is uniform. The layout of the contact portion for extracting current from the current limiting resistor 2 to the bootstrap diode 1 is uniform. As a result, the extraction of current from the back side of the semiconductor substrate 10 to the BSC through the bootstrap diode 1 becomes uniform. All contact holes 18b are preferably equal in planar shape and surface area. The planar shape of the contact hole 18b can also be, for example, rectangular or circular. The contact holes 18b and the contact holes 18c penetrate the interlayer insulating film 16 in the depth direction. Figure 1 , Figure 2 In FIG. 1 , contact hole 18a and contact hole 18c are indicated by bold lines, and contact hole 18b is indicated by a filled rectangle (■).

[0107] In addition, in each polysilicon layer 21 to 24, the width w1 of each direction (the normal direction of the polysilicon connection portion 20) perpendicular to the current flow direction (the direction indicated by the direction of the white arrow) is preferably constant throughout the entire length of the current path in the polysilicon layers 21 to 24. The current path in the polysilicon layers 21 to 24 refers to the path of the current flowing from the lead connected to the limiting resistor electrode 17b through the limiting resistor electrode 17b, the current limiting resistor 2 (the polysilicon connection portion 20 and the polysilicon layers 21 to 24) and the bootstrap diode 1 from the cathode electrode 30 on the back side of the semiconductor substrate 10 to the BSC, and is respectively shunted from the polysilicon connection portion 20 and each connection portion of each polysilicon layer 21 to 24 connected in parallel to the polysilicon connection portion 20 to each polysilicon layer 21 to 24 and reaches the p + The path of the current to the anode contact region 14.

[0108] The anode electrode 17a and the limiting resistor electrode 17b are arranged on the interlayer insulating film 16. The limiting resistor electrode 17b is arranged in the central part of the chip. The limiting resistor electrode 17b has a planar shape, for example, a circular shape. The limiting resistor electrode 17b is opposite to, for example, the entire surface of the polysilicon connecting portion 20 in the depth direction through the interlayer insulating film 16. The limiting resistor electrode 17b can also be opposite to one end of the plurality of polysilicon layers 21 to 24 in the depth direction through the interlayer insulating film 16. In addition, the limiting resistor electrode 17b is connected to an internal power supply not shown in the figure, and is fixed to the internal power supply voltage VCC.

[0109] The anode electrode 17a is separated from the limiting resistor electrode 17b and is arranged in a ring shape surrounding the limiting resistor electrode 17b. The anode electrode 17a is opposite to the innermost polysilicon layer 33a (on the chip center side) among the multiple polysilicon layers 33a to 33f described later in the depth direction through the interlayer insulating film 16. Figure 1In the figure, the limiting resistor electrode 17b is a portion surrounded by a dotted circle, and the anode electrode 17a is a portion sandwiched between two dotted lines thinner than the limiting resistor electrode 17b (in Figure 6 The same is true in Chinese).

[0110] The diode region is surrounded by an edge termination region. The edge termination region is a region between the diode region and the side surface of the semiconductor substrate 10, which is used to mitigate the n - The electric field on the front side of the chip of the type drift region 12 is maintained and the withstand voltage (voltage resistance) is maintained. The withstand voltage refers to the limit voltage that does not cause malfunction and / or damage to the element. From the diode region to the edge terminal region, multiple (here six) polysilicon layers 33a to 33f are arranged on the front side of the semiconductor substrate 10 through the insulating film 15. Figure 1 , Figure 2 In FIG. 1 , a plurality of polysilicon layers 33a to 33f are sequentially arranged from the inside to the outside (in FIG. 1 ). Figure 6 , Figure 7 The same is true in ).

[0111] The plurality of polysilicon layers 33a to 33f are arranged in concentric circles around the current limiting resistor 2, separated from the current limiting resistor 2. The innermost polysilicon layer 33a among the plurality of polysilicon layers 33a to 33f is in contact with the anode electrode 17a via the contact hole 35a. The polysilicon layers 33b to 33f other than the innermost polysilicon layer 33a among the plurality of polysilicon layers 33a to 33f are arranged in the edge termination region, and are respectively connected to the FLR 31 and FP 34 (refer to FIG. 1 ) which are omitted from the illustration and described later, via the contact holes 35b to 35f. Figure 4 ) contact. Figure 1 , Figure 2 In FIG. 1 , contact holes 35 a to 35 f are indicated by bold lines.

[0112] In addition, in the edge termination region, a polysilicon layer 42 is provided on the front surface of the semiconductor substrate 10 via the insulating film 15. The polysilicon layer 42 is separated from the polysilicon layers 33a to 33f and is arranged in a ring shape surrounding the outermost polysilicon layer 33f among the plurality of polysilicon layers 33a to 33f. The polysilicon layer 42 is in contact with the channel stopper electrode 43 and functions as a channel stopper together with the channel stopper electrode 43. The channel stopper electrode 43 is in contact with the polysilicon layer 42 and the p-type channel stopper region 41.

[0113] The channel stopper electrode 43 is separated from the FP 34 described later and is arranged in a ring shape surrounding the outermost FP 34 among the plurality of FP 34. Figure 1, the channel stopper electrode 43 is a portion sandwiched between two imaginary lines thicker than the limiting resistor electrode 17b. The p-type channel stopper region 41 is provided on the outermost side of the semiconductor substrate 10 on the front surface of the semiconductor substrate 10. The p-type channel stopper region 41 is separated from the FLR 32 and is configured in a ring shape surrounding the periphery of the FLR 32.

[0114] like Figure 3 As shown, the positive electrode of the bootstrap capacitor and the cathode of the bootstrap diode 1 ( Figure 4 The gate of the switching power device of the upper bridge arm (not shown) is connected to the negative electrode of the bootstrap capacitor. Between the anode (anode electrode 17a) of the bootstrap diode 1 and the internal power supply, the current limiting resistor 2 is connected in series to the bootstrap diode 1. The current limiting resistor 2 is a composite resistor of multiple (four in this case) polysilicon layers 21 to 24 that function as polysilicon resistors. One end of all the polysilicon layers 21 to 24 is connected to the internal power supply, and the other end is connected to the anode of the bootstrap diode 1.

[0115] Generally, in a bootstrap circuit, when the switch device of the upper arm of the half-bridge circuit is in the on state and the switch device of the low potential side (lower arm) is in the off state, the bootstrap diode 1 is turned on, and the voltage obtained by subtracting the voltage drop of the current limiting resistor 2 and the bootstrap diode 1 from the internal power supply voltage VCC is charged to the bootstrap capacitor. At this time, the switch device of the upper arm is not turned on because the gate voltage is zero potential.

[0116] On the other hand, when the switch device of the upper bridge arm of the half-bridge circuit is in the off state and the switch device of the lower bridge arm is in the on state, the gate voltage of the switch device of the upper bridge arm becomes a voltage value obtained by adding the potential of the positive electrode of the bootstrap capacitor to the drain voltage VDD of the switch device of the upper bridge arm. As a result, the switch device of the upper bridge arm is completely turned on. The operation of such a bootstrap circuit is repeated according to the cycle of the switching frequency input to the gate drive circuit.

[0117] The charge amount of the bootstrap capacitor is determined by the product of the combined resistance value of the bootstrap diode 1 resistance value R1 and the combined resistance value of the current limiting resistor 2 (= the combined resistance value of the bootstrap diode 1 R1 + the combined resistance value of the current limiting resistor 2) and the capacity of the bootstrap capacitor (time constant). The combined resistance value of the current limiting resistor 2 is the reciprocal of the sum of the reciprocals of the resistance values ​​R21 to R24 of the polysilicon layers 21 to 24 (= (1 / R21+1 / R22+1 / R23+1 / R24) -1 ≈R21 / 4, R21≈R22≈R23≈R24).

[0118] Next, the cross-sectional structure of the semiconductor device according to Embodiment 1 is described. Figure 4 As shown, Figure 1 , Figure 2The bootstrap diode 1 and the current limiting resistor 2 are arranged in the same semiconductor substrate 10, for example, in the diode region 51. The bootstrap diode 1 is composed of a p-type anode region 13 and an n-type - Type drift region 12 and n + A pn junction of the cathode region 11 is formed.

[0119] Make it n + Type cathode region 11 and n - The semiconductor substrate 10 is formed by epitaxially growing each semiconductor layer of the n-type drift region 12. + Type cathode region 11 n + Type substrate to make it n - The semiconductor substrate 10 is formed by epitaxial growth of a semiconductor layer of an n-type drift region 12. - The main surface of the drift region 12 is the front surface, and the n + The main surface on the side of the p-type cathode region 11 is the back surface. The p-type anode region 13 is provided in the diode region 51 on the surface layer (n - Inside the p-type anode region 13, a p + Type anode contact region 14.

[0120] In the ratio + The front surface of the semiconductor substrate 10 is covered by an insulating film 15 including an oxide film such as LOCOS (Local Oxidation of Silicon) at a position further inside the anode contact region 14. On the insulating film 15, a polysilicon connection portion 20 and polysilicon layers 21 to 24 (in the middle) constituting the current limiting resistor 2 are arranged. Figure 4 The polysilicon layer 24 is not shown in the figure. The polysilicon connection portion 20 is arranged at a position further inside than the polysilicon layers 21 to 24. In the portion where the illustration is omitted, all the polysilicon layers 21 to 24 are connected to the polysilicon connection portion 20.

[0121] The thickness t1 of the polysilicon layers 21 to 24 is preferably, for example, greater than 0.2 μm and less than 1 μm, and may also be, for example, about 0.5 μm. This is because when the thickness t1 of the polysilicon layers 21 to 24 exceeds the above upper limit, the specified resistance values ​​R21 to R24 of the polysilicon layers 21 to 24 cannot be obtained. In addition, as the thickness t1 of the polysilicon layers 21 to 24 becomes thinner, the cross-sectional area of ​​the polysilicon layers 21 to 24 becomes smaller, and thus the resistance values ​​R21 to R24 of the polysilicon layers 21 to 24 become higher, and it is difficult for current to flow in the polysilicon layers 21 to 24. This is because when the thickness t1 of the polysilicon layers 21 to 24 is less than the above lower limit, the current is concentrated in the polysilicon layers 21 to 24, resulting in the degradation of the current limiting resistor 2.

[0122] The end of the p-type anode region 13 and the p + The anode contact region 14, the polysilicon connection portion 20, and the polysilicon layers 21 to 24 are covered with an interlayer insulating film 16. In the interlayer insulating film 16 and the insulating film 15, there is provided a layer that penetrates the interlayer insulating film 16 and the insulating film 15 in the depth direction and reaches the p + The contact hole 18a of the anode contact region 14 is formed in the interlayer insulating film 16. A plurality of (four in this case) contact holes 18b are provided in the interlayer insulating film 16 so as to penetrate the interlayer insulating film 16 in the depth direction. The other ends of the different polysilicon layers 21 to 24 are exposed in the plurality of contact holes 18b.

[0123] In addition, the interlayer insulating film 16 is provided with a contact hole 18c that penetrates the interlayer insulating film 16 in the depth direction and reaches the polysilicon connection portion 20. In the contact hole 18c, the outer periphery of the polysilicon connection portion 20 is exposed. On the interlayer insulating film 16, the anode electrode 17a and the limiting resistance electrode 17b are provided separately from each other. The anode electrode 17a and the limiting resistance electrode 17b are metal electrodes composed of an alloy including, for example, aluminum (Al), and may be, for example, an aluminum-silicon (Al-Si) electrode, an aluminum-copper (Al-Cu) electrode, or an aluminum-silicon-copper (Al-Si-Cu) electrode.

[0124] The limiting resistor electrode 17b contacts the polysilicon connection portion 20 via the contact hole 18c, and is electrically connected to all the polysilicon layers 21 to 24 through the polysilicon connection portion 20. By electrically connecting the limiting resistor electrode 17b to the polysilicon layers 21 to 24 using the polysilicon connection portion 20, the resistance value of the current limiting resistor 2 can be reduced. The portion of the polysilicon connection portion 20 that is further inside than the contact hole 18c functions as a buffer material for reducing the impact of, for example, ultrasonic vibration on the semiconductor substrate 10 when the bonding wire is bonded to the limiting resistor electrode 17b.

[0125] The limiting resistor electrode 17b and all the polysilicon layers 21 to 24 may be electrically connected via the polysilicon connection portion 20, or the polysilicon connection portion 20' may be disposed only directly below the contact hole 18c (see Figure 5 ). Directly below the contact hole 18c refers to a portion exposed from the contact hole 18c on the insulating film 15. When the polysilicon connection portion 20' is disposed only directly below the contact hole 18c, the planar shape of the polysilicon connection portion 20' is substantially annular.

[0126] In the edge termination region 52, a plurality of field limiting rings (FLR: Field Limiting Ring) 31 and a p-type channel stop region 41 as floating p-type regions are selectively provided on the surface layer (n) of the front surface of the semiconductor substrate 10. -The FLR 31 is disposed in a surface layer of the p-type drift region 12. The FLR 31 is disposed separately from the p-type anode region 13. Although not shown in the figure, the plurality of FLRs 31 are disposed in a concentric circle shape surrounding the p-type anode region 13.

[0127] Inside each FLR 31, p + Although not shown in the figure, each p + The p-type contact region 32 is arranged in a ring shape along the corresponding FLR 31. The p-type channel stop region 41 is selectively provided in the surface layer of the front surface of the semiconductor substrate 10 at a position further outside than the FLR 31. In addition, the p-type channel stop region 41 is provided separately from the FLR 31 and is arranged so as to be exposed on the side surface of the semiconductor substrate 10.

[0128] In the edge termination region 52, the front surface of the semiconductor substrate 10 is covered by an insulating film 15. On the insulating film 15, polysilicon layers 33a to 33f are provided at positions further outward than the current limiting resistor 2 in a manner separated from the current limiting resistor 2. The polysilicon layers 33a to 33f are covered by an interlayer insulating film 16, and a field plate (FP: Field Plate) 34 is provided on the interlayer insulating film 16. In the interlayer insulating film 16 of the edge termination region 52, a contact hole 35a is provided that penetrates the interlayer insulating film 16 in the depth direction and reaches the innermost polysilicon layer 33a among the multiple polysilicon layers 33a to 33f.

[0129] In addition, in the interlayer insulating film 16 and the insulating film 15 of the edge termination region 52, there is provided a layer penetrating in the depth direction through the interlayer insulating film 16, the polysilicon layers 33b to 33f that are opposed in the depth direction, and the insulating film 15 to reach the p-type silicon layer. + The contact holes 35b to 35f of the type contact region 32 are formed. Different p + The polysilicon layers 33a to 33f are arranged to be separated from each other. The thickness t2 of the polysilicon layers 33a to 33f may be equal to the thickness t1 of the polysilicon layers 21 to 24 constituting the current limiting resistor 2, for example.

[0130] Among the plurality of polysilicon layers 33a to 33f, the innermost polysilicon layer 33a is disposed in, for example, the diode region 51, and is opposed to the p-type anode region 13 in the depth direction via the insulating film 15. In addition, the innermost polysilicon layer 33a is opposed to the anode electrode 17a in the depth direction via the interlayer insulating film 16, and is in contact with the anode electrode 17a via the contact hole 35a. Among the plurality of polysilicon layers 33a to 33f, the polysilicon layers 33b to 33f other than the innermost polysilicon layer 33a are disposed in the edge termination region 52.

[0131] Among the plurality of polysilicon layers 33a to 33f, the polysilicon layers 33b to 33f other than the innermost polysilicon layer 33a are respectively opposed to different FLRs 31 in the depth direction via the insulating film 15, and are opposed to different FPs 34 in the depth direction via the interlayer insulating film 16 on the opposite side to the FLR 31 side. In addition, the polysilicon layers 33b to 33f are in contact with the FLR 31 and FP 34 opposed in the depth direction via the contact holes 35b to 35f. The plurality of polysilicon layers 33b to 33f function as FPs together with the FP 34.

[0132] The front surface of the semiconductor substrate 10 is covered by an insulating film 15 such as a LOCOS film between the outermost FLR 31 among the plurality of FLRs 31 and the p-type channel stop region 41. On the insulating film 15, a polysilicon layer 42 is provided separately from the polysilicon layers 33b to 33f. A channel stopper electrode 43 is provided on the interlayer insulating film 16 covering the polysilicon layer 42, and contacts the polysilicon layer 42 and the p-type channel stop region 41 via a contact hole. The polysilicon layer 42 functions as a channel stopper electrode together with the channel stopper electrode 43.

[0133] The FP34 and the channel stopper electrode 43 are, for example, the same metal electrode as the anode electrode 17a. The passivation film 19 is provided in a manner covering the FP34 and the channel stopper electrode 43. The passivation film 19 may also extend from the edge termination region 52 to the surface of the limiting resistor electrode 17b. + The cathode region 11 is formed on the back side of the semiconductor substrate 10. The cathode electrode 30 is disposed on the entire back side of the semiconductor substrate 10 and is connected to the n + The cathode region 11 is connected to the cathode electrode 30. The cathode electrode 30 is electrically connected to the positive electrode of the bootstrap capacitor.

[0134] As described above, according to Embodiment 1, the polysilicon layer that functions as a polysilicon resistor of a current limiting resistor is divided into a plurality of layers, and one end of each polysilicon layer is connected to a polysilicon connection portion that is a connection portion with a limiting resistor electrode, and the other end of each polysilicon layer is connected to a p-type anode region of a bootstrap diode. Thus, a plurality of current paths (hole movement paths) formed based on the polysilicon layer are formed in parallel between the limiting resistor electrode and the p-type anode region of the bootstrap diode. Thus, the current can be made to flow evenly through all the polysilicon layers that function as a current limiting resistor, so there is no part where electrons are locally concentrated in the current limiting resistor. Therefore, it is possible to suppress the heat release of the current limiting resistor from becoming locally larger, so it is possible to suppress the reduction in the accuracy of the resistance value of the current limiting resistor. In addition, according to embodiment 1, by configuring each polysilicon layer that functions as a polysilicon resistor that limits the current into a roughly curved planar shape that surrounds the polysilicon connection portion from the connection portion with the polysilicon connection portion, it is possible to ensure that the current path is long and the polysilicon resistor can be set to a high resistance.

[0135] (Implementation Method 2)

[0136] Next, the structure of the semiconductor device according to the second embodiment will be described. Figure 6 This is a plan view showing an example of the structure of a semiconductor device according to Embodiment 2. Figure 7 It is shown in an enlarged manner Figure 6 A part of the floor plan. Figure 7 In the figure, the enlarged Figure 6 Part of the current limiting resistor 2. Figure 8 is a circuit diagram showing an equivalent circuit of a semiconductor device according to Embodiment 2. Figure 8 In Figure 6 Equivalent circuit of bootstrap diode 1 and current limiting resistor 2.

[0137] The semiconductor device of embodiment 2 is different from the semiconductor device of embodiment 1 in that the polysilicon layer constituting the current limiting resistor 2 is further divided, and the number of multiple polysilicon layers 61~n (where n=62, 63, 64, ...) connected in parallel between the limiting resistor electrode 17b and the bootstrap diode 1 that function as polysilicon resistors of the current limiting resistor 2 is increased.

[0138] exist Figure 6 , Figure 7For example, an example of a case where eight polysilicon layers functioning as polysilicon resistors of the current limiting resistor 2 are configured (i.e., n=68) is shown, but the number of polysilicon layers functioning as polysilicon resistors of the current limiting resistor 2 can be changed in various ways. The semiconductor device of the second embodiment is the same as the semiconductor device of the first embodiment except for the number and layout of the polysilicon layers 61 to 68.

[0139] In the second embodiment, as in the first embodiment, the eight polysilicon layers 61 to 68 are arranged in a substantially curved plane shape that surrounds the polysilicon connection portion 20 from the connection portion between the polysilicon connection portion 20 and each of the polysilicon layers 61 to 68. Thus, as in the first embodiment, eight current paths (hole movement paths) formed by the polysilicon layers 61 to 68 are formed in parallel between the limiting resistor electrode 17b and the p-type anode region 13 of the bootstrap diode 1.

[0140] By adjusting the width w1 of the polysilicon layers 61 to 68 and / or the length of the current path, the layout of the polysilicon layers 61 to 68 can be changed in various ways. Therefore, by adjusting the width w1 of the polysilicon layers 61 to 68 and / or the length of the current path, the degree of freedom in designing the current limiting resistor 2 is increased. As a result, the chip size can be reduced, or the resistance values ​​R61 to R68 of the polysilicon layers 61 to 68 can be adjusted without changing the chip size.

[0141] As described above, according to the second embodiment, even when the number of polysilicon layers functioning as polysilicon resistors that limit current is increased, the same effects as those of the first embodiment can be obtained.

[0142] (Implementation method 3)

[0143] Next, the structure of the semiconductor device according to the third embodiment will be described. Fig. 9 , Fig.11 , Fig.13 This is a plan view showing the layout of the semiconductor device according to the third embodiment as viewed from the front side of the semiconductor substrate. Fig.10 , Fig.12 , Fig.14 They are shown respectively Fig. 9 , Fig.11 , Fig.13 A part of the floor plan. Fig.10 , Fig.12 , Fig.14 In the figure, only Fig. 9 , Fig.11 , Fig.13 The contact holes 18b and 18c and the polysilicon layer functioning as a polysilicon resistor of the current limiting resistor 2.

[0144] The semiconductor device of the third embodiment includes a current limiting resistor 2, which is composed of one or more polysilicon layers serving as both a polysilicon connection portion and a polysilicon resistor. That is, as long as the path of the current flowing from the limiting resistor electrode 17b to the bootstrap diode 1 (the path of the movement of holes) can be formed uniformly through the polysilicon layer constituting the current limiting resistor 2, the planar shape of the polysilicon layer constituting the current limiting resistor 2 can be changed in various ways.

[0145] Specifically, if Fig. 9 , Fig.10 As shown, a polysilicon layer 71 having a substantially circular planar shape can be configured as the current limiting resistor 2. The polysilicon layer 71 is opposed to the anode electrode 17a and the limiting resistor electrode 17b in the depth direction via an interlayer insulating film. The polysilicon layer 71 contacts the anode electrode 17a via the contact hole 18b', and contacts the limiting resistor electrode 17b via the contact hole 18c. That is, the polysilicon layer 71 constituting the current limiting resistor 2 serves as both the polysilicon connection portion and the polysilicon resistor of the first embodiment, and is not divided.

[0146] The contact hole 18b' that becomes the contact portion between the anode electrode 17a and the polysilicon layer 71 is configured in a generally annular shape with a diameter larger than the inner diameter of the anode electrode 17a and smaller than the diameter of the polysilicon layer 71. The contact hole 18c that becomes the contact portion between the limiting resistance electrode 17b and the polysilicon layer 71 is configured in a generally annular shape with a diameter smaller than the diameter of the limiting resistance electrode 17b. The diameter of the polysilicon layer 71 is larger than the diameter of the contact hole 18b'. The diameter of the polysilicon layer 71 may also be smaller than the outer diameter of the anode electrode 17a.

[0147] like Fig.11 , Fig.12 As shown, the planar shape of the polysilicon layer 71' constituting the current limiting resistor 2 can be set to be roughly annular. In this case, the contact hole 18b' that becomes the contact portion between the anode electrode 17a and the polysilicon layer 71' is configured to be roughly annular in shape, with a diameter larger than the inner diameter of the anode electrode 17a and smaller than the outer diameter of the polysilicon layer 71'. The contact hole 18c that becomes the contact portion between the limiting resistor electrode 17b and the polysilicon layer 71' is configured to be roughly annular in shape, with a diameter smaller than the diameter of the limiting resistor electrode 17b and larger than the inner diameter of the polysilicon layer 71'. Fig.11 , Fig.12 The structure of the semiconductor device of the third embodiment shown in the figure is the same as that of the semiconductor device of the third embodiment except for the planar shape of the polysilicon layer 71'. Fig. 9 , Fig.10 The semiconductor device of Embodiment 3 shown is the same.

[0148] In addition, if Fig.13 , Fig.14As shown, the current limiting resistor 2 may also be composed of a plurality of (here, four) polysilicon layers 72 to 75 formed by dividing a polysilicon layer 71' having a roughly annular planar shape into a fan-shaped planar shape centered on the center of the polysilicon layer 71'. In this case, the plurality of polysilicon layers 72 to 75 are arranged separately from each other. The contact hole 18b' that serves as the contact portion between the anode electrode 17a and each polysilicon layer 72 to 75, and the contact hole 18c that serves as the contact portion between the limiting resistor electrode 17b and the polysilicon layer 71' are divided into a roughly arc shape that is opposed only to each polysilicon layer 72 to 75 having a fan-shaped planar shape. Fig.13 , Fig.14 The structure of the semiconductor device of the third embodiment shown in the figure is the same as that of the semiconductor device of the third embodiment except for the planar shape of the polysilicon layers 72 to 75. Fig.11 , Fig.12 The semiconductor device of Embodiment 3 shown is the same.

[0149] exist Fig. 9 , Fig.11 , Fig.13 In the figure, the polysilicon layers 71, 71', 72 to 75 that function as the polysilicon resistors of the current limiting resistor 2 are dotted shaded portions. The limiting resistor electrode 17b is a shaded portion that is inclined downward to the right and is surrounded by a dotted circle. The anode electrode 17a is a shaded portion that is inclined upward to the right and is sandwiched between two dotted lines that are denser than the limiting resistor electrode 17b. The contact holes 18b' and 18c are indicated by thick solid lines.

[0150] As described above, according to the third embodiment, current can be uniformly passed through one or more polysilicon layers serving as both polysilicon connecting portions and polysilicon resistors, thereby achieving the same effects as those of the first and second embodiments.

[0151] In addition, although omitted from the illustration, the planar shape of the bootstrap diode 1 (i.e., the planar shape of the p-type anode region 13) can also be set to be roughly rectangular. In this case, the polysilicon connection portion of the current limiting resistor 2 is set to, for example, a rectangular planar shape. The multiple polysilicon layers that function as the polysilicon resistor of the current limiting resistor 2 can also be configured as a layout that surrounds the polysilicon connection portion in a rectangular and multiple manner. Alternatively, the multiple polysilicon layers that function as the polysilicon resistor of the current limiting resistor 2 can also be configured as: a lightning-shaped planar shape that connects multiple straight-line portions together and has a locally bent portion, and a vortex shape with the connection portion with the polysilicon connection portion as the starting point and the contact hole with the anode electrode as the end point, extending outward in a manner separated from the polysilicon connection portion.

[0152] As mentioned above, the present invention is not limited to the above-mentioned embodiments, and various changes can be made within the scope of the purpose of the present invention. For example, in the above-mentioned embodiments, the metal electrodes (anode electrode, limiting resistor electrode and FP) are arranged in a manner of burying the contact holes, but it is not limited to this. Barrier metal or plugs can also be buried inside the contact holes, and the metal electrodes are electrically connected to the corresponding parts through the barrier metal or plug inside the contact holes. In addition, components and / or circuits other than the bootstrap diode and the current limiting resistor can also be mounted on the same semiconductor substrate as the bootstrap diode and the current limiting resistor.

[0153] Industrial Applicability

[0154] As described above, the semiconductor device of the present invention is useful as a power semiconductor device used in a power conversion device such as an inverter, a power supply device for various industrial machines, an ignition device for an automobile, and the like.

Claims

1. A semiconductor device, characterized in that: have: A first semiconductor region of the second conductivity type is selectively disposed on a surface layer of the front surface of the semiconductor substrate of the first conductivity type; A second semiconductor region of the first conductivity type is a portion of the semiconductor substrate other than the first semiconductor region; A bootstrap diode formed by a pn junction of the first semiconductor region and the second semiconductor region; an insulating layer, covering the front surface of the semiconductor substrate; a polysilicon layer, disposed inside the insulating layer and facing the first semiconductor region across the insulating layer; a first electrode, electrically contacting the first semiconductor region and the polysilicon layer; a second electrode, electrically contacting the polysilicon layer; as well as a third electrode, disposed on the back side of the semiconductor substrate and in contact with the second semiconductor region, The first contact portion between the first electrode and the first semiconductor region is configured in a ring shape surrounding the polysilicon layer. Second contacts between the first electrode and the polysilicon layer are evenly arranged at positions inside the ring of the first contact portion and with respect to the ring of the first contact portion. A third contact portion between the second electrode and the polysilicon layer is uniformly arranged with respect to the second contact portion at a position further inside than the second contact portion, The polysilicon layer has: The first polysilicon portion is in electrical contact with the second electrode via the third contact portion. a plurality of second polysilicon portions, arranged at positions further outward than the first polysilicon portion, connected to the first polysilicon portion at inner ends thereof, and electrically contacting the first electrode at outer ends thereof via the second contact portions, A plurality of the second polysilicon portions are evenly arranged with respect to the third contact portion.

2. The semiconductor device according to claim 1, wherein: The widths of the plurality of second polysilicon portions are constant from a connection portion with the first polysilicon portion to the second contact portion.

3. The semiconductor device according to claim 1, wherein: A plurality of the second polysilicon portions are connected in parallel between the third contact portion and the second contact portion.

4. The semiconductor device according to claim 2, wherein: A plurality of the second polysilicon portions are connected in parallel between the third contact portion and the second contact portion.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The first polysilicon portion has a circular planar shape, The plurality of second polysilicon portions extend outward in a spiral shape and surround the first polysilicon portion, wherein the spiral shape starts from a connection portion with the first polysilicon portion and ends at the second contact portion.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that: The second contact portion is arranged at an equal distance from the first contact portion.

7. The semiconductor device according to claim 5, wherein: The second contact portion is arranged at an equal distance from the first contact portion.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that: The third contact portion is arranged at an equal distance from the second contact portion.

9. The semiconductor device according to claim 5, wherein: The third contact portion is arranged at an equal distance from the second contact portion.

10. The semiconductor device according to claim 6, wherein: The third contact portion is arranged at an equal distance from the second contact portion.

11. The semiconductor device according to claim 7, wherein: The third contact portion is arranged at an equal distance from the second contact portion.

12. The semiconductor device according to any one of claims 1 to 4, characterized in that: The surface area of ​​the polysilicon layer is greater than 40% of the surface area of ​​the first semiconductor region.

13. The semiconductor device according to claim 5, wherein: The surface area of ​​the polysilicon layer is greater than 40% of the surface area of ​​the first semiconductor region.

14. The semiconductor device according to claim 6, wherein: The surface area of ​​the polysilicon layer is greater than 40% of the surface area of ​​the first semiconductor region.

15. The semiconductor device according to claim 8, wherein: The surface area of ​​the polysilicon layer is greater than 40% of the surface area of ​​the first semiconductor region.

16. The semiconductor device according to claim 12, wherein: The surface area of ​​the polysilicon layer is equal to the surface area of ​​the first semiconductor region.

17. The semiconductor device according to claim 13, wherein: The surface area of ​​the polysilicon layer is equal to the surface area of ​​the first semiconductor region.

18. The semiconductor device according to claim 14, wherein: The surface area of ​​the polysilicon layer is equal to the surface area of ​​the first semiconductor region.

19. The semiconductor device according to claim 15, wherein: The surface area of ​​the polysilicon layer is equal to the surface area of ​​the first semiconductor region.

20. A semiconductor device, characterized in that: have: A first semiconductor region of the second conductivity type is selectively disposed on a surface layer of the front surface of the semiconductor substrate of the first conductivity type; A second semiconductor region of the first conductivity type is a portion of the semiconductor substrate other than the first semiconductor region; A bootstrap diode formed by a pn junction of the first semiconductor region and the second semiconductor region; an insulating layer, covering the front surface of the semiconductor substrate; a polysilicon layer, disposed inside the insulating layer and facing the first semiconductor region across the insulating layer; a first electrode, electrically contacting the first semiconductor region and the polysilicon layer; a second electrode, electrically contacting the polysilicon layer; as well as a third electrode, disposed on the back side of the semiconductor substrate and in contact with the second semiconductor region, The first contact portion between the first electrode and the first semiconductor region is configured in a ring shape surrounding the polysilicon layer. Second contacts between the first electrode and the polysilicon layer are evenly arranged at positions inside the ring of the first contact portion and with respect to the ring of the first contact portion. A third contact portion between the second electrode and the polysilicon layer is uniformly arranged with respect to the second contact portion at a position further inside than the second contact portion, The second contact portion is configured as a ring having an equal distance from the first contact portion, The third contact portion is configured as a ring with an equal distance from the second contact portion, The polysilicon layer has a ring-shaped plane shape, The third contact portion is located outside the inner periphery of the polysilicon layer. The polysilicon layer is separated into a plurality of sector-shaped plane shapes.

21. The semiconductor device according to claim 20, wherein: The surface area of ​​the polysilicon layer is greater than 40% of the surface area of ​​the first semiconductor region.

22. The semiconductor device according to claim 21, wherein: The surface area of ​​the polysilicon layer is equal to the surface area of ​​the first semiconductor region.

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