Adaptive digital controllers including linear and nonlinear control mechanisms

Abstract

Some embodiments include devices and methods of using such devices. One of these devices includes a control circuit for: generating error information based on the value of a feedback voltage generated from an output voltage, generating output information based on the error information provided to a forward path in the control circuit to control a power switching unit, and adjusting the gain of the forward path based on a gain factor calculated at least in part based on a first value of the output information so that the output information has a second value. When the output voltage is within a target value range, the control circuit also calculates a value of correction information, and when the output voltage is outside the target value range, the control circuit adjusts the control information based on the correction information.

Description

[0001] Priority claim

[0002] This patent application claims the benefit of priority to U.S. Patent Application No. 15 / 484,404, filed on April 11, 2017, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments described herein relate to power management in electronic systems.Some embodiments relate to voltage regulators. Background Art

[0004] Many electronic devices or systems (e.g., computers, tablet devices, and cellular phones) have power management components (e.g., voltage regulators) to control the voltage (e.g., supply voltage) in the device or system. The power management component can periodically monitor the voltage value in the device or system to maintain the voltage within a target value range. During some events in the operation of the device (e.g., a surge in current consumption), the value of the voltage may suddenly deviate from the target value range. Some conventional technologies provide control mechanisms to handle such events. However, different devices have different operating schemes. Therefore, some conventional control mechanisms designed for certain devices may not be suitable for certain other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A block diagram of an apparatus including a voltage regulator and a load is shown according to some embodiments described herein.

[0006] Figure 2 The present invention shows some embodiments according to the present invention. Figure 1 Schematic diagram of the error code generator for the voltage regulator.

[0007] Figure 3 The invention is shown in accordance with some embodiments described herein. Figure 1 The controlled object model (plant model) of the power FET (field effect transistor) structure implemented in the voltage regulator.

[0008] Figure 4 The present invention shows some embodiments according to the present invention. Figure 1 A simplified implementation of a digital linear controller for a voltage regulator.

[0009] Figure 5A The present invention shows some embodiments according to the present invention. Figure 4 Schematic diagram of the adaptive gain circuit of a digital linear controller.

[0010] Figure 5B The present invention shows some embodiments according to the present invention. Figure 5A The multiplier of the adaptive gain circuit.

[0011] Figure 6 The present invention shows some embodiments according to the present invention. Figure 4 FIG. 1 is a diagram of another adaptive gain circuit of a digital linear controller.

[0012] Figure 7 Example waveforms of output voltage and load current during an example droop event are shown according to some embodiments described herein.

[0013] Figure 8 The present invention shows some embodiments according to the present invention. Figure 1 Figure 1 is a simplified diagram of the architecture of a nonlinear controller for a voltage regulator.

[0014] Fig. 9 The present invention shows some embodiments according to the present invention. Figure 8 Block diagram of the counting measurement logic circuit of the nonlinear controller.

[0015] Fig.10 An apparatus is shown in the form of an electronic system according to some embodiments described herein.

[0016] Fig.11 is a flow chart of a method of operating an apparatus according to some embodiments described herein. DETAILED DESCRIPTION

[0017] In many devices (e.g., processors), power management (e.g., fine-grained power management using dynamic voltage and frequency scaling (DVFS)) has become important in improving the performance-to-power ratio at different power states of the device. In these devices, entry and exit of certain operating modes (e.g., idle mode to burst mode) can occur very quickly (e.g., in a few core clock cycles, where the core frequency is in the GHz range). Functional units in these devices (e.g., multi-core central processing units (CPUs)) can operate at a wide range of load currents (I 负载 ) range, which in turn can cause wide variations in the rate at which the load current changes (di / dt) during load steps (when the load current increases). These fast load transients (e.g., rapid changes in load current) can cause large droops (sudden decreases in voltage value) in the supply voltage of the device, where the on-die load capacitance may be limited (e.g., due to a small die area). Such droops in the supply voltage can limit the speed (e.g., core frequency) of the device.

[0018] Conventional low dropout (LDO) regulator circuits provide a viable low-cost solution where it is impractical to integrate a switching voltage controller into the die / package. LDO circuits can also allow for second-level power management (second-level fine-grained power management) if the voltage supply from the same supply rail provides power to multiple functional units in the same device. LDO circuits can provide optimal voltage supply for each functional unit. Digital LDO circuits are becoming increasingly popular due to their scalability and ultra-low voltage operation (operation close to the threshold) where analog circuits may not be suitable. Digital control of LDO circuits and associated power transistors can allow flexibility in device reconfigurability. Some conventional linear digital controllers can provide stable and smooth transient responses with low steady-state errors for different ranges of load current and output voltage conditions. However, such linear digital controllers may operate at a fixed sampling frequency and may be limited by the bandwidth of the control loop. This may make such conventional linear controllers unsuitable for providing adequate response during some operating conditions, such as fast transient response during droop events.

[0019] In addition, some conventional linear control techniques are designed for a relatively small range of load currents and for worst-case operating conditions. Such techniques may not provide adequate response for a relatively wide range of load currents. Furthermore, loop performance in such conventional linear control techniques may be degraded even for a small load current range because conventional techniques typically apply a fixed compensation to correct errors caused by droop regardless of load variations. Furthermore, the lack of robust nonlinear control is prone to over- and under-correction for a relatively wide range of load currents and is prone to large variations at the beginning and end of the rate of change of load current across the output voltage range.

[0020] References Figures 1 to 11 The described technology includes a voltage regulator that includes digital linear control and nonlinear control that can support a wide range of load current and voltage dropout. Figures 1 to 11 Detailed circuit components, operation, and improvements are described.

[0021] Figure 1 A block diagram of an apparatus 100 including a voltage regulator 110 and a load 115 according to some embodiments described herein is shown. The apparatus 100 may include or may be included in an electronic device or system, such as a computer (e.g., a desktop, laptop, or notebook), a tablet device, a cellular phone, a wearable electronic device (e.g., a smart watch), or other electronic device or system.

[0022] like Figure 1As shown in FIG. 1 , the voltage regulator 110 may include a control unit 111 for generating control information (eg, digital code) control_code to control the power switching unit 112. The control unit 111 may monitor and detect the voltage V at the node 102. 输出 to control (eg, adjust) the value of the control information control_code so as to reduce the voltage V 输出 The value is maintained at the target value. 输出 When the value deviates from the target value, the voltage V 输出 The target value may be a voltage value within a target value range (eg, a predetermined value range).

[0023] The power switching unit 112 can be controlled by the control unit 111 so that the voltage V 输入 (e.g., supply voltage Vcc) and V 输出 The difference between the values ​​of (e.g., output voltage) is relatively small (e.g., low dropout (LDO)). Therefore, V 输出 The value can be greater than the voltage V 输入 The value of is smaller than a relatively small amount. Therefore, the voltage regulator 110 may operate as a low dropout (LDO) voltage regulator.

[0024] The load 115 can use the voltage V 输出as its supply voltage (e.g., a regulated supply voltage). The load 115 may include or be included in a functional unit, such as a processor (e.g., a single-core processor, a multi-core processor) that may include at least one central processing unit (CPU), a memory device, or other functional units. The voltage regulator 110 and the load 115 may be located on the same integrated circuit (IC) die (e.g., IC chip) (e.g., may be formed in the same integrated circuit (IC) die, may be formed on the same integrated circuit (IC) die, or may be integrated in the same integrated circuit (IC) die). The IC die may include a semiconductor die (e.g., a silicon die). Alternatively, the voltage regulator 110 and the load 115 may be located on different IC dies. For example, the voltage regulator 110 may be located on one IC die of a device on a circuit board (e.g., a motherboard), and the load 115 may be located on a different IC die of another device on the circuit board. The power switching unit 112 may be formed external to the voltage regulator 110 and the load 115 (e.g., excluded from the IC die (or multiple IC dies) in which the voltage regulator 110 and the load 115 are located). Alternatively, a portion of the power switching unit 112 or the entire power switching unit 112 may be located in the same IC die as the voltage regulator 110 (e.g., formed in the same IC die, formed on the same IC die, or integrated into the same IC die). The device 100 may include a system on a chip (SoC) or be included in a system on a chip (SoC), such that the voltage regulator 110 and the load 115 may be included (e.g., integrated) in the SoC.

[0025] The voltage regulator 110 can operate in a linear mode (eg, a steady-state mode) and a nonlinear mode. 输出 The error has a value less than a certain (eg, predetermined) value (eg, when V 输出 If the voltage V 输出 The error has a value greater than the specific value (for example, when V 输出 When the value of is outside the target value range), the voltage regulator 110 can change from the linear mode to the nonlinear mode. The error that causes the voltage regulator 110 to change from the linear mode to the nonlinear mode may include the voltage V 输出 The droop (for example, V 输出 Such a droop (or droop event) may occur during a load transient event at the load 115. A load transient event may occur when the load 115 changes from one operating state (e.g., an idle state) to another operating state (e.g., an active state). Figures 2 to 9As described in more detail, the voltage regulator 110 can adaptively and dynamically correct the voltage V 输出 error (e.g., to correct droop) until the voltage V 输出 returns the value to the target value.

[0026] like Figure 1 As shown in FIG. 1 , the control unit 111 may include an error code generator 120 and a control circuit 125, the control circuit 125 including a digital linear controller 130 and a nonlinear controller 140 and a selector 150 (eg, a multiplexer). The control unit 111 may also include a capacitor C i 、Capacitor C 负载 (e.g., load capacitor), resistor R ers , and resistors R1 and R2 (eg, a voltage divider). The components of the control unit 111 may form a digitally controlled LDO circuit in a closed loop to control the voltage V in both the linear mode and the nonlinear mode of the voltage regulator 110. 输出 The value of .

[0027] The error code generator 120 may be operated to generate a voltage V 输出 The error information (eg, digital error code) error_code_p and error information (eg, digital error code) error_code_n are generated. When the voltage V 输出 When the value deviates from the target value, the voltage V 输出 The error occurs.

[0028] The digital linear controller 130 may generate output information (eg, a digital linear output code) dlc_out based on the error information error_code_p. The output information may be used during the linear mode to adjust the voltage V 输出 The value of is maintained at zero error or close to zero error.

[0029] The nonlinear controller 140 may generate output information (e.g., a digital nonlinear output code) nl_out based on the error information error_code_p and error_code_n. The nonlinear controller 140 may also generate a signal nl_mode_en (nonlinear mode enable signal), which may be activated (e.g., changed from a lower signal level (e.g., a logic zero level) to a higher signal level (e.g., a logic one level) to indicate entry into the nonlinear mode (from the linear mode). The output information nl_out may be used during the nonlinear mode to improve the transient response of the voltage regulator 110 during a load step (e.g., when the current at the node 102 increases).

[0030] Depending on which mode (e.g., linear or nonlinear mode) the voltage regulator 110 is operating at a particular time, the selector 150 may select (based on the signal level of the signal nl_mode_en) either the output information dlc_out or the output information nl_out as the control information control_code at the output port 126 of the control circuit 125. Thus, in the linear mode, the control information control_code is based on the output information dlc_out (e.g., in the linear mode, control_code=dlc_out), and in the nonlinear mode, the control information control_code is based on the output information nl_out (e.g., in the nonlinear mode, control_code=nl_out). As an example, if each of the output information dlc_out and the output information dlc_out is an N-bit code (where N is the number of bits), the control information control_code is also an N-bit code in the linear mode or the nonlinear mode. Thus, in this example, in the linear mode, control_code=dlc_out=N, and in the nonlinear mode, control_code=nl_out=N.

[0031] For simplicity, this specification sometimes uses the term "control_code" (with quotes) or the term control_code (without quotes and without the associated label "control information") to refer to the control information control_code or the value of the control information control_code (e.g., the value of N bits). Similarly, the term "dlc_out" (with quotes) or the term dlc_out (without quotes) refers to the output information dlc_out or the value of the output information dlc_out (e.g., the value of N bits). And the term "nl_out" (with quotes) or the term nl_out (without quotes) refers to the output information nl_out or the value of the output information nl_out (e.g., the value of N bits). The same pattern applies to other terms (e.g., variables or parameters) described herein, such that a particular term associated with a term (with quotes or without quotes) refers to the name or value of such a term.

[0032] like Figure 1 As shown in FIG. , the error code generator 120 may receive a voltage V FB and V REF_IN Voltage V FB It can be based on the voltage V 输出 The feedback voltage generated. For example, the voltage V FB The value can be a voltage V based on the values ​​of resistors R1 and R2 输出 The voltage V can be generated from a bandgap-based reference voltage (not shown). REF_INAs described in more detail below, error code generator 120 may generate a voltage V REF_IN Generate a series of reference voltages. The error code generator 120 can convert the voltage V FB The error code generator 120 may be compared with the series of reference voltages, and error information error_code_p and error_code_n may be generated based on the result of the comparison. The error code generator 120 may receive a clock signal Fclk (e.g., a sampling clock signal) that may be used as a timing for comparison. Each of the error information error_code_p and the error information error_code_n is a digital code (e.g., a digital error code) including a plurality of bits. The error code generator 120 may be based on the voltage V at the positive edge (e.g., rising edge) of the clock signal Fclk. FB The error code generator 120 can generate error information error_code_p based on the comparison result with the series of reference voltages. The error code generator 120 can generate error information error_code_p based on the voltage V at the negative edge (eg, falling edge) of the clock signal Fclk. FB The comparison result with this series of reference voltages is used to generate error information error_code_n.

[0033] The control circuit 125 may use the control information control_code to control (eg, turn on or off) a plurality of current paths (eg, “branches”) in the power switching unit 112 so as to increase the voltage V 输出 The value of is maintained within the target value range. The control circuit 125 may periodically adjust (e.g., update) the value of the control information control_code (depending on the mode of the voltage regulator 110, the control information may be the output information dlc_out or nl_out). As described above, the control information control_code may include a plurality of bits (e.g., N bits).

[0034] The output port 126 providing the control information control_code may include conductive nodes (e.g., portions of parallel wires) that may carry different signals (e.g., carry signals in parallel on the output port 126). Each of the signals on the output port 126 may include signal levels corresponding to binary 0 (logic 0) and binary 1 (logic 1). The signal levels of the signals carried by the output port 126 may represent the value of the control information control_code. For example, if the control information control_code has 12 bits (e.g., N=12 bits), the output port 126 may include 12 nodes (or 12 wires) to simultaneously carry 12 corresponding signals including bit values ​​of N=12 bits. As described above, in a linear mode, control_code=dlc_out=N, and in a nonlinear mode, control_code=nl_out=N. Therefore, in the example here, dlc_out includes N=bits, and nl_out includes N=bits.

[0035] like Figure 1 As shown in , the power switching unit 112 may include a transistor group 113, which includes transistors (e.g., power transistors) 114a, 114b, 116a, and 116b coupled between the node 101 and the node 102. Transistors 114a, 114b, 116a, and 116b may include field effect transistors (FETs) (such as p-channel FETs). The transistor group (e.g., power FET group) 113 may be a binary weighted transistor group. Each of the transistors 114a and 114b can be controlled by different bits in the bits (e.g., N bits) included in the control information control_code.

[0036] Transistors 114a, 114b, 116a, and 116b may be part of different current paths (e.g., parallel current paths) between node 101 and node 102. For example, transistors 114a and 114b may be part of current path 164, and transistors 116a and 116b may be part of current path 165. In this specification, current paths 164 and 165 are sometimes referred to as "current branches" or simply "branches." Therefore, the current flowing on each of current paths 164 and 165 may be referred to as "current per leg" or alternatively may be referred to as "I_per_leg." Transistor group 113 may provide current I 负载 (e.g., load current).

[0037] Figure 1A transistor group 113 is shown, which, as an example, includes only four transistors 114a, 114b, 116a, and 116b. The transistor group 113 may include a different number of transistors. The number of transistors may be based on the number of bits (e.g., N bits) of the control information control_code. For example, if the control_code includes 12 bits, the transistor group 113 may include 24 transistors (e.g., 12 transistors similar to transistors 114a and 116a coupled to another 12 transistors similar to transistors 114b and 116b). In this example, the 24 transistors may be part of 24 different current paths (e.g., 24 branches) similar to the current paths (e.g., branches) 164 and 165. As described above, the voltage V 输出 During steady state, the voltage V is maintained within the target value range. The control information control_code can be used to control (eg, turn on or off) an appropriate number of transistors (eg, 114a and 116a) to control the voltage V 输出 The value of .

[0038] like Figure 1 As shown in , the power switching unit 112 may also include a replica portion 117, an amplifier 118, and a reference current source 119 for generating a current Iref, the replica portion 117 including a transistor 117a and a transistor 117b. The value of the current Iref may be a predetermined (e.g., known) value. During operation, the transistors of the transistor group 113 (e.g., transistors 114a, 114b, 116a, and 116b) may use the replica portion 117 to form a current limiter used as a controllable current source, wherein a fixed current per leg (I_per_leg) is maintained within reliability limits of a higher voltage difference (e.g., a voltage difference greater than 100mV). The voltage difference (or voltage difference) is V 输入 With V 输出 The difference between (e.g., voltage difference = V 输入 -V 输出 ).

[0039] The replica portion 117 may use the amplifier 118 to receive a voltage (eg, a reference voltage) Vref_mid to generate a voltage V 偏置 To set each branch current to a multiple of the current "Iref". However, the current source provided by the transistors of transistor group 113 (e.g., 114b and 116b) has a finite output resistance (Ro), which varies with the voltage difference. For lower voltage differences (e.g., voltage differences less than 100mV), transistors 114b and 116b can behave like resistors (e.g., fully turned-on transistors) because the voltage V 偏置It can be zero (e.g., ground potential) or closer to zero, and the current in each branch can fall within safe limits, but is no longer constant. At a lower voltage difference, the current in each branch depends on the voltage difference across transistors 114a, 114b, 116a, and 116b. Transistors 114a and 116a are digitally controlled (e.g., turned on or off) based on the bits (e.g., N bits) of control_code so as to turn on the corresponding number of branches. This allows the power switching unit 112 to provide sufficient current (e.g., source) required by the load 115 at a higher voltage difference, or to provide sufficient current (e.g., source) for the voltage V at a lower voltage difference. 输出 The value of maintains a voltage drop across transistors 114a, 114b, 116a, and 116b.

[0040] As described above, the voltage regulator 110 can operate in a linear mode and a nonlinear mode. In the linear mode (e.g., during steady state), the control circuit 125 can operate at a fixed frequency, updating dlc_out at each positive clock edge based on error_code_p. The control circuit 125 can activate the signal nl_mode_en so that when V 输出 The output information nl_out can be used to correct the voltage V with a much faster response than the output information dlc_out. 输出 The nonlinear controller 140 can operate at twice the frequency of the digital linear controller 130. This can be achieved by using the two edges of the clock signal Fclk to generate "error_code_p" and "error_code_n". Control_code can automatically switch between dlc_out and nl_out based on the latest values ​​of error_code_p and error_code_n.

[0041] Therefore, the voltage regulator 110 can use dlc_out for control_code (eg, control_code=dlc_out=N bits) during the linear mode, as described below with reference to Figures 2 to 6 The voltage regulator 110 may use nl_out for control_code (control_code=nl_out=N bits) during the non-linear mode, as described below. Figures 7 to 9 Give a description.

[0042] Figure 2 The present invention shows some embodiments according to the present invention. Figure 1Schematic diagram of error code generator 120. Error code generator 120 may include reference generation circuit 210 and analog-to-digital converter (ADC) 220, which may include a windowed flash ADC. Reference generation circuit 210 and ADC 220 may be operated to generate a series of reference voltages for comparison with voltage V FB (The voltage V FB Based on the voltage V 输出 ) are compared and used to generate error codes error_code_p and error_code_n.

[0043] The reference generation circuit 210 can be based on V REF_IN (eg, based on a bandgap voltage) and resistors R3 and R4 (eg, a voltage divider) generate a divided voltage V DIV . V DIV The DAC 214 may be buffered by a unity gain buffer 212 to generate a voltage Dac_ref, which is fed to a digital-to-analog converter (DAC) 214 (e.g., a 7-bit main R-DAC). The DAC 214 may include a resistor circuit 214a and a multiplexer circuit (MUX) 214b (e.g., a 2x MUX with 126 taps). The DAC 214 may receive codes Dac_code 1 (e.g., a 7-bit code) and Dac_code 2 (e.g., a 7-bit code) and generate voltages Vref_top and Vref_bot at respective outputs of the DAC 214. The voltages Vref-top and Vref-bot may be the highest threshold and the lowest threshold, respectively, of the ADC 220.

[0044] The voltages Vref_top and Vref_bot may be buffered by unity gain buffers 216a and 216b to feed a secondary DAC 217 (e.g., R-DAC) to generate eight reference voltages Vref_tap_p1, Vref_tap_p2, Vref_tap_p4, Vref_tap_p6, Vref_tap_m1, Vref_tap_m2, Vref_tap_m4, and Vref_tap_m6 (collectively referred to as “ADC input reference voltages” for simplicity). The ADC input reference voltages are provided to the ADC 220 as input reference voltages for determining the voltage V within an error range. 输出 (For example, a voltage V within a + / -60mV error range 输出 )’s error magnitude.

[0045] The value of each of the eight ADC input reference voltages may be relative to a voltage Vref_mid, which may be a midpoint value between the values ​​of Vref_tap_p6 and Vref_tap_m6. The values ​​of each of Vref_tap_p1, Vref_tap_p2, Vref_tap_p4, and Vref_tap_p6 may be the value of Vref_mid plus 1Vx, 2Vx, 4Vx, and 6Vx, respectively. The voltage Vx is an amount of voltage (e.g., a predetermined amount). For example, if Vx=6mV, then

[0046] Vref_tap_p1=Vref_mid+1Vx=Vref_mid+6mV

[0047] Vref_tap_p2=Vref_mid+2Vx=Vref_mid+12mV

[0048] Vref_tap_p4=Vref_mid+4Vx=Vref_mid+24mV

[0049] Vref_tap_p6=Vref_mid+6Vx=Vref_mid+36mV.

[0050] The value of each of Vref_tap_m1, Vref_tap_m2, Vref_tap_m4, and Vref_tap_m6 may be the value of Vref_mid minus 1Vx, 2Vx, 4Vx, and 6Vx, respectively.

[0051] Therefore, if Vx = 6mV (based on the above example), then

[0052] Vref_tap_m1=Vref_mid+1Vx=Vref_mid-6mV

[0053] Vref_tap_m2=Vref_mid+2Vx=Vref_mid-12mV

[0054] Vref_tap_m4=Vref_mid+4Vx=Vref_mid-24mV

[0055] Vref_tap_m6=Vref_mid+6Vx=Vref_mid-36mV.

[0056] like Figure 2 As shown in FIG. 1 , ADC 220 may include a comparator circuit 224 having eight comparators 225 (eg, comparators clocked using the positive edge of clock signal Fclk) to convert V FBThe error_code_p is compared with each of the eight ADC input reference voltages. The output of the comparator 225 can be obtained based on the positive edge of the clock signal Fclk. Based on the result of the comparison, the comparator circuit 224 can generate an error_code_p, which can include 8 bits (8-bit thermometer code) [7:0]. Each of the eight bits [7:0] of error_code_p can be generated at one of the comparators 225 at the rising edge of the clock signal Fclk. The value of the bit [7:0] of error_code_p represents the error code based on V 输出 The voltage V obtained by the positive edge 输出 The voltage error of error_code_p is provided as a digital linear controller 130 and a nonlinear controller 140 ( Figure 1 ) input. The control circuit 125 can perform a thermometric-to-binary conversion to convert bits [7:0] of error_code_p to a positive ADC error level pos_error_code + / -1, + / -2, + / -4, + / -6 (for example), where positive values ​​(e.g., +1, +2, +4, and +6) can indicate that V 输出 droop, and negative values ​​(e.g., -1, -2, -4, and -6) can indicate that V 输出 Overshoot. V 输出 The error value of may be based on pos_error_code (ADC error level) multiplied by a voltage value (eg, a predetermined value). 输出 The error value can be based on pos_error_code*10mV.

[0057] like Figure 2 As shown in FIG. 1 , ADC 220 may further include a comparator circuit 226 having five comparators 227 (eg, comparators clocked using the negative edge of clock signal Fclk) to convert V FBCompare with each of the five input reference voltages (five input reference voltages in eight ADCs) Vref_tap_p1, Vref_tap_p4, Vref_tap_m1, Vref_tap_m4, and Vref_tap_m6. The output of the comparator 227 can be obtained based on the negative clock edge of the clock signal Fclk. Based on the result of the comparison, the comparator circuit 226 can generate an error_code_n, which may include 5 bits (5-bit thermometer code) [4:0]. Each of the five bits [4:0] of error_code_n can be generated at one of the comparators 227 at the falling edge of the clock signal Fclk. The value of the five bits [4:0] of error_code_n represents the voltage V obtained based on the negative edge of the clock signal Fclk. 输出 The voltage error of error_code_n bit [4:0] is used as the nonlinear controller 140 of the control circuit 125 ( Figure 1 ) is provided. The control circuit 125 can perform a thermometer-to-binary conversion to convert bits [4:0] of error_code_n to negative ADC error levels neg_error_code + / -1, + / -4, + / -6 (for example). During a load step, if (for example, due to V 输出 droop or overshoot at V 输出 Upon crossing a nonlinear threshold (eg, + / -4 corresponding to a + / -40 mV output error) on either a positive or negative clock edge, control circuit 125 may enter a nonlinear mode and nonlinear controller 140 may operate to correct the error.

[0058] exist Figure 2 In the embodiment of the present invention, comparator 225 of comparator circuit 224 and comparator 227 of comparator circuit 226 may respectively use auto-zero offset cancellation to ensure that the comparator offset remains low (e.g., within + / - 1 / 2 LSB (least significant bit)) and the ADC output is monotonic.

[0059] The control circuit 125 may perform bubble correction on the 8-bit [7:0] thermometer code of error_code_p and the 5-bit [4:0] thermometer code of error_code_n to ensure proper thermometer code to binary code conversion of the ADC error code. Calibration may be performed in the reference generation to improve the ADC input reference voltage provided to the input of the comparator 225. For example, online calibration may be used to trim the random offset of the unity gain buffers 216a and 216b. The effect of any residual offset in the unity gain buffers 216a and 216b may act on the ADC range rather than on the delta between different references generated due to the use of the secondary DAC 217.

[0060] Figure 2 Comparator circuits 224 and 226 are shown, and as an example, the comparator circuits 224 and 226 include eight comparators 225 and five comparators 227, respectively. However, the number of comparators in one of the comparator circuits 224 and 226 or in both of the comparator circuits 224 and 226 may vary. For example, the number of comparators in one of the comparator circuits 224 and 226 or in both of the comparator circuits 224 and 226 may be increased to provide a higher resolution or range.

[0061] References Figure 1 and Figure 2 The description of FIG. 1 discusses the use of the error code generator 120 to generate error information error_code_p and error_code_n. The nonlinear controller 140 and the digital linear controller 130 ( Figure 1 ) can use the error information error_code_p and error_code_n to adjust the value of the control information control_code so as to adjust the voltage V 输出 The following description discusses the digital linear controller 130 ( Figures 3 to 6 ) and nonlinear controller 140( Figures 7 to 9 ) structure and operation.

[0062] Digital Linear Control Technology

[0063] Voltage regulator 110 ( Figure 1 ) can be defined by static parameters, including V 输入 (input voltage), V 输出 (output voltage), current per leg (I_per_leg), and on-resistance of the IC chip including the process corner of voltage regulator 110. The mentioned parameters may vary over time, but their variation may not be as great as the load current (e.g., I_per_leg) of a resistive load (e.g., load 115) during a load transient. 负载 ). The on-die load capacitance may also vary based on the number of functional units (e.g., processor cores in a multi-core processor in load 115) that are conducting in a given state. The digital linear control techniques described herein employ dynamic load pole cancellation and dynamic adjustment of adaptive direct current (DC) gain to effectively counteract rapid changes in load and slow changes in operating conditions of voltage regulator 110, as described below with reference to Figures 3 to 6 discussed.

[0064] Transfer function of the controlled object

[0065] Figure 3 A plant model 305 is shown of a digital linear control technique that may be implemented in the digital linear controller 130 according to some embodiments described herein. Figure 3 The controlled object model 305 can be used to describe the controlled object (transistor group 113 + load resistor R L + Load capacitor C 负载 ) transfer function. The current Ics presents the ideal current source current value accompanied by the parallel output resistance Ro. The current Ics and the output resistance R O The combination of is used to model the power FET. The term "N" represents the control_code (e.g., N bits generated by the digital linear controller 130 during linear mode) that determines the number of branches (current paths) to be turned on in the transistor group 113. In addition to the load resistance R that varies over a wide load current range (e.g., 0.1A to 15A), L In addition, the output resistance R of the transistor group 113 O can also change, and each branch current I 单位 Can drop in low voltage drop range (e.g., less than 100mV). Intrinsic capacitance C i can vary depending on the functional unit (e.g., processor core) that is turned on in load 115. However, if capacitor C i The change in capacitance C is small relative to the overall load capacitance, so the capacitance C can be ignored. i The digital linear control technique described herein can provide dynamic compensation to tighten the closed-loop response across controlled object variations using a single set of coefficients.

[0066] like Figure 3 The controlled plant model 305 shown in FIG. 3 has a 输出 ) / d(N), which can be rewritten using the approximation method shown below.

[0067]

[0068] Where G0 is the DC voltage gain per unit code change, w z is zero, and w p1 、w p2 are the poles of the transfer function.

[0069] in

[0070] Or G0=I 单位 (R L ||(R o / N)),

[0071] w z=1 / (R esr C 负载 ),

[0072] w p1 =1 / ((R esr +(R L ||(R o / N))C 负载 ),

[0073] w p2 =1 / ((R esr ||R L ||(R o / N))C i )

[0074] R esr Mainly C 负载 Therefore, R esr *C 负载 and w z1 Can remain constant. C i Usually also better than C 负载 Therefore, for the magnitude and phase response of the transfer function in the frequency band of interest, w p2 However, the load resistance R L , N, and G0 can vary significantly with load current. The term "N" represents control_code, which is equal to dlc_out in linear mode (e.g., in linear mode, control_code = dlc_out = N). For example, a change in load current from 250 mA to 15 A can cause R L The ratio is changed to 6000 (where R L = nominal output voltage (e.g., V 输出 ) / load current). In N (where N = load current / I 单位 ) and thus in G0, similar scale changes can occur. Therefore, the dominant pole w p1 The DC gain G0 can vary widely with load current. The output resistance Ro can also vary with the voltage dropout, and R L The output voltage may further vary within some output voltage range (e.g., 0.5V to 1.13V). Designing a digital compensator with fixed coefficients for such a controlled object that may vary significantly (as discussed above) may present challenges. However, as described below, the techniques described herein use a digital compensator across a wide load range to provide fixed coefficients (e.g., a single set of coefficients) without affecting transient performance or stability (e.g., without degrading transient performance or stability). The digital compensator discussed here and below may be included in Figure 1in the digital linear controller 130 (eg, a portion of the digital linear controller 130 ).

[0075] Adaptive Pole Cancellation and Adaptive DC Gain Equations

[0076] The digital compensator (which may be included in the digital linear controller 130) implements dynamic zeros to eliminate the dynamic dominant poles of the controlled object based on the techniques described herein, and implements adaptive DC gain to eliminate changes in the DC gain of the controlled object. Therefore, the transfer function of the digital compensator in the loop will have a dynamic (or adaptive) DC gain that is opposite to the changes in the controlled object, and has dynamic (or adaptive) zeros to eliminate dynamic poles in the controlled object across different operating conditions.

[0077] Therefore, through this understanding, and (R L ||Ro / N) is written in short form as "R eq ”, the initial transfer function of the digital compensator can be written as follows.

[0078] H(s)αH0(1+s / W z )

[0079] in, Among them G 设定点 is the controlled object DC gain at the set point used for coefficient calculation,

[0080] And W z =1 / ((R esr +R eq )C 负载 ), and w of the controlled object p1 Same

[0081]

[0082] In this form, R eq (=R L The term ||Ro / N) appears only in the first term as a gain factor and is completely absent in the second term. That is, the digital compensator can be implemented with adaptive gain and the adaptive coefficient can be ignored (e.g., it can be implemented with only adaptive gain without the adaptive coefficient). In addition to the dynamic zero, the digital compensator also has a static pole for setting the target bandwidth and a proportional integrator (PI) for stabilizing the system and reducing the steady-state error. The following equation indicates the full transfer function of the digital compensator including the static pole and the PI compensator.

[0083]

[0084] Where W p is a point, and K p +Ki / s is the PI compensator. R esr Mainly C 负载 The value calculated per unit, and therefore "R esr .C 负载 " is a constant and can be written as "R uesr Based on the above, the adaptive DC gain term can be expressed as follows.

[0085] Adaptive gain 1, and

[0086] Adaptive gain 2,

[0087]

[0088] where H(s) is a strict function and can therefore be realized.

[0089] Z-domain implementation

[0090] For implementation in the z-domain, the s-transfer function can be converted to the z-transfer function using a bilinear or Tustin transform of s=(z-1) / (z+1)*2 / T.

[0091]

[0092] Where A0, A1, B0, and B1 are constants.

[0093] simplify,

[0094]

[0095] Where a0, a1, a2, a'0, a'1, a'2, b1, and b2 are coefficients of a programmable digital compensator, and AG1 and AG2 are adaptive gain multiplier factors in two forward numerator paths of the digital compensator, which may be included in Figure 1 In the digital linear controller 130.

[0096] The implementation of the described digital compensator

[0097] Figure 4 shows some embodiments described herein. Figure 1 A simplified implementation of the digital linear controller 130 may include a digital compensator based on the above z transfer function H(z). Figure 4As shown in , the digital linear controller 130 may include forward paths (e.g., finite impulse response (FIR) filters) 410 and 420, which include corresponding adaptive gain circuits 411 (which can provide adaptive gain multiplier factors AG1) and adaptive gain circuits 422 (which can provide adaptive gain multiplier factors AG2). The digital linear controller 130 may include a feedback path 430. The FIR filters of the forward paths 410 and 420 may provide information (FIR filter outputs) FIR1_out (FIR1_output) and FIR2_out (FIR2_output), respectively. The forward path 420 may provide information (output of the forward path 420) FWD2_out, which is added to the output of the forward path 410 before the output of the feedback path 430 is subtracted.

[0098] like Figure 4 As shown in FIG. 4 , coefficients a0, a1, and a2 are fixed coefficients in the forward path 410, coefficients a0′, a1′, and a2′ are fixed coefficients in the forward path 420, and coefficients b1 and b2 are fixed coefficients in the feedback path 430. In short, the feedback path 430 can be fixed by inverting the signs of coefficients b1 and b2 using an adder (e.g., Figure 4 shown) to achieve this.

[0099] exist Figure 4 In the adaptive gain circuit 411, the information VID_code (corresponding to V nom The known digital information, and V nom Can be the target V 输出 ) and V voltage difference (for example, V 输入 –V 输出 ) information to adjust the gain of the forward path 410, and the adaptive gain circuit 422 uses each branch current (I 单位 ) Information 单位 yes Figure 1 AG2 (adaptive gain multiplier factor) is used to adjust the gain of forward path 420. 单位 The dependency is only visible in I 单位 At lower pressure differentials in descending conditions.

[0100] like Figure 4 As shown in FIG. 1 , the digital linear controller 130 may receive error_code_p and generate dlc_out (eg, an N-bit code). The value of dlc_out may also be based on feedback from nl_out ( Figure 1The output of the nonlinear controller 140 in FIG. 4 ) can be selected by multiplexers 433 and 435 using the signal nl_mode_en, such as Figure 4 In operation, the value of dlc_out may be updated at each clock cycle based on error_code_p to control (eg, turn on or off) transistor group 113 ( Figure 1 ) in the branches (e.g., current paths 164 and 165). The output information dlc_out can also be fed back to the adaptive gain circuit 411 to adjust the gain based on the current operating conditions. Since the error code only takes a few known values ​​(e.g., 0, + / -1, + / -2, + / -4, + / -6), the coefficients multiplied by error_code_p can be stored (e.g., pre-programmed) and kept ready by using the binary code information as a selection line of the multiplexer or using these coefficients as inputs to the multiplexer. This avoids the use of an additional multiplier (or multiple multipliers) in the forward path 410 in addition to the multiplier used in the adaptive gain circuit 411 to adjust the DC as described herein. This helps the voltage regulator 110 operate at a relatively high frequency (e.g., in the range of hundreds of megahertz) with relatively no timing issues or with negligible timing issues.

[0101] Adaptive Gain 1 (AG1) Derivation and Implementation

[0102] In the equations for AG1 and AG2 as described above, I 单位 (current per branch) and R eq (It is R L ||Ro / N) can both be changed. 单位 depends on the voltage difference, because the current in each branch drops at a lower voltage difference. Therefore, I 单位 can be adjusted only in the low dropout range. However, R eq Possibly with the load resistance R L and the output resistance Ro of transistor group 113. When transistor group 113 operates in a mostly linear region and is not saturated, the output resistance Ro may vary with the voltage difference, especially for voltage differences in the mid-range (e.g., 100 mV to 400 mV). Therefore, AG1 may need to be recalculated and refreshed every clock cycle.

[0103] I 单位 R eq =I 单位 (R L ||R o / N)

[0104]

[0105] Since for small droop / overshoot, ,therefore

[0106]

[0107] = > For higher pressure difference, For voltage differences <100 mV, the transistors of transistor group 113 may behave as resistors, and I 单位 can vary with the pressure difference. Therefore, the above equation can be rewritten as shown below.

[0108] = > For lower pressure difference,

[0109] Among them, V nom It can be obtained from the target information VID_code (corresponding to V nom The target output voltage (e.g., target V 输出 ). For a given dropout voltage, I 单位 *Ro is mostly constant and can be fed from a lookup table of differential pressure 单位 *Ro. From the known information VIN_code (corresponding to V 输入 digital information) and VID_code to calculate V 压差 The value of V 压差 = VIN_code - VID_code. The changing load current is indirectly represented by the control_code (e.g., N) of the previous cycle (because in linear mode, control_code = dlc_out, and the control_code of the previous cycle = dlc_out of the previous cycle), and V nom , "I 单位 .Ro", and V 压差 It is available according to the digital code.

[0110] Figure 5A The present invention shows some embodiments described in this paper. Figure 4 FIG. 4 is a diagram of an adaptive gain circuit 411. Figure 5A As shown in , AG1 (adaptive gain multiplier factor) can be calculated as a function of dlc_out from the previous cycle so that AG1 is adaptive to the load current. For example, if dlc_out is an N-bit code (where N is a digital bit), then dlc_out from the previous cycle can be provided by the value of N bits from the previous cycle.

[0111] like Figure 5A As shown in , dlc_out can be divided by a factor M1 (where M1 = 1 / G设定点 ) and M2 (where M2 = 1 / N 设定点 ). Divider 502 and divider 503 (e.g., using a right shift register as a divider) may be used to divide dlc_out from the previous cycle. Multiplexer 504 may be used to select the outputs of divider 502 and divider 503 as information N / M (based on signal Low_dropout_thres_sel). Dividing factors M1 and M2 may be selected as powers of 2 to implement a divider using a shifter. Using multiplier 550 ( Figure 5B ), and then provides information N / M as input information, which is used to multiply the gain factor selected using the final index, which is based on VID_code (V nom ) and V 压差 information to calculate, as described below. As mentioned above, V nom is the target output voltage known from the target VID_code, “I 单位 .Ro” is mostly constant for a given dropout voltage and can be fed from a lookup table of dropout voltages to “I 单位 .Ro”, and can be obtained from the known VIN_code (V 输入 ) and VID_code (Vnom, which is the target V 输出 ) Calculate V in digital form 压差 .

[0112] Figure 5B The present invention shows some embodiments according to the present invention. Figure 5A The multiplier 550 of the adaptive gain circuit 411. Figure 5B As shown in FIG. 1 , the gain factor multiplication using final_index (eg, 8-bit [7:0] final_index) can use the output code N / M (from Figure 5A ) to avoid the use of direct(multiple) multipliers / (multiple) dividers. Figure 5B The shift and add logic in is of the form 2^3*x(7)+2^2*x(6)+2^1*x(5)+2^0*x(4)+2^-1*x(3)+2^-2*x(2)+2^-3*x(1)+2^-4*x(0), where x is based on the bit from the final index.

[0113] Final index calculation

[0114] Reference again Figure 5A , the index (adaptive gain multiplier factor) for AG1 can be calculated using a lookup table based implementation instead of actual arithmetic calculations.

[0115] The value can be stored as for the target V nom A fixed lookup table "vid_lut" for a range (e.g., 0.5V to 1.13V) can be divided into multiple equal sub-ranges. Figure 5A As shown in , “vid_lut” may be divided into 16 values ​​vid_lut0 to vid_lut15 , which may be provided as inputs to the multiplexer 510 .

[0116] The value of can be stored in a programmable lookup table "reg_IuRo_lut" and can be divided into multiple sub-ranges. Figure 5A As shown in , "reg_IuRo_lut" can be divided into 16 values ​​reg_IuRo_lut 0 to reg_IuRo_lut0 15, which can be provided as inputs to multiplexer 511. The values ​​reg_IuRo_lut 0 to reg_IuRo_lut15 can be selected based on the current voltage difference, for example, with higher resolution in the middle voltage difference region where it varies the most in the resolution of 20mV-40mV (for example, a voltage difference range of 100mV to 400mV). The lookup table can be based on the known output resistance Ro that varies with deflection and the known measured I 单位 Information to program.

[0117] Values ​​can also be stored as 压差 The fixed lookup table "vdrop_lut" for the pressure drop information is obtained from the information. For example, Figure 5A As shown in can be divided into 16 values ​​vdrop_lut0 to vdrop_lut15, which can be provided as inputs to multiplexer 512. As described above, V 压差 =V 输入 –V 输出 (It is based on V nom , and V nom Based on VID_code). Therefore, in Figure 5A In the example, the VIN_code (for example, V 输入 ) minus VID_code (for example, V nom ) code to get V 输出 Therefore, V 压差 The digital value of = VIN_code - VID_code.

[0118] This value can be stored only in the region of low voltage difference (e.g., with a resolution of 10 mV).

[0119] In operation, (e.g., always) use the value, and this value is selected by the logic circuit 520 using the signal VID_index (VID index) (based on VID_code). However, the logic circuit 521 and the logic circuit 522 (using Vdrop_index1 (Vdrop index 1) and Vdrop_index2 (Vdrop index 2) respectively) select the index value 压差 (e.g., low voltage difference or high voltage difference) from either or Figure 5A As shown in, the multiplexer 530 can use the signal low_dropout_thres_sel to select between Figure 5A based on the voltage difference explained in the equation of AG above and shown in and If V 压差 < V_threshold (V threshold) (e.g., approximately 100 mV) or if the per-branch current I 单位 drops below the threshold (e.g., the voltage regulator 110 enters the low voltage difference region), the signal low_dropout_thres_sel can be activated (e.g., from logic 0 level to logic 1 level). The selected look-up table value (selected by low_dropout_thres_sel) either is added (using the adder 540) to the selected look-up table value (selected by the signal VID_index of the logic circuit 520) to generate final_index. final_index is used to select an appropriate gain based on the operating point (as described above with reference to Figure 5B ).

[0120] The digital linear controller 130 or the control circuit 125 or both may include a memory circuit (e.g., a register or other type of memory, not shown) to store (e.g., program) as well as the values (e.g., in the form of look-up table entries). As described above, the value of final_index is based on as well as the values. Therefore, the value of final_index is based on the values stored in the memory circuit of the digital linear controller 130 or the control circuit 125 or both.

[0121] Sometimes you can ignore For example, due to the The contribution to gain relative to The contribution to the gain is much lower and can therefore be neglected in the lower dropout region. However, at a certain pressure difference (e.g., a relatively high pressure difference), can start to dominate, from The contribution of is small or negligible because the output resistance Ro generally increases at higher voltage drops (e.g., in some technology nodes).

[0122] The above description discusses the methods used to calculate and implement Figure 4 4. The same technique is used to implement adaptive gain circuit 411 for calculating AG1 (adaptive gain multiplier factor). Similar techniques can be used to implement adaptive gain circuit 422 in forward path 420 (ie, AG2 - adaptive gain multiplier factor).

[0123] Figure 6 The present invention shows some embodiments according to the present invention. Figure 4 FIG. 4 is a diagram of an adaptive gain circuit 422 of a digital linear controller 130. Figure 6 In the example, the structure of the multiplier 650 of the adaptive gain circuit 422 of the forward path 420 can be the same as Figure 5B The structure of the multiplier 550 is similar (or the same). Figure 6 As shown in The values ​​can be stored in the lookup table "I 单位 _lut", the lookup table may include different optional values. For example, "Iunit_lut" may include 16 values ​​Iunit_lut0 to Iunit_lut15, which may be provided as inputs to the multiplexer 622. The information sensed_Iunit_code (sensed_I 单位 _code) (e.g., 4-bit [3:0] code) to appropriately select the value I 单位 _lut0 to I 单位 _lut15. The value of sensed_Iunit_code can be based on the dynamic I from the current sensing logic (not shown) of the power gate for telemetry purposes. 单位 Information. R_eq at the set point (which is R L ||Ro / N) is consumed in the coefficient term associated with the forward path 420 so that the term AG2 (adaptive gain 2) depends only on the ratio of the per-branch current at the set point to the per-branch current at the operating point, which may vary primarily at lower voltage differences. Figure 6As shown in FIG. 6 , the multiplier 650 can be based on one of the values ​​Iunit_lut0 to Iunit_lut15 (selected as the output of the multiplexer 622) and (from Figure 4 The information FWD_out is generated by multiplying the information FIR2_out (FIR2_output) of the FIR filter of the forward path 420 in FIG. 4 to generate the information FWD_out (FWD_output). The information FWD_out can be added to the information from the forward path 410, as described above with reference to FIG. Figure 4 described.

[0124] Therefore, as mentioned above Figures 1 to 6 As described, the linear control technique in the voltage regulator 110 can utilize the corresponding zero and the new adaptive DC gain adjustment technique to eliminate the main pole and the DC gain of the controlled object that depend on the change of the load. The described technique is applicable to different load conditions and is not limited to specific load conditions. This means that the voltage regulator 110 dynamically adjusts itself to offset the changes that occur in the controlled object under different load conditions over time. Therefore, the described linear control technique helps improve the closed-loop performance of fast and stable response and reduced peak droop, overshoot, or fast and stable response and reduced peak droop, overshoot across a wide range of current loads and a wide output voltage range. The described linear control technique also allows a single coefficient set to be used for a digital filter across the wide operating range of the voltage regulator 110 for different load conditions. All these factors make the described linear control technique have improvement relative to some traditional techniques.

[0125] For example, as described above, some conventional linear control techniques are designed for the worst case at specific output voltage and load conditions. If such specific load conditions are changed, it may result in degraded performance, slow response time, higher droop / overshoot due to low bandwidth. Such conventional techniques can handle a relatively small range of load currents using a set of coefficients.

[0126] In the techniques described herein, the voltage regulator 110 uses a single set of coefficients for a much wider range of load currents, input voltage ranges, and load capacitances. In addition, the performance of the loop in the described techniques can remain relatively constant over the range in terms of stability and loop bandwidth, which results in better transient response in terms of worst-case droop and settling time.

[0127] Nonlinear control technology

[0128] As referenced above Figure 1 As described, when V 输出 When an error (e.g., a droop or overshoot event) is detected at Figure 1) enters the nonlinear mode. In the nonlinear control technique described herein, the nonlinear controller 140 uses the output information nl_out (nl_output) (digital nonlinear output code) to perform nonlinear correction to correct V in two stages (initial stage and subsequent stage). 输出 The calculation of nl_out is different in the initial stage and the subsequent stages. In the nonlinear control technique described in this article, when V 输出 When the target value is still within the range (at V 输出 Before crossing the nonlinear target threshold, the nonlinear controller 140 calculates (e.g., pre-calculates) the correction information nl_dlc_step. This allows the nonlinear controller 140 to detect V 输出 Outside the target value range (for example, in a half cycle of the clock signal Fclk), V is quickly corrected. 输出 The nonlinear controller 140 also calculates (eg, precalculates) the value of the correction information nl_dlc_step based on the operating conditions at that moment, so that the nonlinear controller 140 can smoothly and accurately correct V 输出 to avoid over-correction or under-correction.

[0129] As part of the operation of calculating nl_dlc_step, the nonlinear controller 140 calculates the error code (eg, generated based on error_code_p and error_code_n) outside the zero error region and at V 输出 The number of clock edges (positive and negative) before the value of crosses the nonlinear entry threshold (e.g., +4 for a droop event and -4 for an overshoot event) is counted. The value of the count value is used for the nonlinear entry time calculation. The correction information nl_dlc_step is calculated based on the calculated nonlinear entry time calculation. The nonlinear controller 140 then calculates nl_out using the calculated nl_dlc_step and makes nl_out ready to be used when V is detected. 输出 After the initial stage, the nonlinear controller 140 uses a different calculation for nl_out in subsequent stages and continues to correct V 输出 The error in V 输出 Returning to the target value range, at which the nonlinear controller 140 exits the nonlinear mode and hands over the operation to the digital linear controller 130 .

[0130] The following description discusses the calculation of the correction information nl_dlc_step used to calculate the correction error V when entering the nonlinear mode. 输出 The initial stage of nl_out (digital nonlinear output code).

[0131] Calculate the correction V based on the following equation 输出 The value of n1_out (initial value) used in the initial stage of the error in (e.g., droop or overshoot).

[0132] nl_out = dlc_out (previous cycle) + nl_dlc_step (for droop)

[0133] nl_out = dlc_out (previous cycle) - nl_dlc_step (for overshoot)

[0134] Figure 7 shows the voltage V during an example droop event according to some embodiments described herein 输出 and current I 负载 Example waveform of . Figure 7 An example of the effect of propagation delay on droop and the start time of droop correction is also shown. 负载 Can have an initial value (in Figure 7 The initial load is shown in the Figure 7 As described above, the nonlinear controller 140 uses the count of the number of clock edges (positive and negative) as part of the operation of calculating the correction information nl_dlc_step. Figure 7 In , the "count" can be set (or reset) at time TRS1. Then, the "count" can start at time Tc with count=1 and continue (e.g., sequentially increase) until (e.g., at time TRS2) it is reset to count=0. For simplicity, Figure 7 Only a few values ​​of "Count" are shown in (eg, Count=0, 1, 2).

[0135] exist Figure 7 In the example, the target value range 714 is the voltage V 输出 . In this example, it is assumed that the target value range 714 is between an upper target value 714U and a lower target value 714L. The upper target value 714U may correspond to an ADC error = -4 (e.g., +40 mV). The lower target value 714L may correspond to an ADC error = +4 (e.g., -40 mV). Assume that nl_entry_threshold is at ADC error = +4 (e.g., lower target value 714L). Therefore, in this example, if the voltage V is detected 输出 If the value of V is 40 mV less than its target value (e.g., droop occurs) or 40 mV greater than its target value (e.g., overshoot occurs), the nonlinear mode is entered and the nonlinear controller 140 may start to correct V 输出Errors in the PWM frequency domain (e.g., droop or overshoot). Figure 7 , the zero error region 710 indicates where V 输出 The region (range) where there is considered to be no error (zero error or close to zero error). Therefore, in this example, if the voltage V 输出 If the value of is less than 10 mV lower (or higher) than the target value, the linear mode is maintained (for example, the nonlinear mode is not entered), and the digital linear controller 130 ( Figure 1 ) to maintain control V 输出 The operation when the value is .

[0136] Time calculation from the start of the load step to the application of the nonlinear correction

[0137] In the following discussion, Ts is the clock signal Fclk ( Figure 1 and Figure 2 ) period (e.g., 2.5 ns), the clock signal Fclk is used by ADC 120 to 输出 The error in is adopted. Samples for the nonlinear logic in the nonlinear controller 140 can be obtained every half cycle (half cycle or Ts / 2) based on the positive and negative edges of the clock signal Fclk.

[0138] T_nlentry=Ts / 2+(count+1)*(Ts / 2), where T_nlentry is the time at which the nonlinearity enters (e.g., at time T0) after the load step starts (e.g., at time T0). Figure 7 The count is the value of the count obtained at a time (e.g., time T1) that is half a cycle of the clock signal Fclk earlier than the time (e.g., time T2) when the nonlinear entry threshold crossing is detected. Figure 7 In the example of FIG. 1 , the count used in the equations for timing calculations (eg, T_nlentry and Tstart_recovery (below)) is count=2 (eg Figure 7 1). However, the value of the count may vary based on the di / dt of the load step. For example, at a time half a cycle of the clock signal Fclk earlier than the time when the nonlinear entry threshold crossing is detected, the value of the count may be less than 2 (e.g., if the load step is fast) or greater than 2 (e.g., if the load step is slow). In the description here, the period refers to the period of the clock signal Fclk (sampling clock signal).

[0139] exist Figure 7In the example, T_nlentry = Ts / 2 + (count + 1) * (Ts / 2) = Ts / 2 + (2 + 1) * (Ts / 2) = Ts / 2 + 3 * (Ts / 2) = 4 * (TS / 2). This means that T_nlentry is four half cycles later than the time T0 (the time when the load step starts) (which is at the time T2), as shown in Figure 7 as shown in .

[0140] Tstart_recovery = T_nlentry + Ts / 2 (where Ts / 2 is added due to the propagation delay of the ADC output from where the nonlinearity enters), where Tstart_recovery is the time at which the correction starts after the load step is applied (e.g., at Figure 7 at time T0 in the graph).

[0141] Based on the above,

[0142] Tstart_recovery = (count + 3) * (Ts / 2) (Equation 1)

[0143] Therefore, in Figure 7 In the example of , Tstart_recovery = (2+3)*(Ts / 2) = 5*(Ts / 2). This means that Tstart_recovery (T start_recovery) is five half cycles later than the time T0 (the time when the load step starts) (which is at the time T2), such as Figure 7 as shown in .

[0144] The nonlinear correction described herein applies correction information nl_dlc_step (included in n1_out) to provide (e.g., source) sufficient current in the half cycle (Ts / 2) immediately following the start of recovery. The applied current will give an incremental voltage (e.g., ΔV) rise that is greater than the incremental voltage droop that would have occurred if the nonlinear correction had not been applied and the load current had continued to increase at the same di / dt rate for that cycle. This prevents the droop from decreasing further because the voltage (e.g., ΔV) is calculated to be expected to cause the voltage V 输出 For this reason, the di / dt and voltage error of the load when nonlinearity enters can be determined so that the correction information nl_dlc_step satisfies the above criteria.

[0145] For example, assuming that “ΔV” is the additional droop that would be present in a half cycle if no nonlinear correction was applied, then to prevent the voltage V 输出 Further decreases in the immediately following half cycle, the same amount of charge can be replenished in the immediately following half cycle (based on ΔV). This allows the voltage V 输出 After detecting V 输出Recovery begins (eg, begins returning to the target value range) in the next half cycle immediately after an error in ΔV is detected (eg, after nonlinearity is detected). The calculation of “ΔV” and “nl_dlc_step” is as follows.

[0146] Based on I=C*dv / dt, then

[0147] nl_dlc_step*I_per_leg=C_load*deltaV / (Ts / 2)

[0148] nl_dlc_step=(C load / I_per_leg)*(2 / Ts)*deltaV(nl_dlc_step=(C 负载 / I_each_branch)*(2 / Ts)*ΔV) (Equation 2)

[0149] Among them C 负载 is the total load capacitance seen at the output, and I_per_leg (I_each_leg) is the transistor group 113 ( Figure 1 ) with a fixed current per branch, and the “ΔV” calculation is shown below.

[0150] ΔV=I 负载 *dt / C 负载 In Tstart_recovery (for example, Figure 7 time T3 in the figure) to Tstart_recovery+Ts / 2 (for example, Figure 7 The integral between the moments T4).

[0151] By using the approximate calculation of I between the above two times (for example, between time T3 and time T4), 负载 The area under the curve, and substituting Tstart_recovery from Equation 1, "ΔV" can be obtained as follows.

[0152] ΔV = delta_Ih*(count+3)*(Ts / 2) / C 负载 (Equation 3)

[0153] Where Δ_Ih is the change in load current in half a cycle of a linear load step. The value of Δ_Ih can be calculated as shown below.

[0154] In the following description, droop_at_entry is the value at the nonlinear entry point (e.g., at Figure 7 The voltage sag at time T2 in the figure is detected at the nonlinear entry point. 输出The value of droop_at_entry is approximately known from nl_error_at_entry (which is the sampled ADC error at entry) and the known ADC resolution (which is also known), eg, a fixed voltage value (eg, 0.01V).

[0155] There may be additional droop compared to the “nl_error_at_entry” sampled for faster load transients (e.g., when “count” has a lower value). When the load step is slow (e.g., when “count” has a higher value), the accuracy of “nl_error_at_entry” (e.g., how close nl_error_at_entry is to the actual voltage droop) may be improved because V 输出 The time it takes to cross the nonlinear entry threshold (nl_entry_threshold), voltage V 输出 takes more time to cross the nonlinear entry threshold. Based on these relationships, the voltage droop at entry can be accurately determined as a function of 'count' and 'nl_error_at_entry'. If a relatively high number of samples (e.g., four or more) are taken within one ADC clock cycle (e.g., a cycle of the clock signal Fclk), or if the ADC 220 ( Figure 2 ) can further improve the accuracy.

[0156] The following equation can be used to calculate the voltage droop at entry (droop_at_entry) which is based on a function of "count" and "nl_error_at_entry".

[0157] nl_err_entry_adj=nl_error_at_entry+1 (for count <= 3)

[0158] nl_err_entry_adj=nl_error_at_entry (for count > 3 and <= 5)

[0159] nl_err_entry_adj = nl_error_at_entry - 1 (for count > 5)

[0160] Where "nl_error_at_entry" is the magnitude of the error code at the non-linearity entry. As an example, "nl_error_at_entry" may be 4 or 6, and the non-linearity entry threshold may be, for example, 40 mV error.

[0161] droop_at_entry=nl_err_entry_adj*0.01=(I 负载 *dt) / C 负载 The integral from t=0 (e.g., time T0) to T_nlentry (e.g., time T2)

[0162] Assume a linear variation of the load current and calculate I 负载 The calculated area under the curve is given by,

[0163] droop_at_entry=(1 / C 负载 )*(1 / 2)*T_nlentry*delta_Ih*T_nlentry / (Ts / 2)

[0164] After replacing "T_nlentry", it gives,

[0165] delta_Ih=4*C_load*fs*0.01*nl_err_entry_adj / [(count+2)^2] (Equation 4)

[0166] Where fs = 1 / Ts (which is the sampling clock frequency)

[0167] Combining Equation 2, Equation 3, and Equation 4, the value of the correction information nl_dlc_step (eg, the final controller step half a cycle earlier than the nonlinearity is detected to enter) that can be applied in the nonlinear mode is as follows.

[0168] nl_dlc_step=(0.04*C 负载 *fs / I_per_leg)*

[0169] nl_err_entry_adj*(count+3) / [(count+2)^2] (Equation 5)

[0170] As described above, nl_dlc_step is correction information that the nonlinear controller 140 uses to calculate (eg, pre-calculate) the correction information for the voltage V detected. 输出 The value of nl_out used in the initial stage of nonlinear correction after being outside the target value range (eg, for adjusting control_code).

[0171] Nonlinear Controller Implementation

[0172] Figure 8 The present invention shows some embodiments according to the present invention. Figure 1For implementation, the above equation 5 for the correction information nl_dlc_step may be rewritten as follows.

[0173] nl_dlc_step = K_fixed*K_count (Equation 6)

[0174] Where K_fixed = (0.04*C_load*fs / I_per_leg), which can be based on the load capacitance C 负载 The actual measured (known) value of the programmable value (in Figure 8 10 bits of reg_K_fixed[0:9]), I_per_leg is the transistor group 113 ( Figure 1 ), and "fs" is the sampling frequency (e.g., the frequency of the clock signal Fclk). The digital linear controller 140 or the control circuit 125 or both may include a memory circuit (e.g., a register or other type of memory, not shown) to store (e.g., program) the value of K_fixed (given by Figure 8 The value represented by the 10-bit reg_K_fixed).

[0175] K_count = nl_err_entry_adj * (count + 3) / [count + 2) ^ 2], which can be implemented as a lookup table based on "count" of nl_error_at_entry = 4. In a wide range of load scenarios, the value of "count" ( Figure 7 ) can vary. For example, "count" can vary between 0 and 9. Therefore, in this example, the lookup table can include 10 different entries (values) for "K_count", such as count values ​​(e.g., reg_Kcount_val0 (reg_K count_val0) to reg_Count_val9 (reg_K count_val9), each with 8 bits [7:0], such as Figure 8 ), these different entries (values) may be provided as inputs to multiplexer 810. Nonlinear controller 140 or control circuit 125 or both may include memory circuits (e.g., registers or other types of memory, not shown) to store (e.g., program) values ​​of K_count (e.g., reg_Kcount_val0 to reg_Kcount_val9), which may be different selectable values.

[0176] During operation of the nonlinear controller 140, the count measurement logic circuit 805 ( Figure 8) can generate count information “Kcount_meas_sel” to select an appropriate “K_count” value from the stored count values ​​from the lookup table. According to the value of “Kcount_meas_sel”, the multiplexer 810 can select one of reg_Kcount_val0 to reg_Kount_val9 as the selected “K_count” (referred to as “K_count_selected”). “K_count_selected” is multiplied by reg_K_fixed (reg_K_fixed corresponds to “K_fixed” in Equation 6) by the multiplier 812 to generate the correction information nl_dlc_step.

[0177] like Figure 8 As shown in , for the case when nl_error_at_entry=6, before the correction information nl_dlc_step is applied to the output of the nonlinear controller 140, “K_count” (K_count is one of reg_Kcount_val0 to reg_Kount_val9) may be adjusted by 1.5 times (eg, may be multiplied by 1.5 by circuit 814).

[0178] The nonlinear controller 140 may use the signal nl_error_at_entry_sel to cause the multiplexer 816 to select nl_dlc_step=reg_K_fixed*K_count_selected (e.g., if nl_error_at_entry=4) or nl_dlc_step=reg_K_fixed*K_count_selected*1.5 (e.g., if nl_error_at_entry=6). As described above, “K_count_selected” is one of reg_Kcount_val0 to reg_Count_val9 selected based on the value of “Kcount_meas_sel”.

[0179] Fig. 9 1 shows a method for generating a value for "Kcount_meas_sel" according to some embodiments described herein. Figure 8 The block diagram of the counting measurement logic circuit 805 is shown in FIG. Fig. 9As shown in FIG. 1 , the count measurement logic circuit 805 may include modules 911 and 912 and an adder 923 to generate “Kcount_meas_sel” based on error information pos_error_code and neg_error_code and signals nl_mode_en and nl_exit. As described above, “Kcount_meas_sel” corresponds to “count”. The value of “Kcount_meas_sel” is determined from V 输出 At times outside of the zero error region 710 (e.g., Figure 7 ) to the time when the value reaches the nonlinear entry threshold (e.g., time T2) (e.g., at Figure 7 Medium V 输出 How many clock edges (positive and negative) occur at a time outside the target value range 714. Fig. 9 , module 911 may include positive edge counting logic 911a for counting the number of positive edges of the clock signal Fclk. Module 912 may include negative edge counting logic 912a for counting the number of negative edges of the clock signal Fclk. Adder 923 may be operable to add the count values ​​from module 911 and module 912 to generate "Kcount_meas_sel".

[0180] In operation, based on the error codes pos_error_code and neg_error_code and the ADC error level (e.g., Figure 7 ), Fig. 9 The counting measurement logic circuit 805 can be 输出 In the zero error region (e.g. Figure 7 710) outside the zero error zone in V 输出 Stop counting when it is within the zero error zone, and then reset the count. For example, using Figure 7 For example, the count measurement logic circuit 805 can set (or reset) “count” (for example, at time TRS1) so that when V 输出 When the value of is within the zero error region 710, count = 0. 输出 After a time outside the zero error region 710 (eg, at time Tc), the count measurement logic circuit 805 may start counting, with count=1. 输出 When the value of is again within the zero error region 710 (e.g., half a cycle after exiting the nonlinear mode), the count measurement logic circuit 805 may stop and reset the count (e.g., at Figure 7 The moment T RS2 At , count = 0). Fig. 9In addition to the error codes pos_error_code and neg_error_code, one or both of the signals nl_mode_en and nl_exit may be used to generate 'Kcount_meas_sel'. For example, the signal nl_mode_en may be used to start and stop counting, and the signal nl_exit may be used to reset counting.

[0181] Refer again Figure 8 After calculating the correction information nl_dlc_step based on the multiplication of K_fixed (fixed value) and K_count (one of reg_Kcount_val0 to reg_Kount_val9 selected based on “Kcount_meas_sel”), nl_dlc_step can be combined with dlc_out (added to dlc_out or subtracted from dlc_out) to provide nl_out. 输出 The pre-computed nl_out can be ready half a cycle before the error in the input (e.g., droop or overshoot) is detected.

[0182] exist Figure 8 The label "For Droop" indicates the method used to calculate nl_out in preparation for correcting V 输出 The adder 822 may add nl_dlc_step to dlc_out from the previous cycle. Before entering non-linear mode, the result (nl_out=dlc_out+nl_dlc_step) may be available (e.g., stored in positive and negative edge triggered flip-flops (+ve FF and -ve FF) 823 and 824).

[0183] Figure 8 The label "For Overshoot" indicates the time for calculating nl_out to prepare for the correction of V 输出 The operation of overshoot in. Subtractor 832 can subtract nl_dlc_step from dlc_out from the previous cycle. Before entering non-linear mode, the result (nl_out=dlc_out-nl_dlc_step) can be available (e.g., stored in positive and negative edge triggered flip-flops (+ve FF and -ve FF) 833 and 834).

[0184] The clock signal Fclk may be used to trigger flip-flops 823, 824, 833, and 834. Saturation monitors (SATs) 825 and 835 may be used to maintain the pre-calculated value of nl_out (nl_out = 'dlc_out' + 'nl_dlc_step' and nl_out = 'dlc_out' - 'nl_dlc_step', respectively) within saturation limits. The pre-calculated nl_out may be used to correct V 输出 The initial stage (e.g. Figure 7 Adjust control_code during the period between moments T3 and T4).

[0185] In the above description, count information Kcount_meas_sel (which is 'count') for selecting count values ​​reg_Kcount_val0 to reg_Count_val9 is available half a cycle earlier than nonlinear entry, which enables 'nl_dlc_step' after K_count is multiplied by K_fixed. Therefore, before 'nl_out' is applied to V 输出 At a time (e.g., time T3) during the correction of the nonlinear entry (after the nonlinear entry is detected), "nl_out" is a pre-calculated value, where nl_out = dlc_out_prev + / -nl_dlc_step (where dlc_out_prev is the previous value of dlc_out (e.g., at time T2)). Once a nonlinear entry threshold crossing is detected (e.g., at Figure 7 ) and “nl_mode_en” is activated (e.g., changes to a logic one level), the pre-calculated value can be propagated. Following the threshold crossing, the nonlinear controller 140 can select the appropriate pre-calculated nl_out (nl_out=dlc_out+nl_dlc_step or nl_out=dlc_out-nl_dlc_step) based on the sign of the error at entry represented by the signal “entry_error_sign_bit” (for controlling multiplexer 842), the nonlinear entry clock edge signal “entry_pos_or_neg_edge” (for controlling multiplexers 826 and 836), and the nonlinear error at entry (e.g., nl_error_at_entry=4 or 6). The structure of the nonlinear controller 140 is configured such that, in addition to the transmission from the nonlinear controller 140 to the transistor group 113 ( Figure 1 ) and adds insignificant logic delay to the path.

[0186] like Figure 8As shown in , the nonlinear controller 140 may include: a bubble correction 851 for improving the accuracy of error_code_p; and a thermometer-binary converter 852 for performing a thermometer-to-binary conversion to convert bits [7:0] of the information error_code_p into a positive ADC error level pos_error_code (e.g., 5 bits [4:0]). The nonlinear controller 140 may include: a bubble correction 861 for improving the accuracy of error_code_n; and a thermometer-binary converter 862 for performing a thermometer-to-binary conversion to convert bits [7:0] of the information error_code_n into a positive ADC error level neg_error_code (e.g., 5 bits [4:0]). The counting measurement logic circuit 805 (also in Fig. 9 ) is used to generate count information “Kcount_meas_sel” (eg, 4 bits [3:0]), which is used to select count values ​​reg_Kcount_val0 to reg_Kount_val9.

[0187] like Figure 8 As shown in FIG. 8 , the nonlinear controller 140 may include an error threshold detector 872 to generate signals nl_mode_en (nonlinear mode enable signal) and nl_exit (nonlinear exit signal) based on the ADC error levels “pos_error_code” and neg_error_code and nl_entry_threshold. 输出 When the value of crosses nl_entry_threshold (for example, in Figure 7 At time T2 in the 输出 When the value of is outside the target value range 714 ( Figure 7 ), the error threshold detector 872 may activate the signal nl_mode_en (eg, provide a logic 1 level to). 输出 The value returned (for example, in Figure 7 When the error threshold detector 872 reaches the target value range 714 at time T3 in the error threshold detector 872 , the error threshold detector 872 may activate the signal n1_exit (eg, provide a logic 1 level to).

[0188] like Figure 8As shown in FIG. 8 , the value of the information pos_error_code may be multiplied by a scaling factor K2 and may be added (via adder 874) to the value of nl_out from the previous cycle. The nonlinear controller 140 may include a saturation monitor (SAT) 875 to keep the value of pos_error_code (after multiplication by the scaling factor K2) within saturation limits. The scaling factor K2 may be a factor smaller than “nl_dlc_step” in order to apply fine steps and avoid excessive saturation when restoring V 输出 The linear code nl_out is provided back to the digital linear controller 130 ( Figure 1 ) to ensure smooth switching between modes at n1_exit before the digital linear controller 130 settles to the new “dlc_out” code to maintain zero error in steady state.

[0189] like Figure 8 As shown in , the nonlinear controller 140 may include a multiplexer 876 that may be controlled by a signal State for selecting the value of nl_out during an initial stage (e.g., initial portion) and a subsequent stage (e.g., subsequent portion) of the nonlinear correction (described above). The signal State may be generated by a state machine (not shown) of the voltage regulator 110. The signal State may be controlled so that it may have a signal level corresponding to a logic zero (e.g., State=0) during the linear mode and may have a signal level corresponding to a logic zero (e.g., State=0) at some point after entering the nonlinear mode (e.g., Figure 7 At time T4 in the example, the signal level corresponds to logic one (e.g., state = 1). After entering the nonlinear mode (e.g., at Figure 7 The value of nl_out relative to the value of the signal State) after moment T2 in the graph is as follows.

[0190] State = 0 (for example, in Figure 7 Before time T3)

[0191] nl_out=dlc_out+nl_dlc_step (if V 输出 The error in is droop), or

[0192] nl_out = dlc_out - nl_dlc_step (if V 输出 The error in is the overshoot), or

[0193] State = 1 (for example, in Figure 7 After time T3 in

[0194] nl_out=nl_out_prev+K2*pos_error_code

[0195] where pos_error_code is based on error_code_p.

[0196] Therefore, after entering the nonlinear mode and before the signal State is activated to State=1, nl_out=dlc_out+nl_dlc_step (if V 输出 The error in is droop), or nl_out = dlc_out - nl_dlc_step (if V 输出 The error in is the overshoot). After State = 1 (e.g., after time T4), the dynamic error code (pos_error_code) on the positive edge can be used to calculate "nl_out" at each cycle of the clock signal Fclk. After State = 1, the "nl_out" code can be incremented / decremented by K2*pos_error_code every cycle until V 输出 The value of is returned to the target value range 714 (e.g., in Figure 7 At time T5 in FIG. 8 ). Error threshold detector 872 ( Figure 8 ) can be in V 输出 After returning to the target value range 714 (eg, providing a logic one level to) the signal nl_exit is activated to exit the nonlinear mode. The digital linear controller 130 ( Figure 1 ) can take over control V 输出 Repeat the described process of linear and nonlinear operations to convert V 输出 Remain in the zero error zone 710 and remain within the target value range 714 .

[0197] References Figures 7 to 9 The description of FIG. 1 shows that the correction information nl_dlc_step can be accurately and dynamically pre-calculated by digitally extracting the rate of change (di / dt) of the load current with respect to time. Therefore, the output information nl_out=dlc_out_prev+ / -nl_dlc_step (when nl_out is applied after nonlinear entry is detected (e.g., within a half cycle)) is based on the pre-calculated correction information nl_dlc_step, which is when V 输出 The error output is calculated when the error is within the target value range and before an error (e.g., droop) is detected. The error output is a programmable threshold (e.g., Figure 7nl_entry_threshold in the output port 126 ( Figure 1 ) selects a pre-calculated nonlinear code nl_out as control_code. The control_code can adjust the number of conducting branches (e.g., additional branches that are turned on) in the transistor group 113, where the propagation delay in the path is relatively small (e.g., a delay of hundreds of picoseconds in the worst case). Therefore, the output droops across the threshold (e.g., V 输出 The worst case response time from a voltage drop of -40 mV) to the turn-on of the additional branch can be relatively small.

[0198] Therefore, as mentioned above Figures 7 to 9 As described, during a fast load transient, the voltage regulator 110 autonomously enters a nonlinear mode and the output voltage (V 输出 ) after recovery and then switching back to linear mode. The nonlinear control technique described herein digitally calculates (e.g., pre-calculates) the loss of charge droop or voltage droop that would occur if no nonlinear correction was applied and the load current continued to rise at the same average rate. The described technique then uses the pre-calculated information to determine the digital nonlinear step of the transistors that control the transistor group 113. This allows the voltage regulator 110 to turn on enough branches to source an amount of current sufficient to add charge in the next cycle that follows. Even if the load current continues to increase at the same rate in the next cycle, applying the amount of current in this manner allows the droop to recover instantaneously. This can also prevent overcorrection, thereby avoiding overshoot and oscillation. All of these factors allow the described nonlinear control technique to be improved over some conventional techniques.

[0199] For example, as described above, some conventional techniques apply fixed compensation to correct the error caused by droop regardless of load changes. This may result in over-correction and under-correction for a relatively wide range of load currents and large current change rates across the output voltage range.

[0200] In the nonlinear technique described herein, the voltage regulator 110 provides a single modular reconfigurable solution to cover applications with a relatively wide range of load currents and widely varying di / dt. This can be particularly useful for loads with multiple functional units (e.g., processor cores in a multi-core processor). The nonlinear step gain can be programmable based on the output load and the power transistor (e.g., power FET) that provides the output voltage. In addition, the step is adaptive to the load di / dt because the load di / dt is digitally calculated internally in the nonlinear controller 140, thereby avoiding overshoot or oscillation in the nonlinear response. The described technique can also be used for different specifications of the controlled object through a fusion option other than the internal adaptive control of the nonlinear step without adding significant delay.

[0201] Fig.10 An apparatus in the form of a system (eg, electronic system) 1000 is shown according to some embodiments described herein. System 1000 may include, or may be included in, a computer, a tablet device, or other electronic system. Fig.10 As shown in , system 1000 may include a processor 1005, a memory device 1020 (e.g., system memory), a system memory controller 1030, a graphics controller 1040, an input and output (I / O) controller 1050, a display 1052, a keyboard 1054, a pointing device 1056, at least one antenna 1058, a connector 1015, and a bus 1060 (e.g., conductors formed on a circuit board (not shown) of system 1000).

[0202] Each of the processor 1005 , the memory device 1020 , the memory controller 1030 , the graphic controller 1040 , and the I / O controller 1050 may include an IC chip.

[0203] In some arrangements, the system 1000 need not include a display. Thus, the display 1052 may be omitted from the system 1000. In some arrangements, the system 1000 need not include any antennas. Thus, the antenna 1058 may be omitted from the system 1000.

[0204] The processor 1005 may include a general-purpose processor or an ASIC. The processor 1005 may include a central processing unit (CPU).

[0205] The memory device 1020 may include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory, a combination of these memory devices, or another type of memory. Fig.10An example is shown in which the memory device 1020 is a stand-alone memory device separate from the processor 1005. In an alternative arrangement, the memory device 1020 and the processor 1005 may be located on the same die. In such an alternative arrangement, the memory device 1020 is an embedded memory in the processor 1005, such as embedded DRAM (eDRAM), embedded SRAM (eSRAM), embedded flash memory, or another type of embedded memory.

[0206] Display 1052 may include a liquid crystal display (LCD), a touch screen (eg, a capacitive or resistive touch screen), or another type of display. Pointing device 1056 may include a mouse, a stylus, or another type of pointing device.

[0207] I / O controller 1050 may include a communication module for wired or wireless communications, such as communications through one or more antennas 1058. Such wireless communications may include communications according to WiFi communication technology, Long Term Evolution Advanced (LTE-A) communication technology, or other communication technology.

[0208] The I / O controller 1050 may also include modules that allow the system 1000 to communicate with other devices or systems in accordance with one or more of the following standards or specifications (e.g., I / O standards or specifications), including Universal Serial Bus (USB), Display Port (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), Ethernet, and other specifications.

[0209] Connector 1015 may be arranged (e.g., may include terminals such as pins) to allow system 1000 to be coupled to external devices (or systems). This may allow system 1000 to communicate (e.g., exchange information) with such devices (or systems) via connector 1015. Connector 1015 may be coupled to I / O controller 1050 via connection 1016 (e.g., a bus).

[0210] Connector 1015, connection 1016, and at least a portion of bus 1060 may include elements (e.g., conductive terminals, wires, or other conductive elements) that comply with at least one of USB, DP, HDMI, Thunderbolt, PCIe, Ethernet, and other specifications.

[0211] As an example, Fig.10Elements (e.g., devices and controllers) of system 1000 are shown arranged separately from each other. For example, each of processor 1005, memory device 1020, memory controller 1030, graphics controller 1040, and I / O controller 1050 may be located on a separate IC chip (e.g., a separate semiconductor die). In some arrangements, two or more elements of system 1000 (e.g., processor 1005, memory device 1020, graphics controller 1040, and I / O controller 1050) may be located on the same die (e.g., the same IC chip) forming a system on chip (SoC).

[0212] like Fig.10 As shown in FIG. 1 , each of the processor 1005, the memory device 1020, the memory controller 1030, the graphics controller 1040, and the I / O controller 1050 may include a voltage regulator 1010. The voltage regulator 1010 may include the voltage regulator 110. Therefore, the voltage regulator 1010 may adopt the above reference Figures 1 to 9 Linear and nonlinear control techniques are described.

[0213] Fig.11 is a flow chart of a method 1100 of operating a device according to some embodiments described herein. The device used in the method 1100 may include the above reference Figures 1 to 10 Any of the apparatus described herein (e.g., apparatus 100 and system 1000, including voltage regulators 110 and 1010). Some of the activities in method 1100 may be performed by hardware, software, firmware, or any combination of hardware, software, and firmware. For example, some of the activities in method 1100 may be performed by hardware, software, firmware, or any combination of hardware, software, and firmware, which hardware, software, firmware, or any combination of hardware, software, and firmware are implemented in the above reference Figures 1 to 10 In any of the described devices (eg, device 100 and system 1000 , including voltage regulators 110 and 1010 ).

[0214] like Fig.11 As shown in , activity 1110 of method 1100 may include: generating control information at a first controller of a voltage regulator to control a voltage at a node. Activity 1120 may include: during a first mode of the voltage regulator when the voltage has a first value within a target value range, calculating a gain of a forward path in the first controller to adjust a first value of the control information. Activity 1130 may include: during the first mode, generating correction information at a second controller of the voltage regulator. Activity 1140 may include: during a second mode of the voltage regulator when the voltage has a second value outside the target value range, adjusting a second value of the control information based on the correction information.

[0215] Method 1100 may include: Fig.11 1100, 1120, 1130, and 1140 may be fewer or more activities. For example, method 1100 may include activities and operations of apparatus 100 and system 1000, including the above reference Figures 1 to 10 The operation of voltage regulators 110 and 1010 is described.

[0216] The illustrations of the apparatus and methods described above are intended to provide a general understanding of the structures of the various embodiments and are not intended to provide a complete description of all of the elements and features of apparatus that may utilize the structures described herein.

[0217] The above described device and method may include the following or be included in the following: high-speed computer, communication and signal processing circuit system, single processor module or multi-processor module, single embedded processor or multiple embedded processors, multi-core processor, message information switch and special module including multi-layer or multi-chip module. Such device may be further included as a sub-component in various other devices (e.g., electronic system), such as television, cellular phone, personal computer (e.g., laptop computer, desktop computer, handheld computer, etc.), tablet device (e.g., tablet computer), workstation, radio, video player, audio player (e.g., MP3 (Moving Picture Experts Group, Audio Layer 3) player), vehicle, medical equipment (e.g., heartbeat monitor, blood pressure monitor, etc.), set-top box, etc.

[0218] Additional Notes and Examples

[0219] Example 1 includes a subject matter (such as an apparatus, an electronic device (e.g., a circuit, an electronic system, or both) or a machine) comprising: an output terminal for providing output information to a control transistor of a power switching unit; a node for receiving a feedback voltage based on an output voltage generated by the power switching unit; and a control circuit for: generating error information based on a value of the feedback voltage generated from the output voltage; generating output information based on the error information provided to a forward path coupled to the output terminal; and adjusting a gain of the forward path based on a gain factor calculated at least in part based on a first value of the output information during a first time interval so that the output information has a second value during a second time interval.

[0220] In Example 2, the subject matter of Example 1 may optionally include, wherein the control circuit is configured to: when the output voltage is within a target value range, cause the output information to have a first value and a second value.

[0221] In Example 3, the subject matter of Example 1 may optionally include, wherein the control circuit includes a linear controller, the linear controller includes a multiplier, the multiplier including: a first input terminal, the first input terminal is used to receive input information based on a first value of the output information; a second input terminal, the second input terminal is used to receive information from a memory circuit in the control circuit; and an output terminal, the output terminal is used to provide a gain factor.

[0222] In Example 4, the subject matter of Example 1 can optionally include, wherein the control circuit is to receive a clock signal and generate error information based on a timing of the clock signal, and the control circuit is to adjust a gain of the forward path in each cycle of the clock signal.

[0223] In Example 5, the subject matter of Example 1 may optionally include, wherein the control circuit is used to: generate output information based on error information provided to an additional forward path coupled to the output; and adjust the gain of the additional forward path based on an additional gain factor calculated at least in part based on a first value of the output information during a first time interval so that the output information has a second value during a second time interval.

[0224] In Example 6, the subject matter of any one of Examples 1-5 can optionally include further comprising an analog-to-digital converter for generating error information based on the feedback voltage and a series of reference voltages.

[0225] In Example 7, the subject matter of any one of Examples 1-6 may optionally include, wherein the control circuit includes: a first forward path, the first forward path being used to receive error information, the first forward path including a first adaptive gain circuit for generating a gain factor to adjust the gain of the first forward path; a second forward path, the second forward path being used to receive error information, the second forward path including a second adaptive gain circuit for generating an additional gain factor to adjust the gain of the second forward path; and a feedback path coupled to the output terminal, the first forward path and the second forward path.

[0226] Example 8 includes a subject matter (such as an apparatus, an electronic device (e.g., a circuit, an electronic system, or both) or a machine) comprising: an output port for providing control information to control a transistor of a power switching unit; and a control circuit for: generating control information so that the value of an output voltage generated by the power switching unit is less than the value of an input voltage provided to the power switching unit; calculating the value of correction information during a first time interval when the output voltage has a first value within a target value range; and adjusting the value of the control information based on the correction information during a second time interval when the output voltage has a second value outside the target value range.

[0227] In Example 9, the subject matter of Example 8 can optionally include, wherein the control circuit is to calculate a value of the correction information based on a rate of change of a current at a node where the output voltage is provided.

[0228] In Example 10, the subject matter of Example 8 can optionally include, wherein the correction information indicates an amount of current to be adjusted at the node during the second time interval.

[0229] In Example 11, the subject matter of any of Examples 8-10 may optionally include, wherein the control circuit is used to receive a clock signal, and the control circuit is used to: adjust the value of the control information at a moment less than one cycle of the clock signal from the moment when the second value of the output voltage is detected to be outside the target value range.

[0230] In Example 12, the subject matter of any of Examples 8-10 may optionally include, wherein the control circuit is used to receive a clock signal, and wherein a second value of the output voltage is detected to be outside a target value range at a first edge of the clock signal, and the control circuit begins adjusting the value of the control information at a second edge of the clock signal, the second edge occurring within less than one cycle of the clock signal from the time the first edge occurs.

[0231] In Example 13, the subject matter of any one of Examples 8-10 can optionally include, wherein the control circuit is to receive a clock signal, and the control circuit is to calculate the correction information during a time interval between two consecutive edges of the clock signal.

[0232] In Example 14, the subject matter of any of Examples 8-10 may optionally include, wherein the control circuit is to receive a clock signal, the control circuit is to calculate the correction information based on a count value, and the count value corresponds to the number of rising edges and falling edges of the clock signal.

[0233] In Example 15, the subject matter of any of Examples 8-10 may optionally include, wherein the control circuit is used to calculate the value of the correction information based on the rate of change of current from the moment when the second value of the output voltage is detected to be outside the target value range to the moment half a cycle after the moment when the second value of the output voltage is detected to be outside the target value range.

[0234] In Example 16, the subject matter of any of Examples 8-10 may optionally include, wherein the control circuit is used to adjust the value of the control information during a first portion of the second time interval based on the correction information, and the control circuit is used to adjust the value of the control information during a second portion of the second time interval based on error information generated by comparing a series of reference voltages with a feedback voltage generated from the output voltage.

[0235] In Example 17, the subject matter of Example 16 can optionally include further comprising an analog-to-digital converter to perform the comparison.

[0236] Example 18 includes a subject matter (such as an apparatus, an electronic device (e.g., a circuit, an electronic system, or both) or a machine) comprising: a power switching unit for receiving an input voltage to provide an output voltage having a value less than the value of the input voltage; an error code generator for generating first error correction information and second error correction information based on an error in the output voltage; a first controller for generating first output information to control the power switching unit during a first mode when the output voltage has a first value within a target value range, the first controller for calculating a gain of a forward path during the first mode so that the first output information has a second value during the first mode; and a second controller for calculating the value of the correction information during the first mode, and for controlling the power switching unit based on the correction information during the second mode when the output voltage has a second value outside the target value range.

[0237] In Example 19, the subject matter of Example 18 can optionally include, wherein the first controller includes a forward path implemented based on a single set of coefficients.

[0238] In Example 20, the subject matter of any one of Examples 15-19 can optionally include, wherein the first controller includes a memory circuit to store information for calculating the gain.

[0239] In Example 21, the subject matter of any of Examples 15-19 can optionally include, wherein the second controller is to calculate the value of the correction information based on a rate of change of a current at a node at which the output voltage is provided.

[0240] In Example 22, the subject matter of any one of Examples 15-19 may optionally include, wherein the second controller is used to control the power switching unit in an initial stage of the second mode, and the second controller is used to control the power switching unit in a second stage of the second mode based on error information different from the correction information.

[0241] Example 23 includes a subject matter (such as an apparatus, an electronic device (e.g., a circuit, an electronic system, or both) or a machine) comprising a semiconductor die, a processing unit located on the semiconductor die, and a voltage regulator located on the semiconductor die and coupled to the processing unit, the voltage regulator comprising: a power switching unit for receiving an input voltage to provide an output voltage having a value less than a value of the input voltage; an error code generator for generating first error correction information and second error correction information based on an error in the output voltage; a first controller for generating first output information to control the power switching unit during a first mode when the output voltage has a first value within a target value range, the first controller for calculating a gain of a forward path during the first mode so that the output information has a second value during the first mode, and a second controller for calculating a value of the correction information during the first mode and for controlling the power switching unit based on the correction information during the second mode when the output voltage has a second value outside the target value range.

[0242] In Example 24, the subject matter of Example 23 can optionally include wherein the first mode comprises a linear mode and the second mode comprises a non-linear mode.

[0243] In Example 25, the subject matter of Example 23 or 24 can optionally include wherein the semiconductor die, the processing unit, and the voltage regulator are part of a system on a chip (SoC).

[0244] Example 26 includes subject matter (such as a method of operating an apparatus, an electronic device (e.g., a circuit, an electronic system, or both) or a machine) comprising: generating control information at a first controller of a voltage regulator to control a voltage at a node; during a first mode of the voltage regulator when the voltage has a first value within a target value range, calculating a gain of a forward path in the first controller to adjust the first value of the control information; during the first mode, generating correction information at a second controller of the voltage regulator; and during a second mode of the voltage regulator when the voltage has a second value outside the target value range, adjusting the second value of the control information based on the correction information.

[0245] In Example 27, the subject matter of Example 26 can optionally include, wherein the forward path is a portion of a plurality of forward paths of the first controller, and wherein the plurality of paths are implemented using a single set of coefficients.

[0246] In Example 28, the subject matter of Example 26 or 27 can optionally include, wherein generating the correction information comprises: calculating a value of the correction information based on a rate of change of the current at the node.

[0247] In Example 29, the subject matter of Example 26 or 27 may optionally include, wherein adjusting the value of the control information includes: applying correction information to the voltage less than one cycle of a clock signal in the voltage regulator after detecting that the second value of the voltage is outside the target value range.

[0248] Example 30 includes subject matter (such as an apparatus, an electronic device (e.g., a circuit, an electronic system, or both), or a machine) that includes a device for performing any of the methods of Examples 26-29.

[0249] The subject matter of Examples 1 to 30 can be combined in any combination.

[0250] The above description and accompanying drawings illustrate some embodiments to enable those skilled in the art to implement various embodiments of the present invention. Other embodiments may be combined with structural, logical, electrical, process, and other changes. Examples represent possible variants only. Multiple parts and features of some embodiments may be included in multiple parts and features of other embodiments, or replace multiple parts and features of other embodiments. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art. Therefore, the scope of each embodiment is determined by the complete scope of the equivalent technical solutions granted by the attached claims and these claims.

[0251] As used in the detailed description and claims, any combination of the listed items may be meant by the term “at least one of”. For example, if items A and B are listed, the phrase “at least one of A and B” may mean: only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase “at least one of A, B, and C” may mean: only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0252] As used in the detailed description and claims, by the term "one of" may mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" may mean: only A (excluding B) or only B (excluding A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" may mean: only A; only B; or only C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0253] The abstract is provided to ascertain the nature and gist of the technical disclosure to the reader. It should be understood that the abstract will not be used to limit or interpret the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, wherein each claim stands on its own as a separate embodiment.

Claims

1. An electronic device, comprising: an output terminal for providing control information to a control transistor of a power switching unit; a node for receiving a feedback voltage based on an output voltage generated by the power switching unit; an error code generator for generating first error information and second error information based on a value of the feedback voltage generated from the output voltage; as well as A control circuit, the control circuit comprising a linear controller and a nonlinear controller, wherein: The linear controller includes a forward path for generating first output information based on the first error information provided to the forward path coupled to the output terminal, and adjusting a gain of the forward path based on a gain factor calculated at least in part based on a first value of the first output information during a first time interval so that the first output information has a second value during a second time interval; and The nonlinear controller is used to generate second output information based on the first error information, the second error information and the first output information, The control information is one of the first output information and the second output information.

2. The device according to claim 1, characterized in that The control circuit is used for: when the output voltage is within a target value range, causing the first output information to have the first value and the second value.

3. The device according to claim 1, characterized in that The linear controller comprises a multiplier, wherein the multiplier comprises: A first input terminal, used for receiving input information based on the first value of the first output information; a second input terminal for receiving information from a memory circuit in the control circuit; and The output terminal is used to provide the gain factor.

4. The device according to claim 1, characterized in that The control circuit is used to receive a clock signal and generate the first error information and the second error information based on a timing of the clock signal, and the control circuit is used to adjust the gain of the forward path in each cycle of the clock signal.

5. The device according to claim 1, characterized in that The control circuit is used for: generating the first output information based on the first error information provided to an additional forward path coupled to the output; as well as The gain of the additional forward path is adjusted based on an additional gain factor calculated at least in part based on the first value of the first output information during the first time interval so that the first output information has the second value during the second time interval.

6. The apparatus of any one of claims 1-5, further comprising an analog-to-digital converter, the analog-to-digital converter being configured to generate the first error information and the second error information based on the feedback voltage and a series of reference voltages.

7. The device according to any one of claims 1 to 5, characterized in that The control circuit comprises: a first forward path, configured to receive the first error information, the first forward path comprising a first adaptive gain circuit, the first adaptive gain circuit configured to generate the gain factor to adjust the gain of the first forward path; a second forward path, configured to receive the first error information, the second forward path comprising a second adaptive gain circuit, the second adaptive gain circuit configured to generate an additional gain factor based on the additional gain factor to adjust a gain of the second forward path; and A feedback path is coupled to the output terminal, the first forward path, and the second forward path.

8. An electronic device comprising: an output port for providing control information to control a transistor of a power switching unit; a control circuit configured to generate the control information so that a value of an output voltage generated by the power switching unit is less than a value of an input voltage provided to the power switching unit; as well as an error code generator for generating first error information and second error information based on a value of the feedback voltage generated from the output voltage, The control circuit includes a linear controller and a nonlinear controller, wherein: The linear controller is configured to generate first output information based on first error information during a first time interval when the output voltage has a first value within a target value range, and the nonlinear controller being configured to calculate a value of correction information based on the first error information and second error information, and to adjust a value of the control information based on the correction information and the first output information to generate second output information during a second time interval when the output voltage has a second value outside the target value range, The control information is one of the first output information and the second output information.

9. The device according to claim 8, characterized in that The control circuit is configured to calculate a value of the correction information based on a rate of change of a current at a node where the output voltage is provided.

10. The device according to claim 8, characterized in that The correction information indicates an amount of current to be adjusted at a node where the output voltage is provided during the second time interval.

11. The device according to any one of claims 8 to 10, characterized in that The control circuit is used to receive a clock signal, and the control circuit is used to: adjust the value of the control information at a time less than one cycle of the clock signal from a time when the second value of the output voltage is detected to be outside the target value range.

12. The device according to any one of claims 8 to 10, characterized in that The control circuit is used to receive a clock signal, and wherein: At a first edge of the clock signal, the second value of the output voltage is detected to be outside the target value range; and The control circuit is used to start adjusting the value of the control information at a second edge of the clock signal, where the second edge occurs within less than one cycle of the clock signal from the time when the first edge occurs.

13. The device according to any one of claims 8 to 10, characterized in that The control circuit is configured to receive a clock signal, and the control circuit is configured to calculate the correction information during a time interval between two consecutive edges of the clock signal.

14. The device according to any one of claims 8 to 10, characterized in that The control circuit is used to receive a clock signal, and the control circuit is used to calculate the correction information based on a count value, and the count value corresponds to the number of rising edges and falling edges of the clock signal.

15. The device according to any one of claims 8 to 10, characterized in that The control circuit is used to calculate the value of the correction information based on the rate of change of current from the moment when the second value of the output voltage is detected to be outside the target value range to the moment half a cycle after the moment when the second value of the output voltage is detected to be outside the target value range.

16. The device according to any one of claims 8 to 10, characterized in that: the control circuit being configured to adjust a value of the control information during a first portion of the second time interval based on the correction information; and The control circuit is configured to adjust a value of the control information during a second portion of the second time interval based on the first error information and the second error information generated by comparing a series of reference voltages with a feedback voltage generated from the output voltage.

17. An electronic device comprising: a power switching unit for receiving an input voltage to provide an output voltage, the output voltage having a value less than a value of the input voltage; an error code generator, configured to generate first error information and second error information based on an error of the output voltage; a linear controller for generating first output information to control the power switching unit based on the first error information during a first mode when the output voltage has a first value within a target value range, the linear controller for calculating a gain of a forward path during the first mode so that the first output information has a second value during the first mode; as well as A nonlinear controller for calculating a value of correction information based on the first error information and the second error information during the first mode, and for controlling the power switching unit based on second output information during a second mode when the output voltage has a second value outside the target value range, the second output information being generated based on the first output information and the correction information.

18. The device according to claim 17, characterized in that The linear controller includes a forward path implemented based on a single set of coefficients.

19. The device according to claim 17, characterized in that The linear controller includes a memory circuit for storing information used to calculate the gain.

20. The device according to any one of claims 17 to 19, characterized in that The nonlinear controller is used to control the power switching unit in an initial stage of the second mode, and the nonlinear controller is used to control the power switching unit based on error information different from the correction information in a second stage of the second mode.

21. An electronic device comprising: Semiconductor die; a processing unit, the processing unit being located on the semiconductor die; as well as a voltage regulator located on the semiconductor die and coupled to the processing unit, the voltage regulator comprising: a power switching unit for receiving an input voltage to provide an output voltage, the output voltage having a value less than a value of the input voltage; an error code generator, configured to generate first error information and second error information based on an error of the output voltage; a linear controller for generating first output information to control the power switching unit based on the first error information during a first mode when the output voltage has a first value within a target value range, the linear controller for calculating a gain of a forward path during the first mode so that the first output information has a second value during the first mode; and A nonlinear controller for calculating a value of correction information based on the first error information and the second error information during the first mode, and for controlling the power switching unit based on second output information during a second mode when the output voltage has a second value outside the target value range, wherein the second output information is generated based on the correction information and the first output information.

22. The device according to claim 21, characterized in that The first mode comprises a linear mode, and the second mode comprises a non-linear mode.

23. The device according to claim 21 or 22, characterized in that The semiconductor die, the processing unit and the voltage regulator are part of a system on a chip (SoC).

24. A method of operating an electronic device, the method comprising: generating control information at a linear controller of the voltage regulator to control a voltage at a node; generating a first value of the control information based on first error information during a first mode of the voltage regulator when the voltage has a first value within a target value range, and calculating a gain of a forward path in the linear controller to adjust the first value of the control information so that the control information has a second value during the first mode; generating correction information at a nonlinear controller of the voltage regulator during the first mode based on the first error information and second error information; as well as adjusting, at the nonlinear controller, a second value of the control information based on the correction information during a second mode of the voltage regulator when the voltage has a second value outside the target value range, The first error information and the second error information are based on an error in a voltage at the node.

25. The method of claim 24, wherein: The forward path is part of a plurality of forward paths of the first controller, and the plurality of paths are implemented using a single set of coefficients.

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