Connectors, power control devices, and host interface devices

Abstract

A connector, a power control device, and a host interface device are provided. A host interface device includes: a first pin connected to a first node and a second pin connected to a second node. The host interface device includes: a switch, the switch is connected between the second node and a first voltage terminal, and is configured to provide a voltage from the first voltage terminal to the second pin in response to a voltage level of the first node. The host interface device includes a pull-up resistor connected between the first node and the second voltage terminal. In addition, the host interface device is configured to receive a memory detection signal from the storage device via the first pin when the first pin is electrically connected to the storage device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0051389 filed on May 3, 2018, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2018-0130844 filed on October 30, 2018, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a host interface, and more specifically, to a host interface device for controlling the power supplied from a host to a storage device. A solid state drive (SSD) is a storage device. For the purpose of inputting and outputting data, the SSD can be connected to a host such as a desktop computer, a notebook computer, a laptop computer, a tablet computer, a smart phone, or a server. The SSD can be connected to the host through a connector (or slot). The standard of the connector for connecting the SSD to the host can vary with the type of the SSD. That is, the connector on which the SSD can be installed can be determined according to the type of the SSD. For example, an M.2 SSD can be installed on a connector suitable for the M.2 standard and can be connected to the host. Background Art

[0004] The demand for data centers for storing various data has increased. Therefore, SSDs of new form factors are being developed to store large amounts of data at data centers with limited space. A connector of a new standard may be used to connect the SSD of the new form factor to a host. In the case where an SSD of the new form factor is mounted on a connector that complies with conventional standards or a conventional SSD is mounted on a connector that complies with the new standard, the SSD may be damaged due to an abnormal supply of power. For example, in the case where an SSD of the conventional M.2 standard is mounted on a connector that complies with the new standard, the M.2 SSD may be damaged due to an abnormal supply of power from the host. Summary of the invention

[0005] Embodiments of the inventive concept provide a host interface device that can prevent / suppress damage of a storage device due to abnormal supply of power when a storage device of a different standard is mounted on a connector.

[0006] Embodiments of the inventive concept provide a host interface device that can quickly supply power to a storage device of a new form factor.

[0007] According to an example embodiment, a host interface device may include a first pin connected to a first node. The host interface device may include a second pin connected to a second node. The host interface device may include a switch connected between the second node and a first voltage terminal. The switch may be configured to provide a voltage from the first voltage terminal to the second pin in response to a voltage level of the first node. The host interface device may include a pull-up resistor connected between the first node and the second voltage terminal. In addition, the host interface device may be configured to receive a memory detection signal from a storage device via the first pin when the first pin is electrically connected to the storage device.

[0008] According to an example embodiment, a power control device capable of being electrically connected to a storage device through a plurality of pins of a connector is provided. The power control device may include a first memory detection circuit configured to output a first output signal at a first level in response to detecting that the storage device is not connected to the connector, and output the first output signal at a second level in response to a first memory detection signal sent from the storage device through a first pin among the plurality of pins when the storage device is connected to the connector. The power control device may include a second memory detection circuit configured to output a second output signal at the first level in response to detecting that the storage device is not connected to the connector, and output the second output signal at the second level in response to a second memory detection signal sent from the storage device through a second pin among the plurality of pins when the storage device is connected to the connector. In addition, the power control device may include a voltage supply circuit configured to block the supply of a voltage in response to the first output signal being at the first level, and supply the voltage to the storage device in response to the first output signal being at the second level.

[0009] According to an example embodiment, a connector electrically connecting a storage device and a power control device is provided. The connector may include a memory detection pin, and the power control device receives a memory detection signal from the storage device through the memory detection pin when the storage device is connected to the connector. In addition, the connector may include a voltage pin, and the power control device supplies a voltage to the storage device through the voltage pin in response to the memory detection signal. The length of the memory detection pin may be the longest length among multiple lengths of multiple pins included in the connector. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the inventive concept will become apparent by describing in detail example embodiments of the inventive concept with reference to the attached drawings.

[0011] Figure 1 is a block diagram illustrating a memory system according to some embodiments of the inventive concept.

[0012] Figure 2 It is shown in detail Figure 1 Block diagram of the storage system.

[0013] Figure 3 It is shown Figure 2 A circuit diagram of an example of a power supply control device.

[0014] Figure 4 is shown when no storage device is installed on the connector. Figure 3 FIG. 1 is a diagram of an example of the operation of a power control device.

[0015] Figure 5 is shown in Figure 1 In the case where a storage device of a different standard is mounted on the connector, Figure 3 FIG. 1 is a diagram of an example of the operation of a power control device.

[0016] Figure 6 It is shown in Figure 1 The storage device is installed on the connector. Figure 3 FIG. 1 is a diagram of an example of the operation of a power control device.

[0017] Figure 7 is a diagram illustrating an example of signals of a power control device according to some embodiments of the inventive concept.

[0018] Figure 8 It is shown Figure 2 A block diagram of an example of a connector of a storage system.

[0019] Fig. 9 It is shown Figure 2 A flow chart of the operation of a power control device.

[0020] Fig.10 is a block diagram illustrating a computing system including a memory system according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0021] In the following, example embodiments of the inventive concept are described in detail.

[0022] Figure 1 is a block diagram illustrating a storage system according to some embodiments of the inventive concept. Figure 1, the storage system 1000 may include a power control device 100, a connector 200, and a storage device 300. Each of the power control device 100 and the connector 200 may be one of a plurality of devices included in the host 1100. For example, the power control device 100 and the connector 200 may be devices mounted on a mainboard of a server. The storage device 300 may be mounted on the connector 200. Therefore, the storage device 300 may be electrically connected to the power control device 100 through the connector 200.

[0023] The power control device 100 may provide a signal associated with the operation of the storage device 300 to the storage device 300 through the connector 200. For example, the power control device 100 may supply a voltage "V" to the storage device 300 through the connector 200. The power control device 100 may be implemented in the form of a package or chip including circuits that perform various functions. However, the inventive concept is not limited thereto. For example, the power control device 100 may be implemented in the form of hardware, software, or a combination thereof.

[0024] The connector 200 may include a plurality of pins V_P to MD_P. The plurality of pins V_P to MD_P may be connected to a signal line of the power control device 100. For example, the pin V_P may be connected to a signal line providing a voltage "V" of the power control device 100.

[0025] When the storage device 300 is mounted on the connector 200, the plurality of pins V_P to MD_P may be used to transmit signals provided by the power control device 100 to the storage device 300. Additionally or alternatively, the plurality of pins V_P to MD_P may be used to transmit signals provided by the storage device 300 to the power control device 100.

[0026] The inventive concept is not limited to installing the storage device on the connector. On the contrary, when the storage device is on the connector and / or electrically connected to the connector (but not necessarily installed on the connector), any operation and / or configuration described herein about installing the storage device can be more widely implemented.

[0027] The storage device 300 may be mounted on the connector 200 (or otherwise on / connected to the connector 200) by using edge pins (e.g., gold fingers). When the storage device 300 is mounted on the connector 200, the plurality of pins V_P to MD_P may contact pins of the storage device 300. Thus, the power control device 100 and the storage device 300 may be electrically connected.

[0028] When the storage device 300 is mounted on the connector 200 through the plurality of pins V_P to MD_P, the storage device 300 may receive a signal from the power control device 100 and may provide the signal to the power control device 100. For example, the storage device 300 may receive data from the power control device 100 and may store the received data. The storage device 300 may provide the stored data to the power control device 100.

[0029] The storage device 300 may be a storage device having a specific standard among storage devices of various standards. For example, the storage device 300 may be an SSD having a small form factor (SFF). However, the inventive concept is not limited thereto. For example, the storage device 300 may include an SSD having various standards such as a next generation small form factor (NGSFF).

[0030] The power control device 100 may include a memory detection circuit 110 and a voltage supply circuit 120. The memory detection circuit 110 may receive a memory detection signal MDS from the memory device 300. In response to the power control device 100 and the memory device 300 being connected to each other, such as by having the memory device 300 mounted on the connector 200 so that the power control device 100 and the memory device 300 are connected to each other, the memory detection circuit 110 may receive the memory detection signal MDS. By receiving the memory detection signal MDS, the memory detection circuit 110 may detect that a memory device 300 of a specific standard is installed. The memory detection circuit 110 may receive the memory detection signal MDS through a memory detection pin MD_P.

[0031] When the storage device 300 is not installed on the connector 200, the memory detection circuit 110 may not be able to receive the memory detection signal MDS. In addition, when a storage device of a standard different from that of the storage device 300 is installed on the connector 200, the memory detection circuit 110 may not be able to receive the memory detection signal MDS. For example, when a storage device of a different standard is installed on the connector 200, the memory detection pin MD_P may not be connected to any pin of the storage device. Alternatively, the pin of the storage device connected to the memory detection pin MD_P may be in an open circuit state. In this case, the memory detection signal MDS may not be sent through the memory detection pin MD_P. When a storage device 300 of a specific standard is installed, the memory detection circuit 110 may receive the memory detection signal MDS.

[0032] In some embodiments, the reception of the memory detection signal MDS may mean that the voltage level of the memory detection pin MD_P has become a specific level. On the other hand, the non-reception of the memory detection signal MDS may mean that the voltage level of the memory detection pin MD_P has become a level different from the specific level.

[0033] The memory detection circuit 110 may output an output signal OS. In some embodiments, in response to detecting that the storage device 300 is not installed, the memory detection circuit 110 may output an output signal OS at a first level. In response to detecting that the storage device 300 is installed, the memory detection circuit 110 may output an output signal OS at a second level based on the memory detection signal MDS. For example, in response to detecting that the storage device 300 is not installed, the memory detection circuit 110 may output an output signal OS having a logic high value. In response to detecting that the storage device 300 is installed, the memory detection circuit 110 may output an output signal OS having a logic low value. In some embodiments, the memory detection signal MDS may be a signal having a logic low value.

[0034] The voltage supply circuit 120 may receive an output signal OS. Depending on the level of the output signal OS, the voltage supply circuit 120 may output a voltage “V” or may prevent the output of the voltage “V”. In some embodiments, the voltage supply circuit 120 may prevent (i.e., may not output) the voltage “V” in response to the output signal OS at a first level. The voltage supply circuit 120 may output the voltage “V” in response to the output signal OS at a second level. That is, the voltage supply circuit 120 may output the voltage “V” when it is determined that the storage device 300 is connected (e.g., installed), and may prevent the output of the voltage “V” when it is determined that the storage device 300 is not connected (e.g., not installed).

[0035] The output voltage “V” may be provided to the memory device 300 through the voltage pin V_P. Figure 1 , an example is shown in which the voltage "V" is provided to the storage device 300 through one signal line (i.e., one voltage pin V_P), but the inventive concept is not limited thereto. The voltage supply circuit 120 may provide the voltage "V" through multiple signal lines (i.e., multiple voltage pins V_P). In some embodiments, the same voltage "V" or different voltages "V" may be provided to multiple signal lines.

[0036] In response to the output voltage "V" being provided to the storage device 300, the storage device 300 may start operating. For example, the storage device 300 may set up an interface for data communication by performing an initialization operation. By using the voltage "V", the storage device 300 may store data provided from the host 1100 or may provide the stored data to the host 1100.

[0037] As described above, when a storage device 300 of a specific standard is installed, the power control device 100 can detect the connection of the storage device 300 and can provide a voltage "V" to the storage device 300. In response to detecting that a storage device of a standard different from that of the storage device 300 is installed, the power control device 100 can block the supply of the voltage "V". On the contrary, if the voltage "V" is provided to a storage device of a different standard, the signal line of the storage device supplied with the voltage "V" may be connected to the ground terminal. As a result, an overcurrent may flow to the signal line supplied with the voltage "V", and thus the storage device may be damaged. The power control device 100 can therefore prevent storage devices of different standards from being damaged / protect storage devices of different standards from being damaged by blocking the supply of the voltage "V".

[0038] Figure 2 It is shown in detail Figure 1 Block diagram of the storage system. Figure 2 , the storage system 1000 may include a connector 200 , a storage device 300 , and a power control device 400 . Figure 2 The operation of the connector 200 and the storage device 300 is Figure 1 The operations of the connector 200 and the storage device 300 are substantially the same or similar, and redundant descriptions may be omitted.

[0039] The connector 200 may include an input signal pin IS_P, a main voltage pin MV_P, a memory detection pin MD_P, a sub voltage pin SV_P, and a presence pin PR_P.

[0040] The power control device 400 may include a first memory detection circuit 410 , a main voltage supply circuit 420 , a sub voltage supply circuit 430 , a second memory detection circuit 440 , and a controller 450 .

[0041] The first memory detection circuit 410 may receive the first memory detection signal MDS1, depending on the connection state of the power control device 400 and the storage device 300. When the power control device 400 and the storage device 300 are not connected to each other, the first memory detection circuit 410 may not receive the first memory detection signal MDS1. When the power control device 400 and the storage device 300 are connected to each other, the first memory detection circuit 410 may receive the first memory detection signal MDS1 from the storage device 300 through the memory detection pin MD_P.

[0042] The first memory detection circuit 410 may output a first output signal OS1. The first output signal OS1 may be provided to the main voltage supply circuit 420, the auxiliary voltage supply circuit 430, and the controller 450. The level of the first output signal OS1 may change depending on whether the first memory detection signal MDS1 is received. In response to detecting that the first memory detection signal MDS1 is not received, the first memory detection circuit 410 may output the first output signal OS1 at a first level. In response to detecting that the first memory detection signal MDS1 is received, the first memory detection circuit 410 may output the first output signal OS1 at a second level. If the first memory detection signal MDS1 is received, the level of the first output signal OS1 may be the same as the level of the first memory detection signal MDS1. For example, in response to not receiving the first memory detection signal MDS1, the first output signal OS1 at a high level may be output, whereas in response to receiving the first memory detection signal MDS1 at a low level, the first output signal OS1 at a low level may be output.

[0043] That is, the first memory detection circuit 410 may determine whether the power control device 400 and the storage device 300 are connected to each other based on the first memory detection signal MDS1. The first memory detection circuit 410 may output the first output signal OS1 at different levels according to the connection status of the power control device 400 and the storage device 300.

[0044] The main voltage supply circuit 420 may receive a first output signal OS1. Depending on the level of the first output signal OS1, the main voltage supply circuit 420 may output a first voltage V1 or may prevent the output of the first voltage V1. In response to receiving the first output signal OS1 at a first level, the main voltage supply circuit 420 may prevent the output of the first voltage V1. In response to receiving the first output signal OS1 at a second level, the main voltage supply circuit 420 may output the first voltage V1. The first voltage V1 thus outputted may be provided to the memory device 300 through the main voltage pin MV_P.

[0045] That is, in response to detecting that the power control device 400 and the storage device 300 are not connected to each other, the main voltage supply circuit 420 can prevent (i.e., avoid) the supply of the first voltage V1. In response to detecting that the power control device 400 and the storage device 300 are connected to each other, the main voltage supply circuit 420 can supply the first voltage V1.

[0046] The first voltage V1 may be a voltage necessary for the operation of the storage device 300 / a voltage sufficient to operate the storage device 300. In some embodiments, the storage device 300 may operate an internal circuit based on the first voltage V1. Based on the first voltage V1, the storage device 300 may store data or may output the stored data. For example, the first voltage V1 may be, but is not limited to, 12 volts (V).

[0047] The secondary voltage supply circuit 430 may receive the first output signal OS1. Depending on the level of the first output signal OS1, the secondary voltage supply circuit 430 may output the second voltage V2 or may prevent the output of the second voltage V2. In response to receiving the first output signal OS1 at the first level, the secondary voltage supply circuit 430 may prevent the output of the second voltage V2. In response to receiving the first output signal OS1 at the second level, the secondary voltage supply circuit 430 may output the second voltage V2. The second voltage V2 thus outputted may be provided to the storage device 300 through the secondary voltage pin SV_P.

[0048] That is, in response to detecting that the power control device 400 and the storage device 300 are not connected to each other, the secondary voltage supply circuit 430 can block the supply of the second voltage V2. In response to detecting that the power control device 400 and the storage device 300 are connected to each other, the secondary voltage supply circuit 430 can supply the second voltage V2.

[0049] The second voltage V2 may be a voltage necessary for the storage device 300 to operate in a special / specific situation / a voltage sufficient for the storage device 300 to operate in a special / specific situation. In some embodiments, in response to the first voltage V1 being blocked from being supplied to the storage device 300, the storage device 300 may communicate with the power control device 400 based on the second voltage V2. That is, the storage device 300 may communicate with the power control device 400 via a sideband. For example, the second voltage V2 may be, but is not limited to, 3.3V.

[0050] The second memory detection circuit 440 may receive the second memory detection signal MDS2 according to the connection state of the power control device 400 and the storage device 300. When the power control device 400 and the storage device 300 are not connected to each other, the second memory detection circuit 440 may not receive the second memory detection signal MDS2. When the power control device 400 and the storage device 300 are connected to each other, the second memory detection circuit 440 may receive the second memory detection signal MDS2 from the storage device 300 through the presence pin PR_P. Therefore, the pin to which the first memory detection signal MDS1 is sent (i.e., the memory detection pin MD_P) may be different from the pin to which the second memory detection signal MDS2 is sent (i.e., the presence pin PR_P).

[0051] The second memory detection signal MDS2 may be received later than the first memory detection signal MDS1. For example, the time when the presence pin PR_P is connected to the pin of the memory device 300 may be later than the time when the memory detection pin MD_P is connected to the pin of the memory device 300. Therefore, the second memory detection signal MDS2 may be provided later than the first memory detection signal MDS1.

[0052] The second memory detection circuit 440 may output a second output signal OS2. The second output signal OS2 may be provided to the controller 450. The level of the second output signal OS2 may change depending on whether the second memory detection signal MDS2 is received. In response to not receiving the second memory detection signal MDS2, the second memory detection circuit 440 may output the second output signal OS2 at a first level. In response to receiving the second memory detection signal MDS2, the second memory detection circuit 440 may output the second output signal OS2 at a second level. If the second memory detection signal MDS2 is received, the level of the second output signal OS2 may be the same as the level of the second memory detection signal MDS2. For example, if the second memory detection signal MDS2 is not received, the second output signal OS2 at a high level may be output, whereas if the second memory detection signal MDS2 at a low level is received, the second output signal OS2 at a low level may be output.

[0053] That is, the second memory detection circuit 440 may determine whether the power control device 400 and the storage device 300 are connected to each other based on the second memory detection signal MDS2. Since the second memory detection signal MDS2 is received later than the first memory detection signal MDS1, the second memory detection circuit 440 may detect the connection of the power control device 400 and the storage device 300 later than the first memory detection circuit 410. Therefore, the time when the level of the second output signal OS2 changes may be later than the time when the level of the first output signal OS1 changes.

[0054] The controller 450 may receive the first output signal OS1 and the second output signal OS2. The controller 450 may provide the initialization signal INIT to the storage device 300 in response to the level change of the second output signal OS2. In response to the second output signal OS2 changing from the first level to the second level, the controller 450 may provide the initialization signal INIT to the storage device 300 through the input signal pin IS_P. When the storage device 300 is connected to the power control device 400, the controller 450 may initialize the storage device 300 through the initialization signal INIT.

[0055] Since the first memory detection signal MDS1 may be received before the second memory detection signal MDS2, the time at which the level change of the first output signal OS1 is detected may be earlier than the time at which the level change of the second output signal OS2 is detected. If the controller 450 provides the initialization signal INIT based on the level change of the first output signal OS1, the initialization signal INIT may be provided before the first voltage V1 and the second voltage V2 are provided to the memory device 300. As a result, the initialization operation of the memory device 300 may not be performed normally.

[0056] In contrast, if the controller 450 provides the initialization signal INIT based on the level change of the second output signal OS2, the initialization signal INIT may be provided after the first voltage V1 and the second voltage V2 are provided to the memory device 300. As a result, the initialization operation of the memory device 300 may be normally performed.

[0057] However, the inventive concept is not limited thereto. For example, the controller 450 may provide the initialization signal INIT based on the level change of the first output signal OS1. In some embodiments, the controller 450 may provide the initialization signal INIT after a preset / predetermined time has passed after the time when the level change of the first output signal OS1 is detected.

[0058] The storage device 300 may perform an initialization operation in response to the initialization signal INIT. For example, the storage device 300 may set an interface standard (e.g., SATA or PCIe) and a bandwidth for the purpose of communicating with the power control device 400. The power control device 400 and the storage device 300 may transmit data through relevant pins according to the set interface standard and bandwidth.

[0059] As described above, the power control device 400 may include two memory detection circuits 410 and 440. The power control device 400 may provide the voltages V1 and V2 to the memory device 300 by using the first memory detection circuit 410, and may initialize the memory device 300 by using the second memory detection circuit 440. Since the first memory detection signal MDS1 is received earlier than the second memory detection signal MDS2, the power control device 400 may initialize the memory device 300 after supplying power to the memory device 300.

[0060] refer to Figure 2The components of the described power control device 400 may be implemented in the form of software, hardware, or a combination thereof. For example, the software may include machine code, firmware, embedded code, and / or application software. For example, the hardware may include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), passive components, or a combination thereof.

[0061] Figure 3 It is shown Figure 2 A circuit diagram of an example of a power supply control device. Figure 3 , the power control device 400 may include a first memory detection circuit 410 , a main voltage supply circuit 420 , a sub-voltage supply circuit 430 , a second memory detection circuit 440 , and a controller 450 .

[0062] The first memory detection circuit 410 may include a pull-up resistor 411. A first end of the pull-up resistor 411 may be connected to a terminal to which a second voltage V2 is supplied (hereinafter referred to as a "V2 terminal"), and a second end of the pull-up resistor 411 may be connected to a first node N1. The first node N1 may be connected to a memory detection pin MD_P of the connector 200. For example, the second voltage V2 may be 3.3V.

[0063] The first node N1 may be directly connected to the output terminal of the first memory detection circuit 410. Therefore, the level of the first output signal OS1 output from the first memory detection circuit 410 may be determined according to the level of the first node N1. If the first node N1 is at the first level, the first output signal OS1 may have the first level. If the first node N1 is at the second level, the first output signal OS1 may have the second level.

[0064] The main voltage supply circuit 420 may include first to fourth main switches 421 to 424. For example, the main switches 421 to 424 may be implemented with p-channel MOSFETs (hereinafter referred to as "PMOS transistors"). However, the inventive concept is not limited thereto. For example, the main switches 421 to 424 may be implemented with various types of transistors.

[0065] The first ends of the main switches 421 to 424 may be connected to a terminal supplied with a first voltage V1 (hereinafter referred to as a "V1 terminal"), and the second ends thereof may be connected to the second node N2 to the fifth node N5, respectively. The second node N2 to the fifth node N5 may be connected to the first main voltage pin MV_P1 to the fourth main voltage pin MV_P4, respectively. The gates of the main switches 421 to 424 may be connected to the output terminal (i.e., the first node N1) of the first memory detection circuit 410.

[0066] The main switches 421 to 424 may be turned on or off according to the level of the first output signal OS1. When the main switches 421 to 424 are in an off state, the first voltage V1 may be blocked from being supplied to the main voltage pins MV_P1 to MV_P4. When the main switches 421 to 424 are in an on state, the first voltage V1 may be supplied to the main voltage pins MV_P1 to MV_P4. For example, in response to the first output signal OS1 at a first level (e.g., logic high), the main switches 421 to 424 may be turned off. In response to the first output signal OS1 at a second level (e.g., logic low), the main switches 421 to 424 may be turned on.

[0067] like Figure 3 As shown in FIG. 4 , the main voltage supply circuit 420 may supply the first voltage V1 through four pins MV_P1 to MV_P4 , but the inventive concept is not limited thereto. For example, the main voltage supply circuit 420 may supply the first voltage V1 through a different number of pins.

[0068] The secondary voltage supply circuit 430 may include a side switch 431. For example, the side switch 431 may be implemented with a PMOS transistor. However, the inventive concept is not limited thereto. For example, the side switch 431 may be implemented with various types of transistors.

[0069] The first end of the side switch 431 may be connected to the V2 terminal, and the second end of the side switch 431 may be connected to the sixth node N6. The sixth node N6 may be connected to the secondary voltage pin SV_P. The gate of the side switch 431 may be connected to the output terminal (ie, the first node N1) of the first memory detection circuit 410.

[0070] The side switch 431 may be turned on or off according to the level of the first output signal OS1. When the side switch 431 is turned off, the second voltage V2 may be blocked from being supplied to the secondary voltage pin SV_P. When the side switch 431 is turned on, the second voltage V2 may be supplied to the secondary voltage pin SV_P. For example, in response to the first output signal OS1 being at a first level (e.g., logic high), the side switch 431 may be turned off. In response to the first output signal OS1 being at a second level (e.g., logic low), the side switch 431 may be turned on.

[0071] like Figure 3 As shown in FIG. 4 , the secondary voltage supply circuit 430 may supply the second voltage V2 through one pin SV_P, but the inventive concept is not limited thereto. For example, the secondary voltage supply circuit 430 may supply the second voltage V2 through a different number of pins.

[0072] The second memory detection circuit 440 may include a first detection resistor 441 and a second detection resistor 442. The first end of the first detection resistor 441 may be connected to the ground terminal GND, and the second end of the first detection resistor 441 may be connected to the seventh node N7. The seventh node N7 may be connected to the first presence pin PR_P1. The first end of the second detection resistor 442 may be connected to the V2 terminal, and the second end thereof may be connected to the eighth node N8. The eighth node N8 may be connected to the second presence pin PR_P2. For example, the second voltage V2 may be 3.3V.

[0073] The eighth node N8 may be directly connected to the output terminal of the second memory detection circuit 440. Therefore, the level of the second output signal OS2 output from the second memory detection circuit 440 may be determined according to the level of the eighth node N8. When the eighth node N8 is at the first level, the second output signal OS2 may have the first level. When the eighth node N8 is at the second level, the second output signal OS2 may have the second level.

[0074] The controller 450 may provide an initialization signal INIT necessary for / used for the initialization operation of the storage device 300 through the first input signal pin IS_P1 to the mth input signal pin IS_Pm. However, the inventive concept is not limited thereto. For example, the controller 450 may provide the initialization signal INIT to the storage device 300 by using a different number of pins.

[0075] Next, we will refer to Figures 4 to 7 The operation of the power supply control device 400 is described.

[0076] Figure 4 is shown when no storage device is installed on the connector. Figure 3 FIG. 1 is a diagram of an example of the operation of a power control device.

[0077] In response to detecting that no storage device is mounted on the connector 200 (or otherwise on / connected to the connector 200), the pull-up resistor 411 may pull up the first node N1 to a first level (①-1) by using the second voltage V2. For example, the first level may be the second voltage V2. As a result, a first output signal OS1 at a first level may be output from the first memory detection circuit 410.

[0078] In response to the first output signal OS1 of the first level, the main switches 421 to 424 and the side switch 431 (②-1) may be turned off. Therefore, the supply of the first voltage V1 to the first to fourth main voltage pins MV_P1 to MV_P4 may be blocked, and the supply of the second voltage V2 to the sub voltage pin SV_P may be blocked.

[0079] In response to detecting that no storage device is mounted on the connector 200, the second detection resistor 442 may pull up the eighth node N8 to the first level (①-2) by using the second voltage V2. For example, the first level may be the second voltage V2. As a result, a second output signal OS2 at the first level may be output from the second memory detection circuit 440.

[0080] In response to receiving the first output signal OS1 at the first level or the second output signal OS2 at the first level, the controller 450 may maintain a standby state. That is, the controller 450 may not provide a signal (eg, initialization signal INIT) through the first to mth input signal pins IS_P1 to IS_Pm.

[0081] Figure 5 is shown in Figure 1 In the case where a storage device of a different standard is mounted on the connector, Figure 3 FIG. 1 is a diagram of an example of the operation of a power control device. Figure 5 , the storage device 500 may have Figure 1 and Figure 2 The storage devices 300 are of different standards (ie, different size and form factors).

[0082] When the storage device 500 is mounted on the connector 200, the memory detection pin MD_P may not be connected to any pin of the storage device 500, or the pin or signal line of the storage device 500 connected to the memory detection pin MD_P may be open (i.e., the pin or signal line of the storage device 500 may not be connected to a specific circuit or a specific terminal). Therefore, the first node N1 may maintain the state (①-1) in which the first node N1 is pulled up to the first level by the second voltage V2. As a result, the first output signal OS1 at the first level may be output from the first memory detection circuit 410.

[0083] In response to the first output signal OS1 of the first level, the main switches 421 to 424 and the side switch 431 (②-1) may be turned off. Therefore, the first voltage V1 may be blocked from being supplied to the first to fourth main voltage pins MV_P1 to MV_P4, and the second voltage V2 may be blocked from being supplied to the sub voltage pin SV_P.

[0084] When the storage device 500 is mounted on the connector 200, the pin or signal line of the storage device 500 connected to the second presence pin PR_P2 may be open. Therefore, the eighth node N8 may maintain the state (①-2) in which the eighth node N8 is pulled up to the first level by the second voltage V2. As a result, the second output signal OS2 at the first level may be output from the second memory detection circuit 440.

[0085] In response to receiving the first output signal OS1 at the first level or the second output signal OS2 at the first level, the controller 450 may be maintained in a standby state. That is, the controller 450 may not provide a signal (e.g., an initialization signal INIT) to the storage device 500 through the first to m-th input signal pins IS_P1 to IS_Pm.

[0086] As described above, in response to detecting that a storage device 500 of a standard different from that of the storage device 300 is mounted on the connector 200, the power control device 400 may not supply any voltage to the storage device 500. When the standard of the storage device 500 is different from the standard supported by the power control device 400, one of the plurality of pins supplied with voltage may be directly connected to the ground terminal. As a result, an overcurrent may flow to the storage device 500, thereby causing damage to the storage device 500. Therefore, the power control device 400 may prevent / suppress damage to the storage device 500 by blocking the supply voltage to the storage device 500.

[0087] Figure 6 It is shown in Figure 1 The storage device is installed on the connector. Figure 3 FIG. 1 is a diagram of an example of the operation of a power control device.

[0088] When the storage device 300 is mounted on the connector 200, the signal line of the storage device 300 connected to the memory detection pin MD_P may be connected to the ground terminal GND. Therefore, a first memory detection signal MDS1 at a second level may be provided from the storage device 300 through the memory detection pin MD_P (①). For example, the second level may be 0V. Based on (e.g., in response to) the first memory detection signal MDS1, the first node N1 may be pulled down to the second level (②).

[0089] If the first node N1 is pulled down to the second level, the first output signal OS1 of the second level may be output. In response to the first output signal OS1 of the second level, the main switches 421 to 424 and the side switch 431 may be turned on (③). Therefore, the first voltage V1 may be supplied to the storage device 300 through the first to fourth main voltage pins MV_P1 to MV_P4, and the second voltage V2 may be supplied to the storage device 300 through the sub voltage pin SV_P (④).

[0090] When the storage device 300 is mounted on the connector 200, the first presence pin PR_P1 and the second presence pin PR_P2 can be connected through the signal line SL of the storage device 300. Therefore, the seventh node N7 and the eighth node N8 of the second memory detection circuit 440 can be connected. The ground terminal GND of the second memory detection circuit 440 can be connected to the seventh node N7 and the eighth node N8 through the first detection resistor 441. Therefore, a second memory detection signal MDS2 (⑤) of a second level can be provided from the storage device 300 through the second presence pin PR_P2. For example, the second level can be 0V. According to the second memory detection signal MDS2, the eighth node N8 can be pulled down to the second level (⑥). That is, the first detection resistor 441 can pull the eighth node N8 down to the second level.

[0091] When the eighth node N8 is pulled down to the second level, the second output signal OS2 of the second level may be output. In response to the second output signal OS2 changing from the first level to the second level, the controller 450 may provide the initialization signal INIT to the storage device 300 through the first input signal pin IS_P1 to the mth input signal pin IS_Pm (⑦). The storage device 300 may perform an initialization operation (⑧) in response to the initialization signal INIT.

[0092] As described above, when a storage device 300 of a specific standard is installed, the power control device 400 may detect the connection of the storage device 300, and may first supply power to the storage device 300. After supplying power to the storage device 300, the power control device 400 may initialize the storage device 300. Therefore, power may be quickly supplied to the storage device 300, and an initialization operation of the storage device 300 may be quickly performed.

[0093] Figure 7 is a diagram illustrating an example of signals of a power control device according to some embodiments of the inventive concept. Figure 7 The horizontal axis of t represents time. At a first time t1, the storage device 300 may be mounted on the connector 200 (or otherwise on / connected to the connector 200).

[0094] refer to Figures 4 to 7 , before the storage device 300 is mounted on the connector 200 (i.e., before the first time t1), the first node N1 may be in a pull-up state with a first level LV1. In a state where the voltage of the first node N1 corresponds to the first level LV1, the supply of the first voltage V1 and the second voltage V2 may be blocked. Therefore, the voltage output to the first main voltage pin MV_P1 to the fourth main voltage pin MV_P4 and the auxiliary voltage pin SV_P may be 0V. Before the storage device 300 is mounted on the connector 200, the eighth node N8 may be in a pull-up state with a first level LV1. In response to the voltage of the eighth node N8 being maintained at the first level LV1, the controller 450 may not provide any signal to the storage device 300. Therefore, no signal may be output to the first input signal pin IS_P1 to the mth input signal pin IS_Pm.

[0095] When the storage device 300 is mounted on the connector 200 (i.e., at the first time t1), the first memory detection circuit 410 may receive the first memory detection signal MDS1. Therefore, at the first time t1, the first node N1 may be pulled down to the second level LV2 based on the first memory detection signal MDS1. In a state where the first node N1 is at the second level LV2, the first voltage V1 and the second voltage V2 may be supplied to the storage device 300. Therefore, the voltage output to the first main voltage pin MV_P1 to the fourth main voltage pin MV_P4 may be the first voltage V1, and the voltage output to the sub voltage pin SV_P may be the second voltage V2.

[0096] A predetermined time after the first voltage V1 and the second voltage V2 are supplied to the memory device 300 (i.e., at the second time t2), the second memory detection circuit 440 may receive the second memory detection signal MDS2. Therefore, at the second time t2, the eighth node N8 may be pulled down to the second level LV2 based on the second memory detection signal MDS2. In response to the eighth node N8 changing from the first level LV1 to the second level LV2, the controller 450 may initialize the memory device 300. In the process of initializing the memory device 300, an initialization sequence (or a power-on sequence) may be sent through the first input signal pin IS_P1 to the mth input signal pin IS_Pm.

[0097] like Figure 7 As shown in , when the storage device 300 is mounted, the first node N1 of the power control device 400 may be pulled down first before the eighth node N8. Therefore, after power is supplied to the storage device 300, the storage device 300 may perform an initialization operation.

[0098] Figure 8 It is shown Figure 2 A block diagram of an example of a storage system connector. Figure 8 , the storage system 1000 may include a connector 200, a storage device 300, and a power control device 400. The connector 200 may include a first presence pin PR_P1, an input signal pin IS_P, a main voltage pin MV_P, a memory detection pin MD_P, a secondary voltage pin SV_P, and a second presence pin PR_P2. The storage device 300 may include a first memory pin MP1 to a sixth memory pin MP6 (e.g., a gold finger).

[0099] The first presence pin PR_P1 may be connected to the ground terminal GND of the power control device 400. When the memory device 300 is mounted on the connector 200, the first presence pin PR_P1 may be connected to the first memory pin MP1 of the memory device 300. The first presence pin PR_P1 may correspond to Figure 4 The first one exists on pin PR_P1.

[0100] When the storage device 300 is mounted on the connector 200, the input signal pin IS_P may be connected to the second memory pin MP2 of the storage device 300. The input signal pin IS_P may be used to transmit an initialization signal INIT provided from the power control device 400 to the storage device 300. The input signal pin IS_P may correspond to Figure 4 one of the first to mth input signal pins IS_P1 to IS_Pm.

[0101] When the storage device 300 is mounted on the connector 200, the main voltage pin MV_P may be connected to the third memory pin MP3 of the storage device 300. The main voltage pin MV_P may be used to transmit the first voltage V1 provided from the power control device 400 to the storage device 300. The main voltage pin MV_P may correspond to Figure 4 One of the first to fourth main voltage pins MV_P1 to MV_P4.

[0102] When the storage device 300 is mounted on the connector 200, the memory detection pin MD_P may be connected to the fourth memory pin MP4 of the storage device 300. The fourth memory pin MP4 may be connected to the ground terminal GND of the storage device 300. Therefore, when the storage device 300 is mounted on the connector 200, the memory detection pin MD_P may be connected to the ground terminal GND of the storage device 300. The memory detection pin MD_P may be used to transmit the first memory detection signal MDS1 provided from the storage device 300 based on the ground terminal GND of the storage device 300 to the power control device 400. The memory detection pin MD_P may correspond to Figure 4The memory detection pin MD_P.

[0103] When the storage device 300 is mounted on the connector 200, the secondary voltage pin SV_P may be connected to the fifth memory pin MP5 of the storage device 300. The secondary voltage pin SV_P may be used to transmit the second voltage V2 provided from the power control device 400 to the storage device 300. The secondary voltage pin SV_P may correspond to Figure 4 The secondary voltage pin SV_P.

[0104] When the storage device 300 is mounted on the connector 200, the second presence pin PR_P2 may be connected to the sixth memory pin MP6 of the storage device 300. The sixth memory pin MP6 may be connected to the first memory pin MP1 through the signal line SL. Therefore, when the storage device 300 is mounted on the connector 200, the second presence pin PR_P2 may be connected to the first presence pin PR_P1. The second presence pin PR_P2 may be used to transmit the second memory detection signal MDS2 provided from the storage device 300 based on the ground terminal GND of the power control device 400 to the power control device 400. The second presence pin PR_P2 may correspond to Figure 4 The second exists at pin PR_P2.

[0105] like Figure 8 As shown in , the length Lmd of the memory detection pin MD_P may be the longest of the lengths of the pins included in the connector 200. That is, the memory detection pin MD_P may be the longest pin among the plurality of pins included in the connector 200. Therefore, when the storage device 300 is mounted on the connector 200, the memory detection pin MD_P may be the target of the first mating connection. That is, the memory detection pin MD_P may be first connected to the fourth memory pin MP4 of the storage device 300 before any other pin of the connector 200. Therefore, the memory detection pin MD_P may first send the first memory detection signal MDS1 to the power control device 400 before the second memory detection signal MDS2. The power control device 400 may supply the first voltage V1 and the second voltage V2 in response to the first memory detection signal MDS1.

[0106] like Figure 8As shown in , the length Lpr1 of the first existence pin PR_P1 and the length Lpr2 of the second existence pin PR_P2 may be shorter than the length Lmd of the memory detection pin MD_P. Each of the first existence pin PR_P1 and the second existence pin PR_P2 may be the shortest pin among the plurality of pins included in the connector 200. Therefore, when the storage device 300 is mounted on the connector 200, the first existence pin PR_P1 and the second existence pin PR_P2 may be the target of the last pairing connection. That is, the first existence pin PR_P1 and the second existence pin PR_P2 may be connected to the first memory pin MP1 and the sixth memory pin MP6 of the storage device 300 later than any other pin of the connector 200. Therefore, the second existence pin PR_P2 may send the second memory detection signal MDS2 to the power control device 400 later than the first memory detection signal MDS1. The power control device 400 may output the initialization signal INIT in response to the second memory detection signal MDS2. Therefore, after power is supplied to the storage device 300, the initialization operation of the storage device 300 may be performed sequentially.

[0107] exist Figure 8 , an example is shown in which the first presence pin PR_P1 and the second presence pin PR_P2 are the targets of the last pairing connection, but the inventive concept is not limited thereto. For example, one of the first presence pin PR_P1 and the second presence pin PR_P2 may be the target of the last pairing connection, while the other may not be. In other words, the first presence pin PR_P1 or the second presence pin PR_P2 may be the target of the last pairing connection.

[0108] For the convenience of description, Figure 8 2 shows an example in which one pin is provided for each corresponding function (eg, when one input signal pin IS_P and one main voltage pin MV_P are provided), but the inventive concept is not limited thereto. For example, the connector 200 may include a plurality of pins that perform the same function.

[0109] In addition, for the convenience of description, Figure 8 , the remaining pins except the memory detection pin MD_P have the same length, but the inventive concept is not limited thereto. For example, at least one of the first presence pin PR_P1 and the second presence pin PR_P2 may be shorter in length than any other pin.

[0110] As described above, the power control device 400 may detect that a storage device 300 of a specific standard is mounted on the connector 200 (or is otherwise on / connected to the connector 200), and may provide power to the storage device 300. Figure 8As shown in , the first memory pin MP1 and the sixth memory pin MP6 of the storage device 300 may be connected by the signal line SL, and the fourth memory pin MP4 may be connected to the ground terminal GND. In response to detecting that no storage device is mounted on the connector 200 or a storage device of a different standard is mounted on the connector 200, the power control device 400 may block the supply of power. Therefore, in response to detecting that a storage device of a different standard is mounted on the connector 200, the power control device 400 may prevent the storage device of the different standard from being damaged by the power supply / protect the storage device of the different standard from being damaged by the power supply.

[0111] Fig. 9 It is shown Figure 2 A flowchart of the operation of the power control device. Figure 2 and Fig. 9 In block 101, the power control device 400 may be in a default state. The default state may refer to a state in which the power control device 400 blocks the supply of power and does not output a signal. In response to detecting that the storage device 300 is not installed, the power control device 400 may maintain the default state.

[0112] In block 102, the power control device 400 may detect whether the first memory detection signal MDS1 is received. When the first memory detection signal MDS1 is received, the power control device 400 may determine that the storage device 300 is installed. When the first memory detection signal MDS1 is not received, the power control device 400 may determine that the storage device 300 is not installed. For example, the power control device 400 may detect Figure 4 The voltage change of the first node N1 is used to detect whether the first memory detection signal MDS1 is received.

[0113] When the first memory detection signal MDS1 is received, in block 103, the power control device 400 may supply power to the storage device 300. If the first memory detection signal MDS1 is not received, the power control device 400 may maintain a default state until the first memory detection signal MDS1 is received. That is, in response to detecting that the storage device 300 is connected, the power control device 400 may supply power to the storage device 300.

[0114] In block 104, the power control device 400 may detect whether the second memory detection signal MDS2 is received. For example, the power control device 400 may detect Figure 4 Whether the second memory detection signal MDS2 is received is detected by the voltage change of the eighth node N8.

[0115] When receiving the second memory detection signal MDS2, the power control device 400 may initialize the memory device 300 in block 105. For initialization of the memory device 300, the power control device 400 may provide an initialization signal INIT to the memory device 300. The memory device 300 may perform an initialization operation in response to the initialization signal INIT.

[0116] Fig.10 is a block diagram illustrating a computing system including a storage system according to some embodiments of the inventive concept. Fig.10 The computing system 2000 may include a desktop computer, a server, and a mobile device. The computing system 2000 may include a host 2100 and a storage device 2200 .

[0117] The host 2100 may include a power supply 2110, a processor 2120, a memory 2130, and a host interface 2140. The power supply 2110 may provide power to devices and circuits of the host 2100. For example, the power supply 2110 may supply power to the processor 2120 and the host interface 2140.

[0118] The processor 2120 may perform overall operations of the computing system 2000. For example, the processor 2120 may control operations of the memory 2130 and the host interface 2140. The processor 2120 may control the storage device 2200 through the host interface 2140.

[0119] The memory 2130 may store data processed by or to be processed by the processor 2120. For example, the memory 2130 may be implemented with a volatile memory or a nonvolatile memory.

[0120] The host interface 2140 may supply power to the storage device 2200 and may transmit data provided from the processor 2120. The host interface 2140 may provide various signals to the storage device 2200 under the control of the processor 2120. The host interface 2140 may include a reference Figures 1 to 9 The power control device 100 or 400 and the connector 200 are described.

[0121] The storage device 2200 may be connected to the host 2100 through the host interface 2140. For example, the storage device 2200 may be mounted on the host 2100 through edge pins (e.g., gold fingers) to be connected to the host 2100. The storage device 2200 may be supplied with power through the host interface 2140 and may receive signals through the host interface 2140. The storage device 2200 may store data provided from the host 2100 and may provide the stored data to the host 2100. The storage device 2200 may include a reference Figures 1 to 9The described storage device 300. Therefore, in response to detecting that a storage device 2200 of a specific standard is connected to the host interface 2140, the host interface 2140 may supply power to the storage device 2200.

[0122] A host interface device according to the present invention may prevent / protect storage devices of different standards from being damaged by blocking the supply of power in response to detecting that a storage device is mounted on a connector (or otherwise on / connected to a connector).

[0123] Also, the host interface device according to the inventive concept can quickly supply power to a storage device of a specific predetermined size form factor.

[0124] While the inventive concepts have been described with reference to example embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the scope of the inventive concepts as set forth in the appended claims.

Claims

1. A host interface device, comprising: a first pin electrically connected to a first node of the host interface device; a second pin electrically connected to a second node of the host interface device; a switch electrically connected between the second node and a first voltage terminal and configured to operate in an on state in response to a voltage level of the first node to provide a voltage from the first voltage terminal to the second pin; a pull-up resistor electrically connected between the first node and a second voltage terminal; a third pin, the third pin being electrically connected to a third node; a fourth pin, the fourth pin being electrically connected to a fourth node; The fifth pin; a first detection resistor electrically connected between the third node and a ground terminal; as well as a second detection resistor electrically connected between the fourth node and the second voltage terminal, wherein the host interface device is configured to receive a memory detection signal from the storage device via the first pin when the first pin is electrically connected to the storage device, Wherein, the memory detection signal comprises a first memory detection signal, The host interface device is further configured to send a second memory detection signal to the memory device via the third pin and receive the second memory detection signal from the memory device via the fourth pin when the third pin and the fourth pin are electrically connected to the memory device. wherein, when the third pin and the fourth pin are not electrically connected to the storage device, the second detection resistor is configured to maintain the voltage level of the fourth node at a first level, wherein when the third pin and the fourth pin are electrically connected to the storage device, the first detection resistor is configured to pull down the voltage level of the fourth node to a second level, and The host interface device is further configured to send an initialization signal to the storage device through the fifth pin when the voltage level of the fourth node changes from the first level to the second level.

2. The host interface device according to claim 1, in, The pull-up resistor is configured to maintain a voltage level of the first node at a first level when the first pin is not electrically connected to the memory device, and When the first pin is electrically connected to the storage device, in response to the memory detection signal, the voltage level of the first node is pulled down to a second level.

3. The host interface device according to claim 1, in, When the storage device has a specific size, the first pin is electrically connected to a ground terminal of the storage device. Wherein, when the storage device has a size and shape different from the specific size and shape, the first pin is not electrically connected to any pin of the storage device, or the first pin is electrically connected to an open pin or signal line of the storage device, and The switch is further configured to operate in an off state to prevent the voltage from being supplied to the storage device when the storage device has a different size.

4. The host interface device according to claim 1, wherein: The switch comprises a first switch, and wherein the host interface device further comprises: A second switch is electrically connected between the third node and the first voltage terminal and is configured to provide the voltage from the first voltage terminal to the third pin in response to a voltage level of the first node.

5. The host interface device according to claim 1, wherein: The voltage includes a first voltage, wherein the host interface device further includes: a side switch electrically connected between the third node and the second voltage terminal and configured to provide a second voltage from the second voltage terminal to the third pin in response to a voltage level of the first node, and The second voltage is lower than the first voltage.

6. The host interface device according to claim 1, wherein: The first pin is longer than the fourth pin.

7. A power control device capable of being electrically connected to a storage device through a plurality of pins of a connector, the power control device comprising: a first memory detection circuit configured to output a first output signal at a first level in response to detecting that the memory device is not electrically connected to the connector, and to output the first output signal at a second level in response to a first memory detection signal sent from the memory device through a first pin of the plurality of pins when the memory device is electrically connected to the connector; a second memory detection circuit configured to output a second output signal at the first level in response to detecting that the memory device is not electrically connected to the connector, and to output the second output signal at the second level in response to a second memory detection signal transmitted to the memory device through a third pin among the plurality of pins and received from the memory device through a fourth pin among the plurality of pins when the memory device is electrically connected to the connector; a controller configured to initialize the storage device in response to the second output signal being at the second level; as well as A voltage supply circuit is configured to block supply of a voltage in response to the first output signal being at the first level, and to supply the voltage to the memory device in response to the first output signal being at the second level.

8. The power control device according to claim 7, wherein: The first pin is longer than the third pin and the fourth pin.

9. The power control device according to claim 7, wherein: The voltage supply circuit includes a first voltage supply circuit, wherein the voltage includes a first voltage, and wherein the power supply control device further includes: A second voltage supply circuit is configured to block supply of a second voltage lower than the first voltage in response to the first output signal being at the first level, and to supply the second voltage to the memory device in response to the first output signal being at the second level.

10. The power control device according to claim 7, in, The first memory detection circuit includes a pull-up resistor configured to maintain the first output signal at the first level when the memory device is not electrically connected to the connector, and Wherein, when the storage device is electrically connected to the connector, the first output signal is pulled down to the second level.

11. The power control device according to claim 7, wherein: The voltage supply circuit comprises: A switch is configured to supply the voltage to the memory device through a second pin of the plurality of pins in response to the first output signal being at the second level.

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