Non-volatile memory device, in particular phase change memory and reading method

Abstract

Embodiments of the present disclosure relate to non-volatile memory devices, particularly phase change memory and reading methods. A non-volatile memory device has a circuit branch associated with a bit line connected to a memory cell. When reading the memory cell, in a precharge step, the bit line is precharged. In a characteristic drift step, the memory cell is activated, and a current source is activated to provide a drift current to the first bit line and cause the bit line to be charged or discharged based on the data stored in the memory cell. In a detection step, the current source is deactivated, the memory cell is decoupled, and the bit line is coupled to the input of a comparator stage, which compares the voltage on the bit line with a reference voltage to provide an output signal indicative of the data stored in the memory cell.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Application No. 102018000005084, filed on May 4, 2018, which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a nonvolatile memory device, in particular to a phase change memory device and a reading method thereof. Background Art

[0004] As is well known, and as Figure 1 As schematically shown in FIG. 1 , a nonvolatile memory device (here, of a phase-change type) indicated by 1 generally comprises a memory array 2 including a plurality of memory cells 3 arranged in rows and columns and storing corresponding data.

[0005] Each memory cell 3 is formed here by a phase-change storage element 4 designed to store binary data, and a selection element 5 formed here by an NMOS transistor in series with the storage element 4. The gate terminals of the selection elements 5 for the memory cells 3 arranged in the same row are coupled together and coupled to the corresponding word lines WL0, WL1, .... The corresponding first conductive terminals of the selection elements 5 of the memory cells 3 arranged in the same column are coupled together and coupled to the corresponding local bit lines LBL1, ..., LBLn, .... In addition, the second conductive terminal of each selection element 5 is coupled to a reference potential line (for example, connected to the ground).

[0006] The local bit lines LBL0, ..., LBLi, ... are coupled to a column decoder stage 6 (shown in a simplified manner), which in turn is coupled to a bias and read circuit 7, only the sense amplifier stage 12 of which is shown. The word lines WL0, WL1, ... are coupled to Figure 1 In a known manner, the bias and read circuits 7, the column decoding stage 6 and the row decoding stage 8 allow one or more memory cells 3 to be selected at a time based on address signals generated by a control unit 10 (also schematically represented).

[0007] In the example shown, the memory 1 has a hierarchical bit line structure (in the simplified example, with two levels, but three levels are conceivable), in which the local bit lines LBL1, ..., LBLi, ... are coupled to the global bit lines (also called "master bit lines") MBL0, MBL1, ... via first switches 13.0, 13.1, ..., which in turn are coupled to the bias and read circuit 7 via second switches 14.0, 14.1, .... Figure 1 In the schematic diagram of , first switches 13.0, 13.1, ..., second switches 14.0, 14.1, ..., and global bit lines MBL0, MBL1, ... form a column decoding stage 6. In some embodiments, as described above, the column decoding stage 6 may include further levels with further bit lines and corresponding third switches in a manner known to those skilled in the art (not shown).

[0008] The bias and read circuit 6 notably forms one or more read paths which can be activated individually or in parallel and each of which is designed to generate a conductive path between a memory cell 3 of the memory array 2 (each time it is selected) and a sense amplifier stage 12. The sense amplifier stage 12 is of the differential type and is intended to compare the current circulating in the selected memory cell 3 with a reference current in order to determine the value of the stored data and to generate a corresponding digital read signal.

[0009] Recently, the use of memory devices produced in the back-end steps of the process (whose storage elements are provided in the last layers of the device) has become more important since it is possible to simplify the manufacturing process and therefore reduce manufacturing costs, provide embedded memory devices, possibly integrated in the same die with other circuits and obtained using advanced CMOS technology.

[0010] In particular, the back-end integration of non-volatile phase change memory devices is becoming increasingly important. In these memory devices, the storage element is formed by a material region that is able to change its physical structure when subjected to a sufficient current value, from an amorphous phase to a crystalline phase, or vice versa, with a consequent change in its ohmic resistance. This change in ohmic resistance is used to store digital data.

[0011] The two states of a storage element are called:

[0012] a set state, associated with a crystalline phase characterized by lower resistance and, therefore, higher current in the case of a constant voltage read of the memory element; and

[0013] The reset state is associated with the amorphous phase characterized by a higher resistance and, therefore, a lower current in the case of a constant voltage read of the memory element.

[0014] In this type of memory, the phase change in the storage element is activated at a specific temperature and is acquired by applying a current pulse of a few microseconds in duration, which locally raises the temperature and modifies the physical structure of the material by the Joule effect.

[0015] Therefore, this type of memory device may be sensitive to problems with data retention, especially when the device is exposed to intermediate temperatures, not even very high temperatures (up to 165°C), but for a long time (up to several thousand hours). This often happens, for example, when the memory device is used in automotive applications and therefore usually operates at temperatures of 150-160°C.

[0016] In particular, in this case, phenomena that may occur and may lead to failures or in any case erroneous operation are associated with the loss of the amorphous and crystalline states (associated with the conditions of reset and setting) due to partial crystallization, i.e. to less ordered crystalline conditions of the material in the amorphous or crystalline phase.

[0017] For applications where temperature plays a fundamental role, the type of material selected, and in particular its composition, can be optimized to meet the requirements for reliability and retention of data.

[0018] However, also in this case, the application of an intermediate temperature can lead to a non-negligible phase change of the optimized material and thus to a gradual reduction of the difference between the current values ​​or resistance values ​​associated with the two states of the memory.

[0019] Considering the read current I r The normalized distribution of the number of cells N as a function of and its evolution over time at constant temperature can highlight this phenomenon, as Figure 2A In the case where the memory cell is programmed in the reset state, and as shown in Figure 2B In the memory cell, the program is in the set state and in the reset and set states (t s =0) is shown in the case where the temperature is kept constant at 150°C from the time of programming.

[0020] In particular, in these figures, curves A1 and A2 represent the cumulative distribution of reset and set cells, respectively, that conduct the read current to the value I reported at time zero. r, and the other curves represent similar cumulative distributions of memory cells that conduct read current to values ​​I plotted after gradually increasing times (as indicated by arrows) from 3 h (curves B1 and B2, respectively) to 2000 h (curves C1 and C2, respectively) from programming. r .

[0021] It can be noticed that the distribution of reset cells and the distribution of set cells drift towards the left, that is, towards lower current values, as the time elapsed since their programming increases. This phenomenon is observed in the set cells ( Figure 2B ), these setting cells drift from read current values ​​comprised between 22 μA and 30 μA to much lower current values ​​as low as 5 μA after 2000 h.

[0022] It can be found in the distribution and the equiprobability straight line ECC (in Figure 2A and 2B In the example, it is set to 10 -6 ) is identified at the intersection between the worst cells of the distribution which are defined as being unrecoverable by an error correction read scheme.

[0023] This means that without reprogramming or refreshing, the difference in read current between the worst cell that has been SET before reading (and has a read current of, for example, a few mA) and the worst cell that has been recently reset is very low or even zero.

[0024] This fact is Figure 3 The curves D1 and D2 are highlighted. These curves will Figure 2A and 2B The data are presented as the storage time t of the worst cell in the distribution for reset and set cells. s (at a fixed temperature) is a function of s = 0 and then kept at 150° C. for a period of about 1000 h. Therefore, the distance between the two curves D1 and D2 represents the read window for the memory.

[0025] In particular, Figure 3 It is shown that for t s =0, the difference between the read current of the worst set cell and the worst reset cell is high and tends to decrease over time due to the applied temperature.

[0026] Figure 4 Shown on an enlarged scale Figure 3 part, where the arrows indicate the different storage times t s The read current I r The difference between the reading current I rA "free" scope, i.e. a scope with no set or reset cells.

[0027] The above range represents an operating window of about 1 μA, which is effective for the storage time t s The low values ​​of are clearly separated from curves D1 and D2, but then approach the curve D2 of the worst-set cell and reach it at a storage time slightly above 1000 h. After this, in the case of fast reading, i.e. a few nanoseconds, the operating window overlaps with the curve D2 of the worst-set cell and thus cannot be read with a sufficiently low error margin. Therefore, in this operating window, the cell must be reprogrammed via a refresh operation after a maximum time of 1000 h.

[0028] Also in this way, the reading of the cell will be problematic. In fact, in non-flash memory types, the reading current I r Reading is performed by comparison with a reference current which is generated by a reference cell formed in the same memory array so as to have the same electrical characteristics or is generated by an equivalent current source.

[0029] In theory, the reference current can be variable in time as a function of the programming time or constant.

[0030] However, in the case where the reference current is variable over time, it is necessary to keep track of the time that has passed since the programming of the cell to be read and to adapt the characteristics of the reference element to the Figure 4 However, this solution is not feasible because tracking the programming time of each cell would be complex and require high costs and unacceptable read times.

[0031] On the other hand, reading via a fixed reference proves to be complex at high read speeds (e.g., current requirements call for a read time of about 10 ns). In fact, for example, the same memory array may include cells that have been set for nearly 1000 h and have a read current slightly above 6 μA and just reset cells with a read current slightly below 5 μA. Therefore, the reference current may be set in the middle between these values, for example 5.5 μA. In this case, the read circuit may be designed so as to be able to distinguish a read current of 5 μA relative to a reference of 5.5 μA or a read current of 6 μA relative to the same reference of 5.5 μA.

[0032] In practice, this requires being able to distinguish currents that differ by 0.5 μA, which is difficult enough at the read rates considered. In addition, the resolution is a small fraction of the read current, both for the set and reset cells, further complicating the problem and making some fast read solutions for other types of memory inapplicable.

[0033] For example, in Italian patent application 102016000024496 filed in the name of the present applicant (corresponding to US patent 9,865,356 and European patent application EP 3 217 405), a reading method and circuit are described in which the voltage across a selected bit line is compared with the voltage across an adjacent bit line, the adjacent bit line being precharged with an intermediate value between the values ​​that the selected bit line can reach in the two states stored by the memory cell to be read. In particular, the reading method disclosed in this patent application described with reference to a floating gate flash memory cell exploits the parasitic capacitance present in the memory array and charges two global bit lines (the bit line of the cell to be read and the adjacent bit line) with an intermediate value. Then, the cell to be read is read. If the cell stores a bit "1", it conducts current and causes its own local bit line to discharge and thereby causes its own global bit line to discharge by charge sharing, so that the voltage value of the global bit line is lower than the intermediate value on the adjacent global bit lines. If the cell to be read stores a bit "0" and therefore does not conduct current, its local bit line does not discharge, but instead brings its own global bit line to a higher voltage value than the median value on the neighboring global bit lines.

[0034] The read circuit described in the above-mentioned Italian patent application 102016000024496 works very well when one of the two programmed states is characterized by zero current, for example for the application mentioned for floating gate flash memory cells, but is not usable when there is a common current contribution, as in the case of PCM type memory cells having the above-mentioned electrical characteristics.

[0035] It is an object of the present invention to provide a reading circuit and method that overcome the limitations of the prior art. Summary of the invention

[0036] According to an embodiment of the invention, there is provided a phase change non-volatile memory device and a corresponding reading method as defined in the accompanying claims.

[0037] According to an embodiment of the present invention, a nonvolatile memory device has a circuit branch associated with a bit line connected to a memory cell to be read. When reading the memory cell, in a precharge step, the bit line is precharged. In a characteristic drift step, the memory cell is activated, and a current source is activated to provide a drift current to the bit line, and the bit line is caused to charge or discharge based on the data stored in the memory cell. In a detection step, the current source is deactivated, the memory cell is decoupled, and the bit line is coupled to the input of a comparator stage, which compares the voltage on the bit line with a reference voltage to provide an output signal indicating the data stored in the memory cell. The drift current is selected so as to be higher than the current of the memory cell when the memory cell is in a first programming state, and less than the current of the memory cell when the memory cell is in a second programming state. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] For a better understanding of the invention, some embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0039] Figure 1 is a schematic diagram of the structure of a non-volatile memory device of the type under consideration;

[0040] Figure 2A and 2B The read current is shown as a function of the reset and set cells, respectively. Figure 1 a normalized cumulative distribution of the number of memory cells of the device;

[0041] Figure 3 showing a graph of read current for the worst cell in reset and set states as a function of time elapsed since programming;

[0042] Figure 4 Shown on an enlarged scale Figure 3 part of the curve;

[0043] Figure 5 1 shows a method of shifting a memory cell by adding a constant current to the memory cell to be read according to one aspect of the present invention. Figure 4 curve.

[0044] Figure 6 A simplified circuit diagram of the present memory device is shown;

[0045] Figure 7 A more complete circuit diagram of the present memory device is shown;

[0046] Figure 8 A table showing the steps of the present reading method; and

[0047] Fig. 9 Shows Figure 7 A graph showing the charge in a circuit. DETAILED DESCRIPTION

[0048] This reading method is based on downward translation Figure 4 The curve of makes the distribution at lower read current (the current of the worst reset cell) become theoretically negative current. Figure 5 , where the arrows indicate the displacement of the read currents of the worst set and reset cells, and the shifted curves are represented by D1 and D2. In fact, since it is impossible to have a negative current, the reset memory cells have zero read current, which helps distinguish them from the set memory cells.

[0049] In practice, by appropriately choosing the drift current value (5 μA in the case shown), the worst set cell (after 1000 h) has a current of 1 μA and the reset cell has zero current again, so the read margin becomes 1 μA; additionally, the read margin is advantageously referenced to zero.

[0050] Furthermore, in order to improve the reading performance, increasing the reading rate while reducing the size of the memory device, use is made of the principle forming the subject of the above-mentioned Italian patent application 102016000024496, comprising a further step of injecting a characteristic conversion current for the programmed memory cell, thereby discharging / charging the corresponding bit line before charge sharing (here between the global bit line and the output capacitance) and unbalancing the bit lines connected to the sense amplifier.

[0051] like Figure 6 As shown, the influence of the above-mentioned read current offset can be obtained.

[0052] Figure 6 A portion of a memory device 30 is shown, and the memory device 30 has Figure 1 Similar general structure and thus includes similar Figure 1 The memory array 33, column decoder 34, and bias and read circuit 35 are arranged in rows and columns of the corresponding stages 2, 6, and 7. Specifically, Figure 6 In FIG. 1 , elements arranged in a read branch 31 are shown in boxes 33 - 35 , which read branch 31 is connected to a memory cell 32 to be read and is useful for understanding the present reading method.

[0053] Specifically, the read branch 31 includes two bits coupled in series to the local bit line LBL. i A local decoding transistor 40 , a global decoding transistor 42 , an output connection transistor 44 and a charging transistor 46 between (physically coupled to the memory cell 32 to be read) and a power supply line 37 .

[0054] In detail, the local decoding transistor 40 (here of NMOS type and belonging to the column decoding stage 34) has a connection to the local bit line LBL coupled to the local bit line LBL. i The first conductive terminal of the local node 41 is connected to the global bit line MBL coupled to j The second conductive terminal of the global node 43 and the control terminal receiving the local decoding signal VY0 from the control unit 36 ​​are similar to Figure 1 The control unit 21.

[0055] The global decoding transistor 42 , here also of NMOS type and belonging to the column decoding stage 34 , has a first conduction terminal coupled to the global node 43 , a second conduction terminal connected to the internal node 45 , and a control terminal receiving the global decoding signal VYN via the control unit 36 ​​.

[0056] The output connection transistor 44 (here also of NMOS type) has a first conduction terminal connected to the internal node 45, a second conduction terminal connected to the output node 47, and receives the bias signal V CA The output node 47 has an output voltage V o The first input of the sense amplifier 50 of the differential type is also coupled to the sense amplifier 50, which has a sense voltage V ref The second input.

[0057] The charging transistor 46 (here of PMOS type) has a first conductive terminal connected to the output node 47, a second conductive terminal connected to the power supply line 37, and a first conductive terminal connected to the output node 47, and a second conductive terminal connected to the power supply line 37. CH The control terminal of the second conductive terminal receives the power supply voltage V DD .

[0058] Furthermore, the current source 48 is coupled to the internal node 45 and generates a drift current I , which is injected into the internal node 45 when the source enable signal EN generated by the control unit 36 ​​is enabled. add .

[0059] Figure 6 The capacitance present in the read branch 31 is also shown.

[0060] Specifically, the local parasitic capacitor 51 (shown by a dotted line and having a local capacitance C 1 ) is coupled to the local bit line LBL i The associated local node 41 is connected to a reference potential line 54 (here ground) of the memory device 30. A global parasitic capacitor 52 (also shown by a dashed line and having a capacitance C g ) is coupled to the global bit line MBL j The output capacitor 53 (here of parasitic type and therefore shown by dashed lines, but it may include physical components and have a capacitance C o ) is coupled between the output node 47 and the reference potential line 54.

[0061] Typically, the capacitance C of the global parasitic capacitor 52 is g (ie, with the global bit line MBL j The associated parasitic capacitance) is higher than the local capacitance C of the local parasitic capacitor 51 1 (ie, local bit line LBLi The associated parasitic capacitance) and is higher than the capacitance C of the output capacitor 53 on the output node 47. o .

[0062] In the read branch 31, the drift current I add The value of the maximum read current of the worst reset cell. For example, refer to Figure 2A , Figure 2B , Figure 3-5 The values ​​shown, drift current I add is 5μA.

[0063] In this case, if the memory cell 32 to be read is programmed to be in the RESET state and therefore draws a current lower than or at most equal to 5 μA (the read value of the worst reset cell), the drift current I add The current drawn by the memory cell is compensated and therefore, to a first approximation, the voltage at the node of the read branch 31 is not modified.

[0064] In contrast, if the memory cell 32 to be read is programmed to be in the SET state and therefore draws a drift current I add If the current is higher, the current of the cell 32 to be read and the drift current I add The difference between the reference voltage V ref has a suitably fixed value.

[0065] In this way, when the memory cell 32 to be read is in the reset state, the current provided by the read branch 31 is zero and the sense amplifier 50 outputs a logic "0", and when the memory cell 32 to be read is in the set state, the current provided by the read branch 31 is higher than zero and the sense amplifier 50 outputs a logic "1".

[0066] As mentioned above, the above reference Figure 6 The principles set out can be applied to the reading circuit and the reading method described in the aforementioned Italian patent application 102016000024496 to obtain the above-mentioned advantages of reading speed and memory size reduction.

[0067] Figure 7 An implementation of a memory device 30 employing the above-described principles is shown.

[0068] In detail, Figure 7 A reference branch 60 is shown, which comprises a reference branch 60 connected to the global bit line MBL as described in the aforementioned Italian patent application 102016000024496. jAdjacent global bit lines, such as global bit line MBL j+1 , hereinafter referred to as MBL'. For simplicity, in the following, the global bit line MBL coupled to the memory cell to be read j will be represented by MBL, and the local bit line LBL i Will be represented by LBL.

[0069] The reference branch 60 has a similar structure to the read branch 31, and therefore its elements will not be described in detail and are specified below and in Figure 7 denoted by the same numerals as the corresponding elements of the read branch 31, provided with single quotes.

[0070] also, Figure 7 Equalizing elements of the read branch 31 and the reference branch 60 are shown.

[0071] In detail, the memory device 30 has a first equalization transistor 65, a second equalization transistor 66, and a third equalization transistor 67. Here, the first equalization transistor 65 of NMOS type is connected between the global nodes 43 and 43' of the read branch 31 and the reference branch 60, respectively, and has a control terminal receiving the equalization signal ATD generated by the control unit 36. The second equalization transistor 66 of NMOS type is connected between the internal nodes 45 and 45' of the read branch 31 and the reference branch 60, respectively, and has a control terminal receiving the equalization signal ATD. The third equalization transistor 66 of NMOS type is connected between the output nodes 47 and 47' of the read branch 31 and the reference branch 60, respectively, and has a control terminal receiving the equalization signal ATD.

[0072] As discussed in detail below, equalization transistors 65-67 have the function of equalizing the nodes connected to them so that they have substantially the same voltage value during some read operation steps.

[0073] Figure 7 The reading of the memory device 30 includes four different steps (precharge, equalization, characteristic drift and sharing), which will be referred to below. Figure 8 and 9 Detailed description, Figure 8 and 9 A table is shown, which shows the Figure 7 The values ​​of the control signals in the circuit and the timing diagram of the control signals and the word lines connected to the memory cell 32 to be read (corresponding to Figure 1 The voltage on the word line WL (row voltage V R ). Row voltage V Ris also applied to the reference cell 32 ′, even if this cell remains closed during all steps of reading the cell 32 to be read and does not participate in the reading, as explained in detail below.

[0074] In the precharge step, the read branch 31 is precharged and the reference branch 60 is floated. To this end, at time t=t 0 , the local decoding signal VY0 supplied to the read branch 31 is switched to a high state to connect the memory cell 32 to be read to the corresponding global bit line MBL, while the local decoding signal VY0' supplied to the reference branch 60 is kept low and keeps the reference memory cell 32' disconnected from the corresponding global bit line MBL' (this disconnection also continues in subsequent steps). The global decoding signals VYN and VYN' are switched to a high state to connect the global bit lines MBL and MBL' to the corresponding internal nodes 45 and 45'. In the read branch 31, the bias signal V CA The bias signal VCH switches to a high state and the precharge signal VCH switches to a low state to turn on the output connection transistor 44 and the charging transistor 46. In the reference branch 60, the bias signal V CA ' remains in a low state, and the charging signal V CH ' is kept in a high state to keep the output connection transistor 44' and the charging transistor 46' of the branch 60 turned off. In addition, the equalization signal ATD and the source enable signal EN are kept low to keep the equalization transistors 65-67 and the current source 48 turned off.

[0075] In this case, the reference branch 60 is decoupled from the rest of the circuit; the read branch 31 is connected to the supply voltage V DD , which causes the parasitic capacitance C 1 , C g and C o Therefore, the internal node 45, the global node 43 and the local node 41 are charged to substantially the same preset voltage value V P =V dd -V b , where V b Corresponding to the bias signal V CA high value.

[0076] The memory cell 32 to be read is turned off because the corresponding word line (not shown) is still low, such as the row voltage V R As described above, the reference memory cell 32' is also turned off.

[0077] In the equalization step, the read branch 31 and the reference branch 60 are equalized. To this end, at time t=t 1 , pre-charge signal V CH switches to a high state to turn off the charging transistor 46 and connect the read branch 31 to the supply voltage VDD In addition, the equalization signal ATD switches to a high state. Other signals remain in the previous state, and the row voltage V R Keep it low.

[0078] In this case, the equalization transistors 65-67 are turned on and connect the internal node 45, the global node 43 and the local node 41 of the read branch 31 to the corresponding nodes 45', 43' and 41' of the reference branch 60. Therefore, these nodes on the read branch 31 and on the reference branch 360 become approximately the same voltage, which is slightly lower than the preset voltage value V P This is because the local bit line LBL′ of the reference branch 60 remains always disconnected from the reference cell 32 ′ and thus the global capacitance of the reference branch 60 is lower than the global capacitance of the read branch 31 .

[0079] In the characteristic drift (discharge / charge) step, the output node 47 (and therefore the output capacitor 53) is decoupled from the global bit line MBL, and the internal node 45 is discharged or charged depending on the state of the memory cell 32 to be read and provides a drift current I add .

[0080] To this end, at time t = t 2 , bias signal V CA Switches to a low state to isolate output node 47 from the rest of read branch 31, and equalization signal ATD switches to a low state to turn off equalization transistors 65-67 and thus disconnect read branch 31 from reference branch 60. Thus, reference branch 60 remains at the previous voltage level, while read branch 31 can evolve freely.

[0081] After a short delay, the source enable signal EN switches to a high state to turn on the current source 48; the current source 48 thus starts to provide current.

[0082] In this step, the word line connected to the memory cell 32 to be read starts to rise, such as Fig. 9 The row voltage V R As shown. Therefore, the memory cell 32 to be read is switched to the read condition, and the voltage on the internal node 45 becomes the voltage obtained by the current drawn from the memory cell 32 to be read and the drift current I provided by the source 48. add The value expressed as the ratio between . In particular:

[0083] If the current drawn from the memory cell 32 to be read is higher than the drift current I add(the memory cell 32 to be read is in the set state, corresponding to the storage of a logic "1"), the parasitic capacitors 51 and 52 associated with the local node 41 and the global node 43 are discharged, causing the voltage thereon and therefore the voltage on the internal node 45 to decrease;

[0084] If the current drawn from the memory cell 32 to be read is lower than the drift current I provided by the source 48 add (the memory cell 32 to be read is in the reset state, corresponding to the storage of logic "0"), the overcurrent provided by the source 48 charges the parasitic capacitances 51 and 52, and the global node 43 and the internal node 45 rise to a higher voltage value; this behavior corresponds to the memory cell 32 to be read being equal to I add The downward characteristic drift of the amount, such as Figure 5 shown.

[0085] The sharing step enables the voltage on the internal node 45 to be amplified and provided to the output node 47 and includes the drift current I add deactivation (disconnection) of and recoupling of output node 47 from the global bit line.

[0086] Therefore, at time t = t 3 , the local decoding signal VY0 provided to the read branch 31 is switched to a low state to disconnect the memory cell 32 to be read from the corresponding global bit line MBL, the source enable signal EN is switched to a low state to turn off the current source 48, and the bias signal V CA Switches to the high state again to turn on the output connection transistor 44 and cause connection of the internal node 45 to the output node 47 of the read branch.

[0087] In this step, charge is shared between the global parasitic capacitor 52 and the output capacitor 53, the result of which depends on the charge state of the global parasitic capacitor 52, ie, on whether the memory cell 32 to be read is in the set state or the reset state.

[0088] In particular, the sharing is similar to the sharing between local parasitic capacitors (denoted therein by 51) and global parasitic capacitors (denoted therein by 52) described in the above-mentioned Italian patent application 102016000024496 and described in detail there on the basis of the ratio between the capacitance values ​​at the global node and the local node.

[0089] In this regard, again refer to Figure 7 , recall that, as a result of equilibrium, at time t = t 3 The output voltage V at the output nodes 47 and 47' o and V o ' are equal to each other and equal to V ref.

[0090] During the sharing step, the output voltage V at the output node 47 ′ of the reference branch 60 is o '=V ref remains constant because output node 47' is isolated from the rest of the circuit (transistors 46', 67 and 44' are off).

[0091] Conversely, the output voltage V at the output node 47 of the reading branch 31 is o change.

[0092] In particular, if the memory cell 32 to be read is set (stored state: logic "1") and has caused the discharge of the global parasitic capacitor 52 and the reduction of the voltage at the internal node 45 to be equal to -ΔV 45 , then the charge sharing between the global parasitic capacitor 52 and the output capacitor 53 causes the output voltage V on the output node 47 to be o of reduction.

[0093] If, on the other hand, the memory cell 32 to be read is reset (state storage: logic “0”) and has caused a charging of the global capacitor 52 and an increase in the voltage at the internal node 45 equal to ΔV 45 , then the charge sharing between the global parasitic capacitor 52 and the output capacitor 53 causes the output voltage V at the output node 47 to o increase.

[0094] In fact, at the end of the sharing step and if I r is the current drawn from the memory cell 32 to be read, then V od =V ref is the voltage at the output node 47 (equal to the equilibrium value) at the end of the characteristic drift, V os is the voltage value at the output node 47 when sharing is completed, and by setting ΔV o =V os -V od ,get:

[0095] If I r add →V os >V od , then V os >V ref

[0096] If I r >I add →V os <V od , then V os <V ref ​

[0097] as well as

[0098] -ΔV o =ΔV 45 *(C g / C o )

[0099] Among them C g and C o are the capacitance of the global parasitic capacitor 52 associated with the global bit line MBL and the capacitance of the output capacitor 53 coupled to the output node 47, and ΔV 45 is the voltage change on node 45 during the characteristic shift step.

[0100] Now we describe the evaluation step. 4 , bias signal V CA Switching to the low state again turns off the output connection transistor 44 and causes the internal node 45 to be disconnected from the output node 47 of the read branch 31 , thereby freezing the voltage at the output node 47 .

[0101] Therefore, the sense amplifier 50 can output the voltage V o With reference voltage V ref A comparison is made to determine whether the data read is a logical "0" or "1".

[0102] In reality, during actual operation, there is an effect of partially modifying the above contents, however, this does not have any impact on the operating principle.

[0103] In fact, in order to make the threshold current of the memory cell 32 to be read (the voltage values ​​on the output node 47 and the internal node 45 are reversed) equal to the current I provided by the current source 48 add , the voltage value at the internal node 45 and therefore at all the global bit lines MBL should also remain constant during the characteristic drift, which obviously does not happen due to the conduction of the memory cell 32 to be read and the opening of the current source. In fact, during the characteristic drift step, due to its conduction, the voltage value at the internal node 45 drifts and also causes the local parasitic capacitor 51 and the global parasitic capacitor 52 to participate in the dynamics of the characteristic drift step. In fact, if the voltage of the internal node 45 drifts by a few millivolts relative to the equilibrium value during the characteristic drift step, since this node is associated with a resistance in the region of several KΩ (due to the parasitic resistances of various components, including the local decoding and global decoding transistors 40, 42), current variations of the order of magnitude of milliamperes may occur, i.e. current variations of the same order of magnitude as the current to be evaluated. However, in order to solve this problem, during the calibration of the memory device 30, the current value I add so that compensation for this effect is sufficient, and Figure 3 An effective shift of the distributions D1, D2 will take place at a current of the memory cell that is higher than the theoretical value, in order in any case to allow the output node 47 to maintain the same voltage as the reference node 47' at the end of the characteristic shifting step before sharing.

[0104] Also, during calibration, further effects due to leakage currents in the actual circuit can be compensated.

[0105] From the foregoing, the advantages of the memory devices and reading methods described herein are clear.

[0106] In particular, with the help of the proposed solution it is possible to read in a simple way a phase change type or some other type of memory cell, wherein all or at least some of the states stored in the memory cell are associated with the cell conduction conditions and where the use of a fixed reference becomes difficult due to retention etc., resulting in characteristics changing over time or for other reasons.

[0107] Furthermore, the proposed solution advantageously enables the use of global bit lines that are adjacent to the global bit line associated with the memory cell to be read, and therefore have similar electrical characteristics, in particular parasitic capacitances.

[0108] With the described solution, apart from the current source 48, no reference structures have to be used; in particular, the use of reference memory cells is not envisaged.

[0109] Thus, the memory device 30 has smaller dimensions and lower electrical consumption than known solutions.

[0110] In addition, the memory device 30 has a higher reading speed.

[0111] Finally, it is clear that modifications and variations may be made to the memory device and the reading method described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.

[0112] For example, as mentioned above, the present solution may also be applied to other types of non-volatile memory devices (embedded or standalone), such as Flash, EPROM or EEPROM devices (single-level or multi-level), where a current comparison is required for reading stored data.

[0113] Furthermore, instead of acting directly on the current source 48 , the source enable signal EN may act on a switch that couples or decouples the current source 48 to or from the internal node 45 without thereby modifying the above-described operation.

[0114] The first equalizing transistor 65 may not be present.

[0115] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A non-volatile memory device, comprising: a memory array formed of a plurality of memory cells arranged in rows and columns, wherein at least one first memory cell storing data is arranged in a first column and can be coupled to a first bit line; A first circuit branch is associated with the first bit line and has: a first node coupled to the first bit line; Second node; Output node; a switch component configured to selectively couple the first node to the first memory cell and the first bit line to the output node; a comparator stage having a first input coupled to the output node, a second input coupled to a reference voltage, and an output providing an output signal indicative of data stored in the first memory cell; a first connection switch configured to selectively couple the first node to the second node; as well as a second connecting switch configured to selectively couple the second node to the output node, a current source controllable to inject into the first bit line a drift current having a value higher than a current passing through the first memory cell when the first memory cell is in a first programmed state and lower than a current passing through the first memory cell when the first memory cell is in a second programmed state; as well as a control unit configured to control the switch component during reading of the first memory cell so that: In the precharging step, when the first memory cell is disabled, the first bit line is precharged with a line precharge voltage, the first node and the second node are precharged with corresponding precharge voltages, and the current source is deactivated and does not provide the drift current; In the characteristic drifting step, when the first memory cell is enabled and connected to the first bit line, the first bit line is decoupled from the output node, the second connection switch decouples the second node from the output node, and the current source is activated and provides the drift current to the first bit line, so that the first bit line is charged or discharged based on the stored data; as well as In the detection step, the current source is deactivated, the second connection switch connects the second node to the output node, and the switch section connects the first bit line to the output node.

2. The apparatus of claim 1 , further comprising a first capacitor coupled to the first node and a second capacitor coupled to the output node; The control unit is configured such that, in a sharing step after the characteristic drift step and before the detection step, the first memory unit is decoupled from the first node, the current source is deactivated, and the second node is coupled to the output node to cause charge sharing between the first capacitor and the second capacitor.

3. The apparatus of claim 2, wherein the memory array comprises second memory cells storing data, the second memory cells being arranged in a second column and being coupleable to a second bit line different from the first bit line, the apparatus further comprising: a second circuit branch associated with the second bit line and having: a third node coupled to the second bit line; Fourth node; and a reference node coupled to said second input of said comparator stage; a third connection switch, arranged between the third node and the fourth node; a fourth connection switch, arranged between the fourth node and the reference node; as well as A coupling stage comprises a first coupling switch which can be controlled by the control unit to couple the output node and the reference node in an equalization step after the precharging step and before the characteristic drifting step, and to decouple the output node and the reference node in the characteristic drifting step and the detection step.

4. The apparatus of claim 3 , wherein the coupling stage further comprises a second coupling switch controllable by the control unit to couple the second node and the fourth node of the first circuit branch and the second circuit branch during the equalizing step, and to decouple the second node and the fourth node during the characteristic shifting step and the sharing step.

5. The apparatus of claim 4 , wherein the coupling stage further comprises a third coupling switch, which is controllable by the control unit to couple the first node and the third node of the first circuit branch and the second circuit branch during the equalizing step, and to decouple the first node and the third node during the characteristic shifting step and the sharing step.

6. The device of claim 3 , wherein the first bit line comprises a first global bit line and a first local bit line; and the first circuit branch further comprises a fifth connection transistor, the fifth connection transistor having a first terminal coupled to the first local bit line, a second terminal coupled to the first global bit line, and a control terminal for receiving a first local decoding signal from the control unit, wherein the fifth connection transistor is controllable by the control unit so as to couple the first local bit line to the first global bit line in the precharging step, the equalizing step, and the characteristic shifting step, and to decouple the first local bit line from the first global bit line in the sharing step.

7. The apparatus of claim 6 , wherein the second bit line comprises a second global bit line and a second local bit line; and the second circuit branch further comprises a sixth connection transistor having a first terminal coupled to the second local bit line, a second terminal coupled to the second global bit line, and a control terminal for receiving a second local decoding signal from the control unit, wherein the sixth connection transistor is controllable by the control unit so as to keep the second memory cell closed during reading of the first memory cell.

8. The apparatus of claim 7, wherein the first global bit line and the second global bit line are adjacent.

9. The device of claim 1, wherein the memory cell is a phase change memory cell.

10. The apparatus of claim 1, wherein the current source is selectively coupled to the second node.

11. A method for reading a memory cell of a nonvolatile memory device, the nonvolatile memory device having: a memory array formed of a plurality of memory cells arranged in rows and columns, wherein at least one first memory cell storing data is arranged in a first column and can be coupled to a first bit line; A first circuit branch associated with the first bit line and having: a first node coupled to the first bit line; Output node; a second node inserted between the first node and the output node; and a current source controllable to inject a drift current in the first bit line, the drift current having a value higher than a current passing through the first memory cell when the first memory cell is in a first programmed state and lower than a current passing through the first memory cell when the first memory cell is in a second programmed state, The method comprises: a precharging step, wherein the first memory cell is disabled, the first bit line is precharged with a line precharge voltage, the first node and the second node are precharged with respective first voltage values, and the current source is deactivated and does not provide the drift current; a characteristic drifting step, wherein the first memory cell is enabled and connected to the first bit line, the first bit line is decoupled from the output node, the second node is decoupled from the output node, and the current source provides the drift current to the first bit line, and wherein based on the stored data, the first bit line becomes to have a drifted voltage that is lower or higher than the precharge line voltage; and A detection step wherein the drift current is interrupted, the first bit line is connected to the output node, the second node is coupled to the output node, and the drifted voltage is compared to a reference voltage. The method of claim 11 , wherein the drift current is a constant current.

13. The method according to claim 11 further includes a sharing step after the characteristic drift step and before the detection step, wherein the first memory cell is decoupled from the first node, the current source is deactivated, and the first node and the second node are coupled together to generate charge sharing between a first capacitor coupled to the first node and a second capacitor coupled to the second node.

14. The method according to claim 13, wherein in the sharing step, when the stored data is logic "1", the second voltage value on the first node is lower than the first voltage value on the first node; and When the stored data is logic “0”, the second voltage value on the first node is higher than the first voltage value on the first node.

15. The method of claim 11, wherein the memory array includes second memory cells storing data, the second memory cells being arranged in a second column and being coupleable to a second bit line different from the first bit line, and the apparatus further comprises a second circuit branch associated with the second bit line and having a third node coupled to the second bit line, a fourth node selectively coupleable to the third node, and a reference node selectively coupleable to the fourth node and coupled to a second input of a comparator stage to provide the reference voltage; The method further comprises: an equalization step after the precharging step and before the characteristic shifting step, wherein the output node and the reference node are coupled together and reach the same voltage value, wherein in the characteristic drift step, the output node and the reference node are decoupled from each other; as well as During the detection step, the voltage at the output node and the voltage on the reference node are compared. 16 . The method of claim 15 , wherein in the equalizing step, the first node and the third node are coupled together and brought to the same voltage, and the second node and the fourth node are coupled together and brought to the same voltage.

17. A non-volatile memory device comprising: a memory array formed of a plurality of memory cells arranged in rows and columns, wherein at least one first memory cell storing data is arranged in a first column and can be coupled to a first bit line; A first circuit branch is associated with the first bit line and has: a first node coupled to the first bit line; Second node; Output node; as well as a switch configured to selectively couple the first node to the first memory cell and the first bit line to the output node; a first connection switch configured to selectively couple the first node to the second node; as well as a second connecting switch configured to selectively couple the second node to the output node; a comparator stage having a first input coupled to the output node, a second input coupled to a reference voltage, and an output providing an output signal indicative of data stored in the first memory cell; a current source controllable to inject into the first bit line a drift current having a value higher than a current passing through the first memory cell when the first memory cell is in a first programmed state and lower than a current passing through the first memory cell when the first memory cell is in a second programmed state; as well as a control unit configured to control the switch, wherein the control unit is configured to provide: a precharge operation mode in which the first memory cell is disabled, the first bit line is precharged with a line precharge voltage, the first node and the second node are precharged with respective precharge voltages, and the current source is deactivated and does not provide the drift current; a characteristic drift operation mode, wherein the first memory cell is enabled and connected to the first bit line, the first bit line is decoupled from the output node, the second connection switch decouples the second node from the output node, and the current source is activated and provides the drift current to the first bit line, so that the first bit line is charged or discharged based on the stored data; as well as An operation mode is detected in which the current source is deactivated, the second connection switch connects the second node to the output node, and the switch connects the first bit line to the output node.

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