Integrated Metal Spacer and Air Gap Interconnect

Abstract

Embodiments described herein relate to methods of forming air gap interconnects. A metal spacer layer is conformally deposited on a substrate having a mandrel structure formed thereon. The metal spacer layer is etched to form a spacer feature and the mandrel structure is removed from the substrate. A variety of other dielectric deposition, patterning, and etching steps may be performed to desirably pattern the material present on the substrate. Finally, a trench is formed between adjacent spacer features and a cap layer is deposited over the trench to form an air gap between adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent to the air gap.

Description

[0001] This application is a divisional application of the invention patent application with application date of March 3, 2015, application number "201580022152.4", and invention name "Integrated Metal Spacer and Air Gap Interconnection". Technical Field

[0002] Embodiments described herein generally relate to methods for forming semiconductor devices having air gaps. More specifically, embodiments described herein relate to integrated metal spacers and air gap interconnects. Background Art

[0003] For advanced node technologies, interconnect RC delay (switching performance) and power damping due to capacitance are important thresholds for device performance. Given the scaling performance limitations of conventional low-k materials in reducing dielectric constants (k values) (as a result of compromising mechanical strength and current leakage performance), a promising candidate for capacitance scaling includes the use of air gaps between metal lines. Air gaps have k values ​​close to 1.0, which helps reduce the overall effective k value in the component to an acceptable level. However, air gap integration requires additional processing steps, including exclusion mask lithography, dielectric recessing, liner deposition, dielectric deposition, dielectric chemical mechanical polishing (CMP), etc. These additional steps increase the cost of integrating air gaps and reduce the benefits and acceptance of air gap technology.

[0004] In addition, double patterning is often used instead of single print patterning to form air gaps. Some examples of double patterning include lithography-etch-lithography-etch (LELE) and spacer alignment double patterning (SADP). These double patterning techniques not only require additional exposure and etching processes, but also require masks to define connectors and terminals. The double patterning process transfers the desired design to the final product, but it is done at an increased cost and reduced efficiency.

[0005] Therefore, what is needed is an improved method for forming airgap interconnect structures. Summary of the invention

[0006] In one embodiment, a method of forming a semiconductor device is provided. The method includes conformally depositing a metal spacer layer on a mandrel structure and etching at least a portion of the metal spacer layer to form one or more spacer features. The mandrel structure is removed, a dielectric layer is deposited on the spacer features, and the dielectric layer is patterned and etched between adjacent spacer features. A cap layer is then non-conformally deposited on the spacer features to form air gaps between adjacent spacer features.

[0007] In another embodiment, a method for forming a semiconductor device is provided. The method includes conformally depositing a metal spacer layer on a mandrel structure and etching at least a portion of the metal spacer layer to form one or more spacer features. The mandrel structure is removed, a flowable dielectric layer is deposited on the metal spacer layer, and a first region of the flowable dielectric layer is patterned. Then, at least one of the spacer features and the flowable dielectric layer are etched to form a first groove, and the flowable dielectric layer is redeposited in the first groove. A second region of the flowable dielectric layer is patterned and etched between adjacent spacer features to form a second groove. A cap layer is non-conformally deposited on the spacer features, the second groove, and the flowable dielectric layer to form an air gap in the second groove. Finally, the cap layer and at least a portion of the flowable dielectric layer are planarized.

[0008] In yet another embodiment, a method for forming a semiconductor device is provided. The method includes providing a substrate having an oxide mandrel structure formed thereon and conformally depositing a metal spacer layer on the oxide mandrel structure. Etching at least a portion of the metal spacer layer to form one or more spacer features. Etching the mandrel structure, depositing a flowable dielectric layer on the metal spacer layer, and patterning a first region of the flowable dielectric layer. Etching at least one of the spacer features and the flowable dielectric layer in the first region to form a first trench, and redepositing the flowable dielectric layer in the first trench. Patterning a second region of the flowable dielectric layer, and etching the flowable dielectric layer between adjacent spacer features in the second region to form a second trench. Depositing a silicon-containing cap layer on the spacer features, the second trench, and the flowable dielectric layer to form an air gap in the second trench. Grinding the cap layer and at least a portion of the flowable dielectric layer to form a planarized surface, and an interconnect is formed through the substrate to at least one of the spacer features adjacent to the air gap. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Therefore, in order to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more particular description of the present disclosure, briefly summarized above, may be derived with reference to certain embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings depict only typical embodiments of the present disclosure and are therefore not to be considered as limiting the scope of the present disclosure, as the present disclosure may admit of other equally effective embodiments.

[0010] Figure 1-15 is a schematic cross-sectional view of a substrate depicting a sequence for forming an airgap interconnect according to one embodiment disclosed herein.

[0011] Fig.16 is a schematic plan view of an apparatus that can be used to perform the various processes described herein.

[0012] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

[0013] [Example]

[0014] Embodiments described herein relate to methods of forming air gap interconnects. A metal spacer layer is conformally deposited on a substrate having a mandrel structure formed thereon. The metal spacer layer is etched to form a spacer feature and the mandrel structure is removed from the substrate. A variety of other dielectric deposition, patterning, and etching steps may be performed to desirably pattern the material present on the substrate. As a result of the processing sequence, trenches are formed between adjacent spacer features and a cap layer is deposited over the trenches to form an air gap between adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent to the air gap.

[0015] The formation sequence described in detail below depicts partial views of a semiconductor device at various stages of fabrication. In addition to forming air gap interconnects, it is contemplated that the method described below may be used to form air gaps implemented in other interconnect technologies. The sequence described below provides one embodiment of forming air gap interconnects, however, it should be understood that the formation sequence of the various operations may be rearranged, deleted, repeated, or performed in any combination of the foregoing.

[0016] Figure 1 A schematic cross-sectional view of a device structure 100 is depicted. The device structure 100 includes a substrate 102 and one or more mandrel structures 104 formed on the substrate 102. In one embodiment, the substrate 102 includes an etch stop layer and can be formed of a variety of materials such as SiN, SiCN, SiOC, SiON, Si, C, O, N, metal nitrides (e.g., AlN), and combinations thereof. The mandrel structures 104 are spaced apart from one another to define a template for subsequently deposited materials. The mandrel structures 104 are formed of an oxide or a silicon-containing material. For example, the mandrel structures 104 can be formed of silicon dioxide or polysilicon.

[0017] Figure 2 1 is a schematic cross-sectional view of a device structure 100 depicting the result of a metal deposition process. A metal spacer layer 106 is conformally deposited on the substrate 102 and the mandrel structure 104. Examples of materials used for the metal spacer layer 106 include tungsten by metal organic chemical vapor deposition (MOCVD), metal silicide by physical vapor deposition (PVD), and metal silicide by chemical vapor deposition (CVD). Examples of suitable metal silicide materials include cobalt silicide, titanium silicide, nickel silicide, and combinations thereof.

[0018] The metal spacer material may be selected so that the metal spacer 106 reacts with the mandrel structure 104 material to form the final metal wiring of the device structure 100. After the metal spacer 106 has been deposited, a post-deposition silicidation process may be performed to promote the metal spacer 106 / mandrel structure 104 reaction. The resulting mandrel structure 104 maintains dielectric properties while the metal spacer 106 is formed as a low resistivity conductor.

[0019] Examples of suitable mandrel structure materials and metal spacer material combinations include oxide / MOCVD tungsten, polysilicon / MOCVD tungsten and oxide or silicon / silicide. The metal spacer material may also include nickel, cobalt, tungsten, etc. The metal spacer layer 106 deposited conformally on the mandrel structure 104 forms the metal interconnect wiring, thereby reducing or eliminating the necessity of conventional metal gap filling in conventional air gap interconnect technology. Furthermore, the patterning process described in more detail below is performed directly on the final metal wiring (metal spacer layer 106), which reduces or eliminates the necessity of the pattern transfer (etching) step for air gap interconnect formation.

[0020] Figure 3 is a schematic cross-sectional view of the device structure 100 depicting the result of the etching process. The metal spacer layer 106 is anisotropically etched to remove several portions of the metal spacer layer 106. In one example, an anisotropic dry plasma etching process can be applied. If the metal spacer layer 106 includes tungsten, then a CF4 dry plasma can be applied to etch the metal spacer layer 106. In this example, in an environment having a pressure between about 10mT and about 50mT, a CF4 precursor gas can be flowed at a rate between about 50sccm and about 200sccm. The CF4 can be excited into a plasma with an RF power between about 200W and about 400W and a bias between about 100W and about 500W. An example of a process chamber that can be used to perform the etching process described is a MESA 1000 available from Applied Materials, Inc. of Santa Clara, California. TM However, it is contemplated that other similarly configured chambers from other manufacturers may also perform the described processes.

[0021] As a result of the etching process, at least a portion of the metal spacer layer 106 is removed to expose the top surface 108 of the mandrel structure 104 and the surface 110 of the substrate 102. The etching of the metal spacer layer 106 can be time-dependent or endpoint-controlled so that the remaining portion of the metal spacer layer 106 is coplanar with the top surface 108 of the mandrel structure 104. After etching the metal spacer layer 106, the previously continuous metal spacer layer 106 now includes separated discontinuous structures. These structures may be referred to as spacer features 106. The term spacer feature 107 used subsequently herein refers to the same material as the metal spacer layer 106, however, the spacer feature 107 is the etched form of the metal spacer layer 106.

[0022] Figure 4 1 is a schematic cross-sectional view of the device structure 100 depicting the result of the etching process. The mandrel structure 104 is etched using a selective etching process that does not react with the metal material of the spacer feature 107. In one embodiment, a wet etching process using a dilute HF solution is used to etch the mandrel structure 104. The wet etching process can be performed for a period of time sufficient to completely remove the mandrel structure 104 from the substrate 102. In another embodiment, an anisotropic dry etching process using NF3 and NH3 can be used to remove the mandrel structure 104. In this example, the NF3 precursor gas can be flowed at a rate between about 10 sccm and about 200 sccm and the NH3 precursor gas can be flowed at a rate between about 100 sccm and about 1000 sccm in an environment having a pressure between about 200 mTorr and about 3000 mTorr. The NF3 and NH3 can be excited into a plasma with an RF power between about 200 W and about 2000 W. The resulting device structure 100 includes spacer features 107 separated from one another by the exposed surface 110 of the substrate 102 . Figures 1 to 4 The patterning of the metal spacer layer 106 is completed by the process described in .

[0023] Figure 5 1 is a schematic cross-sectional view of a device structure 100 depicting the result of a flowable CVD deposition process. As shown, a dielectric layer 112 is deposited on the device structure 100 and on the substrate 102 and the spacer features 107 by a flowable or flow-like CVD process. The dielectric layer 112 is deposited in a blanket manner so that the dielectric layer 112 fills the space between adjacent spacer features 107 and contacts the substrate 102. Due to the characteristics of the flowable dielectric layer 112, voids in the dielectric layer 112 are minimized or eliminated and the top surface of the dielectric layer 112 is substantially flat. The dielectric layer 112 is deposited with a thickness configured to extend above the spacer features 107.

[0024] In one example of a flowable CVD process, an organosilicon precursor is reacted with an oxygen precursor at a temperature of about 100° C. or less to form dielectric layer 112. Suitable organosilicon precursors have a carbon atom to silicon atom ratio of less than about 8. Suitable organosilicon compounds may also have an oxygen to silicon atom ratio of about 0 to about 6 and may include Si-O-Si bonds that promote the formation of SiO with reduced contaminants from carbon and hydroxyl groups. x film. Suitable oxygen precursors may include molecular oxygen (O2), ozone (O3), nitrogen-oxygen compounds (such as NO, NO2, or N2O), hydrogen-oxygen compounds (such as water or peroxide), carbon-oxygen compounds (such as carbon monoxide or carbon dioxide), and other oxygen-containing precursors. In one embodiment, dielectric layer 112 includes SiOCH and has a k value between about 2.0 and about 3.0.

[0025] A carrier gas (e.g., an inert gas) may also be provided with the organosilicon and oxygen precursors. The oxygen precursor may be activated prior to being introduced into the chamber, for example using a remote plasma generator, which may include thermal dissociation, ultraviolet light dissociation, RF, DC, and / or microwave dissociation. In one embodiment, 4-6 kW of RF power may be coupled to a flow of 900-1,800 sccm of argon and 600-1,200 sccm of oxygen molecules. The organosilicon precursor may be provided to the chamber separately from the oxygen precursor to avoid reaction outside the chamber. The organosilicon precursor may be introduced into the chamber as a gas at a liquid-equivalent flow rate of about 800 mgm to about 1,600 mgm. Helium may be included as a carrier gas at a flow rate of about 600 sccm to about 2,400 sccm. The activated oxygen precursor may be introduced into the chamber at a flow rate between about 3 sLm and about 20 sLm.

[0026] The precursors react to deposit a flowable oxide layer or dielectric layer 112 on the substrate 102. The CVD process described above can be performed on a CVD process available from Applied Materials, Inc. in Santa Clara, California. ETERNA TM However, it is contemplated that other similarly configured chambers from other manufacturers may also perform the described processes.

[0027] Figure 61 is a schematic cross-sectional view of device structure 100 depicting the results of the mask formation and patterning process. A first mask 114, such as a photoresist material, is deposited on dielectric layer 112 and then patterned. First mask 114 may be a photopolymer material that is blanket deposited on dielectric layer 112. First mask 114 is patterned to form exposed first regions 116. In one embodiment, a 193 nm immersion lithography process is used to pattern first mask 114 and expose first regions 116. First mask 114 in first regions 116 is removed and dielectric layer 112 is exposed. In one embodiment, at least one of spacer features 107 is included below first region 116. In one example, first region 116 defines a terminal that is subsequently removed from device structure 100.

[0028] Figure 7 is a schematic cross-sectional view of the device structure 100 depicting the result of the terminal removal process. An anisotropic etching process may be applied to remove the first region 116 (see Figure 6 ) in order to form the first trench 117. A variety of etching techniques may be applied, including wet etching and dry plasma etching techniques. In this example, one or more etchants are applied to remove the dielectric layer 112 and the spacer features 107 in the first region 116 to form the first trench 117. For example, a single etchant that can remove both the dielectric layer 112 and the spacer features 106 in the first region 116 or multiple etchants that are selective to the dielectric layer 112 or the spacer features 107 may be applied to form the first trench 117. The bottom of the first trench 117 is defined by the surface 110 of the substrate 102, and the sidewalls of the first trench 117 are defined by the dielectric layer 112. By removing the spacer features 107 in the first region 116, the wiring terminals of the device structure 100 are formed to create the desired wiring structure, and further processing may be performed.

[0029] Figure 8 1 is a schematic cross-sectional view of the device structure 100 depicting the result of the mask removal process. As shown, the first mask 114 has been removed to expose the dielectric layer 112. The first mask 114 can be removed by a variety of methods, including ashing or etching the first mask 114. For example, the first mask 114 is removed via a wet cleaning process that is selective to the material of the dielectric layer 112.

[0030] Fig. 9 is a schematic cross-sectional view of a device structure 100 depicting the result of a flowable dielectric deposition process. Figure 5 In the process shown, the first trench 117 is filled with the flowable dielectric layer 112. The resulting dielectric layer 112 has similar characteristics to the dielectric layer 112 as originally deposited.

[0031] Fig.10 1 is a schematic cross-sectional view of the device structure 100 depicting the results of the mask formation and patterning process. A second mask 118 (which may be formed in a manner similar to the first mask 114) is deposited on the dielectric layer 112 and patterned to expose the second region 120. The second mask 118 may protect the previously exposed first region 116 and the subsequently deposited dielectric layer 112 filling the first trench 117. The patterning of the second mask 118 is performed in a manner similar to the patterning of the first mask 114. In one embodiment, the first mask 114 and the second mask 118 may be separate masks or the same mask. If the first mask 114 and the second mask 118 form a single mask, the photolithography process is performed in a reverse tone resist so that the protected regions of the device structure 100 are complementary. The second region 120 exposes at least a portion of the dielectric layer 112 disposed on the adjacent spacer features 107.

[0032] Fig.11 1 is a schematic cross-sectional view of the device structure 100 depicting the result of the dielectric etching process. Here, the dielectric layer 112 in the second region 120 is etched to expose at least a portion of the adjacent spacer features 106 and the surface of the substrate 102. In this way, a second trench 121 is formed between the adjacent spacer features 106. The second trench 121 can have an aspect ratio between about 1.5:1.0 and about 5.0:1.0. The dielectric layer 112 is etched using a passivation dry plasma etching process. The etchant species utilized can exhibit a high selectivity between the dielectric layer 112 and the metal of the spacer features 106.

[0033] In one embodiment, C4F6 is utilized to etch the dielectric layer 112. In this example, the C4F6 precursor gas may be flowed at a rate of about 10 sccm in an environment having a pressure of about 200 mT. The C4F6 may be excited into a plasma with an RF power between about 100 W and about 2000 W and a bias between about 50 W and about 500 W. The etchant species is preferably selected to protect the exposed surface 122 of the spacer feature 107 when etching the dielectric layer 112. Similarly, the etchant species is selective to the substrate 102 and is selected to etch the dielectric layer 112. In one embodiment, a dielectric liner may be deposited to passivate the exposed surface 122 of the spacer feature 107. The dielectric liner may include materials such as Si, O, C, N, H, and combinations thereof.

[0034] Fig.12 1 is a schematic cross-sectional view of device structure 100 depicting the result of the mask removal process. As shown, second mask 118 is removed to expose dielectric layer 112. Second mask 118 may be removed by a process similar to that used to remove first mask 114.

[0035] Fig.13 1 is a schematic cross-sectional view of the device structure 100 depicting the result of the cap layer deposition process. A cap layer 124 is deposited on the device structure 100 and on the exposed surface 122 of the spacer feature 107 adjacent to the second trench 121 (see Fig.12 ) is on at least a portion of the dielectric layer 112. The cap layer 124 includes a low-k silicon-containing material. For example, the cap layer 124 material may include SiOC, SiOCN, SiCN, etc.

[0036] In one embodiment, SiOC is used as the cap layer 124. In this example, the organic silicon-containing precursor gas may be flowed at a rate between about 50 sccm and about 500 sccm and the oxygen-containing precursor may be flowed at a rate between about 200 sccm and about 1000 sccm in an environment having a pressure between about 1000 mT and about 3000 mT. The precursors may be excited into a plasma with an RF power between about 500 W and about 2000 W. In one example, the cap layer 124 deposition is a blanket deposition process related to the surface curvature that bridges the second trench 121. The deposition process may be a time-dependent CVD process.

[0037] The cap layer 124 deposition is configured to deposit material in a portion of the second trench 121. As such, the cap layer 124 may completely cover the top exposed surface 122 of the spacer feature 106 adjacent to the second trench 121, and only cover a portion of the sidewall exposed surface 122 of the spacer feature 106 adjacent to the second trench 121. The cap layer 124 deposition process is configured to prevent the cap layer 124 from being deposited on the surface 110 of the substrate 102. Thus, an air gap 123 is formed in the second trench 121 between adjacent spacer features 107. The air gap 123 may be defined by the adjacent spacer features 107, the substrate 102, and the cap layer 124. The air gap 123 is substantially free of any material other than air.

[0038] Fig.14 is a schematic cross-sectional view of a device structure depicting the results of a CMP process. The previously deposited dielectric layer 112 and cap layer 124 may have non-uniform thicknesses across the surface of the device structure 100. A CMP process or other planarization process is performed to planarize the top surface of the device structure 100 so that the spacer features 106, the dielectric layer 112, and the cap layer 124 are substantially coplanar. In one embodiment, the spacer features 107 may be applied as a hard stop to determine the planarization / polishing endpoint. The CMP process may be performed on a REFLEXION GT available from Applied Materials, Inc. of Santa Clara, California. TM System or other compatible CMP system. Planarization systems from other manufacturers may also be used to perform the process.

[0039] The CMP process results in the device structure 100 having a planarized upper surface and having a remaining cap layer 124 portion disposed in the upper portion of the second trench 121 to define an air gap 123 thereunder. The CMP process can be performed only once in this air gap integration scheme, thereby eliminating the necessity of multiple CMP processes of metal CMP and dielectric CMP in the conventional air gap integration scheme.

[0040] Fig.15 1 is a schematic cross-sectional view of device structure 100 depicting the result of an interconnect formation process. Interconnect 126 is formed through at least one of the conductive spacer features 107 through substrate 102 to adjacent air gap 123. A through hole (not shown) may be formed by an etching or ablation process, and the resulting through hole may be filled with an interconnect material. Interconnect 126 may be a conductive material such as a metal or metal silicide and may be deposited by a variety of processes including CVD, PVD, atomic layer deposition (ALD), and epitaxial deposition, among others. Interconnect 126 electrically connects spacer feature 107 to other components of the semiconductor device and may be used during semiconductor packaging processes.

[0041] Fig.16 2 is a schematic plan view of an apparatus 200 that can be used to perform various processes described herein. The apparatus 200 includes a substrate handling portion 202 and a substrate processing portion 204. The substrate handling portion 202 includes a loading station 206, a transfer station 208, and an interface station 210. The substrate is loaded into the apparatus 200 at the loading station 206. In some examples, the loading operation may include setting one or more substrates on a carrier for transfer through the apparatus 200. The transfer station 208 moves the substrate from the loading station 206 to the interface station 210. If desired, the transfer station 208 may include substrate handling features (such as fins). The interface station 208 provides the substrate to an entry load lock chamber 212 for entry into the substrate processing portion 204, which is typically operated under vacuum. The substrate processing portion 204 includes a plurality of substrate processing chambers 216 coupled to a transfer chamber 220, in which a transfer robot 218 is disposed. Each of the processing chambers 216 may be an ALD chamber, a low temperature CVD chamber, a high density plasma CVD chamber, a PECVD chamber, an etching chamber, or a plasma cleaning chamber. In one embodiment, the chamber 216 includes a plasma CVD chamber for forming a flowable dielectric layer and a plasma etching chamber for etching a silicon layer, an oxide layer, and / or a metal layer. The plasma CVD chamber may be an HDP CVD chamber, and the plasma etching chamber may be a remote plasma chamber. The exit load lock chamber 214 receives the processed substrate to be transferred back to the substrate handling portion 202.

[0042] In embodiments featuring multiple substrates disposed on a substrate carrier for processing, each of the processing chambers 216 may process multiple substrates at the same time. When the apparatus 200 is used to practice the methods described above, any or all processes may be performed on multiple substrates simultaneously.

[0043] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope of the disclosure, which is determined by the claims that follow.

Claims

1. A method for forming a semiconductor device, the method comprising: conformally depositing a metal spacer layer on the mandrel structure on the substrate; etching at least a portion of the metal spacer layer to form a metal spacer-containing feature; removing the mandrel structure; depositing a dielectric layer over the metal-containing spacer features; patterning the dielectric layer; etching the dielectric layer between adjacent metal-containing spacer features; and A capping layer is deposited over the metal-containing spacer features, wherein air gaps are formed between adjacent metal-containing spacer features. 2 . The method of claim 1 , wherein the metal spacer layer comprises tungsten or a metal silicide material.

3. The method of claim 1, wherein the metal spacer layer is selected from the group consisting of tungsten, cobalt, and nickel. The method of claim 2 , wherein the tungsten is deposited by a MOCVD process. The method of claim 1 , wherein the dielectric layer is deposited by a flowable CVD process.

6. The method of claim 5, wherein the dielectric layer comprises SiOCH and has a dielectric constant between 2.0 and 3.

0.

7. The method of claim 1 wherein adjacent metal-containing spacer features define a trench having an aspect ratio between 1.5:1 and 5:

1. The method of claim 7 , wherein an upper region of the trench is defined by the cap layer.

9. The method of claim 8, wherein the cap layer comprises a silicon-containing material.

10. A method for forming a semiconductor device, the method comprising: forming a silicon-containing mandrel structure on a substrate; conformally depositing a metal spacer layer on the silicon-containing mandrel structure; etching at least a portion of the metal spacer layer to form a spacer feature on the substrate; removing the silicon-containing mandrel structure; depositing a flowable dielectric layer over the spacer features; patterning the flowable dielectric layer; etching the flowable dielectric layer between adjacent spacer features to form trenches; depositing a capping layer over the spacer features, the trenches, and the flowable dielectric layer, wherein an air gap is formed in the trenches; as well as The cap layer and at least a portion of the flowable dielectric layer are planarized.

11. The method of claim 10, further comprising forming an interconnect to at least one of the spacer features adjacent to the air gap.

12. The method of claim 10, wherein planarizing comprises a dielectric CMP process.

13. The method of claim 12, wherein the spacer feature defines an endpoint for the planarization.

14. The method of claim 10, wherein the capping layer extends into the trench and below a top surface of the spacer feature. The method of claim 14 , wherein the cap layer comprises a silicon-containing material.

16. The method of claim 10, wherein the trench has an aspect ratio between 1.5:1 and 5:

1.

17. A method of forming a semiconductor device, the method comprising: positioning a substrate having metal-containing spacer features formed thereon in a first processing chamber; depositing a dielectric layer over the metal-containing spacer features; etching at least one of the metal-containing spacer features and the dielectric layer in a first region to form a first trench; etching the dielectric layer between adjacent metal-containing spacer features in a second region to form a second trench; depositing a capping layer over the metal-containing spacer feature, the second trench, and the dielectric layer, wherein an air gap is formed in the second trench; and planarizing at least a portion of the cap layer and the dielectric layer, The metal-containing spacer feature is formed on the substrate by the following steps: conformally depositing a metal spacer layer on the mandrel structure on the substrate; etching at least a portion of the metal spacer layer to form the metal-containing spacer feature; The mandrel structure is removed.

18. The method of claim 17, further comprising: An interconnect is formed through the substrate to at least one of the metal-containing spacer features adjacent the air gap.

Images