Wiring structures, electronic devices and their manufacturing methods

Abstract

A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening through the insulating layer. The conductive structure is located in the opening of the insulating layer and includes a first barrier layer and a wetting layer. The first barrier layer is located on a sidewall of the opening of the insulating layer and defines a perforation through the first barrier layer. The wetting layer is located on the first barrier layer. A portion of the wetting layer is exposed from the perforation of the first barrier layer and the lower surface of the insulating layer to form a ball-shaped pad.

Description

Technical Field

[0001] The present invention relates to wiring structures, electronic devices, and manufacturing methods, and specifically to a wiring structure in which a portion of a wetting layer is exposed from a barrier layer to form a ball pad, an electronic device comprising the wiring structure, and a method for manufacturing the electronic device. Background Technology

[0002] In radio frequency (RF) die packaging, redistribution layer (RDL) structures are used to couple with the RF die. Due to impedance matching issues, such RDL structures are typically designed with five passivation layers and five metal layers (5P5M). The fabrication process for a structure with one passivation layer and one metal layer (1P1M) typically takes about 10 days; therefore, the fabrication process for a 5P5M structure usually requires a total fabrication time of about 60 days. This results in higher manufacturing costs. Furthermore, the greater thickness of such 5P5M structures makes them prone to warpage and / or delamination problems. Summary of the Invention

[0003] In some embodiments, a wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite the upper surface, and defines an opening through the insulating layer. The conductive structure is located in the opening of the insulating layer and includes a first barrier layer and a wetting layer. The first barrier layer is located on a sidewall of the opening of the insulating layer and defines a through-hole through the first barrier layer. The wetting layer is located on the first barrier layer. A portion of the wetting layer is exposed from the lower surface of the first barrier layer and the lower surface of the insulating layer to form a ball pad.

[0004] In some embodiments, an electronic device includes a first insulating layer, a lower conductive structure, and at least one electrical connecting element. The first insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines a first opening through the first insulating layer. The lower conductive structure includes a lower circuit structure located in the first opening of the first insulating layer. The lower circuit structure includes a plurality of metal layers. The lower circuit structure includes a bonding region and an extending region. The number of metal layers in the bonding region differs from the number of metal layers in the extending region. The electrical connecting element is attached to the bonding region of the lower conductive structure.

[0005] In some embodiments, a method for manufacturing an electronic device includes: forming a first opening through a first insulating layer; forming a lower seed layer in the first opening and on the insulating layer; sequentially forming a first barrier layer, a wetting layer, and a second barrier layer on the seed layer to form a lower circuit structure; etching a portion of the first barrier layer to expose a portion of the wetting layer; and attaching at least one electrical connection element to the exposed portion of the wetting layer. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of some embodiments of this disclosure will be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 Cross-sectional views illustrating examples of electronic devices according to some embodiments of the present disclosure.

[0008] Figure 2 illustrate Figure 1 An enlarged view of area "A" shown in the image.

[0009] Figure 3 Cross-sectional views illustrating examples of electronic devices according to some embodiments of the present disclosure.

[0010] Figure 4 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0011] Figure 5 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0012] Figure 6 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0013] Figure 7 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0014] Figure 8 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0015] Figure 9 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0016] Figure 10 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0017] Figure 11 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0018] Figure 12 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0019] Figure 13 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0020] Figure 14 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0021] Figure 15 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0022] Figure 16 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0023] Figure 17 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0024] Figure 18 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0025] Figure 19 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0026] Figure 20 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0027] Figure 21 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0028] Figure 22 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0029] Figure 23 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0030] Figure 24 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0031] Figure 25 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0032] Figure 26 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0033] Figure 27 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0034] Figure 28 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0035] Figure 29 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0036] Figure 30 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0037] Figure 31 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0038] Figure 32 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0039] Figure 33This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0040] Figure 34 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure. Detailed Implementation

[0041] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the detailed description taken in conjunction with the accompanying drawings.

[0042] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of the invention. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, embodiments in which a first feature is formed on or on a second feature may include instances where the first and second features are formed or disposed in direct contact, and embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0043] In packages containing RF dies, redistribution structures can be used to couple with the RF die. Due to impedance matching issues, such redistribution structures are typically designed as 5P5M structures. A comparative manufacturing process for such a 5P5M structure includes providing a carrier on which a seed layer (or metal release film) is disposed; forming a first passivation layer (P1) with a first through-hole on the seed layer; forming a first metal layer (M1) on P1 and in the first through-hole; forming a second passivation layer (P2) with a second through-hole on P1 and covering M1; forming a second metal layer (M2) on P2 and in the second through-hole to electrically connect M1; and then sequentially forming a third passivation layer (P3), a third metal layer (M3), a fourth passivation layer (P4), a fourth metal layer (M4), a fifth passivation layer (P5), and a fifth metal layer (M5) in a similar manner.

[0044] M1 is used solely for external connectivity. The portion of M1 within the first perforation penetrates P1 and is exposed from P1 to form a ball pad. The area of ​​the first perforation may be slightly larger than the area of ​​the second perforation, and the second perforation is located directly above the first perforation. The portion of M2 within the second perforation of P2 forms a conductive via, which is located on the ball pad of M1, forming a "via-on-via" structure. The uneven structure of P1 and M1 surrounding the first perforation causes insufficient exposure and development of the photoresist used to form the conductive via of M2. Therefore, the yield of the re-laid layer structure is low. Similarly, M5 is an under-bump metallization (UBM) layer used solely for external connectivity.

[0045] After forming the 5P5M structure, at least one semiconductor die is attached to the 5P5M structure, and an encapsulant is formed to cover the semiconductor die and the 5P5M structure. Next, the carrier is removed, and the seed layer (or metal release film) is removed by etching. A portion of M1 located in the first through-hole of P1 is exposed from P1 to form a ball pad, and electrical connection elements are connected to the ball pad for external connectivity. Then, a singulation process is performed to form multiple individual package structures.

[0046] During the fabrication of this type of 5P5M structure, each of the five metal layers is formed using a different patterned photoresist corresponding to its layout. Therefore, the fabrication process of this type of 5P5M structure requires five different photomasks. Furthermore, forming the passivation layer and metal layers typically takes about 10 days, so forming a 5P5M structure usually requires a total fabrication time of about 60 days. Therefore, the manufacturing cost is high. In addition, the relatively large thickness of this type of 5P5M structure makes it prone to warpage and delamination problems. Typically, each passivation layer adds approximately 100 μm to approximately 500 μm of warpage.

[0047] As described above, the ball pad is formed from M1, and its material is copper. The electrical connection element connected to the ball pad can be made of solder ball or solder paste, for example, by a solder ball mounting process or a solder paste printing process. The size of the solder ball is typically smaller than the size of the solder paste. However, since the solder ball is primarily composed of tin, an intermetallic compound (IMC) is prone to form at the solder joint boundary between the ball pad (made of copper) and the electrical connection element (made of tin). This IMC reduces the bonding strength between the ball pad and the solder ball. Increasing the thickness of M1 (e.g., greater than 8 μm) can compensate for the IMC effect, but this correspondingly increases the overall package thickness. Furthermore, with the increase in thickness, the gap between the extension of M1 on P1 and M2 decreases, thus easily leading to a short circuit between the extension of M1 and M2. Such a short circuit can be avoided by reducing the area of ​​the extension of M1 on P1. However, a reduced-area extension of M1 cannot provide sufficient support for the ball pad. When the electrical connector is attached to the ball pad, the weight of the electrical connector can cause M1 to delaminate.

[0048] On the other hand, the solder paste material has a lower tin content than the solder balls, thus preventing IMC (Integrated Molding Capacity) from forming between the pads and the electrical connectors. However, the solder paste printing process can only form electrical connectors larger than 250μm*250μm (due to the screen printing board opening size being larger than 250μm*250μm). Therefore, the size of the pads needs to be increased accordingly, which is detrimental to package layout.

[0049] This disclosure addresses at least some of the above-mentioned problems and provides an improved wiring structure, an improved electronic device, and an improved technique for manufacturing said electronic device. In said electronic device and similarly in said wiring structure, a redistribution layer (e.g., M2) is directly situated on a circuit structure (e.g., M1) to form a conductive structure, and a portion of the circuit structure is exposed from an insulating layer (P1) for external connection. The redistribution layer and the circuit structure are combined within the conductive structure and can be formed using the same photomask and / or the same patterned photoresist. The insulating layer (e.g., P2) can be omitted. Therefore, the cost of the manufacturing process can be reduced.

[0050] Figure 1 The illustration shows a cross-sectional view of an electronic device 1 according to some embodiments of the present disclosure. The electronic device 1 includes a first insulating layer 10, a lower conductive structure 2, at least one intermediate conductive structure 3, an upper conductive structure 4, a plurality of insulating layers (e.g., a second insulating layer 20, a third insulating layer 30, and a fourth insulating layer 40), a bump under-metallization layer 5, at least one semiconductor die 6, a package 16, and at least one electrical connection element 14.

[0051] The first insulating layer 10 has an upper surface 101 and a lower surface 102 opposite to the upper surface 101. The first insulating layer 10 defines a first opening 104 extending through the first insulating layer 10. The first opening 104 has sidewalls 103. The material of the first insulating layer 10 may include an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB) polymer or a polyimide (PI). In some embodiments, the first insulating layer 10 may include a curable photoimageable dielectric (PID) material, such as an epoxy resin or PI containing a photoinitiator. The thickness of the first insulating layer 10 may be about 7 μm.

[0052] The lower conductive structure 2 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. The lower conductive structure 2 includes a lower seed layer 21, a lower circuit structure 22 and a lower redistribution layer 23 sequentially located on the first insulating layer 10.

[0053] The lower seed layer 21 is located on the upper surface 101 of the first insulating layer 10 and on the sidewall 103 of the first opening 104 of the first insulating layer 10. The lower seed layer 21 is located between the first insulating layer 10 and the lower circuit structure 22. In some embodiments, the lower seed layer 21 is not exposed from the lower surface 102 of the first insulating layer 10. That is, the portion of the lower seed layer 21 adjacent to the lower surface 102 of the insulating layer 10 is removed or omitted. The material of the lower seed layer 21 may be titanium, copper, another metal, or an alloy. In some embodiments, such as Figure 1 As shown, the lower seed layer 21 comprises a titanium layer 211 and a copper layer 212. However, the lower seed layer 21 may comprise more or fewer layers, or may be omitted. The titanium layer is located on and in contact with the upper surface 101 of the first insulating layer 10 and the sidewall 103 of the first opening 104 of the first insulating layer 10. The copper layer 212 is located on and in contact with the titanium layer 211. The thickness of the titanium layer 211 may be about 0.1 μm, and the thickness of the copper layer 212 may be about 0.2 μm.

[0054] The lower circuit structure 22 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. For example... Figure 1 As shown, the lower circuit structure 22 is located on and completely covers the lower seed layer 21. The lower circuit structure 22 can contact the lower seed layer 21.

[0055] The lower circuit structure 22 includes multiple metal layers (e.g., a first barrier layer 24, a wetting layer 25, and a second barrier layer 26). The first barrier layer 24, the wetting layer 25, and the second barrier layer 26 are sequentially located on the lower seed layer 21. The first barrier layer 24 is located on the upper surface 101 of the first insulating layer 10 and on the sidewall 103 of the first opening 104 of the first insulating layer 10. The first barrier layer 24 is located on the lower seed layer 21 and can contact and completely cover the lower seed layer 21, such as the copper layer 212 of the lower seed layer 21. In some embodiments, the first barrier layer 24 is not exposed from the lower surface 102 of the first insulating layer 10. That is, the portion of the first barrier layer 24 adjacent to the lower surface 102 of the insulating layer 10 is removed or omitted.

[0056] A wetting layer 25 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. The wetting layer 25 is located on the first barrier layer 24 and can contact and completely cover the first barrier layer 24. Because portions of the lower seed layer 21 and the first barrier layer 24 adjacent to the lower surface 102 of the insulating layer 10 are removed or omitted, a portion 254 of the wetting layer 25 is exposed from the lower seed layer 21 and the first barrier layer 24 and from the lower surface 102 of the first insulating layer 10. The exposed portion 254 of the wetting layer 25 forms a ball pad for external connection.

[0057] The second barrier layer 26 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. The second barrier layer 26 is located on the wetting layer 25 and can contact and completely cover the wetting layer 25.

[0058] The lower circuit structure 22 includes a bonding region 22a and an extension region 22b. In some embodiments, each layer of the lower circuit structure 22 within the bonding region 22a and the extension region 22b may be formed concurrently and integrally as a monolithic structure. The bonding region 22a is exposed from the lower surface 102 of the first insulating layer 10 and includes an exposed portion 254 of the wetting layer 25 as a ball pad for external connection. Figure 1 As shown, since the portion of the first barrier layer 24 adjacent to the lower surface 102 of the insulating layer 10 is removed or omitted, the bonding region 22a comprises or consists of two metal layers, namely the wetting layer 25 and the second barrier layer 26. The bonding region 22a does not include the first barrier layer 24, and therefore the bonding region 22a is recessed from the lower surface 102 of the first insulating layer 10.

[0059] Extension region 22b connects to and extends from junction region 22a. Extension region 22b is located on the sidewall 103 of the first opening 104 of the first insulating layer 10, and on the upper surface 101 of the first insulating layer 10. Figure 1 As shown, the extension region 22b comprises or consists of three layers: a first barrier layer 24, a wetting layer 25, and a second barrier layer 26. Correspondingly, the number of metal layers in the bonding region 22a differs from the number of metal layers in the extension region 22b.

[0060] The materials of the first barrier layer 24 and the second barrier layer 26 may include nickel. The material of the wetting layer 25 may include gold. The thickness of the first barrier layer 24 may be about 1 μm, the thickness of the wetting layer 25 may be about 0.3 μm, and the thickness of the second barrier layer 26 may be about 3 μm. In some embodiments, the first barrier layer 24, the wetting layer 25, and the second barrier layer 26 may be formed by plating using the same photomask and / or the same patterned photoresist. Therefore, the peripheral wall 223 of the lower circuit structure 22 including the first barrier layer 24, the wetting layer 25, and the second barrier layer 26 is continuous. That is, the peripheral walls of the first barrier layer 24, the wetting layer 25, and the second barrier layer 26 are coplanar with each other.

[0061] The lower redistribution layer 23 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. The lower redistribution layer 23 is located on the lower circuit structure 22 and can contact and completely cover the lower circuit structure 22, such as the second barrier layer 26 of the lower circuit structure 22. The lower redistribution layer 23 may include at least one pad and at least one trace. The material of the lower redistribution layer 23 may include, for example, copper, another conductive metal, or an alloy thereof. The thickness of the lower redistribution layer 23 may be approximately 4.3 μm. The lower redistribution layer 23 can be formed by plating using the same photomask and / or the same patterned photoresist as the lower circuit structure 22. Therefore, the peripheral wall 233 of the lower redistribution layer 23 can be aligned with the peripheral wall 223 of the lower circuit structure 22. That is, the peripheral wall 233 of the lower redistribution layer 23 can be coplanar with the peripheral wall 223 of the lower circuit structure 22. The lower redistribution layer 23 can be conformal with the lower circuit structure 22. The layout of the lower redistribution layer 23 can be substantially the same as the layout of the lower circuit structure 22.

[0062] The second insulating layer 20 covers at least a portion of the first insulating layer 10 and the lower conductive structure 2. For example... Figure 1As shown, the second insulating layer 20 is located on the upper surface 101 of the first insulating layer 10. The second insulating layer 20 has an upper surface 201 and a lower surface 202 opposite to the upper surface 201. The second insulating layer 20 defines a second opening 204 through the second insulating layer 20 to expose a portion of the lower redistribution layer 23 of the lower conductive structure 2. The material of the second insulating layer 20 may include an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene polymer or a polyimide. In some embodiments, the second insulating layer 20 may include a cured photoimageable dielectric material, such as an epoxy resin or PI containing a photoinitiator. The thickness of the second insulating layer 20 may be about 9 μm.

[0063] The intermediate conductive structure 3 is located between the upper conductive structure 4 and the lower conductive structure 2. For example... Figure 1 As shown, the intermediate conductive structure 3 is located on the upper surface 201 of the second insulating layer 20. Figure 1 Only one intermediate conductive structure 3 is shown. However, the electronic device 1 may include more than one intermediate conductive structure 3. The intermediate conductive structure 3 extends into the second opening 204 of the second insulating layer 20 to form a conductive dielectric hole 38. That is, the conductive dielectric hole 38 of the intermediate conductive structure 3 penetrates the second insulating layer 20. The intermediate conductive structure 3 is electrically connected to the lower conductive structure 2 through the conductive dielectric hole 38.

[0064] The intermediate conductive structure 3 includes an intermediate seed layer 31 and an intermediate redistribution layer 32 sequentially located on the second insulating layer 20. The intermediate seed layer 31 may be made of titanium, copper, another metal, or an alloy. Figure 1 An intermediate seed layer 31 consisting of only one layer is shown. However, the intermediate seed layer 31 may contain more than one layer, or may be omitted. An intermediate redistribution layer 32 is located on the intermediate seed layer 31 and completely covers it. The intermediate redistribution layer 32 may contain at least one pad and at least one trace. The material of the intermediate redistribution layer 32 may include, for example, copper, another conductive metal, or an alloy thereof. The thickness of the intermediate redistribution layer 32 may be about 8 μm.

[0065] The third insulating layer 30 covers at least a portion of the second insulating layer 20 and the intermediate conductive structure 3. For example... Figure 1 As shown, a third insulating layer 30 is located on the upper surface 201 of the second insulating layer 20. The third insulating layer 30 has an upper surface 301 and a lower surface 302 opposite to the upper surface 301. The third insulating layer 30 defines a third opening 304 extending through the third insulating layer 30 to expose a portion of the intermediate redistribution layer 32. The material of the third insulating layer 30 may comprise an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB) polymer or a polyimide. In some embodiments, the third insulating layer 30 may comprise a cured photoimageable dielectric material, such as an epoxy resin or PI containing a photoinitiator. The thickness of the third insulating layer 30 may be about 9 μm.

[0066] The upper conductive structure 4 is located on the upper surface 301 of the third insulating layer 30. For example... Figure 1 As shown, the upper conductive structure 4 is located on the upper surface 301 of the third insulating layer 30. The upper conductive structure 4 extends into the third opening 304 of the third insulating layer 30 to form a conductive dielectric hole 48. That is, the conductive dielectric hole 48 of the upper conductive structure 4 penetrates the third insulating layer 30. The upper conductive structure 4 is electrically connected to the intermediate conductive structure 3 through the conductive dielectric hole 48. Therefore, the upper conductive structure 4 is electrically connected to the lower conductive structure 2 through the intermediate conductive structure 3.

[0067] The conductive structure 4 includes an upper seed layer 41 and an upper redistribution layer 42 sequentially located on the third insulating layer 30. The upper seed layer 41 may be made of titanium, copper, another metal, or an alloy. Figure 1 An upper seed layer 41 consisting of only one layer is shown. However, the upper seed layer 41 may contain more than one layer, or may be omitted. An upper redistribution layer 42 is located on the upper seed layer 41 and completely covers it. The upper redistribution layer 42 may contain at least one pad and at least one trace. The material of the upper redistribution layer 42 may include, for example, copper, another conductive metal, or an alloy thereof. The thickness of the upper redistribution layer 42 may be about 8 μm.

[0068] The fourth insulating layer 40 covers at least a portion of the third insulating layer 30 and the upper conductive structure 4. For example... Figure 1 As shown, a fourth insulating layer 40 is located on the upper surface 301 of the third insulating layer 30. The fourth insulating layer 40 has an upper surface 401 and a lower surface 402 opposite to the upper surface 401. The fourth insulating layer 40 defines a fourth opening 404 through the fourth insulating layer 40 to expose a portion of the upper redistribution layer 42 of the upper conductive structure 4. The material of the fourth insulating layer 40 may include an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene polymer or a polyimide. In some embodiments, the fourth insulating layer 40 may include a curable photoimageable dielectric material, such as an epoxy resin or PI containing a photoinitiator. The thickness of the fourth insulating layer 40 may be about 9 μm.

[0069] The metallization layer 5 under the bump is electrically connected to the upper conductive structure 4, such as the upper redistribution layer 42 of the conductive structure 4. Figure 1 As shown, the under-bump metallization layer 5 is located in the fourth opening 404 of the fourth insulating layer 40, and a portion of the under-bump metallization layer 5 may extend on the upper surface 401 of the fourth insulating layer 40. Figure 1 As shown, the under-bump metallization layer 5 includes an under-bump metallization seed layer 51, a copper layer 52, a nickel layer 53, and a gold layer 54 sequentially located in the fourth opening 404. The material of the under-bump metallization seed layer 51 may be titanium, copper, another metal, or an alloy.

[0070] The semiconductor die 6 is electrically connected to the upper conductive structure 4 via the under-bump metallization layer 5. For example, the semiconductor die 6 includes at least one bump pad 63 and at least one interconnect element 64. The bump pad 63 is located on the semiconductor die 6, and the interconnect element 64 is located on the under-bump metallization layer 5 and connected to the bump pad 63. In some embodiments, the interconnect element 64 may be formed from pre-solder or solder balls.

[0071] Package 16 is located on the fourth insulating layer 40 and encapsulates and covers the semiconductor die 6, bump pad 63, interconnect element 64, and under-bump metallization layer 5. The material of package 16 may be a molding compound with or without filler.

[0072] Electrical connection element 14 is attached to the junction area 22a of the lower conductive structure 22 for external connection. For example... Figure 1 As shown, the electrical connection element 14 is attached to a ball pad formed by the exposed portion 254 of the wetting layer 25. The electrical connection element 14 may be formed of solder balls. In some embodiments, the maximum width or diameter of the electrical connection element 14 may be about 80 μm or less. Correspondingly, the width or diameter of the ball pad formed by the exposed portion 254 of the wetting layer 25 (i.e., the width or diameter of the bonding area 22a of the lower circuit structure 22) may be about 80 μm x 80 μm. In some embodiments, the electrical connection element 14 is connected to a motherboard.

[0073] In electronic device 1, since the lower redistribution layer 23 is located directly on the lower circuit structure 22 rather than via another conductive metal layer, an additional conductive metal layer can be omitted. Furthermore, an additional insulating layer can also be omitted, as no insulating layer is required between the lower redistribution layer 23 and the lower circuit structure 22. Electronic device 1 comprises four conductive metal layers (i.e., lower conductive structure 2, intermediate conductive structure 3, upper conductive structure 4, and bump under-metallization layer 5) and four insulating layers (i.e., first insulating layer 10, second insulating layer 20, third insulating layer 30, and fourth insulating layer 40), instead of five conductive metal layers and five insulating layers. Therefore, the fabrication time and manufacturing cost of electronic device 1 can be reduced. The overall thickness of electronic device 1 can also be reduced, thereby avoiding warping and delamination problems. Furthermore, the lower redistribution layer 23 and the lower circuit structure 22 can be formed using the same photomask and / or the same patterned photoresist, which further reduces the fabrication time and manufacturing cost of electronic device 1.

[0074] Furthermore, since the first barrier layer 24 is omitted in the bonding region 22a (i.e., a portion 254 of the wetting layer 25 is exposed from the first barrier layer 24 to serve as a ball pad), the electrical connection element 14 can be formed from solder balls instead of solder paste. That is, the wetting layer 25 prevents the formation of IMC between the solder balls (e.g., made of tin) and the wetting layer 25 (e.g., made of gold). The size of the ball pad in the electronic device 1 can therefore be reduced to approximately 80 μm x 80 μm, which is much smaller than the ball pad described above with electrical connection elements made of solder paste. The total thickness of the lower circuit structure 22 in the electronic device 1 is approximately 4.3 μm, less than the thickness of the copper ball pad described above (e.g., approximately 8 μm). The reduced thickness of the lower circuit structure 22 is beneficial for reducing the overall thickness of the electronic device 1 and for preventing short circuits between the lower conductive structure 2 and the intermediate conductive structure 3.

[0075] Since the lower circuit structure 22 has the same layout as the lower redistribution layer 23, the area of ​​the extension region 22b of the lower circuit structure 22 located on the upper surface 101 of the first insulating layer 10 is relatively large. The extension region 22b of the lower circuit structure 22 can therefore provide sufficient support for the bonding region 22a of the lower circuit structure 22, thereby preventing delamination caused by the weight of the electrical connection element 14 connected to the bonding region 22a. Furthermore, since the bonding region 22a is recessed from the lower surface 102 of the first insulating layer 10, the contact area between the electrical connection element 14 and the lower conductive structure 2 is increased, thus improving the bonding strength therebetween.

[0076] Since the lower seed layer 21 (e.g., the copper layer 212 of the lower seed layer 21) is made of copper and the wetting layer 25 is made of gold, IMC may occur when the lower seed layer 21 directly contacts the wetting layer 25. However, the first barrier layer 24 located therebetween prevents such IMC. Similarly, with respect to the gold-made wetting layer 25 and the copper-made lower redistribution layer 23, the second barrier layer 26 located therebetween prevents IMC that may occur when the wetting layer 25 directly contacts the lower redistribution layer 23.

[0077] Figure 2 illustrate Figure 1 An enlarged view of area "A" shown in the image. Note that... Figure 2 Wiring structure 12 included in electronic device 1 according to some embodiments of the present disclosure is shown.

[0078] The wiring structure 12 includes an insulating layer (e.g., a first insulating layer 10) and a conductive structure (e.g., a lower conductive structure 2).

[0079] The first insulating layer 10 has an upper surface 101 and a lower surface 102 opposite to the upper surface 101. The first insulating layer 10 defines an opening (e.g., a first opening 104) through the first insulating layer 10. The first opening 104 has a sidewall 103. A lower conductive structure 2 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. The lower conductive structure 2 includes a lower seed layer 21, a lower circuit structure 22, and a lower redistribution layer 23 sequentially located on the first insulating layer 10.

[0080] The lower seed layer 21 is located on the upper surface 101 of the first insulating layer 10 and on the sidewall 103 of the first opening 104 of the first insulating layer 10. The lower seed layer 21 is located between the first insulating layer 10 and the lower conductive structure 22. In some embodiments, the lower seed layer 21 is not exposed from the lower surface 102 of the first insulating layer 10. That is, the portion of the lower seed layer 21 adjacent to the lower surface 102 of the insulating layer 10 is removed or omitted. Accordingly, the lower seed layer 21 defines a through-hole 210 penetrating the seed layer 21. The through-hole 210 of the lower seed layer 21 is located at the opening 104 of the first insulating layer 10. The central axis of the through-hole 210 of the lower seed layer 21 is aligned with the central axis of the opening 104 of the insulating layer 10. The material of the lower seed layer 21 may be titanium, copper, another metal or alloy. In some embodiments, such as Figure 2 As shown, the lower seed layer 21 comprises a titanium layer 211 and a copper layer 212. However, the lower seed layer 21 may comprise more or fewer layers, or may be omitted. The titanium layer 211 is located on and in contact with the upper surface 101 of the first insulating layer 10 and the sidewall 103 of the first opening 104 of the first insulating layer 10. The copper layer 212 is located on and in contact with the titanium layer 211.

[0081] The lower circuit structure 22 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. For example... Figure 2 As shown, the lower circuit structure 22 is located on and completely covers the lower seed layer 21. The lower circuit structure 22 can contact the lower seed layer 21.

[0082] The lower circuit structure 22 includes multiple metal layers (e.g., a first barrier layer 24, a wetting layer 25, and a second barrier layer 26). The first barrier layer 24, the wetting layer 25, and the second barrier layer 26 are sequentially located on the lower seed layer 21. The first barrier layer 24 is located on the upper surface 101 of the first insulating layer 10 and on the sidewall 103 of the first opening 104 of the first insulating layer 10. The first barrier layer 24 is located on the lower seed layer 21 and can contact and completely cover the lower seed layer 21, such as the copper layer 212 of the lower seed layer 21. In some embodiments, the first barrier layer 24 is not exposed from the lower surface 102 of the first insulating layer 10. That is, the portion of the first barrier layer 24 adjacent to the lower surface 102 of the insulating layer 10 is removed or omitted. Accordingly, the first barrier layer 24 defines a through-hole 240 penetrating the first barrier layer 24. The perforations 240 of the first barrier layer 24 can be roughly aligned with and communicated with the perforations 210 of the seed layer 21.

[0083] A wetting layer 25 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. The wetting layer 25 is located on the first barrier layer 24 and can contact and completely cover the first barrier layer 24. Because portions of the lower seed layer 21 and the first barrier layer 24 adjacent to the lower surface 102 of the insulating layer 10 are removed or omitted, a portion 254 of the wetting layer 25 is exposed from the lower seed layer 21 and the first barrier layer 24, and from the lower surface 102 of the first insulating layer 10. That is, a portion 254 of the wetting layer 25 is exposed from the perforations 210 of the lower seed layer 21 and the perforations 240 of the first barrier layer 24, and from the lower surface 102 of the first insulating layer 10. The exposed portion 254 of the wetting layer 25 forms a ball pad for external connection.

[0084] The second barrier layer 26 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. The second barrier layer 26 is located on and in contact with the wetting layer 25. The materials of the first barrier layer 24 and the second barrier layer 26 may contain nickel. The material of the wetting layer 25 may contain gold.

[0085] The lower circuit structure 22 includes a bonding region 22a and an extension region 22b. The bonding region 22a is exposed from the first opening 104 of the first insulating layer 10 and includes an exposed portion 254 of the wetting layer 25 and a second barrier layer 26. The extension region 22b is connected to and extends from the bonding region 22a. The extension region 22b is located on the sidewall 103 of the first opening 104 of the first insulating layer 10 and on the upper surface 101 of the first insulating layer 10.

[0086] The lower redistribution layer 23 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulation layer 10. The lower redistribution layer 23 is located on the lower circuit structure 22 and can contact and completely cover the lower circuit structure 22, such as the second barrier layer 26 of the lower circuit structure 22. The material of the lower redistribution layer 23 may include, for example, copper, another conductive metal or an alloy thereof.

[0087] Figure 3 A cross-sectional view of an electronic device 1a according to some embodiments of the present disclosure is illustrated. The electronic device 1a is similar to... Figure 1 The electronic device 1 shown is different in that the under-bump metallization layer 5 is omitted in the electronic device 1a, and the upper conductive structure 4 of the electronic device 1 is replaced by the upper conductive structure 4a in the electronic device 1a.

[0088] like Figure 3 As shown, the upper conductive structure 4a in the electronic device 1a includes an upper seed layer 41, an upper redistribution layer 42, and an upper circuit structure 43 sequentially located on the third insulating layer 30. The material of the upper seed layer 41 may be titanium, copper, another metal, or an alloy. Figure 3 An upper seed layer 41 consisting of only one layer is shown. However, the upper seed layer 41 may contain more than one layer, or may be omitted. An upper redistribution layer 42 is located on the upper seed layer 41 and completely covers it. The upper redistribution layer 42 may contain at least one pad and at least one trace. The material of the upper redistribution layer 42 may include, for example, copper, another conductive metal, or an alloy thereof.

[0089] The upper circuit structure 43 comprises multiple metal layers. The upper circuit structure 43 can contact and completely cover the upper redistribution layer 42. For example, the upper circuit structure 43 includes a nickel layer 44, a palladium layer 45, and a gold layer 46 sequentially located on the upper redistribution layer 42. The nickel layer 44 and palladium layer 45 serve a copper barrier function, and the gold layer 46 serves a wetting function for connection to the interconnect element 64a. The upper circuit structure 43 can be formed by plating using the same photomask and / or the same patterned photoresist as the upper redistribution layer 42. Therefore, the peripheral wall 433 of the upper circuit structure 43 can be aligned with the peripheral wall 423 of the upper redistribution layer 42. The upper circuit structure 43 can be conformally fitted to the upper redistribution layer 42. The layout of the upper circuit structure 43 can be substantially the same as the layout of the upper redistribution layer 42.

[0090] Because in Figure 3 The electronic device 1a shown in the figure is omitted Figure 1The electronic device 1 shown has an under-bump metallization layer 5, so the semiconductor die 6 in the electronic device 1a is electrically connected to the upper conductive structure 4a (e.g., the gold layer 46 of the upper circuit structure 43) instead of the under-bump metallization layer 5. For example, a fourth insulating layer 40 defines a fourth opening 404a positioned substantially corresponding to the third opening 304 of the third insulating layer 30. The fourth opening 404a of the fourth insulating layer 40 exposes a portion of the upper conductive structure 4a (e.g., the conductive via 48), and the semiconductor die 6 is connected to the exposed portion of the upper conductive structure 4a via at least one interconnect element 64a. The interconnect element 64a may be formed of solder balls, such as solder balls made of tin.

[0091] In electronic device 1a, since the upper circuit structure 43 is directly located on the upper redistribution layer 42, the under-bump metallization layer can be omitted (e.g., Figure 1 The bump under-metallization layer 5 of the electronic device 1 is shown in the figure. Therefore, the formation time, manufacturing cost and total thickness of the electronic device 1a can be further reduced. In addition, the upper circuit structure 43 and the upper redistribution layer 42 can be formed using the same photomask and / or the same patterned photoresist.

[0092] Figures 4 to 28 This invention describes a method for manufacturing an electronic device according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture, for example... Figure 1 The electronic device 1 shown in the figure is an electronic device.

[0093] refer to Figure 4 A first carrier 90 is provided. The first carrier 90 may be made of glass and may contain a release film thereon. A substrate seed layer 91 is then formed on the release film of the first carrier 90 by, for example, sputtering. The substrate seed layer 91 may be made of copper.

[0094] refer to Figure 5 A first insulating layer 10 is formed on the substrate seed layer 91. The first insulating layer 10 has an upper surface 101 and a lower surface 102 opposite to the upper surface 101. A first opening 104 is formed through the first insulating layer 10 and exposes a portion of the substrate seed layer 91. The first opening 104 has sidewalls 103. The material of the first insulating layer 10 may include an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene polymer or a polyimide. In some embodiments, the first insulating layer 10 may include a curable photoimageable dielectric material, such as an epoxy resin or PI containing a photoinitiator. The thickness of the first insulating layer 10 may be about 7 μm.

[0095] refer to Figure 6A lower seed layer 21 is formed, for example, by sputtering, on the upper surface of the first insulating layer 10 and within the first opening 104 of the first insulating layer 10. The material of the lower seed layer 21 may be titanium, copper, another metal, or an alloy. In some embodiments, such as... Figure 6 As shown, the lower seed layer 21 comprises a titanium layer 211 and a copper layer 212. However, the lower seed layer 21 may comprise more or fewer layers. The titanium layer 211 is located on and in contact with the upper surface 101 of the first insulating layer 10 and the sidewall 103 of the first opening 104 of the first insulating layer 10. The copper layer 212 is located on and in contact with the titanium layer 211. The thickness of the titanium layer 211 may be about 0.1 μm, and the thickness of the copper layer 212 may be about 0.2 μm.

[0096] refer to Figure 7 A first photoresist layer 92a is disposed on the first insulating layer 10 and the lower seed layer 21. Then, the first photoresist layer 92a is exposed to patterned strong light. For example, a first photomask 94a is disposed adjacent to the first photoresist layer 92a to cover a portion of the first photoresist layer 92a. Then, the first photoresist layer 92a is exposed to a light source 96.

[0097] refer to Figure 8 The first photoresist layer 92a is then developed using a developer. That is, the first photoresist layer 92a is patterned to define a plurality of openings 921a to expose portions of the lower seed layer 21 located on the upper surface 102 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10.

[0098] refer to Figure 9A first barrier layer 24, a wetting layer 25, and a second barrier layer 26 are sequentially formed to form a lower circuit structure 22 on a lower seed layer 21. The lower circuit structure 22 is formed, for example, by plating, in the opening 921a of the first photoresist layer 92a and on the lower seed layer 21. The lower circuit structure 22 includes multiple metal layers (e.g., the first barrier layer 24, the wetting layer 25, and the second barrier layer 26). The first barrier layer 24 is formed on the lower seed layer 21 and is in contact with the lower seed layer 21, for example, the copper layer 212 of the lower seed layer 21. The wetting layer 25 is formed on the first barrier layer 24 and is in contact with and completely covers the first barrier layer 24. The second barrier layer 26 is formed on the wetting layer 25 and is in contact with and completely covers the wetting layer 25. The materials of the first barrier layer 24 and the second barrier layer 26 may include nickel. The material of the wetting layer 25 may include gold. The thickness of the first barrier layer 24 can be about 1 μm, the thickness of the wetting layer 25 can be about 0.3 μm, and the thickness of the second barrier layer 26 can be about 3 μm. Since the first barrier layer 24, the wetting layer 25, and the second barrier layer 26 are formed using the same photomask 94a and / or the same patterned photoresist 92a, the outer wall 223 of the lower circuit structure 22 containing the first barrier layer 24, the wetting layer 25, and the second barrier layer 26 is continuous.

[0099] refer to Figure 10 The lower redistribution layer 23 is formed, for example, by plating, in the opening 921a of the first photoresist layer 92a and on the lower circuit structure 22. The lower redistribution layer 23 is formed on the surface of the second barrier layer 26 of the lower circuit structure 22. The lower redistribution layer 23 may contact and completely cover the lower circuit structure 22, such as the second barrier layer 26 of the lower circuit structure 22. The lower redistribution layer 23 may include at least one pad and at least one trace. The material of the lower redistribution layer 23 may include, for example, copper, another conductive metal or an alloy thereof. The thickness of the lower redistribution layer 23 may be about 4.3 μm.

[0100] like Figure 9 and 10 As shown, the lower circuit structure 22 and the lower redistribution layer 23 are formed using the same photoresist (e.g., first photoresist 92a). That is, the lower circuit structure 22 and the lower redistribution layer 23 are formed using the same photomask (e.g., first photomask 94b). Therefore, the outer perimeter wall 233 of the lower redistribution layer 23 can be aligned with the outer perimeter wall 223 of the lower circuit structure 22. The lower redistribution layer 23 can be conformally fitted to the lower circuit structure 22. The layout of the lower redistribution layer 23 can be substantially the same as the layout of the lower circuit structure 22.

[0101] refer to Figure 11The first photoresist layer 92a is removed, and portions of the lower seed layer 21 not covered by the lower conductive structure 22 are removed, for example, by etching. Accordingly, a lower conductive structure 2 is formed, comprising the lower seed layer 21, the lower circuit structure 22, and the lower redistribution layer 23. The lower conductive structure 2 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. The lower seed layer 21 is located between the first insulating layer 10 and the lower conductive structure 22. The lower circuit structure 22, such as the first barrier layer 24 of the lower circuit structure 22, may completely cover the lower seed layer 21.

[0102] refer to Figure 12 A second insulating layer 20 is formed on the first insulating layer 10. The second insulating layer 20 covers at least a portion of the first insulating layer 10 and the lower conductive structure 2. Figure 12 As shown, the second insulating layer 20 is located on the upper surface 101 of the first insulating layer 10. The second insulating layer 20 has an upper surface 201 and a lower surface 202 opposite to the upper surface 201. A second opening 204 is formed through the second insulating layer 20 to expose a portion of the lower reconstituted layer 23. The material of the second insulating layer 20 may include an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB) polymer or a polyimide (PI). In some embodiments, the second insulating layer 20 may include a curable photoimageable dielectric material, such as an epoxy resin or PI containing a photoinitiator. The thickness of the second insulating layer 20 may be about 9 μm.

[0103] refer to Figure 13 An intermediate seed layer 31 is formed, for example, by sputtering, on the upper surface 201 of the second insulating layer 20 and in the second opening 204 of the second insulating layer 20. The material of the intermediate seed layer 31 may be titanium, copper, another metal or alloy. Figure 13 An intermediate seed layer 31 consisting of only one layer is shown. However, the intermediate seed layer 31 may contain more than one layer.

[0104] refer to Figure 14 A second photoresist 92b is placed on the second insulating layer 20 and the intermediate seed layer 31. The second photoresist layer 92b is patterned to define a plurality of openings 921b to expose portions of the intermediate seed layer 31 located on the upper surface 201 of the second insulating layer 20 and in the second opening 204 of the second insulating layer 20.

[0105] refer to Figure 15An intermediate redistribution layer 32 is formed, for example, by plating, in the opening 921b of the second photoresist layer 92b and on the intermediate seed layer 31. The intermediate redistribution layer 32 is located on the intermediate seed layer 31. The intermediate redistribution layer 32 may include at least one pad and at least one trace. The material of the intermediate redistribution layer 32 may include, for example, copper, another conductive metal or an alloy thereof. The thickness of the intermediate redistribution layer 32 may be about 8 μm. Next, the second photoresist layer 92b is removed, and the portion of the intermediate seed layer 31 not covered by the intermediate redistribution layer 32 is removed, for example, by etching. Accordingly, an intermediate conductive structure 3 is formed and includes the intermediate seed layer 31 and the intermediate redistribution layer 32. The intermediate conductive structure 3 is located on the upper surface 201 of the second insulating layer 20. The intermediate conductive structure 3 extends into the second opening 204 of the second insulating layer 20 to form a conductive dielectric hole 38. That is, the conductive dielectric hole 38 of the intermediate conductive structure 3 penetrates the second insulating layer 20. The intermediate conductive structure 3 is electrically connected to the lower conductive structure 2 through the conductive interlayer hole 38.

[0106] refer to Figure 16 A third insulating layer 30 is formed on the second insulating layer 20. The third insulating layer 30 covers at least a portion of the second insulating layer 20 and the intermediate conductive structure 3. Figure 16 As shown, a third insulating layer 30 is located on the upper surface 201 of the second insulating layer 20. The third insulating layer 30 has an upper surface 301 and a lower surface 302 opposite to the upper surface 301. A third opening 304 is formed through the third insulating layer 30 to expose a portion of the intermediate rework layer 32. The material of the third insulating layer 30 may comprise an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB) polymer or a polyimide (PI). In some embodiments, the third insulating layer 30 may comprise a curable photoimageable dielectric material, such as an epoxy resin or PI containing a photoinitiator. The thickness of the third insulating layer 30 may be about 9 μm.

[0107] refer to Figure 17 An upper seed layer 41 is formed, for example, by sputtering, on the upper surface 302 of the third insulating layer 30 and in the third opening 304 of the third insulating layer 30. The material of the upper seed layer 41 may be titanium, copper, another metal or alloy. Figure 17 The upper seed layer 41, consisting of only one layer, is shown. However, the upper seed layer 41 may contain more than one layer.

[0108] refer to Figure 18 A third photoresist 92c is placed on the third insulating layer 30. The third photoresist layer 92c is patterned to define a plurality of openings 921c to expose portions of the upper seed layer 41 located on the upper surface 302 of the third insulating layer 30 and in the third opening 304 of the third insulating layer 30.

[0109] refer to Figure 19An upper redistribution layer 42 is formed, for example, by plating, in the opening 921c of the third photoresist layer 92c and on the upper seed layer 41. The upper redistribution layer 42 is located on the upper seed layer 41. The upper redistribution layer 42 may include at least one pad and at least one trace. The material of the upper redistribution layer 42 may include, for example, copper, another conductive metal, or an alloy thereof. The thickness of the upper redistribution layer 42 may be about 8 μm. Next, the third photoresist layer 92c is removed, and the portion of the upper seed layer 41 not covered by the intermediate redistribution layer 42 is removed, for example, by etching. Accordingly, an upper conductive structure 4 is formed, which includes the upper seed layer 41 and the upper redistribution layer 42. The upper conductive structure 4 is located on the upper surface 301 of the third insulating layer 30. Figure 19 As shown, the upper conductive structure 4 is located on the upper surface 301 of the third insulating layer 30. The upper conductive structure 4 extends into the third opening 304 of the third insulating layer 30 to form a conductive dielectric hole 48. That is, the conductive dielectric hole 48 of the upper conductive structure 4 penetrates the third insulating layer 30. The upper conductive structure 4 is electrically connected to the intermediate conductive structure 3 through the conductive dielectric hole 48. Therefore, the upper conductive structure 4 is electrically connected to the lower conductive structure 2 through the intermediate conductive structure 3. The intermediate conductive structure 3 is located between the upper conductive structure 2 and the lower conductive structure 4.

[0110] refer to Figure 20 A fourth insulating layer 40 is formed on the third insulating layer 30. The fourth insulating layer 40 covers at least a portion of the upper conductive structure 4. Figure 20 As shown, a fourth insulating layer 40 is located on the upper surface 301 of the third insulating layer 30. The fourth insulating layer 40 has an upper surface 401 and a lower surface 402 opposite to the upper surface 401. A fourth opening 404 is formed through the fourth insulating layer 40 to expose a portion of the upper reconstituted layer 42. The material of the fourth insulating layer 40 may include an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene polymer or a polyimide. In some embodiments, the fourth insulating layer 40 may include a curable photoimageable dielectric material, such as an epoxy resin or PI containing a photoinitiator. The thickness of the fourth insulating layer 40 may be about 9 μm.

[0111] refer to Figure 21 A seed layer 51 under the bump is formed on the upper surface 401 of the fourth insulating layer 40 by, for example, sputtering. The material of the seed layer 51 under the bump can be titanium, copper, another metal or alloy.

[0112] refer to Figure 22 A fourth photoresist 92d is placed on the fourth insulating layer 40. The fourth photoresist layer 92d is patterned to define a plurality of openings 921d to expose portions of the under-bump metallization seed layer 51 located on the upper surface 401 of the fourth insulating layer 40 and in the fourth opening 404 of the fourth insulating layer 40.

[0113] refer to Figure 23 A copper layer 52, a nickel layer 53, and a gold layer 54 are sequentially formed in the opening 921d of the fourth photoresist layer 92d and on the under-bump metallization seed layer 51 by means of, for example, plating. Next, the fourth photoresist layer 92d is removed, and the portion of the under-bump metallization seed layer 51 not covered by the copper layer 52 is removed by, for example, etching. Accordingly, an under-bump metallization layer 5 is formed, comprising the under-bump metallization seed layer 51, the copper layer 52, the nickel layer 53, and the gold layer 54. The under-bump metallization layer 5 is located in the fourth opening 404 of the fourth insulating layer 40, and a portion of the under-bump metallization layer 5 may extend on the upper surface 401 of the fourth insulating layer 40.

[0114] refer to Figure 24 The semiconductor die 6 is connected to the under-bump metallization layer 5. The semiconductor die 6 is electrically connected to the upper conductive structure 4 through the under-bump metallization layer 5. For example, the semiconductor die 6 includes at least one bump pad 63 and at least one interconnect element 64. The bump pad 63 is located on the semiconductor die 6, and the interconnect element 64 is located on the under-bump metallization layer 5 and connected to the bump pad 63. In some embodiments, the interconnect element 64 may be formed from pre-solder or solder balls. Next, a package 16 is formed on the fourth insulating layer 40 to encapsulate and cover the semiconductor die 6, the bump pad 63, the interconnect element 64, and the under-bump metallization layer 5. The material of the package 16 may be an encapsulation compound with or without filler.

[0115] refer to Figure 25 The second carrier 90a is attached to the package 16 via the adhesive layer 98. The second carrier 90a may be the same as or different from the first carrier 90.

[0116] refer to Figure 26 Remove the first carrier 90 and expose the substrate seed layer 91.

[0117] refer to Figure 27 The base seed layer 91 is removed, for example, by etching. In some embodiments, portions of the first barrier layer 24 and the lower seed layer 21 adjacent to the lower surface 102 of the first insulating layer 10 are removed simultaneously, forming a perforation through the first barrier layer 24 (e.g., Figure 2 The perforation 240 shown in the figure) and the perforation through the lower seed layer 21 (e.g., Figure 2 (See perforation 210 shown). That is, a portion of the first barrier layer 24 is etched to expose a portion 254 of the wetting layer 25. Accordingly, the first barrier layer 24 is located only on the upper surface 101 of the first insulating layer 10 and the sidewall 103 of the first opening 104 of the first insulating layer 10, and not from the lower surface 102 of the first insulating layer 10 and the perforation 210 of the lower seed layer 21. Figure 2The wetting layer 25 is located on the upper surface 101 of the first insulating layer 10 and in the first opening 104 of the first insulating layer 10. A portion 254 of the wetting layer 25 emerges from the perforation 210 of the lower seed layer 21. Figure 2 ) and the perforation 240 of the first barrier layer 24 Figure 2 ), and exposed from the lower surface 102 of the first insulating layer 10. The exposed portion 254 of the wetting layer 25 forms a ball pad for external connection.

[0118] The lower circuit structure 22 includes a junction region 22a and an extension region 22b. Each layer of the lower circuit structure 22 within the junction region 22a and the extension region 22b can be simultaneously and integrally formed as a single structure. The junction region 22a is exposed from the lower surface 102 of the first insulating layer 10 and includes an exposed portion 254 of the wetting layer 25 as a ball pad for external connection. Figure 27 As shown, the bonding region 22a consists of two metal layers, namely a wetting layer 25 and a second barrier layer 26, and is recessed from the lower surface 102 of the first insulating layer 10.

[0119] Extension region 22b connects to and extends from junction region 22a. Extension region 22b is located on the sidewall 103 of the first opening 104 of the first insulating layer 10, and on the upper surface 101 of the first insulating layer 10. Figure 27 As shown, the extension region 22a consists of three metal layers: a first barrier layer 24, a wetting layer 25, and a second barrier layer 26. Correspondingly, the number of metal layers in the bonding region 22a differs from the number of metal layers in the extension region 22b.

[0120] refer to Figure 28 At least one electrical connection element 14 is attached to the exposed portion 254 of the wetting layer 25 for external connection. In other words, the electrical connection element 14 is attached to the bonding region 22a of the lower conductive structure 2. Figure 28 As shown, the electrical connection element 14 is attached to a ball pad formed by the exposed portion 254 of the wetting layer 25. The electrical connection element 14 can be formed from solder balls. In some embodiments, the maximum diameter or width of the electrical connection element 14 can be about 80 μm or less. Correspondingly, the size of the ball pad formed by the exposed portion 254 of the wetting layer 25 (i.e., the size of the bonding area 22a of the lower circuit structure 22) can be about 80 μm * 80 μm. Next, a single-cutting process is performed, and the second carrier 90a and the adhesive layer 98 are removed, forming as shown. Figure 1 The electronic device 1 shown. In some embodiments, the electronic device 1 can then be electrically connected to the motherboard by attaching an electrical connection element to the motherboard.

[0121] Figures 29 to 34 This invention describes a method for manufacturing an electronic device according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture, for example... Figure 3 The electronic device 1a shown is an electronic device. The initial stage of the described process and Figures 4 to 17 The stages shown are the same or similar. Figure 29 Depicted in Figure 17 The stage following the stage described in the text.

[0122] refer to Figure 29 A fifth photoresist layer 92e is placed on the third insulating layer 30 and the upper seed layer 41. Next, the fifth photoresist layer 92e is exposed to patterned strong light. For example, a fifth photomask 94e is placed adjacent to the fifth photoresist layer 92e to cover a portion of the fifth photoresist layer 92e. Then, the fifth photoresist layer 92e is exposed to a light source 96.

[0123] refer to Figure 30 Next, the fifth photoresist layer 92e is developed using a developer. That is, the fifth photoresist layer 92e is patterned to define a plurality of openings 921e to expose portions of the upper seed layer 41 located on the upper surface 302 of the third insulating layer 30 and in the third opening 304 of the third insulating layer 30.

[0124] refer to Figure 31 The upper redistribution layer 42 is formed, for example, by plating in the opening 921e of the fifth photoresist layer 92e and on the upper seed layer 41. The upper redistribution layer 42 may include at least one pad and at least one trace. The material of the upper redistribution layer 42 may include, for example, copper, another conductive metal, or an alloy thereof.

[0125] refer to Figure 32 The upper circuit structure 43 is formed, for example, by plating in the opening 921e of the fifth photoresist layer 92e and on the upper redistribution layer 42. The upper circuit structure 43 includes multiple metal layers. The upper circuit structure 43 can contact and completely cover the upper redistribution layer 42. For example, the upper circuit structure 43 includes a nickel layer 44, a palladium layer 45, and a gold layer 46 sequentially formed on the upper redistribution layer 42. The nickel layer 44 and palladium layer 45 serve a copper barrier function, and the gold layer 46 serves a wetting function for connection with interconnect element 64a. Figure 3 (Connection.) For example... Figure 31 and 32 As shown, since the upper circuit structure 43 is formed using the same photomask (e.g., fifth photomask 94e) and / or the same patterned photoresist (e.g., fifth photoresist 92e) as the upper redistribution layer 42, the outer periphery 433 of the upper circuit structure 43 is aligned with the outer periphery 423 of the upper redistribution layer 42. The upper circuit structure 43 may be conformally compatible with the upper redistribution layer 42. The layout of the upper circuit structure 43 may be substantially the same as the layout of the upper redistribution layer 42.

[0126] refer to Figure 33The fifth photoresist layer 92e is removed, and the portion of the upper seed layer 41 not covered by the upper redistribution layer 42 is removed, for example, by etching. Accordingly, an upper conductive structure 4a is formed, which includes the upper seed layer 41, the upper redistribution layer 42, and the upper circuit structure 43. The upper redistribution layer 42 can completely cover the upper seed layer 41. The upper conductive structure 4 extends into the third opening 304 of the third insulating layer 30 to form a conductive dielectric hole 48. That is, the conductive dielectric hole 48 of the upper conductive structure 4 penetrates the third insulating layer 30. The upper conductive structure 4 is electrically connected to the intermediate conductive structure 3 through the conductive dielectric hole 48. Therefore, the upper conductive structure 4 is electrically connected to the lower conductive structure 2 through the intermediate conductive structure 3.

[0127] refer to Figure 34 A fourth insulating layer 40 is formed on the third insulating layer 30. The fourth insulating layer 40 covers at least a portion of the upper conductive structure 4a. Figure 34 As shown, a fourth insulating layer 40 is located on the upper surface 301 of the third insulating layer 30. The fourth insulating layer 40 has an upper surface 401 and a lower surface 402 opposite to the upper surface 401. The fourth insulating layer 40 defines a fourth opening 404a, the location of which generally corresponds to the third opening 304 of the third insulating layer 30. The fourth opening 404a of the fourth insulating layer 40 exposes a portion of the upper conductive structure 4a (e.g., a conductive dielectric hole 48). The material of the fourth insulating layer 40 may comprise an insulating material, a passivating material, a dielectric material, or a solder resist material, such as a benzocyclobutene polymer or a polyimide. In some embodiments, the fourth insulating layer 40 may comprise a curable photoimageable dielectric material, such as an epoxy resin or PI containing a photoinitiator. The thickness of the fourth insulating layer 40 may be about 9 μm or less.

[0128] In the process described Figure 34 The stages following the stages shown in the diagram are similar to... Figures 24 to 28 The stages shown, therefore forming Figure 3 The electronic device 1a shown is shown.

[0129] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not affected by such arrangements.

[0130] As used herein, the terms “approximately,” “basically,” “generally,” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with numerical values, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same or equal.

[0131] If the displacement between two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0132] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators.

[0133] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials typically indicate those that exhibit very little or no resistance to current flow. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of the material is measured at room temperature.

[0134] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0135] While the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. An electronic device comprising: A first insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines a first opening through the first insulating layer; The lower conductive structure includes a lower circuit structure located in the first opening of the first insulating layer, wherein the lower circuit structure includes a plurality of metal layers, the lower circuit structure includes a bonding region and an extension region, and the number of metal layers in the bonding region is different from the number of metal layers in the extension region. At least one electrical connection element is attached to the junction region of the lower conductive structure; An upper conductive structure is electrically connected to the lower conductive structure; An intermediate conductive structure is located between the upper conductive structure and the lower conductive structure, and the upper conductive structure is electrically connected to the lower conductive structure through the intermediate conductive structure; A second insulating layer covers at least a portion of the first insulating layer and the lower conductive structure, and the intermediate conductive structure is located on the second insulating layer; A third insulating layer covers at least a portion of the second insulating layer and the intermediate conductive structure, with the upper conductive structure located on the third insulating layer; and A fourth insulating layer that covers at least a portion of the third insulating layer and the upper conductive structure.

2. The electronic device of claim 1, wherein the extension region comprises three metal layers and the bonding region comprises two metal layers.

3. The electronic device according to claim 2, wherein the extension region comprises a first barrier layer, a wetting layer, and a second barrier layer.

4. The electronic device of claim 1, wherein the bonding region is recessed from the lower surface of the first insulating layer.

5. The electronic device of claim 1, wherein the lower conductive structure further comprises a lower redistribution layer located on the lower circuit structure.

6. The electronic device of claim 5, wherein the outer wall of the lower redistribution layer is aligned with the outer wall of the lower circuit structure.

7. The electronic device of claim 5, wherein the material of the lower re-fabricated layer comprises copper.

8. The electronic device of claim 1, wherein the lower conductive structure further comprises a lower seed layer located between the first insulating layer and the lower conductive structure.

9. The electronic device of claim 8, wherein the lower seed layer comprises a titanium layer and a copper layer located on the titanium layer.

10. The electronic device of claim 1, wherein the upper conductive structure comprises an upper circuit structure comprising a plurality of metal layers.

11. The electronic device of claim 10, wherein the upper conductive structure further comprises an upper redistribution layer, and the outer wall of the upper circuit structure is aligned with the outer wall of the upper redistribution layer.

12. The electronic device of claim 1, further comprising at least one semiconductor die electrically connected to the upper conductive structure.

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