Memory device, memory system, and method for refreshing memory device

Abstract

A memory device, a memory system, and a method for refreshing a memory device are provided. An example memory device may include: a memory cell array including a plurality of memory cell rows; a row hammering processor configured to determine whether to perform a row hammering operation for refreshing adjacent memory cell rows adjacent to a first row that is intensively accessed among the plurality of memory cell rows, and generate a determination result; and a refresh manager configured to perform a normal refresh operation or a row hammering operation for sequentially refreshing the memory cell rows based on the determination result of the row hammering processor.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2018-0053196, filed on May 9, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a memory device and a memory system including the memory device, and more particularly, to a memory device that performs a row hammer process for reducing the occurrence of a row hammer phenomenon by precharging a word line adjacent to a frequently accessed word line, and a memory system including the memory device. Background Art

[0003] The memory device is a storage device and may be implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). The memory device may be divided into a volatile memory device and a nonvolatile memory device.

[0004] A nonvolatile memory device is a memory device in which data stored therein does not disappear even when power is interrupted. Examples of nonvolatile memory devices may include NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RAM), phase change memory, magnetoresistive random access memory (MRAM), etc.

[0005] A volatile memory device is a memory device in which data stored therein disappears when power is interrupted. Examples of volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), latches, flip-flops, registers, and the like.

[0006] Volatile memory devices such as DRAM determine data based on charges stored in capacitors. However, since the charges stored in the capacitors may leak in various forms over time, volatile memory devices periodically perform refresh operations. As the process for manufacturing memory devices shrinks and the intervals between word lines narrow, the influence of the charges of memory cells connected to another word line adjacent to the word line due to the voltage distribution of the word line increases. When one word line is intensively accessed, a row hammer phenomenon occurs, that is, data stored in memory cells connected to other word lines adjacent to the word line is lost due to the voltage of the activated state of one word line. Summary of the invention

[0007] The present disclosure provides a memory device configured to reduce the influence of the row hammer phenomenon and / or the occurrence rate of the row hammer phenomenon through effective row hammer processing.

[0008] The present disclosure also provides a memory system including a memory device, wherein the memory device is configured to reduce the influence of the row hammer phenomenon and / or the occurrence rate of the row hammer phenomenon through an effective row hammer processing.

[0009] Some aspects of the present inventive concept provide a memory device, which may include: a memory cell array having a plurality of memory cell rows; a row hammering processor configured to determine whether to perform a row hammering processing operation for refreshing adjacent memory cell rows among the plurality of memory cell rows adjacent to a first intensively accessed row; and a refresh manager configured to perform a normal refresh operation or a row hammering processing operation for sequentially refreshing the memory cell rows based on a determination result from the row hammering processor.

[0010] The row hammer processor may be configured to determine whether to perform a row hammer processing operation based on access to the memory cell array.

[0011] The row hammer processor may be configured to count the number of accesses to the memory cell array, wherein when the access count of the number of accesses to the memory cell array is equal to or greater than a first reference count, the determination result instructs the refresh manager to perform a row hammer processing operation.

[0012] The row hammer processor may be configured to count the number of accesses to the memory cell array during a reference time, wherein when the access count of the number of accesses to the memory cell array during the reference time is equal to or greater than a second reference count, a determination result instructs the refresh manager to perform a row hammer processing operation.

[0013] The row hammer processor may determine whether to perform a row hammer processing operation based on the number of accesses to the first region in the memory cell array.

[0014] The memory device may further include: a first memory configured to store an access table, wherein the access table includes access information about a first memory cell row group among the plurality of memory cell rows, wherein the row hammering processor determines whether to perform a row hammering processing operation based on the access table.

[0015] The row hammer processor may also be configured to obtain multiple access counts for at least some memory cell rows in the first memory cell row group, wherein when a sum of the multiple access counts is equal to or greater than a third reference count, a determination result instructs the refresh manager to perform a row hammer processing operation.

[0016] The row hammer processor may be further configured to obtain multiple access counts for at least some memory cell rows in the first memory cell row group, wherein when a weighted sum of the multiple access counts is equal to or greater than a fourth reference count, a determination result instructs the refresh manager to perform a row hammer processing operation.

[0017] When a row change count is equal to or greater than a fifth reference count, the determination result may instruct the refresh manager to perform a row hammering operation, wherein the row change count is the number of times addresses of memory cell rows included in the first memory cell row group are changed during a reference time.

[0018] The determination result may indicate that after the first row of hammer processing operations, the refresh manager performs a second row of hammer processing operations after N first normal refresh operations, wherein, after a preset event occurs, the determination result may indicate that the refresh manager performs a third row of hammer processing operations instead of at least one of the N first normal refresh operations, wherein N is a preset natural number.

[0019] The row hammer processor may determine whether to perform a row hammer processing operation based on a row hammer processing ratio between the number of normal refresh operations and the number of row hammer processing operations, wherein the row hammer processing processor is further configured to adjust the row hammer processing ratio based on the occurrence of a preset event.

[0020] The row hammering processor may be configured to adjust a time interval between a normal refresh operation and a row hammering operation based on the adjusted row hammering ratio.

[0021] According to some aspects of the inventive concept, there is provided a memory system, the memory system may include: a memory device including a memory cell array and a refresh manager, wherein the memory cell array includes a plurality of memory cell rows, the refresh manager is configured to refresh at least some of the plurality of memory cell rows; a memory controller is configured to output a command for performing access to the memory device to the memory device. The memory device may be configured to: perform a first row hammering operation for refreshing adjacent memory cell rows adjacent to a first row that is intensively accessed among the plurality of memory cell rows based on an access count that may be a result of counting accesses to the memory cell array.

[0022] The memory device may be configured to perform a second row hammering operation when a count of accesses to the memory cell array is equal to or greater than a first reference count.

[0023] The count of accesses to the memory cell array may be a count of accesses to a first region in the memory cell array, wherein the first region in the memory cell array is smaller than an entire region of the memory cell array.

[0024] The memory device may be configured to: after performing a first row hammering operation, perform a second row hammering operation after N first normal refresh operations occur, wherein the memory device is configured to: perform a third row hammering operation after a preset event occurs instead of at least one of the N first normal refresh operations, wherein N is a preset natural number.

[0025] The memory device may be configured to perform a first row hammering operation based on a row hammering ratio between the number of normal refresh operations performed and the number of row hammering operations performed, the memory device being configured to adjust the row hammering ratio in response to occurrence of a preset event.

[0026] The memory controller may include a row hammer processor configured to determine whether to perform a first row hammer processing operation.

[0027] According to some aspects of the present invention, there is provided a method for refreshing a memory device including a memory cell array, the method comprising: counting accesses to the memory cell array and generating an access count; comparing the access count with a reference count; and refreshing an adjacent memory cell row adjacent to a first row of intensive accesses when the access count is equal to or greater than the reference count, or sequentially refreshing a plurality of memory cell rows included in the memory cell array when the access count is less than the reference count.

[0028] Counting accesses to the memory cell array and generating the access count may include counting accesses to a first region in the memory cell array, wherein the first region in the memory cell array is smaller than an entire region of the memory cell array. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram illustrating a memory system according to some aspects of the present disclosure;

[0030] Figure 2 is a block diagram illustrating a memory device according to some aspects of the present disclosure;

[0031] Figure 3 is a flow chart illustrating the operation of a memory device according to some aspects of the present disclosure;

[0032] Figure 4 is a timing diagram illustrating the operation of a refresh manager according to some aspects of the present disclosure;

[0033] Figure 5A is a block diagram illustrating a row hammering processor according to some aspects of the present disclosure;

[0034] Figure 5B is a flow chart illustrating the operation of a row hammering processor according to some aspects of the present disclosure;

[0035] Fig. 6A is a block diagram illustrating a row hammering processor according to some aspects of the present disclosure;

[0036] Figure 6B is a flow chart illustrating the operation of a row hammering processor according to some aspects of the present disclosure;

[0037] Fig. 7A is a block diagram illustrating a row hammering processor according to some aspects of the present disclosure;

[0038] Figure 7B is a flow chart illustrating the operation of a row hammering processor according to some aspects of the present disclosure;

[0039] Fig. 8A is a block diagram illustrating a row hammering processor according to some aspects of the present disclosure;

[0040] Figure 8B and Figure 8C is an access table according to some aspects of the present disclosure;

[0041] Fig.8D is a flow chart illustrating the operation of a row hammering processor according to some aspects of the present disclosure;

[0042] Fig.9A is a diagram illustrating the operation of a row hammering processor according to some aspects of the present disclosure;

[0043] Fig. 9B is a flow chart illustrating the operation of a row hammering processor according to some aspects of the present disclosure;

[0044] Fig.10 is a block diagram illustrating a row hammering processor according to some aspects of the present disclosure;

[0045] Fig.11A is a block diagram illustrating a memory device according to some aspects of the present disclosure;

[0046] Fig. 11B is a flow chart illustrating the operation of a row hammering processor according to some aspects of the present disclosure;

[0047] FIG. 12A to FIG. 12C is a timing diagram illustrating the operation of a memory device according to some aspects of the present disclosure;

[0048] Fig.13A is a block diagram illustrating a memory device according to some aspects of the present disclosure;

[0049] Fig. 13B is a timing diagram illustrating the operation of a memory device according to some aspects of the present disclosure;

[0050] Fig.14 is a block diagram illustrating a memory system according to some aspects of the present disclosure;

[0051] Fig.15 is a block diagram illustrating a computer system according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0052] Figure 1 is a block diagram illustrating a memory system according to some aspects of the present disclosure.

[0053] Reference Figure 1 , a memory system 1 may include a memory device 10 and a memory controller 20 .

[0054] The memory controller 20 may provide various signals to the memory device 10 through the memory interface, thereby controlling the memory operation (e.g., writing and reading). For example, the memory controller 20 may access the data DATA of the memory cell array 160 by providing the command CMD and the address ADDR to the memory device 10. As an example, the command CMD may include an activation command for normal memory operation (e.g., writing and reading data), a precharge command, and / or a refresh command for a refresh operation. The activation command may represent a command for switching the state of the memory cell array 160 to an activation state so as to write data to the memory cell array 160 or read data from the memory cell array 160. According to the activation command, the memory cells included in the memory cell array 160 may be driven. Here, the term "access" may indicate that the memory cell row included in the memory cell array 160 is driven according to the activation command of the memory controller 20.

[0055] The precharge command may refer to a command for switching the state of the memory cell array 160 from an active state to a standby state after writing or reading data. The refresh command may refer to a command for performing a refresh operation on the memory cell array 160. The memory controller 20 may access the memory device 10 according to a request from a host outside the memory system 1. The memory controller 20 may communicate with the host by using various protocols.

[0056] The memory device 10 may be a memory device based on a semiconductor device. For example, the memory device 10 may be a random access memory (RAM) device, such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate (DDR) SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), and a resistive RAM (RRAM). In some aspects, the memory device 10 may be any memory device that requires a refresh operation. For example, some resistive memory devices that are or include non-volatile memories may perform a refresh operation, and thus, the memory device 10 may be a non-volatile memory device. The memory device 10 may receive and / or output data DATA via a data line, and / or the memory device 10 may perform a refresh operation in response to an address ADDR and a command CMD received from a memory controller 20. The memory device 10 may include a row hammering processor 120, a refresh manager 140, and a memory cell array 160.

[0057] The row hammer processor 120 may determine whether to perform a row hammer processing operation in response to a refresh command of the memory controller 20. In other words, the row hammer processor 120 may determine whether to perform a row hammer processing operation or a normal refresh operation in response to the refresh command of the memory controller 20, and the row hammer processor 120 may output the determined result to the refresh manager 140. Here, the "row hammer processing operation" may refer to an operation for reducing the influence of the row hammer phenomenon and / or the occurrence of the row hammer phenomenon by refreshing the memory cell rows adjacent to the intensively accessed memory cell rows, and the "normal refresh operation" may refer to an operation for sequentially refreshing the memory cell rows of the memory cell array 160. Here, the memory cell rows that are being intensively accessed may be referred to as intensively accessed memory cell rows, and the memory cell rows adjacent to the intensively accessed memory cell rows will be referred to as adjacent memory cell rows. For example, referring to FIG. 5A to FIG. 10 Some examples of determining rows of memory cells that are being intensively accessed are provided. Figure 1 An example embodiment is shown in which the row hammer processor 120 determines whether to perform a row hammer processing operation in response to a refresh command of the memory controller 20, but this is merely an example, and it should be understood that the inventive concept can also be applied to a self-refresh situation in which a refresh operation is periodically performed within the memory device 10.

[0058] The row hammer processor 120 according to the present disclosure may determine whether to perform a row hammer processing operation based on accesses to the memory cell array 160. In some embodiments, the row hammer processor 120 may determine whether to perform a row hammer processing operation based on an access count with respect to the memory cell array 160. In some embodiments, the row hammer processor 120 may determine whether to perform a row hammer processing operation based on an access count with respect to a specific region in the memory cell array 160. In some embodiments, the row hammer processor 120 may determine whether to perform a row hammer processing operation based on an access frequency, wherein the access frequency indicates an access count with respect to the memory cell array 160 or a portion or region of the memory cell array 160 during a reference time period. In some embodiments, the row hammer processor 120 may determine whether to perform a row hammer processing operation based on an access table including information about a densely accessed memory cell row or a memory cell row that has been densely accessed.

[0059] The refresh manager 140 may perform a row hammering operation or a normal refresh operation based on the result of the determination of the row hammering processor 120. When the row hammering processor 120 determines to perform the row hammering operation, the refresh manager 140 may refresh addresses corresponding to adjacent memory cell rows. When the row hammering processor 120 determines to perform the normal refresh operation, the refresh manager 140 may sequentially refresh a plurality of memory cell rows of the memory cell array 160.

[0060] The memory cell array 160 may include a plurality of memory cells. The plurality of memory cells may be located at points where a plurality of word lines and a plurality of bit lines intersect each other, respectively. The plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines. The plurality of memory cells may be arranged in a matrix form. Here, a "memory cell row" may represent a plurality of memory cells included in a single row among a plurality of memory cells. A plurality of word lines may be connected to a plurality of memory cell rows of the memory cell array 160, respectively.

[0061] Figure 2 is a block diagram illustrating a memory device according to various aspects of the present disclosure. Figure 1 Given the same description, the description will be omitted.

[0062] Reference Figure 2, the memory device 10 may include a control logic 100, a refresh manager 140, a memory cell array 160, a plurality of row decoders (e.g., first row decoders 220a to fourth row decoders 220d), a plurality of column decoders (e.g., first column decoders 230a to fourth column decoders 230d), an address buffer 250, a bank control logic 270, a row address selector 281, a column address latch 282, an input / output gating circuit 283, and a data input / output buffer 284. In addition, the memory cell array 160 may include a plurality of banks (e.g., first bank 160a to fourth bank 160d), and a plurality of sense amplifiers respectively corresponding to the banks 160a to 160d may be provided.

[0063] The memory device 10 may be a DRAM such as DDR SDRAM, low power DDR (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, and Rambus DRAM (RDRAM).

[0064] The control logic 100 may control the overall operation of the memory device 10, and may include a command decoder 110, a mode register 115, and a row hammer processor 120. The control logic 100 may be configured to receive a command CMD ( Figure 1 ) generates a control signal for performing a write operation or a read operation. In addition, the control logic 100 may generate a control signal for performing a write operation or a read operation according to a refresh command ( Figure 1 ) generates a control signal for performing a refresh operation on the first to fourth memory banks 160a to 160d. Alternatively, the control logic 100 may generate a control signal for performing a refresh operation on the first to fourth memory banks 160a to 160d in a self-refresh mode. The mode register 115 may include a plurality of registers for storing information for setting an operating environment of the memory device 10. The command decoder 110 may output an access signal or a refresh command corresponding to an access to the memory cell array 160 to the row hammer processor 120 based on the command CMD. For example, when the command CMD is an activate command, the command decoder 110 may output an access signal to the row hammer processor 120. When the command CMD is a refresh command, the command decoder 110 may output a refresh command to the row hammer processor 120.

[0065] The address buffer 250 may receive an address ADDR provided from the memory controller 20. The address ADDR may include a bank address BA. In addition, the address ADDR may include a row address ROW_ADDR for indicating a row of the memory cell array 160 and a column address COL_ADDR for indicating a column of the memory cell array 160. The row address ROW_ADDR may be provided to the first to fourth row decoders 220a to 220d via the row address selector 281, and the column address COL_ADDR may be provided to the first to fourth column decoders 230a to 230d via the column address latch 282. In addition, the bank address BA may be provided to the bank control logic 270. In some embodiments, the row address ROW_ADDR may be provided to the row hammer processor 120, and the row hammer processor 120 may determine whether to perform a row hammer processing operation based on the row address ROW_ADDR.

[0066] The bank control logic 270 may generate a bank control signal in response to the bank address BA. In addition, in response to the bank control signal, a row decoder corresponding to the bank address BA among the first row decoder 220a to the fourth row decoder 220d may be activated, and a column decoder corresponding to the bank address BA among the first column decoder 230a to the fourth column decoder 230d may be activated.

[0067] The row hammer processor 120 may output a row hammer process enable signal En_RHH to the refresh manager 140 in response to the refresh command. The refresh manager 140 may generate a refresh address REF_ADDR for selecting a memory cell row to be refreshed in the memory cell array 160 based on the row hammer process enable signal En_RHH. For example, when the row hammer processor 120 outputs a logic high as the row hammer process enable signal En_RHH for performing a row hammer process operation, the refresh manager 140 may output an address of a preset adjacent memory cell row as the refresh address REF_ADDR.

[0068] For example, when the row hammer processor 120 outputs a logic low as the row hammer process enable signal En_RHH for performing a normal refresh operation, the refresh manager 140 may sequentially generate refresh addresses REF_ADDR, wherein the value of the refresh address REF_ADDR may be increased by a counting operation of a counter included in the refresh manager 140. The row address selector 281 may be implemented as a multiplexer and may output a row address received from the memory controller 20 ( Figure 1 ) and may output a refresh address REF_ADDR generated by the refresh manager 140 during a refresh operation. As described herein (e.g., with reference to Figure 3), a refresh address REF_ADDR indicating a row to be refreshed may be generated within the memory device 10. However, in some embodiments, the refresh address REF_ADDR may be generated from the memory controller 20 ( Figure 1 ) directly provides the refresh address REF_ADDR.

[0069] Figure 3 is a flow chart illustrating the operation of a memory device according to aspects of the present disclosure.

[0070] Reference Figure 1 and Figure 3 , the memory device 10 may receive a refresh command from the memory controller 20 (operation S100). According to some example embodiments, the memory device 10 may perform a row hammering operation at fixed time intervals instead of a normal refresh operation in response to the refresh command. Therefore, the row hammering processor 120 may determine whether a hammering operation in response to the refresh command is to be performed (operation S200). When the row hammering processor 120 determines that this is a case of performing a row hammering operation, the memory device 10 may perform a row hammering operation by performing a refresh operation on an adjacent memory cell row (operation S400).

[0071] Otherwise, when the row hammering processor 120 determines that it is not a case of performing a row hammering process operation, the row hammering processor 120 may determine whether to perform an additional row hammering process operation (operation S300). In the case of performing an additional row hammering process operation, the memory device 10 may perform a row hammering process operation by performing a refresh operation on an adjacent memory cell row (operation S400). In the case of not performing an additional row hammering process operation, the memory device 10 may perform a normal refresh operation by sequentially refreshing a plurality of memory cell rows (operation S500).

[0072] Figure 4 is a timing diagram illustrating the operation of a refresh manager according to aspects of the present disclosure. In detail, Figure 4 It is shown that the memory device 10 may perform an additional row hammering operation RH2 in addition to the periodic row hammering operations (such as the row hammering operation RH1 , the row hammering operation RH3 , and the row hammering operation RH4 ) in some embodiments. Figure 4 An example embodiment is shown in which the memory device 10 performs the periodic row hammering operations RH1 , RH3 , and RH4 after performing six normal refresh operations REF.

[0073] Reference Figure 2 and Figure 4, when the row hammer process enable signal En_RHH received from the row hammer processor 120 is logic high, the refresh manager 140 may perform the row hammer process operations RH1 to RH4, and when the row hammer process enable signal En_RHH is logic low, the refresh manager 140 may perform the normal refresh operation REF. Although the example herein uses the above association, the present disclosure is not limited thereto, and in some embodiments, when the row hammer process enable signal En_RHH received from the row hammer processor 120 is logic low, the refresh manager 140 may perform the row hammer process operations RH1 to RH4, and when the row hammer process enable signal En_RHH is logic high, the refresh manager 140 may perform the normal refresh operation REF.

[0074] The row hammering processor 120 may convert the row hammering process enable signal En_RHH to a logic high to periodically perform the row hammering process operations RH1, RH3, and RH4 every six normal refresh operations REF. Correspondingly, the refresh manager 140 may periodically perform the row hammering process operations RH1, RH3, and RH4. According to the inventive concept, when a preset event Event occurs, although it may be a case of performing a normal refresh operation REF, the row hammering processor 120 may convert the row hammering process enable signal En_RHH to a logic high to perform the row hammering process operation RH2. Based on this, the refresh manager 140 may also perform the row hammering process operation RH2. The following will refer to FIG. 5A to FIG. 10 An example embodiment in which the row hammer processor 120 determines the occurrence of an event is described.

[0075] The memory device 10 according to the present disclosure may perform an additional row hammering operation RH2 in addition to the periodic row hammering operations RH1, RH3, and RH4 corresponding to or based on the occurrence of the detected event Event. The row hammering phenomenon may be reduced by adaptively performing the row hammering operation.

[0076] Figure 5A is a block diagram illustrating a row hammering processor according to aspects of the present disclosure.

[0077] Reference Figure 5A The row hammer processor 120a may include an access counter 121a and a row hammer process determiner 122a. The access counter 121a may be used to determine the memory cell array 160 ( Figure 1 ) and may output the access count CNT_Acc1 to the row hammer process determiner 122a. The row hammer process determiner 122a may generate a row hammer process enable signal En_RHH by comparing the access count CNT_Acc1 with the reference count CNT_Ref1 and may output the row hammer process enable signal En_RHH to the refresh manager 140 ( Figure 1 ). In some embodiments, the row hammering process determiner 122a may include a comparator.

[0078] Figure 5B is a flow chart illustrating the operation of a row hammering processor according to some aspects of the present disclosure. In detail, Figure 5B is an illustration of an operation for determining whether to perform an additional row hammering process operation (such as, Figure 3 Flowchart of an example embodiment of operation S300 in FIG.

[0079] Reference Figure 5A and Figure 5B The row hammer processor 120a may receive information including information about the memory cell array 160 ( Figure 1 ) of the access information Acc and the reference count CNT_Ref1 (operation S311). The row hammer processor 120a may generate the access count CNT_Acc1 by counting the access Acc (operation S312). The row hammer processor 120a may compare the access count CNT_Acc1 with the reference count CNT_Ref1 (operation S313). When the access count CNT_Acc1 is greater than the reference count CNT_Ref1, the row hammer processor 120a may output a logic high as the row hammer processing enable signal En_RHH, and thus the refresh manager 140 ( Figure 1 ) may perform a row hammering process operation (operation S400). Otherwise, when the access count CNT_Acc1 is not greater than the reference count CNT_Ref1, the row hammering processor 120a may output a logic low as the row hammering process enable signal En_RHH, and thus, the refresh manager 140 ( Figure 1 ) may perform a normal refresh operation (operation S500).

[0080] Fig. 6A is a block diagram illustrating a row hammering processor according to some aspects of the present disclosure. Figure 5A Given the same description, the description will be omitted.

[0081] Reference Fig. 6A The row hammering processor 120b may include an access counter 121b, a row hammering process determiner 122b, and a timer 123b. The timer 123b may output a reset signal Rst to the access counter 121b at every preset reference time. Therefore, the access counter 121b may reset the memory cell array 160 ( Figure 1 ) to count the access Acc to output the access count CNT_Acc2 to the row hammering process operation determiner 122b. The access count CNT_Acc2 may represent the access to the memory cell array 160 ( Figure 1The row hammer process determiner 122b may generate a row hammer process enable signal En_RHH by comparing the access count CNT_Acc2 with the reference count CNT_Ref2, and output the row hammer process enable signal En_RHH to the refresh manager 140 ( Figure 1 ).

[0082] Figure 6B is a flow chart illustrating the operation of a row hammering processor according to some aspects of the present disclosure. In detail, Figure 6B is an illustration of an operation for determining whether to perform an additional row hammering process operation (such as, Figure 3 Flowchart of an example embodiment of operation S300 in FIG.

[0083] Reference Fig. 6A and Figure 6B The row hammer processor 120a may receive information including information about the memory cell array 160 ( Figure 1 ) of the access information Acc and the reference count CNT_Ref2 (operation S321). The row hammer processor 120b may generate the access count CNT_Acc2 by counting the access Acc after the reset signal Rst (operation S322). The row hammer processor 120b may compare the access count CNT_Acc2 with the reference count CNT_Ref2 (operation S323). When the access count CNT_Acc2 is greater than the reference count CNT_Ref2, the row hammer processor 120b may output a logic high as the row hammer processing enable signal En_RHH, and thus the refresh manager 140 ( Figure 1 ) may perform a row hammering process operation (operation S400). Otherwise, when the access count CNT_Acc2 is not greater than the reference count CNT_Ref2, the row hammering processor 120b may output a logic low as the row hammering process enable signal En_RHH, and thus, the refresh manager 140 ( Figure 1 ) may perform a normal refresh operation (operation S500).

[0084] Fig. 7A is a block diagram illustrating a row hammering processor according to aspects of the present disclosure. Figure 5A Given the same description, the description will be omitted.

[0085] Reference Fig. 7A, the row hammer processor 120c may include an access counter 121c and a row hammer process determiner 122c. The access counter 121c may receive an access Acc, an address ADDR corresponding to the access Acc, and a first area Area1, and when the address ADDR is included in the first area Area1, the access counter 121c may count the access Acc corresponding to the address ADDR, thereby outputting the access count CNT_Acc3 to the row hammer process determiner 122c. The first area Area1 in the memory cell array is smaller than the entire area of ​​the memory cell array. The address ADDR may represent a first access to the memory cell array from the memory controller 20( Figure 1 ) received address ADDR. In other words, the access counter 121c may generate the access count CNT_Acc3 by counting only the access Acc with respect to the first area Area1. The row hammer process determiner 122c may generate the row hammer process enable signal En_RHH by comparing the access count CNT_Acc3 with the reference count CNT_Ref3, and output the row hammer process enable signal En_RHH to the refresh manager 140 ( Figure 1 ).

[0086] Figure 7B is a flow chart illustrating the operation of a row hammering processor according to aspects of the present disclosure. In detail, Figure 7B is an illustration of an operation for determining whether to perform an additional row hammering process operation (such as, Figure 3 Flowchart of an example embodiment of operation S300 in FIG.

[0087] Reference Fig. 7A and Figure 7B The row hammer processor 120c may receive information including information about the memory cell array 160 ( Figure 1 ), the address ADDR corresponding to the access Acc, the first area Area1, and the reference count CNT_Ref3 (operation S331). The row hammer processor 120c may determine whether the access Acc is an access to the first area Area1 based on the address ADDR, and generate an access count CNT_Acc3 by counting only the access Acc of the first area Area1 (operation S332). The row hammer processor 120c may compare the access count CNT_Acc3 with the reference count CNT_Ref3 (operation S333). When the access count CNT_Acc3 is greater than the reference count CNT_Ref3, the row hammer processor 120c may output a logic high as the row hammer processing enable signal En_RHH, and thus the refresh manager 140 ( Figure 1) may perform a row hammering process operation (operation S400). Otherwise, when the access count CNT_Acc3 is not greater than the reference count CNT_Ref3, the row hammering processor 120c may output a logic low as the row hammering process enable signal En_RHH, and thus, the refresh manager 140 ( Figure 1 ) may perform a normal refresh operation (operation S500).

[0088] Fig. 8A is a block diagram illustrating a row hammering processor according to aspects of the present disclosure. Figure 5A Given the same description, the description will be omitted.

[0089] Reference Fig. 8A , the row hammer process determiner 122d may include an access counter 121d, a row hammer process determiner 122d, and a memory 123d. The access counter 121d may receive an access Acc and an address ADDR corresponding to the access Acc, and count the access Acc corresponding to the address ADDR, thereby storing a row access count CNT in the memory 123d. The memory 123d may store an access table AT including information about the row access count CNT. The row hammer process determiner 122d may read the access table AT from the memory 123d, and generate an access count based on the access table AT. The row hammer process determiner 122d may generate a row hammer process enable signal En_RHH by comparing the access count with the reference count CNT_Ref4, and output the row hammer process enable signal En_RHH to the refresh manager 140 ( Figure 1 ).

[0090] Figure 8B and Figure 8C is an access table according to aspects of the present disclosure. In detail, Figure 8B and Figure 8C is a diagram showing an embodiment for generating the access count CNT_Acc4 in a different manner.

[0091] Reference FIG. 8A to FIG. 8C , the access table AT can store row access counts CNT for each memory cell row. In addition, the access table AT can sort the row access counts CNT in the order of ranking Rank, where the order of ranking Rank is the order of access density. In other words, Figure 8B and Figure 8C In an embodiment, access may become intensive in the order of the first memory cell row R1, the second memory cell row R2, the third memory cell row R3, and the fourth memory cell row R4. For example, the first memory cell row R1 may be the most intensively accessed row among the first memory cell row R1 to the fourth memory cell row R4.

[0092] Reference Figure 8B , the row hammer process determiner 122d may generate the access count CNT_Acc4 by adding the row access counts CNT corresponding to at least some of the memory cell rows Row of the access table AT. In one embodiment, at least some of the memory cell rows Row used to generate the access count CNT_Acc4 may be the top N (where N is a natural number) memory cell rows from Rank. In other words, the row hammer process determiner 122d may generate the access count CNT_Acc4 by adding the row access counts CNT corresponding to the most densely accessed N memory cell rows Row. Therefore, the row hammer process determiner 122d may generate "C1+C2+C3" as the access count CNT_Acc4, where "C1+C2+C3" is the sum of the row access counts C1, C2, and C3 corresponding to the three most densely accessed memory cell rows R1, R2, and R3, respectively.

[0093] Reference Figure 8C , the row hammer process determiner 122d may generate an access count CNT_Acc4 by a weighted sum of row access counts CNT corresponding to at least some memory cell rows Row of the access table AT. In some embodiments, the row hammer process determiner 122d may apply a higher weight to a higher-ranked memory cell row. The row hammer process determiner 122d may generate “a×C1+b×C2+c×C3” as the access count CNT_Acc4, where “a×C1+b×C2+c×C3” is a weighted sum of row access counts C1, C2, and C3 corresponding to the top three memory cell rows R1, R2, and R3. In addition, in some embodiments, a higher weight may be applied to a higher-ranked memory cell row, so that a may be a natural number greater than b, and b may be a natural number greater than c.

[0094] although Figure 8B and Figure 8C Embodiments are shown in which the access count CNT_Acc4 is generated using only the row access count CNT regarding three memory cell rows, but these embodiments are merely examples, and the inventive concept can also be applied to embodiments in which the access count CNT_Acc4 is generated using the row access count CNT based on less than or more than three memory cell rows.

[0095] Fig.8D is a flow chart illustrating the operation of a row hammering processor according to aspects of the present disclosure. In detail, Fig.8D is an illustration of an operation for determining whether to perform an additional row hammering process operation (such as, Figure 3 Flowchart of an example embodiment of operation S300 in FIG.

[0096] Reference Fig. 8A and Fig.8D The row hammer processor 120d may receive information including information about the memory cell array 160 ( Figure 1 ), an address ADDR corresponding to the access Acc, and a reference count CNT_Ref4 of access information of the row hammer processor 120d (operation S341). The row hammer processor 120d may generate an access table AT based on the address ADDR, and generate an access count CNT_Acc4 based on the generated access table AT (operation S342). In one embodiment, the row hammer processor 120d may generate the access count CNT_Acc4 by summing the top N (where N is a natural number) row access counts CNT. In another embodiment, the row hammer processor 120d may generate the access count CNT_Acc4 by a weighted sum of the top N (where N is a natural number) row access counts CNT. The row hammer processor 120d may compare the access count CNT_Acc4 with the reference count CNT_Ref4 (operation S343). When the access count CNT_Acc4 is greater than the reference count CNT_Ref4, then the row hammer processor 120d may output a logic high as the row hammer process enable signal En_RHH, and thus the refresh manager 140 ( Figure 1 ) may perform a row hammering process operation (operation S400). Otherwise, when the access count CNT_Acc4 is not greater than the reference count CNT_Ref4, then the row hammering processor 120d may output a logic low as the row hammering process enable signal En_RHH, and thus the refresh manager 140 ( Figure 1 ) may perform a normal refresh operation (operation S500).

[0097] Fig.9A is a diagram illustrating the operation of a row hammering processor according to aspects of the present disclosure.

[0098] Reference Fig. 8A and Fig.9A The hammer processor 120d may perform a hammering operation on the memory controller 20 ( Figure 1 ) to store the access table AT differently according to the number of accesses to each memory cell row of the memory controller 20 ( ). In other words, the memory cell row corresponding to the fourth rank in the access table AT can be accessed according to the number of accesses to each memory cell row of the memory controller 20 ( Figure 1 ). As an example, the memory cell row corresponding to the fourth rank in the first access table AT0 is the fourth memory cell row R4. However, thereafter, when the fifth memory cell row R5 is intensively accessed (e.g., more intensively accessed than the fourth memory cell row R4), then as shown in the second access table AT1, the memory cell row corresponding to the fourth rank may be changed to the fifth memory cell row R5.

[0099] The row hammering processor 120d may count the number of times the row of memory cells corresponding to the lowest rank and / or the number of times the lowest rank of the access table AT is changed as described above. Fig.9A In the embodiment of the present invention, when the first access table AT0 is changed to the second access table AT1, the row hammer processor 120d may count the row change count RCC to "1". When the fourth rank is changed n times in the above manner, the row hammer processor 120d may count the row change count RCC to "n".

[0100] According to some embodiments, the row hammer processor 120d may determine whether to perform a row hammer processing operation by comparing the row change count RCC with a reference count.

[0101] Fig. 9B is a flow chart illustrating the operation of a row hammering processor according to aspects of the present disclosure. In detail, Fig. 9B is an illustration of an operation for determining whether to perform an additional row hammering process operation (such as, Figure 3 Flowchart of an example embodiment of operation S300 in FIG.

[0102] Reference Fig.9A and Fig. 9B The hammer processor 120d can be used as above. Fig.9A The row change count for the lowest ranking of the access table is generated in the manner described in (operation S351). The row hammer processor 120d may compare the row change count with the reference count (operation S352). When the row change count is greater than the reference count, the row hammer processor 120d may output a logic high as the row hammer processing enable signal En_RHH, and thus the refresh manager 140 ( Figure 1 ) may perform a row hammering process operation (operation S400). Otherwise, when the row change count is not greater than the reference count, the row hammering processor 120d may output a logic low as the row hammering process enable signal En_RHH, and thus, the refresh manager 140 ( Figure 1 ) may perform a normal refresh operation (operation S500).

[0103] although Fig. 9B An example of an embodiment for determining whether to perform a row hammering operation by using a row change count for a lowest rank is shown, but this is merely an example, and the inventive concept may also be applied to an embodiment for determining whether to perform a row hammering operation by using a row change count for a rank different from the lowest rank.

[0104] Fig.10 is a block diagram illustrating a row hammering processor according to aspects of the present disclosure. Figure 5A Given the same description, the description will be omitted.

[0105] Reference Fig.10 The row hammering processor 120e may include a temperature sensor 123e and a row hammering process determiner 122e. The temperature sensor 123e may sense the temperature of the memory device 10( Figure 1 ) and outputs the sensed temperature T_MD to the row hammer process determiner 122e. The row hammer process determiner 122e may generate a row hammer process enable signal En_RHH by comparing the sensed temperature T_MD with the reference temperature T_Ref1, and output the row hammer process enable signal En_RHH to the refresh manager 140 ( Figure 1 In one embodiment, when the sensed temperature T_MD is higher than the reference temperature T_Ref1, the row hammering processor 120d may output a logic high as the row hammering process enable signal En_RHH, and thus, the refresh manager 140 ( Figure 1 ) can perform hammering operations.

[0106] When the sensed temperature T_MD is not higher than the reference temperature T_Ref1, the row hammering processor 120d may output a logic low as the row hammering process enable signal En_RHH, and thus the refresh manager 140 ( Figure 1 ) can perform normal refresh operations.

[0107] Fig.11A is a block diagram illustrating a memory device according to aspects of the present disclosure.

[0108] Reference Fig.11A , the memory device 10f may include a row hammer processor 120f and a refresh manager 140f. The row hammer processor 120f may determine a row hammer processing ratio rRHH of the row hammer processing enable signal En_RHH based on the access Acc. Here, the row hammer processing ratio rRHH may represent a ratio between the number of row hammer processing operations and the number of normal refresh operations. When more row hammer processing operations need to be performed as the row hammer phenomenon becomes more intense and / or more frequent, the row hammer processing ratio rRHH may be increased by the row hammer processor 120f. On the other hand, when fewer row hammer processing operations need to be performed as the row hammer phenomenon decreases and / or is less frequent, the row hammer processing ratio rRHH may be reduced by the row hammer processor 120f.

[0109] The hammering processor 120f can be operated as described above. FIG. 5A to FIG. 10 The row hammering ratio rRHH is determined by an operation similar to the operation described above for determining whether to perform an additional row hammering operation. FIG. 5A to FIG. 6B Similar to the operation described above, the row hammering processor 120f may be based on the memory cell array 160 ( Figure 1) is accessed or the access frequency is determined by the row hammering processor 120f. For example, when the number of accesses is greater than the first reference count, the row hammering processor 120f may increase the row hammering processing ratio rRHH, and when the number of accesses is less than the second reference count, the row hammering processor 120f may decrease the row hammering processing ratio rRHH. For example, when the access frequency is greater than the third reference count, the row hammering processor 120f may increase the row hammering processing ratio rRHH, and when the access frequency is less than the fourth reference count, the row hammering processor 120f may decrease the row hammering processing ratio rRHH.

[0110] In some embodiments, according to the reference Fig. 7A and Figure 7B Similar to the operation described above, the row hammering processor 120f may be based on the memory cell array 160 ( Figure 1 ) in a particular area in the row hammering process ratio rRHH. In some embodiments, the row hammering process ratio rRHH is determined by comparing the row hammering process ratio rRHH with the reference FIG. 8A to FIG. 9B Similar to the operation described above, the row hammering processor 120f may determine the row hammering ratio rRHH based on an access table including information about intensively accessed rows of memory cells. Fig.10 In operations similar to those described above, the row hammering processor 120f may determine a row hammering ratio rRHH based on the temperature of the memory device.

[0111] Fig. 11B is a flow chart illustrating the operation of a row hammering processor according to aspects of the present disclosure.

[0112] Reference Fig.11A and Fig. 11B , the row hammering processor 120f may determine the row hammering processing ratio rRHH (operation S600). Fig.11A As described above, the hammering processor 120f can be used as described above. FIG. 5A to FIG. 10 The row hammering process ratio rRHH is determined similarly to the operation of determining whether to perform an additional row hammering process operation as described above. The row hammering processor 120f may output a row hammering process enable signal En_RHH to the refresh manager 140f based on the determined row hammering process ratio rRHH, and the refresh manager 140f may perform a normal refresh operation or a row hammering process operation based on the row hammering process enable signal En_RHH (operation S700).

[0113] FIG. 12A to FIG. 12C is a timing diagram illustrating the operation of a memory device according to aspects of the present disclosure. In detail, FIG. 12A to FIG. 12C An example of an embodiment in which a memory device changes a row hammering ratio in response to an event is shown.

[0114] Reference Fig.11A and Fig. 12A When the preset event Event occurs, the row hammering processor 120f may increase the row hammering processing ratio rRHH. Fig. 12A In an embodiment, before the preset event Event occurs, the memory device 10f may have a row hammering ratio rRHH of 1 / 5 for performing the row hammering operations RH1 and RH2 once for every five refresh operations REF. When the preset event Event occurs, the memory device 10f may increase the row hammering ratio rRHH to 1 / 2, and the memory device 10f may perform the row hammering operations RH3 and RH4 once for every two refresh operations REF based on the modified row hammering ratio rRHH. In some embodiments, the preset event Event may indicate a case where the number of accesses becomes greater than the reference count. In some embodiments, the preset event Event may indicate a case where the access frequency becomes greater than the reference count.

[0115] Reference Fig.11A and Fig. 12B When the preset event Event occurs, the row hammering processor 120f can reduce the row hammering processing ratio rRHH. Fig. 12B In an embodiment, before the preset event Event occurs, the memory device 10f may have a row hammering ratio rRHH of 1 / 2 for performing the periodic row hammering operations RH1, RH2, and RH3 once for every two refresh operations REF. When the preset event Event occurs, the memory device 10f may reduce the row hammering ratio rRHH to 1 / 5, and the memory device 10f may perform the periodic row hammering operation RH4 once for every five refresh operations REF based on the modified row hammering ratio rRHH. In some embodiments, the preset event Event may indicate a case where the number of accesses becomes less than a reference count. In some embodiments, the preset event Event may indicate a case where the access frequency becomes less than a reference count.

[0116] Reference Fig.11A and Fig. 12C When the preset event Event occurs, the row hammering processor 120f may change the row hammering processing ratio rRHH to 0. Fig. 12CIn an embodiment, before the preset event Event occurs, the memory device 10f may have a row hammering ratio rRHH of 1 / 2 for performing the periodic row hammering operations RH1, RH2, and RH3 for every two refresh operations REF. When the preset event Event occurs, the memory device 10f may reduce the row hammering ratio rRHH to 0, and thus, the memory device 10f may temporarily or permanently stop performing the periodic row hammering operations. In some embodiments, the preset event Event may indicate a situation where the number of accesses becomes less than a reference count. In some embodiments, the preset event Event may indicate a situation where the access frequency becomes less than a reference count.

[0117] Fig.13A is a block diagram illustrating a memory device according to aspects of the present invention.

[0118] Reference Fig.13A , the memory device 10g may include a row hammering processor 120g and a refresh manager 140g. The row hammering processor 120g may determine a row hammering process ratio rRHH and a time interval int of a row hammering process enable signal En_RHH based on an access Acc. Here, the time interval int may represent a time interval between a normal refresh operation and / or a row hammering process operation. As the row hammering process ratio rRHH changes, a refresh time for one memory cell row may be changed. According to some example embodiments, the memory device 10g may maintain a refresh time even when the row hammering process ratio rRHH is changed by adjusting the time interval int.

[0119] The row hammer processor 120g may determine the time interval int based on the row hammer process ratio rRHH. In one embodiment, the row hammer process ratio rRHH may be inversely proportional to the time interval int. The row hammer process processor 120g may output a row hammer process enable signal En_RHH to the refresh manager 140g based on the row hammer process ratio rRHH and the time interval int.

[0120] Fig. 13B is a timing diagram illustrating the operation of a memory device according to aspects of the present disclosure. In detail, Fig. 13B An embodiment is shown in which a memory device changes row hammering rates and time intervals in response to events.

[0121] Reference Fig.13A and Fig. 13B When the preset event Event occurs, the row hammer processor 120g may increase the row hammer processing ratio rRHH. In addition, the row hammer processor 120g may determine the time interval int based on the row hammer processing ratio rRHH. Fig. 13BIn an embodiment of the present invention, before the event Event occurs, the memory device 10g may have a row hammering process ratio rRHH of 1 / 5 for performing the row hammering process operations RH1 and RH2 once for every five refresh operations REF and a first time t1 as a time interval int. When the preset event Event occurs, the memory device 10g may increase the row hammering process ratio rRHH to 1 / 2 and determine the second time t2 as the time interval int based on the row hammering process ratio rRHH. The memory device 10g may perform a plurality of row hammering process operations RH3 and RH4 and a plurality of refresh operations REF based on the modified row hammering process ratio rRHH and the time interval int.

[0122] Fig.14 is a block diagram illustrating a memory system according to aspects of the present disclosure. Figure 1 Given the same description, the description will be omitted.

[0123] Reference Fig.14 The memory system 1h may include a memory device 10h and a memory controller 20h. The memory controller 20h may include a row hammer processor 120h. The row hammer processor 120h may be as described above. Figures 1 to 13B The refresh manager 140h includes a memory device 10h and a refresh manager 140h. ...

[0124] Fig.15 is a block diagram illustrating a computer system according to aspects of the present disclosure.

[0125] Reference Fig.15 , the computer system 1900 may be installed on a mobile device, a desktop computer, etc. The computer system 1900 may include a DRAM memory system 1901, a CPU 1905, a user interface 1907, and a modem 1908 (e.g., a baseband chipset) electrically connected to a system bus 1904. The computer system 1900 may also be provided with an application chipset, a camera image processor (CIS), an input / output device, etc.

[0126] The user interface 1907 may be an interface for sending data to or receiving data from a communication network. The user interface 1907 may be a wired interface or a wireless interface, and may include an antenna or a wired / wireless transceiver. The data provided via the user interface 1907 or the modem 1908 or the data processed by the CPU 1905 may be stored in the DRAM memory system 1901.

[0127] DRAM memory system 1901 may include the Figures 1 to 14 DRAM memory system 1901 may include DRAM 1902 and memory controller 1903. DRAM 1902 stores data processed by CPU 1905 or input from the outside. DRAM 1902 may determine whether to perform an additional row hammering operation and adjust the number of row hammering operations for the memory cell array based on this.

[0128] When the computer system 1900 is a device for performing wireless communication, the computer system 1900 can be used in a communication system such as, for example, a code division multiple access (CDMA) system, a global system for mobile communications (GSM), a North American multiple access (NADC) system, a time division multiple access (TDMA) system, and / or a CDMA2000 system. The computer system 1900 can be installed in an information processing device such as, for example, a personal digital assistant (PDA), a portable computer, a web tablet, a digital camera, a portable media player (PMP), a mobile phone, a wireless phone, or a laptop computer.

[0129] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cell rows; a row hammer processor configured to determine whether to perform a row hammer processing operation for refreshing an adjacent memory cell row among the plurality of memory cell rows adjacent to a first memory cell row that is intensively accessed among the plurality of memory cell rows to generate a determination result; a refresh manager configured to perform a normal refresh operation or a row hammering operation for sequentially refreshing the plurality of memory cell rows based on the determination result, The refresh manager is configured to: periodically perform a row hammering operation, and based on the occurrence of a preset event, perform an additional row hammering operation in addition to the periodic row hammering operation, The row hammering processor is configured to determine whether to perform an additional row hammering processing operation by: The number of accesses to a specific area of ​​a memory cell array is counted, the specific area including all or at least two rows of the multiple memory cell rows, wherein when the access count of the number of accesses to the specific area is equal to or greater than a first reference count, a determination result instructs a refresh manager to perform an additional row hammering operation, and when the access count of the number of accesses to the specific area is less than the first reference count, the determination result instructs the refresh manager to perform a normal refresh operation for sequentially refreshing the multiple memory cell rows.

2. The memory device according to claim 1, wherein: The row hammer processor is configured to count the number of accesses to a specific area of ​​the memory cell array during a reference time, wherein when the access count of the number of accesses to the specific area of ​​the memory cell array during the reference time is equal to or greater than a second reference count, a determination result instructs the refresh manager to perform additional row hammer processing operations.

3. The memory device according to claim 1, wherein: The row hammer processor determines whether to perform an additional row hammer processing operation based on an access count of the number of accesses to a first area in the memory cell array, wherein the first area in the memory cell array is smaller than an entire area of ​​the memory cell array.

4. The memory device according to claim 1, further comprising: a first memory configured to store an access table, wherein the access table includes access information about a first memory cell row group among the plurality of memory cell rows, The row hammer processor determines whether to perform additional row hammer processing operations based on the access information.

5. The memory device according to claim 4, wherein: The row hammer processor is further configured to obtain multiple access counts for at least some memory cell rows in the first memory cell row group, wherein when a sum of the multiple access counts is equal to or greater than a third reference count, a determination result instructs the refresh manager to perform additional row hammer processing operations.

6. The memory device according to claim 4, wherein: The row hammer processor is also configured to obtain multiple access counts for at least some memory cell rows in the first memory cell row group, wherein when a weighted sum of the multiple access counts is equal to or greater than a fourth reference count, a determination result instructs the refresh manager to perform additional row hammer processing operations.

7. The memory device according to claim 4, wherein: When a row change count is equal to or greater than a fifth reference count, the determination result instructs the refresh manager to perform an additional row hammering operation, wherein the row change count is the number of times addresses of memory cell rows included in the first memory cell row group are changed during a reference time.

8. The memory device according to claim 1, wherein: The determination result indicates that after the first row of hammer processing operations, the refresh manager performs a second row of hammer processing operations after the execution of N first normal refresh operations, wherein, after the occurrence of a preset event, the determination result indicates that the refresh manager performs a third row of hammer processing operations instead of at least one of the N first normal refresh operations, wherein N is a preset natural number.

9. The memory device according to claim 1, wherein: The row hammer processor determines whether to perform a row hammer processing operation based on a row hammer processing ratio between the number of normal refresh operations and the number of row hammer processing operations, wherein the row hammer processing is further configured to adjust the row hammer processing ratio based on the occurrence of a preset event.

10. The memory device according to claim 9, wherein: The row hammer processor is configured to adjust a time interval between a normal refresh operation and a row hammer processing operation based on the adjusted row hammer processing ratio.

11. A memory system comprising: A memory device comprising a memory cell array and a refresh manager, wherein the memory cell array comprises a plurality of memory cell rows, and the refresh manager is configured to refresh at least some of the plurality of memory cell rows; a memory controller configured to output a command for executing access to the memory device to the memory device, wherein the memory device is configured to: periodically perform a row hammering operation for refreshing adjacent memory cell rows of the plurality of memory cell rows adjacent to a first memory cell row of intensive access among the plurality of memory cell rows, and based on the occurrence of a preset event, perform an additional row hammering operation outside the periodic row hammering operation, The memory device is configured to determine whether to perform an additional row hammering operation by: When a count of accesses to a specific area of ​​a memory cell array is equal to or greater than a first reference count, an additional row hammering operation is performed based on the count of accesses to the memory cell array, and when the count of accesses to the specific area is less than the first reference count, the plurality of memory cell rows included in the memory cell array are sequentially refreshed, wherein the specific area includes all or at least two of the plurality of memory cell rows.

12. The memory system according to claim 11, wherein: The count of accesses to the memory cell array is a count of accesses to a first region in the memory cell array, wherein the first region in the memory cell array is smaller than an entire region of the memory cell array.

13. The memory system according to claim 11, wherein: The memory device is configured to: after performing a first row hammering processing operation, perform a second row hammering processing operation after N first normal refresh operations occur, wherein the memory device is configured to: perform a third row hammering processing operation instead of at least one of the N first normal refresh operations after an occurrence of a preset event, wherein N is a preset natural number.

14. The memory system according to claim 11, wherein: The memory device is configured to perform a row hammering operation based on a row hammering ratio between the number of normal refresh operations performed and the number of row hammering operations performed, and the memory device is configured to adjust the row hammering ratio in response to occurrence of a preset event.

15. The memory system according to claim 11, wherein: The memory controller includes a row hammer processor configured to determine whether to perform a row hammer processing operation.

16. A method of refreshing a memory device comprising a memory cell array, the method comprising: periodically performing a row hammering operation for refreshing a neighboring memory cell row neighboring a first intensively accessed row among a plurality of memory cell rows included in a memory cell array, and performing an additional row hammering operation other than the periodic row hammering operation based on occurrence of a preset event; Among them, whether to perform additional row hammering processing operations is determined by the following method: counting accesses to the memory cell array and generating an access count; Compare the access count to the reference count; When the access count is equal to or greater than the reference count, an additional row hammering process operation is performed, or when the access count is less than the reference count, the plurality of memory cell rows included in the memory cell array are sequentially refreshed.

17. The method according to claim 16, wherein: The step of counting accesses to the memory cell array and generating an access count includes counting accesses to a first area in the memory cell array, wherein the first area in the memory cell array is smaller than the entire area of ​​the memory cell array.

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