Resistive memory device with calibrated reference resistor

Abstract

A resistive memory device of a calibration reference resistor is disclosed. The resistive memory device configured as a calibration reference resistor includes: a calibration resistor circuit including a calibration resistor; a first reference resistor; a first sense amplifier configured to compare input currents; a first switch group including a plurality of switches; and a controller configured to control the first switch group to allow the first sense amplifier to compare a first reference current passing through the first reference resistor with a first read current passing through a first memory cell during a read operation, and to compare the first reference current with a first calibration current passing through the calibration resistor during a calibration operation. The path of the first reference current during the read operation is different from the path of the first reference current during the calibration operation.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2018-0055046 filed on May 14, 2018, and Korean Patent Application No. 10-2018-0111020 filed on September 17, 2018, respectively, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Exemplary embodiments of the inventive concept relate to a resistive memory device, and more particularly, to a resistive memory device providing reference calibration and an operating method of the resistive memory device. Background Art

[0003] A resistive memory device is capable of storing data in a memory cell including a variable resistance element. In order to detect data stored in a memory cell of the resistive memory device, for example, a read current or a read voltage may be provided to the memory cell, and a corresponding read voltage or a read current changed by the variable resistance element of the memory cell may be detected. A reference resistance for determining the resistance of the variable resistance element may change due to changes in process, voltage, temperature, etc., and such a change in the reference resistance may reduce the reliability of a read operation in the resistive memory device. Summary of the invention

[0004] According to an exemplary embodiment of the inventive concept, a resistive memory device configured as a calibration reference resistor may include: a calibration resistor circuit including a calibration resistor; a first reference resistor; a first sense amplifier configured to compare a plurality of input currents; a first switch group including a plurality of switches; and a controller configured to control the first switch group to allow the first sense amplifier to compare a first reference current passing through the first reference resistor with a first read current passing through a first memory cell during a read operation, and to compare the first reference current with a first calibration current passing through the calibration resistor during a calibration operation. The path of the first reference current during the read operation may be different from the path of the first reference current during the calibration operation.

[0005] According to an exemplary embodiment of the inventive concept, a resistive memory device configured to calibrate a plurality of reference resistors may include: a calibration resistor; a plurality of reference resistors; a plurality of sense amplifiers, each configured to compare a reference current passing through one of the plurality of reference resistors with a read current passing through a memory cell during a read operation, and to compare the reference current with a calibration current passing through the calibration resistor during a calibration operation; and a plurality of switches configured to form a second path during the calibration operation to allow the reference current to pass through the second path. The second path may have substantially the same length as the first path, wherein the calibration current passes through the first path between the plurality of sense amplifiers and the calibration resistor.

[0006] According to an exemplary embodiment of the inventive concept, a resistive memory device configured to calibrate a plurality of reference resistors may include: a calibration resistor; a plurality of read circuits each configured to compare a reference current passing through one of the plurality of reference resistors with a read current passing through a memory cell during a read operation, and to compare the reference current with a calibration current passing through the calibration resistor during a calibration operation; a first conductive line connected to the plurality of read circuits and the calibration resistor and configured to allow the calibration current to pass through the first conductive line during the calibration operation; and a second conductive line connected to the plurality of read circuits and configured to allow the reference current to pass through the second conductive line during the calibration operation. The first conductive line and the second conductive line may have substantially the same length as each other.

[0007] According to an exemplary embodiment of the present invention, a resistive memory device configured as a calibration reference resistor may include: a calibration resistor circuit including a calibration resistor; a first reference resistor; a first sense amplifier including a first input terminal and a second input terminal; a first wire and a second wire connected to the calibration resistor circuit; and a switch group including a first switch and a second switch. The second input terminal of the first sense amplifier may be connected to the first reference resistor. The first switch may be configured to connect the first input terminal of the first sense amplifier to the calibration resistor via the first wire. The second switch may be configured to connect the first reference resistor and the second wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0009] Figure 1 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept.

[0010] Figure 2 is a diagram showing an exemplary embodiment of the present invention including Figure 1Schematic diagram of a memory cell in a cell array.

[0011] Figure 3 is a graph illustrating resistance distribution provided by a memory cell according to an exemplary embodiment of the inventive concept.

[0012] Figure 4 is a circuit diagram illustrating a sense amplifier according to an exemplary embodiment of the inventive concept.

[0013] Figure 5A and Figure 5B is a circuit diagram illustrating an equivalent circuit of a read circuit and its surrounding circuits according to an exemplary embodiment of the inventive concept.

[0014] Fig. 6A and Figure 6B is a circuit diagram illustrating a memory device that performs a calibration operation using one wire according to a comparative example.

[0015] Fig. 7A and Figure 7B is a circuit diagram illustrating a memory device that performs a calibration operation using two conductive lines according to an exemplary embodiment of the inventive concept.

[0016] Figure 8 is a circuit diagram illustrating a portion of a memory device according to an exemplary embodiment of the inventive concept.

[0017] Fig. 9 is a circuit diagram illustrating a portion of a memory device according to an exemplary embodiment of the inventive concept.

[0018] Fig.10 is a circuit diagram illustrating a portion of a memory device according to an exemplary embodiment of the inventive concept.

[0019] Fig.11 is a circuit diagram illustrating a portion of a memory device according to an exemplary embodiment of the inventive concept.

[0020] Fig. 12A is a side view schematically illustrating a portion of a memory device according to an exemplary embodiment of the inventive concept, Fig. 12B is a schematic diagram showing an exemplary embodiment according to the inventive concept Fig. 12A A circuit diagram of a portion of a memory device.

[0021] Fig.13 is a diagram illustrating conductive lines according to an exemplary embodiment of the inventive concept.

[0022] Fig.14 is a flowchart illustrating a method of calibrating a reference in a memory device according to an exemplary embodiment of the inventive concept.

[0023] Fig.15 is a diagram showing an exemplary embodiment according to the inventive concept Fig.14 Flowchart of the operation of a method of calibrating a read circuit.

[0024] Fig.16 is a circuit diagram illustrating a portion of a memory device according to an exemplary embodiment of the inventive concept.

[0025] Fig.17 is a block diagram illustrating a memory system including a memory device according to an exemplary embodiment of the inventive concept.

[0026] Fig.18 is a block diagram illustrating a system on chip including a memory device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0027] Exemplary embodiments of the inventive concept provide a resistive memory device, and more particularly, provide a resistive memory device capable of accurately reading a value stored in a memory cell by providing accurate reference calibration, and an operating method of the resistive memory device.

[0028] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings.Throughout the application, like reference numerals may denote like elements.

[0029] Figure 1 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept. Specifically, Figure 1 A cell array 11 , a row decoder 12 , a column decoder 13 , a read circuit 14 , a calibration resistor circuit 15 , and a controller 16 , which are some elements included in the memory device 10 , are shown.

[0030] The memory device 10 may receive commands and addresses externally, and may receive or output data. For example, the memory device 10 may receive a command (such as a write command or a read command) and an address corresponding to the command. The memory device 10 may receive data in response to a write command, and may output data in response to a read command. In an exemplary embodiment of the present invention, commands, addresses, and data may be received or sent via independent channels. In an exemplary embodiment of the present invention, at least two of the commands, addresses, and data may be received or sent via the same channel.

[0031] The cell array 11 may include a plurality of memory cells (eg, M ij ). The memory cell Mij may include a variable resistance element (eg, Figure 2 MTJ), and the variable resistance element may have aij The resistance corresponding to the value in . Therefore, the memory device 10 may be referred to as a resistive memory device or a resistive random access memory (RRAM) (or ReRAM) device. For example, as a non-limiting example, the memory device 10 may include a cell array 11 having a structure of a phase change random access memory (PRAM), a ferroelectric random access memory (FRAM), etc. In an exemplary embodiment of the present inventive concept, the memory device 10 may include a cell array 11 having a structure of a magnetic random access memory (MRAM) (such as a spin transfer torque magnetic random access memory (STT-MRAM), a spin torque transfer magnetization switch RAM (Spin-RAM), or a spin momentum transfer RAM (SMT-RAM)). Although the exemplary embodiments of the present inventive concept will be described mainly with reference to MRAM (as will be described below with reference to Figure 2 and Figure 3 However, it should be noted that the present invention is not limited thereto.

[0032] like Figure 1 As shown in FIG. 1 , the memory cell M ij Can be connected to word line WL i , and can be connected to the source line SL j and bit line BL j In order to detect the presence of a signal included in the memory cell M during a read operation ij In an exemplary embodiment of the present inventive concept, the resistance of the variable resistance element in the memory cell M can be determined by applying a predetermined current to the memory cell M. ij To detect the memory cell M ij In an exemplary embodiment of the present inventive concept, a predetermined voltage may be applied to the memory cell M. ij To detect the memory cell M ij In an exemplary embodiment of the present inventive concept, both current and voltage may be detected.

[0033] Although the following will mainly refer to the process of generating a voltage by setting a predetermined voltage (e.g., a read voltage (e.g., V RD1 To V RDn )) is applied to the memory cell M ij To detect the memory cell M ij The current generated in (e.g., the reading current (e.g., I RDk ))'s operations are used to describe exemplary embodiments of the present inventive concept, but it will be understood that the present inventive concept is not limited thereto.

[0034] The row decoder 12 may activate one of the plurality of word lines WL according to an address received together with a read command, and a memory cell connected to the activated word line may be selected. iWhen activated, the memory cell M ij can be selected and read the current I RDk The source line SL j Flow through the memory cell M ij Arrives at bit line BL j In exemplary embodiments of the inventive concept, memory cells selected by one word line or data stored in such memory cells may be referred to as a page.

[0035] The column decoder 13 may select a word line WL connected to the activated word line WL in the memory cell according to the address received together with the read command. i For example, some memory cells connected to word line WL i n memory cells (where n is a positive integer) are selected from among the memory cells, and the selected n memory cells may be connected to the read circuit 14 through source lines and bit lines.

[0036] During the read operation, the read circuit 14 can generate a read voltage V RD1 To V RDn For example, the kth read circuit in the read circuit 14 can read the voltage V RDk Provided to memory unit M ij (where 1≤k≤n), therefore, after passing through the memory unit M ij The read current I RDk The kth reading circuit may be based on the reading current I RDk The detection includes the memory cell M ij The resistance of the variable resistance element in the controller can be detected, and a signal corresponding to the detected resistance can be output.

[0037] In an exemplary embodiment of the inventive concept, the kth reading circuit can read the current I RDk The resistance of the variable resistance element is detected by comparing the size of the reference current with the size of the reference current. Therefore, when the size of the reference current changes, the resistance of the variable resistance element is detected by comparing the size of the reference current with the size of the reference current. ij The value read may include errors. Figure 1 Only the read circuit 14 is shown, but the memory device 10 may also include a read circuit 14 for reading the memory cell M. ij A write circuit provides a write current and / or a write voltage. In an exemplary embodiment of the inventive concept, the memory device 10 may include a write / read circuit having a write circuit and a read circuit implemented as one block.

[0038] As will be referred to below Figure 5A and Figure 5BAs described above, each read circuit 14 may include a reference resistor for generating a reference current. The reference resistor included in the read circuit 14 may have different resistances due to changes in process, voltage, temperature, etc. In order to have a desired resistance (e.g., reference resistance) through such a reference resistor, the memory device 10 may include a calibration resistor circuit 15, and the controller 16 may control an operation of adjusting the resistance of the reference resistor to a desired resistance (e.g., an operation of calibrating the reference resistor). In this specification, the operation of adjusting the resistance of the reference resistor included in the read circuit 14 may be referred to as a calibration operation.

[0039] The calibration resistor circuit 15 may include a calibration resistor (e.g., Figure 5A In addition, during the calibration operation, the calibration resistor circuit 15 can receive the calibration current I from the reading circuit 14 through the first conductive line CL1. CAL , and can receive the reference current I from the reading circuit 14 through the second wire CL2 REF . Calibration current I CAL The reference current I REF The reference resistor may be provided to the calibration resistor circuit 15 via a reference resistor included in one of the read circuits 14. 6A to 7B As described above, the first conductive line CL1 and the second conductive line CL2 may have substantially the same or identical structure, and when the reference current I REF When the calibration current I flows into the calibration resistor circuit 15 through the second wire CL2, the calibration current I CAL and reference current I REF The deviation between the flow paths can be reduced. Therefore, when the reference current I REF The size of the calibration current I CAL When the sizes of are matched, the resistance of the reference resistor may match the resistance of the calibration resistor (eg, the calibration resistor (or a resistor including a constant offset from the calibration resistor)).

[0040] like Figure 1 As shown in , the first conductive line CL1 and the second conductive line CL2 may extend across the read circuit 14 and may have substantially the same structure as each other. In an exemplary embodiment of the inventive concept, the first conductive line CL1 and the second conductive line CL2 may have substantially the same length, may be a pattern formed in the same wiring layer, and / or may extend substantially parallel to each other. In addition, as will be described below with reference to Fig.13 As described above, the first conductive line CL1 and the second conductive line CL2 may be disposed between two or more shielding lines to which an electrostatic potential is applied.

[0041] The controller 16 can control the read circuit 14 and the calibration resistor circuit 15. For example, the controller 16 can control the read circuit 14 so that the read circuit 14 can convert the read voltage V RD1 To V RDn Provided to the cell array 11, and the read current (eg, I RDk ) is compared with the reference current. In addition, the controller 16 can control the read circuit 14 and the calibration resistor circuit 15 so that during the calibration operation, at least one read circuit 14 can read the calibration current I CAL and reference current I REF Provided to the calibration resistor circuit 15. In an exemplary embodiment of the present inventive concept, the reading circuit 14 may include a plurality of switches, and the controller 16 may control the plurality of switches included in the reading circuit 14. In an exemplary embodiment of the present inventive concept, the controller 16 may include a logic block including a state machine, etc., or alternatively, may include software including a series of instructions and a processor for executing the software. Figure 5A and Figure 5B Describes examples of read operations and calibration operations.

[0042] Figure 2 is a diagram showing an exemplary embodiment of the present invention including Figure 1 A diagram of a memory cell in a cell array of Figure 3 is a diagram showing an exemplary embodiment according to the inventive concept. Figure 2 In detail, Figure 2 A memory cell M including a magnetic tunnel junction (MTJ) device as a variable resistance element is shown. ij , Figure 3 Show Figure 2 Resistance distribution of the variable resistance element MTJ.

[0043] like Figure 2 As shown in FIG. 1 , the memory cell M ij may include a source line SL connected in series j and bit line BL j In an exemplary embodiment of the present invention, the variable resistance element MTJ and the unit transistor CT are connected. Figure 2 As shown in FIG. 1 , the variable resistance element MTJ and the cell transistor CT may be connected to the bit line BL in this order. j and the source line SL j In an exemplary embodiment of the present invention, different from Figure 2 In the exemplary embodiment shown in FIG. 1 , the cell transistor CT and the variable resistance element MTJ may be connected to the bit line BL in this order. j and the source line SLj between.

[0044] The variable resistance element MTJ may include a free layer FL and a pinned layer PL, and may include a barrier layer BL between the free layer FL and the pinned layer PL. Figure 2 As shown by the arrow in , while the magnetization direction of the pinned layer PL may be pinned, the free layer FL may have a magnetization direction that is the same as or opposite to the magnetization direction of the pinned layer PL. When the pinned layer PL and the free layer FL have magnetization directions in substantially the same direction, the variable resistance element MTJ may be referred to as being in a parallel state P. When the pinned layer PL and the free layer FL have magnetization directions in directions opposite to each other, the variable resistance element MTJ may be referred to as being in an antiparallel state AP. In an exemplary embodiment of the inventive concept, the variable resistance element MTJ may further include an antiferromagnetic layer for causing the pinned layer PL to have a pinned magnetization direction.

[0045] The variable resistance element MTJ can have a relatively low resistance R in the parallel state P. P At the same time, the variable resistance element MTJ can have a relatively high resistance R in the anti-parallel state AP. AP In this specification, it is assumed that the memory cell M ij The variable resistance element MTJ in the parallel state P has a low resistance R P The variable resistance element MTJ stores "0" when in the antiparallel state AP and has a high resistance R AP In addition, in this specification, the resistor R corresponding to "0" P Can be called parallel resistance R P , and the resistance R corresponding to "1" AP Can be called anti-parallel resistance R AP .

[0046] The cell transistor CT may have a i The gate (or control terminal) and the source line SL j and the drain and source of the variable resistance element MTJ. The cell transistor CT can be applied to the word line WL according to i The voltage of the variable resistance element MTJ is electrically connected to the source line SL j or electrically disconnect the variable resistance element MTJ and the source line SL j For example, during a write operation, in order to write a "0" to a memory cell M ij , activated word line WL i may have a positive power supply voltage VDD, so that the cell transistor CT is turned on from the bit line BLj Flows to the source line SL j The current can pass through the variable resistance element MTJ. In addition, in order to write "1" into the memory cell M ij , activated word line WL i may have a positive power supply voltage VDD, and thus, the cell transistor CT is turned on from the source line SL j Flow to bit line BL j The current may pass through the variable resistance element MTJ. During the read operation, the cell transistor CT may be turned on and the source line SL j Flow to bit line BL j The current from the bit line BL j Flows to the source line SL j The current (eg, read current) may pass through the cell transistor CT and the variable resistance element MTJ. In this specification, it is assumed that the read current is from the source line SL j Flow to bit line BL j .

[0047] Reference Figure 3 , the resistance of the variable resistance element MTJ may have a distribution characteristic. Figure 3 As shown in FIG, in the memory cell storing “0”, there may be a plurality of cells having an average value R P ′ parallel resistance R P The distribution of the memory cell storing "1" may have a mean value R AP ′’s anti-parallel resistance R AP In addition, the parallel resistor R P The distribution of the antiparallel resistance R AP There may be a reference resistor R between the distribution REF .

[0048] Figure 4 is a circuit diagram showing a sense amplifier according to an exemplary embodiment of the inventive concept. Figure 2 and Figure 3 In order to detect the ij The value in memory cell M ij The resistance of the variable resistance element MTJ in can be detected.

[0049] In an exemplary embodiment of the inventive concept, the sense amplifier 40 may apply a voltage to an input terminal and may generate an output signal OUT based on a current caused by the applied voltage. Figure 4As shown in , the sense amplifier 40 may include a first voltage source VS1 that provides a first voltage V1 and a second voltage source VS2 that provides a second voltage V2. In an exemplary embodiment of the inventive concept, the first voltage V1 and the second voltage V2 may match each other, for example, the first voltage source VS1 and the second voltage source VS2 may be source followers that receive substantially the same bias voltage. Likewise, the sense amplifier 40 that applies a voltage and senses a current caused by the voltage may be referred to as a current input sense amplifier.

[0050] The first resistor R1 and the second resistor R2 may be connected to the sense amplifier 40, for example, the first resistor R1 may be a reference resistor for detecting the resistance of the second resistor R2. While the first current I1 may be generated by the first voltage V1 and the first resistor R1, the second current I2 may be generated by the second voltage V2 and the second resistor R2. The first current I1 and the second current I2 may be inversely proportional to the resistances of the first resistor R1 and the second resistor R2, respectively, and when the magnitudes of the first voltage V1 and the second voltage V2 match each other, the sense amplifier 40 may generate an output signal OUT corresponding to a comparison result from comparing the magnitude of the first current I1 with the magnitude of the second current I2. As a result, the output signal OUT may correspond to a result of comparing the resistance of the first resistor R1 with the resistance of the second resistor R2. In the following, a reference current is input to the sense amplifier (for example, as a reference Figure 4 ) are used to describe exemplary embodiments of the inventive concept.

[0051] Figure 5A and Figure 5B 1 is a circuit diagram showing an equivalent circuit of a read circuit and its surrounding circuits according to an exemplary embodiment of the inventive concept. Figure 5A FIG. 5 shows an equivalent circuit of a calibration resistor circuit 55 and a k-th read circuit 54 — k that perform a calibration operation in a memory device 50 a. Figure 5B FIG. 5 shows an equivalent circuit of a cell array 51 and a k-th read circuit 54_k for performing a read operation in a memory device 50b. In the present specification, the k-th read circuit 54_k may correspond to a circuit included in Figure 1 Any reading circuit in the reading circuit 14 and may be simply referred to as a reading circuit. A repeated description is omitted below.

[0052] Reference Figure 5A During the calibration operation, the calibration resistor circuit 55 and the read circuit 54_k may be electrically connected, and the calibration current I CAL The negative power supply voltage VSS may flow from the read circuit 54_k through the calibration resistor R_CAL. In this specification, the negative power supply voltage VSS may refer to a voltage lower than the positive power supply voltage VDD and may be referred to as a ground voltage. Figure 4As described above, when the sense amplifier SA of the read circuit 54_k k is the current input sense amplifier, the calibration current I CAL The size of the calibration resistor R_CAL may depend on the resistance of the calibration resistor R_CAL, for example, CAL .

[0053] The read circuit 54_k may include a sense amplifier SA k , reference resistor R_REF k and calibration circuit CAL k . Reference resistor R_REF k Can be connected to sense amplifier SA k , and the reference current I REF The reference resistor R_REF k From the sense amplifier SA k Flows into the negative power supply voltage VSS. Reference resistor R_REF k It can be Figure 5A The variable resistance element shown in FIG. 1 and may have a value according to the calibration circuit CAL k The received adjustment signal ADJ k And change the resistance.

[0054] For example, during a calibration operation, the calibration circuit CAL k can be Figure 1 The controller 16 is enabled and can be based on the sense amplifier SA k The output signal OUT k Generate adjustment signal ADJ k As mentioned above, the sense amplifier SA k The current input to it can be compared and the output signal OUTk can be output k In an exemplary embodiment of the present inventive concept, the calibration circuit CAL k The signal ADJ k Adjust the reference resistor R_REF k The resistance R REFk For example, the calibration circuit CAL k The resistance R can be gradually increased from the lowest value REFk , or gradually reduce the resistance R from the highest value REFk When the output signal OUT k When the calibration circuit CAL k Can maintain the adjustment signal ADJ k , so that the reference resistor R_REF k Can have a current resistance R REFk In an exemplary embodiment of the present inventive concept, the calibration circuit CA k Based on the output signal OUTk Use methods such as binary search algorithms to adjust the reference resistor R_REF k The resistance R REFk .

[0055] Reference Figure 5B , during a read operation, by activating the word line WL i The selected memory cell M ij and the reading circuit 54_k can be electrically connected and read the current I RDk can be sequentially connected through the source line SL j , memory unit M ij and bit line BL j The negative power supply voltage VSS flows in from the read circuit 54 — k. Figure 1 The column decoder 13 can electrically connect the memory cell M between the cell array 51 and the read circuit 54_k. ij and read circuit 54_k. As mentioned above Figure 4 As described above, the reading current I RDk may depend on the memory cell M ij The resistance of the variable resistance element MTJ in.

[0056] During the read operation, the calibration circuit CAL of the read circuit 54_k k Output with Figure 5A The value of the adjustment signal ADJ is determined in k , therefore, the reference resistor R_REF k Can have Figure 5A The resistance determined during the calibration operation (for example, R REFk ).

[0057] therefore, Figure 1 The controller 16 may control a switch group, which will be described below, to allow the sense amplifier SA k During a read operation (e.g., Figure 5B ) will pass through the reference resistor R_REF k The reference current I REF and through the memory unit M ij The read current I RDk is compared, and during a calibration operation (e.g. Figure 5A As shown in REF The calibration current I through the calibration resistor R_CAL CAL In other words, the reference current I during the read operation REF The path of the first reference current I during the calibration operation REF The paths are different.

[0058] Fig. 6A and Figure 6B is a circuit diagram showing a memory device that performs a calibration operation using one wire according to a comparative example. In detail, Fig. 6A 1 shows a memory device 60a performing a calibration operation of a first read circuit 64_1. Figure 6B The memory device 60b is shown to perform the calibration operation of the n-th read circuit 64_n. The repeated description is omitted below.

[0059] Reference Fig. 6A , the read circuit 64 may include first to n-th read circuits 64_1 to 64_n (where n is an integer greater than 2), and the first conductive line CL61 may extend across the read circuit 64. During the calibration operation, one of the first to n-th read circuits 64_1 to 64_n may be connected to the calibration resistor R_CAL of the calibration resistor circuit 65 through the first conductive line CL61. For example, Fig. 6A As shown in FIG. 1 , for the first reading circuit 64_1 (or the first reference resistor R_REF 1 ) is calibrated, the first sense amplifier SA of the first read circuit 64_1 1 The second sense amplifiers SA may have an input terminal electrically connected to the first conductive line CL61 and may be respectively included in the second read circuit 64_2 to the nth read circuit 64_n. 2 To the nth sense amplifier SA n Can be electrically disconnected from the first wire CL61.

[0060] The first conductive line CL61 may have a resistance proportional to its length. Fig. 6A As shown in FIG. 1 , the first conductive line CL61 can be modeled as having a parasitic resistor R_PAR between mutually adjacent read circuits (eg, 64_1 and 64_2) and between the nth read circuit 64_n and the calibration resistor circuit 65. Therefore, the first sense amplifier SA 1 The first reference resistor R_REF 1 The resistance R REF1 The resistance R of the parasitic resistor R_PAR is the same as PAR n times and the resistance of the calibration resistor R_CAL (e.g., the calibration resistor R CAL ) corresponds to the resistance "n×R PAR +R CAL ” to compare and output the first output signal OUT 1 Therefore, the first reference resistor R_REF 1 The resistance R REF1 Can be calibrated to have a resistance of “n×R PAR +R CAL ”.

[0061] Reference Figure 6B , for calibration of the nth read circuit 64_n (or the nth reference resistor R_REFn), the nth sense amplifier SA of the nth read circuit 64_n n The first conductive line CL61 may have an input terminal electrically connected to the first conductive line CL61, and a sense amplifier (eg, SA 64_1, SA 64_2, etc.) included in other read circuits (eg, 64_1, 64_2, etc.) may be electrically connected to the first conductive line CL61. 1 ,SA 2 etc.) can be electrically disconnected from the first conductor CL61. Fig. 6A As described above, the first conductive line CL61 may have a resistance proportional to its length, so the nth sense amplifier SA n The nth reference resistor R_REF n The resistance R REFn The resistance R of the parasitic resistor R_PAR is the same as PAR and the resistance R of the calibration resistor R_CAL CAL The sum of the corresponding resistance is compared to output the nth output signal OUT n Therefore, the nth reference resistor R_REF n The resistance R REFn Can be calibrated to have a resistance "R PAR +R CAL ", which can be compared with the above reference Fig. 6A The first reference resistor R_REF 1 The calibrated resistance "n×R PAR +R CAL " is different. As a result, the first reference resistors R_REF included in the first reading circuit 64_1 to the nth reading circuit 64_n are 1 To the nth reference resistor R_REF n may be calibrated to have different resistances, and errors may occur during read operations.

[0062] Fig. 7A and Figure 7B is a circuit diagram showing a memory device that performs a calibration operation using two conductive lines according to an exemplary embodiment of the inventive concept. In detail, Fig. 7A Memory device 70a is shown performing a calibration operation of first read circuit 74_1, Figure 7B The memory device 70b is shown to perform the calibration operation of the n-th read circuit 74_n. The repeated description is omitted below.

[0063] Reference Fig. 7A, the read circuit 74 may include first to nth read circuits 74_1 to 74_n (where n is an integer greater than 2), and the first and second conductive lines CL71 and CL72 may extend across the read circuit 74. A negative power supply voltage VSS may be applied to each of the first and second conductive lines CL71 and CL72.

[0064] During the calibration operation, one of the first to nth read circuits 74_1 to 74_n may be connected to the calibration resistor circuit 75 through the first conductive line CL71 and the second conductive line CL72. Fig. 7A As shown in FIG. 1 , for the first reading circuit 74_1 (or the first reference resistor R_REF 1 ) is calibrated, the first sense amplifier SA of the first read circuit 74_1 1 The second sense amplifiers SA may have an input terminal electrically connected to the first conductive line CL71 and may be respectively included in the second read circuit 74_2 to the nth read circuit 74_n. 2 To the nth sense amplifier SA n It can be electrically disconnected from the first conductor CL71. Fig. 6A The first reference resistor R_REF having a negative power supply voltage VSS is applied to the first read circuit 64_1 at the end thereof. 1 Differently, the first reference resistor R_REF of the first reading circuit 74_1 1 The second reference resistors R_REF may have an end electrically connected to the second conductive line CL72 and may be respectively included in the second to nth read circuits 74_2 to 74_n. 2 To the nth reference resistor R_REF n Can be electrically disconnected from the second wire CL72.

[0065] In other words, the first conductive line CL71 may include a circuit configured to allow the calibration current (eg, I CAL ) passes through it and flows into at least a portion of the calibration resistor R_CAL. The second conductor CL72 may include a circuit configured to allow the reference current (eg, I REF ) during a calibration operation from a first reference resistor (e.g., R_REF 1 ) through at least a portion thereof.

[0066] The first conductive line CL71 and the second conductive line CL72 may each have a resistance proportional to the length. In an exemplary embodiment of the present inventive concept, the first conductive line CL71 and the second conductive line CL72 may have substantially the same structure (eg, substantially the same length). Fig. 7AAs shown in FIG. 1 , the first conductive line CL71 and the second conductive line CL72 can be modeled as having parasitic resistors R_PAR having substantially the same resistance between mutually adjacent read circuits (eg, 74_1 and 74_2). 1 By connecting the first reference resistor R_REF 1 The resistance R REF1 and the resistance R of the parasitic resistor R_PAR PAR The resistance corresponding to the sum of n times is "R REF1 +n×R PAR ” The resistance R of the parasitic resistor R_PAR is the same as PAR n times and the resistance R of the calibration resistor R_CAL CAL (or calibration resistance) corresponds to the resistance "n×R PAR +R CAL ” to compare and output the first output signal OUT 1 Therefore, the first reference resistor R_REF 1 The resistance R REF1 Can be calibrated to a resistance R with a calibration resistor R_CAL CAL .

[0067] Reference Figure 7B , for calibration of the nth read circuit 74_n (or the nth reference resistor R_REFn), the nth sense amplifier SA of the nth read circuit 74_n n The first conductive line CL71 may have an input terminal electrically connected to the first conductive line CL71, and a sense amplifier (eg, SA 74_1, SA 74_2, etc.) included in other read circuits (eg, 74_1, 74_2, etc.) may be electrically connected to the first conductive line CL71. 1 ,SA 2 etc.) can be electrically disconnected from the first conductor CL71. Figure 6B Unlike the nth reference resistor R_REFn having the negative power supply voltage VSS applied to the end in the nth read circuit 64_n, the nth reference resistor R_REFn of the nth read circuit 74_n may have an end electrically connected to the second conductive line CL72, including reference resistors (e.g., R_REF 1 、R_REF 2 ) can be electrically disconnected from the second conductor CL72. Fig. 7A As described above, the first wire CL71 and the second wire CL72 may have a resistance proportional to their lengths, so the nth sense amplifier SA n The nth reference resistor R_REF n The resistance R REFn and the resistance R of the parasitic resistor R_PAR PAR The resistance corresponding to the sum is "RREFn +R PAR ” The resistance R of the parasitic resistor R_PAR is the same as PAR and the resistance R of the calibration resistor R_CAL CAL (or calibration resistance) and the corresponding resistance "R PAR +R CAL " is compared to output the nth output signal OUT n Therefore, the resistance R of the nth reference resistor R_REFn REFn Can be calibrated to a resistance R with a calibration resistor R_CAL CAL , which can be compared with the above reference Fig. 7A The first reference resistor R_REF described 1 The calibration resistor R CAL As a result, the first reference resistors R_REF included in the first to n-th read circuits 74_1 to 74_n are matched. 1 To the nth reference resistor R_REF n can be calibrated to have substantially the same resistance as the reference Fig. 6A and Figure 6B Unlike the described example, the occurrence of errors during the read operation can be prevented.

[0068] Figure 8 is a circuit diagram showing a portion of a memory device according to an exemplary embodiment of the inventive concept. In detail, Figure 8 FIG. 8 shows an equivalent circuit of a memory device 80 including a cell array 81, a read circuit 84_k, and a calibration resistor circuit 85. The column decoder may electrically connect the memory cells M between the cell array 81 and the read circuit 84_k according to the address. ij and read circuit 84_k.

[0069] Reference Figure 8 , the memory device 80 may include a first conductor CL81 and a second conductor CL82 extending across a read circuit including a read circuit 84_k. Fig. 7A and Figure 7B As described above, the reference resistor R_REF of the read circuit 84_k k Can be calibrated to a resistance R with a calibration resistor R_CAL CAL In the following, reference will be made to Figure 1 describe Figure 8 .

[0070] The cell array 81 may include a cell array connected to a word line WL i The memory cell M ij , and the memory cell M ij During a read operation, the source line SL jConnected to the read circuit 84_k and can be read through the bit line BL j Connected to the negative power supply voltage VSS. The calibration resistor circuit 85 may include a calibration resistor R_CAL and may be connected to the first conductive line CL81 and the second conductive line CL82.

[0071] The read circuit 84_k may include a sense amplifier SA k , reference resistor R_REF k The read circuit 84_k may also include a circuit for reading a circuit based on a sense amplifier SA k The output signal OUT k Adjust the reference resistor R_REF k The resistor calibration circuit (for example, Figure 5A CAL k ). The switch group may include a plurality of switches SW41, SW42, SW44 and SW45, and may be Figure 1 The controller 16 of the control calibration operation is turned on or off. Each of the plurality of switches SW41, SW42, SW44, and SW45 may have any structure capable of electrically connecting or disconnecting both ends according to the control of the controller 16. For example, each of the plurality of switches SW41, SW42, SW44, and SW45 may include an n-channel field effect transistor (NFET) and / or a p-channel field effect transistor (PFET), and the controller 16 may adjust the gate voltage of the NFET.

[0072] The controller 16 may control the plurality of switches SW41, SW42, SW44, and SW45 to form Figure 5B For example, as mentioned above, Figure 5B As described above, the controller 16 may turn on the first switch SW41 and the fourth switch SW44 and turn off the second switch SW42 and the fifth switch SW45 to allow the sense amplifier SA k The reference resistor R_REF k The reference current I REF and through the memory unit M ij The read current I RDK Here, the first switch SW41 can provide the negative power supply voltage VSS to the reference resistor R_REF when turned on. k The negative power supply voltage VSS may be a ground potential. During a read operation, the first conductive line CL81 and the second conductive line CL82 are electrically disconnected from the read circuit.

[0073] On the other hand, the controller 16 may control the plurality of switches SW41, SW42, SW44, and SW45 to form a Figure 5AFor example, the controller 16 may turn off the first switch SW41 and the fourth switch SW44 and turn on the second switch SW42 and the fifth switch SW45 to allow the sense amplifier SA k The reference resistor R_REF k The reference current I REF The calibration current I through the calibration resistor R_CAL CAL Here, the second switch SW42 can be electrically connected to the reference resistor R_REF k The fifth switch SW45 can connect the sense amplifier SA to the second conductor CL82 via the first conductor CL81. k The first input terminal of is electrically connected to the calibration resistor R_CAL.

[0074] For example, the second switch SW42 and the fifth switch SW45 may have substantially the same structure and thus provide substantially the same on-resistance. CAL and reference current I REF All pass through the same number of switches, and the error due to the on-resistance of the switches can be removed.

[0075] Fig. 9 is a circuit diagram showing a portion of a memory device according to an exemplary embodiment of the inventive concept. In detail, Fig. 9 9 shows an equivalent circuit of a memory device 90 including a cell array 91, a column decoder 93, a read circuit 94_k, and a calibration resistor circuit 95. Figure 8 Compared to the examples included in Figure 8 At least one corresponding switch among the plurality of switches SW41, SW42, SW44 and SW45 in the read circuit 84_k may include Fig. 9 In the following, the column decoder 93 will be omitted. Figure 8 Provided Fig. 9 The description of the components in Figure 1 describe Fig. 9 .

[0076] Reference Fig. 9 , the memory device 90 may include a first conductive line CL91 and a second conductive line CL92 extending across a read circuit including a read circuit 94_k. The cell array 91 may include a first conductive line CL91 and a second conductive line CL92 connected to a word line WL i , source line SL j and bit line BL j The memory cell M ij The calibration resistor circuit 95 may include a calibration resistor R_CAL and may be connected to the first conductive line CL91 and the second conductive line CL92. The read circuit 94_k may include a sense amplifier SA k, reference resistor R_REF k and a switch group, and the switch group may include a plurality of switches SW41, SW42 and SW45. Figure 8 Compared with the read circuit 84_k, Fig. 9 The switch group of the read circuit 94_k is omitted and Figure 8 The fourth switch SW44 corresponds to the switch.

[0077] The column decoder 93 may include a first column switch SW31 and a second column switch SW32 controlled based on an address (or a column address). Fig. 9 As shown in FIG. 1 , the first column switch SW31 can apply the negative power supply voltage VSS to the bit line BL. j Or block the negative power supply voltage VSS to the bit line BL j , and the second column switch SW32 can switch the source line SL j Connect to the read circuit 94_k or connect the source line SL j In an exemplary embodiment of the inventive concept, during the calibration operation of the read circuit 94_k, the column decoder 93 may electrically disconnect the cell array 91 from the read circuit 94_k by turning off the second column switch SW32. In other words, Figure 8 The function of the fourth switch SW44 can be performed by the second column switch SW32 included in the column decoder 93. To this end, Figure 1 The controller 16 may control not only the switch group included in the read circuit 94 — k but also the column decoder 93 .

[0078] Fig.10 is a circuit diagram showing a portion of a memory device according to an exemplary embodiment of the inventive concept. In detail, Fig.10 1 shows an equivalent circuit of a memory device 100 including a cell array 101, a column decoder 103, a read circuit 104_k, and a calibration resistor circuit 105. Fig. 9 Compared to the example, Fig.10 The read circuit 104_k can also be connected to the reference resistor R_REF k With the sense amplifier SA k A third switch SW43 is included between them, Fig.10 The calibration resistor circuit 105 may include a first compensation switch SWC1. Fig. 9 Given Fig.10 The description of the components in Figure 1 describe Fig.10 .

[0079] Reference Fig.10, the memory device 100 may include a first conductive line CL101 and a second conductive line CL102 extending across a read circuit including a read circuit 104_k. The cell array 101 may include a first conductive line CL101 and a second conductive line CL102 connected to a word line WL i , source line SL j and bit line BL j The memory cell M ij The calibration resistor circuit 105 may include a calibration resistor R_CAL and a first compensation switch SWC1, and may be connected to a first conductive line CL101 and a second conductive line CL102. The read circuit 104_k may include a sense amplifier SA k , reference resistor R_REF k The column decoder 103 may include a first column switch SW31 and a second column switch SW32. The plurality of switches SW41, SW42, SW43, and SW45 included in the read circuit 104_k and the first compensation switch SWC1 included in the calibration resistor circuit 105 may be formed by Figure 1 The controller 16 controls.

[0080] In an exemplary embodiment of the inventive concept, the read circuit 104_k may include at least one switch to allow the current I to be read during the read operation. RDk and reference current I REF For example, during a read operation, the first switch SW41, the third switch SW43, the first column switch SW31, and the second column switch SW32 may be turned on, and the second switch SW42 and the fifth switch SW45 may be turned off. ij The read current I RDk The current can be transmitted through the second column switch SW32 and the first column switch SW31 while passing through the reference resistor R_REF k The reference current I REF The third switch SW43 and the first switch SW41 can be used. Fig.10 When the switches shown in FIG. 1 have substantially the same structure, each switch can provide substantially the same on-resistance, and when the current I is read RDk and reference current I REF When all pass through the same number of switches, the error caused by the on-resistance of the switch can be removed. To this end, the reading circuit 104_k may include a third switch SW43. In an exemplary embodiment of the inventive concept, while the third switch SW43 may have a structure (or on-resistance) substantially the same as that of the second column switch SW32, the first switch SW41 may have a structure (or on-resistance) substantially the same as that of the first column switch SW31.

[0081] In an exemplary embodiment of the present inventive concept, the read circuit 104_k and the calibration resistor circuit 105 may include at least one switch to allow the calibration current I CAL and reference current I REF For example, during the calibration operation, the second switch SW42, the third switch SW43, the fifth switch SW45, and the first compensation switch SWC1 may be turned on, and the first switch SW41 and the second column switch SW32 may be turned off. In other words, the third switch SW43 may turn the sense amplifier SA k The second input terminal is connected to the reference resistor R_REF k The first compensation switch SWC1 can electrically connect the calibration resistor R_CAL to the negative power supply voltage VSS. Therefore, when the calibration current I CAL The current can be supplied through the fifth switch SW45 and the first compensation switch SWC1 while passing through the reference resistor R_REF k The reference current I REF The voltage may pass through the third switch SW43 and the second switch SW42.

[0082] when Fig.10 When the switches shown in FIG. 1 have substantially the same structure, each switch can provide substantially the same on-resistance, and when the calibration current I CAL and reference current I REF When all pass through the same number of switches, the error caused by the on-resistance of the switch can be removed. To this end, the reading circuit 104_k may include a third switch SW43, and the calibration resistor circuit 105 may include a first compensation switch SWC1. In an exemplary embodiment of the present inventive concept, while the third switch SW43 may have a structure (or on-resistance) substantially the same as that of the fifth switch SW45, the second switch SW42 may have a structure (or on-resistance) substantially the same as that of the first compensation switch SWC1. In an exemplary embodiment of the present inventive concept, the third switch SW43 may be in an on state during the reading operation and the calibration operation.

[0083] Fig.11 is a circuit diagram showing a portion of a memory device according to an exemplary embodiment of the inventive concept. In detail, Fig.11 1 shows an equivalent circuit of a memory device 110 including a cell array 111, a column decoder 113, a read circuit 114_k, and a calibration resistor circuit 115. Fig.10 Compared to the example, Fig.11The calibration resistor circuit 115 may further include a second compensation switch SWC2 and a third compensation switch SWC3. Fig.10 Given Fig.11 The description of the components in Figure 1 describe Fig.11 .

[0084] Reference Fig.11 , the memory device 110 may include a first conductive line CL111 and a second conductive line CL112 extending across a read circuit including a read circuit 114_k. The cell array 111 may include a first conductive line CL111 and a second conductive line CL112 connected to a word line WL i , source line SL j and bit line BL j The memory cell M ij The calibration resistor circuit 115 may include a calibration resistor R_CAL, a first compensation switch SWC1, a second compensation switch SWC2, and a third compensation switch SWC3, and may be connected to a first conductive line CL111 and a second conductive line CL112. The read circuit 114_k may include a sense amplifier SA k , reference resistor R_REF k The column decoder 113 may include a first column switch SW31 and a second column switch SW32. The plurality of switches SW41, SW42, SW43, and SW45 included in the read circuit 114_k and the first to third compensation switches SWC1 to SWC3 included in the calibration resistor circuit 115 may be provided by Figure 1 The controller 16 controls.

[0085] In an exemplary embodiment of the present inventive concept, the calibration resistor circuit 115 may include a third compensation switch SWC3 and may include a second compensation switch SWC2, wherein the third compensation switch SWC3 is connected to the reference current I during the calibration operation when the negative power supply voltage VSS (eg, ground potential) is connected to the reference current I REF The second compensation switch SWC2 provides a conduction resistance substantially the same as that of the third compensation switch SWC3 and is connected in series to the calibration current I CAL The on-resistance of the first compensation switch SWC1 through which the current flows. The second compensation switch SWC2 may be arranged between the first conductive line CL111 and the negative power supply voltage VSS (eg, between the first compensation switch SWC1 and the negative power supply voltage VSS). Fig.10 As described, during the calibration operation, the calibration current I CAL The reference current I REFThe voltage may pass through the third switch SW43 , the second switch SW42 , and the third compensation switch SWC3 .

[0086] Fig. 12A is a side view schematically illustrating a portion of a memory device according to an exemplary embodiment of the inventive concept, Fig. 12B is a schematic diagram showing an exemplary embodiment according to the inventive concept Fig. 12A A circuit diagram of a portion of a memory device. In detail, Fig. 12A One side of the layout of the memory device 120 including the read circuit (124_1, 124_2, etc.), the calibration resistor circuit 125, the first conductive line CL121 and the second conductive line CL122 is shown, Fig. 12B An equivalent circuit of a portion of the memory device 120 is shown.

[0087] Reference Fig. 12A , the memory device 120 may be a semiconductor device manufactured by a semiconductor process, and may include a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion. The first conductive line CL121 through which the calibration current passes and the second conductive line CL122 through which the reference current passes during the calibration operation may be formed in a high-level wiring layer that is relatively unaffected by other patterns for signal routing. For example, Fig. 12A As shown in FIG. 1 , the first conductive line CL121 and the second conductive line CL122 may be formed in the M4 metal layer. In an exemplary embodiment of the inventive concept, the first conductive line CL121 and the second conductive line CL122 may be formed in the M4 metal layer. Fig. 12A The wiring layer shown is a higher or lower wiring layer.

[0088] The components in the FEOL region may be connected to the first conductive line CL121 or the second conductive line CL122 of the M4 metal layer through a plurality of conductive patterns and a plurality of vias. Fig. 12AAs shown in , the elements in the FEOL region of the first read circuit 124_1 can be connected to the first wire CL121 or the second wire CL122 through the vias of the V0 via layer, the pattern of the M1 metal layer, the vias of the V1 via layer, the pattern of the M2 metal layer, the vias of the V2 via layer, the pattern of the M3 metal layer, and the vias of the V3 via layer, and the second read circuit 124_2 and the calibration resistor circuit 125 can also be connected to the first wire CL121 and the second wire CL122 in a similar manner. The pattern and vias between the FEOL element and the pattern of the M4 metal layer may be referred to as a via stack, and the via stack may have a resistance. In an exemplary embodiment of the present inventive concept, the via stack between the first wire CL121 or the second wire CL122 and the read circuit (e.g., 124_1) may have a structure substantially the same as the via stack between the first wire CL121 or the second wire CL122 and the calibration resistor circuit 125. Therefore, as Fig. 12B As shown in , the via stacks can each be modeled or represented as a via resistor R_VIA.

[0089] Reference Fig. 12B , the first wire CL121 and the second wire CL122 may be connected to the read circuit (e.g., 124_1) or the calibration resistor circuit 125 through the via resistor R_VIA, and therefore, the path including the first wire CL121 and the path including the second wire CL122 may include the same number of via resistors R_VIA. For example, during the calibration operation of the first read circuit 124_1, the calibration current I CAL At the same time, the reference current I may flow into the calibration resistor circuit 125 through the via resistor R_VIA, the first conductive line CL121, and the via resistor R_VIA. REF The calibration current I may flow into the calibration resistor circuit 125 through the via resistor R_VIA, the second wire CL122, and the via resistor R_VIA. Therefore, as described above, since the first wire CL121 and the second wire CL122 have substantially the same structure, the calibration current I CAL and reference current I REF The resistance passing from the first reading circuit 124_1 to the calibration resistor circuit 125 may be matched.

[0090] Fig.13 1 is a diagram illustrating a conductive line according to an exemplary embodiment of the inventive concept. In an exemplary embodiment of the inventive concept, the shielding lines SL131 and SL132 may be arranged to be aligned with the calibration current I during the calibration operation. CAL and reference current I REF The first wire CL131 and the second wire CL132 passing through the respective paths are adjacent to each other. Fig.13As shown in FIG. 1 , first and second shielding wires SL131 and SL132 extending in the same wiring layer as the first and second wires CL131 and CL132, parallel to the first and second wires CL131 and CL132, and with the first and second wires CL131 and CL132 therebetween may be provided. The first and second shielding wires SL131 and SL132 may reduce the influence of external noise on the first and second wires CL131 and CL132, and for this purpose, the electrostatic potential (e.g., Fig.13 A negative power supply voltage VSS) shown in FIG. 1 may be applied to the first shield line SL131 and the second shield line SL132.

[0091] Fig.14 is a flowchart illustrating a method of calibrating a reference in a memory device according to an exemplary embodiment of the inventive concept. Calibrating a reference in a memory device may refer to an operation of calibrating a read circuit in a memory device or a reference resistor included in the read circuit. For example, Fig.14 The method can be Figure 1 The memory device 10 performs the reference Figure 1 describe Fig.14 .

[0092] Reference Fig.14 In operation S20, an initialization operation for reference calibration may be performed. Fig.14 As shown in , the variable k may be set to 1, and the variable k may correspond to an index of each of the n read circuits included in the read circuit 14 .

[0093] In operation S40, an operation of calibrating the kth read circuit may be performed. As described above, the memory device 10 may include a first conductive line CL1 and a second conductive line CL2 extending across the read circuit 14, and during the calibration operation of the read circuit 14, the calibration current I CAL At the same time, the reference current I REF can flow through the second conductor CL2. Therefore, each read circuit 14 can be calibrated consistently and read errors can be removed. Fig.15 An example of operation S40 is described.

[0094] In operation S60, it may be determined whether the variable k is less than n. In other words, it may be determined whether the calibration of the last n-th read circuit among the read circuits 14 is completed. When the variable k is less than n (e.g., when calibration still needs to be performed on at least one read circuit), the variable k may be increased by 1 in operation S80, and operation S40 may be subsequently performed. In other words, Figure 1The controller 16 may control the respective switch groups to sequentially perform calibration of the reference resistors in the read circuit 14. On the other hand, when the variable k is not less than n (such as when the variable k matches n), for example, when the calibration of the read circuit 14 is completed, the calibration of the reference resistors may be ended.

[0095] In an exemplary embodiment of the inventive concept, the memory device 10 may be powered on. Fig.14 For example, when power is supplied to the memory device 10, the controller 16 may perform a calibration operation by controlling the read circuit 14 and the calibration resistor circuit 15, and may control the read circuit 14 and the calibration resistor circuit 15 to perform an operation according to an external command (e.g., a read operation and / or a write operation) after the calibration operation is completed. In an exemplary embodiment of the inventive concept, a calibration result of a reference (e.g., a resistance of a reference resistor included in the read circuit 14) may be stored in a volatile memory element (e.g., a register, a synchronous random access memory (SRAM)), etc.).

[0096] In an exemplary embodiment of the inventive concept, the following operations may be performed in response to a signal provided to the memory device 10. Fig.14 For example, the memory device 10 may externally receive a signal indicating calibration of the reference, and the controller 16 may perform a calibration operation by controlling the read circuit 14 and the calibration resistor circuit 15 in response to the received signal. In an exemplary embodiment of the present inventive concept, the calibration result of the reference (e.g., the resistance of the reference resistor included in the read circuit 14) may be stored in a non-volatile memory element (such as a flash memory, an anti-fuse, etc.). The signal indicating calibration may be provided during the manufacturing process of the memory device 10, or alternatively, the memory device 10 may be provided by another device (e.g., Fig.17 171) periodically or non-periodically provides a signal indicating calibration.

[0097] Fig.15 is a diagram showing an exemplary embodiment according to the inventive concept Fig.14 In other words, the following will provide a flow chart of the operation of the calibration reading circuit in the method. Fig.14 An example of operation S40 in FIG. Fig.15 In operation S40′, an operation of calibrating the kth reading circuit is performed, such as Fig.15 As shown in , operation S40′ may include multiple operations S42, S44 and S46. For example, Fig.15 Operation S40′ may be performed by Figure 1 The controller 16 and Figure 5B Calibration circuit CAL k Execution, which will be referred to below Figure 1 and Figure 5B describe Fig.15.

[0098] In operation S42, an operation of controlling the switch group may be performed. Figure 8 As described above, the read circuit 54_k may include a switch group including a plurality of switches, and the controller 16 may control the configuration of the switch group included in the read circuit 54_k. Figure 5B The equivalent circuit of .

[0099] In operation S44, adjusting the reference resistor R_REF may be performed. k The resistance R REFk For example, the calibration circuit CAL k The signal ADJ k Increase or decrease the reference resistor R_REF k The resistance R REFk . See below Fig.16 An example of operation S44 is described.

[0100] In operation S46, determining the reference resistor R_REF may be performed. k The resistance R REFk Is the resistance R of the calibration resistor R_CAL CAL For example, when the calibration circuit CAL k By adjusting the signal ADJ k Gradually increase the reference resistor R_REF k The resistance R REFk When the calibration circuit CAL k The sense amplifier SA k The output signal OUT k When the reference resistor R_REF k The resistance R REFk Determined as the resistance R with the calibration resistor R_CAL CAL When the reference resistor R_REF k The resistance R REFk The resistance R of the calibration resistor R_CAL CAL When there is no match (S46: No) (for example, when the output signal OUT does not occur k On the other hand, when the reference resistor R_REF k The resistance R REFk The resistance R of the calibration resistor R_CAL CAL When the output signal OUT is matched (S46: Yes) (for example, when the output signal OUT k ), operation S40′ may be ended.

[0101] Fig.16is a circuit diagram showing a portion of a memory device according to an exemplary embodiment of the inventive concept. In detail, Fig.16 FIG. 1 shows an equivalent circuit of the memory device 160 including the read circuit 164_k and the calibration resistor circuit 165 during a calibration operation. Fig.16 As shown in FIG. 1 , the read circuit 164 — k may include a sense amplifier SA k , counter CNTk and reference resistor R_REF k , the calibration resistor circuit 165 may include a calibration resistor R_CAL.

[0102] In an exemplary embodiment of the inventive concept, the read circuit 164_k may include a counter CNTk as a calibration circuit. The counter CNTk may output an adjustment signal ADJ having a gradually increasing or decreasing value. k , and the reference resistor R_REF k It can have an adjustment signal ADJ k The value of the resistor R increases or decreases REFk For example, Fig.16 As shown in the figure, the reference resistor R_REF k Resistors having resistances of 4R, 2R, and R, respectively, and connected in series, and transistors respectively connected in parallel to the resistors, and a reference resistor R_REF k The transistor may have an adjustment signal ADJ applied to the gate of the transistor. k And change the resistance. Fig.16 The reference resistor R_REF shown in k The structure of is only an example, and it will be understood that in an exemplary embodiment of the present inventive concept, the reference resistor R_REF k Can have Fig.16 The structure shown in FIG. 1 is different from the structure of the variable resistance element.

[0103] At the beginning of the calibration operation, the counter CNTk can be Figure 1 The controller 16 is reset and may output an adjustment signal ADJ having a gradually increasing value, for example. k When the output signal OUT k When the sense amplifier SA k Output indicates calibration current I CAL Greater than the reference current I REF The output signal OUT is activated k (Instead of indicating the calibration current I CAL Less than the reference current I REF Deactivation of the output signal OUT k ), the counter CNTk can stop increasing the adjustment signal ADJ kThe value of the adjustment signal ADJ k The value of .

[0104] Fig.17 2 is a block diagram illustrating a memory system including a memory device according to an exemplary embodiment of the inventive concept. Fig.17 As shown in , the memory system 170 may communicate with the host 180 and may include a controller 171 and a memory device 172 .

[0105] The interface 190 through which the memory system 170 communicates with the host 180 may use electrical signals and / or optical signals, and as a non-limiting example, the interface 190 may be implemented as a Serial Advanced Technology Attachment (SATA) interface, a SATA Express (SATAe) interface, a Serial Attached Small Computer System Interface (Serial Attached SCSI (SAS)), a Peripheral Component Interconnect Express (PCIe) interface, a Non-Volatile Memory Express (NVMe) interface, an Advanced Host Controller Interface (AHCI), or a combination thereof.

[0106] In an exemplary embodiment of the inventive concept, the memory system 170 may be detachably combined with the host 180 to communicate with the host 180. As a resistive memory, the memory device 172 may be a non-volatile memory, and the memory system 170 may be referred to as a storage system. For example, as a non-limiting example, the memory system 170 may be implemented as a solid state drive or solid state disk (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded multimedia card (eMMC), etc.

[0107] The controller 171 may control the memory device 172 in response to a request received from the host 180 through the interface 190. For example, the controller 171 may write data received together with a write request to the memory device 172 in response to a write request, and may provide data stored in the memory device 172 to the host 180 in response to a read request.

[0108] The memory system 170 may include at least one memory device 172, and the memory device 172 may include a memory cell having a variable resistance element and a reference cell. As described above, the memory device 172 may provide accurate reference calibration, and thus, a value stored in the memory cell may be accurately read regardless of changes in process, voltage, temperature, etc. As a result, the operational reliability of the memory system 170 may be improved.

[0109] Fig.182 is a block diagram illustrating a system on chip (SoC) including a memory device according to an exemplary embodiment of the inventive concept. SoC 200 may represent an integrated circuit in which components of a computing system or components of another electronic system are integrated. For example, as one of a plurality of SoCs 200, an application processor may include a processor and components for other functions. Fig.18 As shown in FIG. 2 , SoC 200 may include core 201, digital signal processor (DSP) 202, graphics processing unit (GPU) 203, embedded memory 204, communication interface 205, and memory interface 206. The components of SoC 200 may communicate with each other through bus 207.

[0110] The core 201 may process instructions and may control the operation of components included in the SoC 200. For example, the core 201 may drive an operating system by processing a series of instructions and may execute an application on the operating system. The DSP 202 may generate useful data by processing digital signals (e.g., digital signals provided from the communication interface 205). The GPU 203 may generate data of an image to be output through a display device from image data provided by the embedded memory 204 or the memory interface 206, and may encode the image data. The communication interface 205 may provide a communication network or an interface for one-to-one communication. The memory interface 206 may provide an interface for an external memory (e.g., a dynamic random access memory (DRAM), a flash memory, etc.) of the SoC 200.

[0111] The embedded memory 204 may store data required for the operations of the core 201, the DSP 202, and the GPU 203. The embedded memory 204 may include a resistive memory device according to an exemplary embodiment of the inventive concept, and thus, in the embedded memory 204, a value stored in a memory cell may be accurately read regardless of changes in process, voltage, temperature, etc. As a result, the operational reliability of the SoC 200 may be improved.

[0112] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A resistive memory device configured to calibrate a reference resistor, the resistive memory device include: a calibration resistor circuit, including a calibration resistor; a first reference resistor; a first sense amplifier configured to compare the input currents; A first switch group, including a plurality of switches; as well as a controller configured to: control the first switch group to allow the first sense amplifier to compare a first reference current through the first reference resistor with a first read current through the first memory cell during a read operation, and to compare the first reference current with a first calibration current through the calibration resistor during a calibration operation, wherein a path of the first reference current during the read operation is different from a path of the first reference current during the calibration operation, The resistive memory device further includes a first calibration circuit configured to adjust a variable resistance of the first reference resistor based on an output signal of the first sense amplifier.

2. The resistive memory device according to claim 1, further comprising: include: A first conductive line including: at least a portion configured to allow a first calibration current to pass through the conductive line and flow into a calibration resistor; and a second conductive line including: a conductive line configured to allow a first reference current to pass through at least a portion of the conductive line from the first reference resistor during a calibration operation; The first conductive line and the second conductive line have substantially the same length.

3. The resistive memory device according to claim 2, in, The first conductive line and the second conductive line are arranged in the same wiring layer and extend substantially parallel to each other.

4. The resistive memory device according to claim 3, further comprising: include: a plurality of shielding wires extending in the same wiring layer as the first conductive wire and the second conductive wire and configured to allow an electrostatic potential to be applied to the plurality of shielding wires, The first conductive wire and the second conductive wire are arranged between the plurality of shielding wires.

5. The resistive memory device according to claim 2, in, The first switch group includes: a first switch connected to the first reference resistor and configured to: provide a ground potential to the first reference resistor when turned on; and a second switch configured to electrically connect the first reference resistor and the second wire when turned on; The controller is configured to turn on the first switch and turn off the second switch during a read operation, and is configured to turn off the first switch and turn on the second switch during a calibration operation.

6. The resistive memory device according to claim 5, in, The calibration resistor circuit further includes: a first compensation switch having substantially the same structure as the second switch, and The first compensation switch is configured to allow a first calibration current to pass through the first compensation switch when turned on.

7. The resistive memory device according to claim 6, in, The calibration resistor circuit also includes: a second compensation switch configured to allow the first calibration current to pass through the second compensation switch when turned on, wherein the second compensation switch is arranged between the first conductor and a ground potential; and The third compensation switch is configured to allow the first reference current to pass through the third compensation switch when turned on, wherein the third compensation switch is arranged between the second conductive line and the ground potential.

8. The resistive memory device according to claim 1, in, The first switch group includes: a third switch connected to the first input terminal of the first sense amplifier and configured to: allow the first reference current to pass through the third switch when turned on; and The fourth switch is connected to the second input terminal of the first sense amplifier and is configured to allow the first calibration current to pass through the fourth switch when turned on.

9. The resistive memory device according to claim 8, in, The third switch has substantially the same structure as the fourth switch, and The controller is configured to turn on the third switch during a read operation and during a calibration operation.

10. The resistive memory device according to claim 1, further comprising: include: a second reference resistor having a variable resistance; a second sense amplifier configured to compare the input currents; as well as A second switch group includes a plurality of switches, wherein the controller is further configured to: control the second switch group to allow the second sense amplifier to compare the second reference current passing through the second reference resistor with the second read current passing through the second memory cell during a read operation, and to compare the second reference current with the first calibration current during a calibration operation, Wherein, a path of the second reference current during the read operation is different from a path of the second reference current during the calibration operation.

11. The resistive memory device according to claim 10, in, The controller is further configured to control the first switch group and the second switch group to sequentially perform calibration of the first reference resistor and calibration of the second reference resistor.

12. The resistive memory device according to claim 10, further comprising: include: The second calibration circuit is configured to adjust the resistance of the second reference resistor based on the output signal of the second sense amplifier.

13. The resistive memory device according to claim 1, in, The controller is also configured to perform a calibration operation when power is supplied to the resistive memory device.

14. A resistive memory device configured to calibrate a plurality of reference resistors, the resistive memory device include: Calibration resistors; Multiple reference resistors; a plurality of sense amplifiers each configured to compare a reference current through a reference resistor of the plurality of reference resistors with a read current through a memory cell during a read operation and to compare the reference current with a calibration current through a calibration resistor during a calibration operation; as well as a plurality of switches configured to form a second path during a calibration operation to allow a reference current to pass through the second path, wherein the second path has substantially the same length as the first path, and the calibration current passes through the first path between the plurality of sense amplifiers and the calibration resistor, The resistive memory device further includes a plurality of calibration circuits each configured to adjust a variable resistance of one of the plurality of reference resistors based on an output signal of one of the plurality of sense amplifiers.

15. The resistive memory device according to claim 14, in, The plurality of switches include: a plurality of first switches respectively connected to the plurality of reference resistors and configured to: provide a ground potential to the plurality of reference resistors during a read operation; and The plurality of second switches are each configured to form a second path during a calibration operation.

16. The resistive memory device according to claim 14, further comprising: include: a first conductive line including at least a portion contained in a first path; as well as a second conductive line including at least a portion included in a second path, The first conductive line and the second conductive line are arranged in the same wiring layer and extend substantially parallel to each other.

17. A resistive memory device configured to calibrate a plurality of reference resistors, the resistive memory device include: Calibration resistors; a plurality of read circuits each configured to compare a reference current through a reference resistor of the plurality of reference resistors with a read current through the memory cell during a read operation and to compare the reference current with a calibration current through the calibration resistor during a calibration operation; a first conductor connected to the plurality of read circuits and the calibration resistor and configured to: allow a calibration current to pass through the first conductor during a calibration operation; as well as a second conductor connected to the plurality of read circuits and configured to: allow a reference current to pass through the second conductor during a calibration operation; wherein the first conductive line and the second conductive line have substantially the same length as each other, Each of the plurality of read circuits includes a calibration circuit configured to adjust a variable resistance of one of the plurality of reference resistors based on a comparison result between a reference current and a calibration current during a calibration operation.

18. The resistive memory device according to claim 17, in, During a read operation, the first conductive line and the second conductive line are electrically disconnected from the plurality of read circuits.

19. The resistive memory device according to claim 17, in, The first conductive line and the second conductive line are arranged in the same wiring layer and extend substantially parallel to each other across the plurality of read circuits.

20. The resistive memory device according to claim 19, further comprising: include: a plurality of shielding wires extending in the same wiring layer as the first conducting wire and the second conducting wire and configured to allow an electrostatic potential to be applied to the plurality of shielding wires, The first conductive wire and the second conductive wire are arranged between the plurality of shielding wires.

21. The resistive memory device according to claim 17, in, The calibration circuit includes: a counter configured to generate an output signal that increases or decreases according to the comparison result, and A corresponding reference resistor among the plurality of reference resistors has a variable resistance that increases or decreases according to an output signal of the counter.

22. A resistive memory device configured to calibrate a reference resistor, the resistive memory device include: a calibration resistor circuit, including a calibration resistor; a first reference resistor; A first sense amplifier including a first input terminal and a second input terminal; A first lead and a second lead connected to a calibration resistor circuit; as well as a switch group, comprising a first switch and a second switch, wherein the second input terminal of the first sense amplifier is connected to the first reference resistor, The first switch is configured to connect the first input terminal of the first sense amplifier to the calibration resistor via the first conductive line, and The second switch is configured to connect the first reference resistor and the second conductor, wherein the first sense amplifier compares a first reference current through the first reference resistor with a first read current through the first memory cell during a read operation and compares the first reference current with a first calibration current through the calibration resistor during a calibration operation, The resistive memory device further includes a first calibration circuit configured to adjust a variable resistance of the first reference resistor based on an output signal of the first sense amplifier.

23. The resistive memory device according to claim 22, in, The first conductive line and the second conductive line have substantially the same length as each other, and extend substantially parallel to each other.

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