Integrated circuit including multi-height cells and method of manufacturing the integrated circuit

Abstract

An integrated circuit includes: first cells arranged in a first row extending in a first horizontal direction; second cells arranged in a second row adjacent to the first row; and third cells arranged consecutively in the first and second rows. The first and second cells include respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line in the first row and extending in the first horizontal direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0057324 filed on May 18, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to an integrated circuit, and more particularly, to an integrated circuit including a multi-height cell and a method of manufacturing the integrated circuit. Background Art

[0004] The size of cells included in an integrated circuit can be reduced to increase the integrated circuit's integration density. As the cell size decreases, the cell's drive current capability may decrease. Therefore, various cell types with different areas can be included in the integrated circuit while maintaining or otherwise providing the same drive current capability. Furthermore, the reduction in cell size may increase the difficulty of wiring within the cell, and cells with more complex structures may require expanded areas for wiring. Summary of the Invention

[0005] The present inventive concept provides an integrated circuit including a multi-height cell, and more particularly, an integrated circuit including a multi-height cell providing higher efficiency by having a structure independent of a structure of a single-height cell, and a method of manufacturing the integrated circuit.

[0006] According to one aspect of the present inventive concept, an integrated circuit is provided, comprising: first cells arranged in a first row extending in a first horizontal direction; second cells arranged in a second row adjacent to the first row; and third cells arranged consecutively in the first and second rows, wherein the first and second cells share or include corresponding portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line in the first row that is electrically connected to the first power line and extends in the first horizontal direction. The second row may not include the second power line.

[0007] According to another aspect of the present invention, an integrated circuit is provided, comprising: a first unit arranged in a first row, the first row extending in a first horizontal direction; a second unit arranged in a second row adjacent to the first row; and a third unit arranged continuously in the first row and the second row, wherein the third unit includes a first active region and a second active region extending parallel to each other in the first horizontal direction and having a first conductivity type and a second conductivity type, respectively, wherein the first active region includes at least a portion arranged in the first row, and the second active region includes at least a portion arranged in the second row.

[0008] According to another aspect of the present invention, an integrated circuit is provided, comprising: a single-height cell arranged in a first row extending along a first horizontal direction and including a first active region extending in the first horizontal direction, the single-height cell having a first conductivity type; and a multi-height cell continuously arranged in the first row and a second row adjacent to the first row, the multi-height cell including a second active region extending in the first horizontal direction and having a second conductivity type, wherein a portion of the first active region is opposite to the second active region in the first horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are not drawn to scale for ease of illustration and may be enlarged or reduced in size. The embodiments of the present invention will be more clearly understood based on the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 shows a plan view of a unit according to some embodiments;

[0011] Figure 2 shows a plan view of a unit according to some embodiments;

[0012] Figure 3 is a plan view illustrating a layout of an integrated circuit according to some embodiments;

[0013] Figures 4A to 4C is a plan view illustrating a layout of an integrated circuit according to some embodiments;

[0014] Figure 5A and Figure 5B is a plan view illustrating a layout of an integrated circuit according to some embodiments;

[0015] 6A to 6D is a plan view illustrating a layout of an integrated circuit according to some embodiments;

[0016] Figure 7A and Figure 7Bare a plan view and a perspective view, respectively, illustrating a layout of an integrated circuit according to some embodiments;

[0017] Figure 8A and Figure 8B is a plan view illustrating a layout of an integrated circuit according to some embodiments;

[0018] Figure 9 is a plan view illustrating a layout of an integrated circuit according to some embodiments;

[0019] Figure 10 shows a plan view of a unit according to some embodiments;

[0020] Figure 11 is a flowchart illustrating a method of manufacturing an integrated circuit according to some embodiments;

[0021] Figure 12 is a block diagram illustrating a system on a chip (SoC) according to some embodiments; and

[0022] Figure 13 is a block diagram illustrating a computing system including memory for storing programs according to some embodiments. DETAILED DESCRIPTION

[0023] Figure 1 1 and 2. A plan view of a first cell C11, a second cell C12, and a third cell C13 according to some embodiments is shown. The terms first, second, third, etc. used herein are merely for the purpose of distinguishing or differentiating one element from another. Figure 1The layout of an integrated circuit is shown as follows: a first cell C11 and a second cell C12, which are single-height cells arranged in a first row R11 and a second row R12, respectively; and a third cell C13, which is a multi-height cell arranged continuously in the first row R11 and the second row R12. The X-axis direction and the Y-axis direction can be referred to as the first horizontal direction and the second horizontal direction, respectively, and the Z-axis direction can be referred to as the vertical direction. The plane formed by the X-axis and the Y-axis can be referred to as the horizontal plane, and a component arranged in the (+) Z-axis direction relative to another component can be referred to as above or above the other component, and a component arranged in the (-) Z-axis direction relative to another component can be referred to as below or below the other component. Unless otherwise specified herein, the height of a component can refer to the length of the component in the Y-axis direction, and the width of a component can refer to the length of the component in the X-axis direction. In addition, the area of a component can refer to the dimension occupied by the component on a plane parallel to the horizontal plane (e.g., the footprint of the component). In the drawings herein, only some layers may be shown for convenience of explanation, and for ease of understanding, through-holes may be shown although they are located under patterns of metal layers.

[0024] A cell may be a layout unit included in an integrated circuit and may be referred to as a standard cell. An integrated circuit may include a plurality of different cells. A cell may have a structure according to a specific standard and may be arranged in multiple rows. For example, Figure 1 As shown, the first cell C11 may be arranged in a first row R11 extending along the X-axis direction, and the second cell C12 may be arranged in a second row R12. The first height D11 of the first row R11 and the second height D12 of the second row R12 may be the same, and the first cell C11 and the second cell C12 may have the same height (first height D11 or second height D12). In this way, cells having a height equal to the height of the row so that the cells are arranged in a row may be referred to as single-height cells.

[0025] refer to Figure 1 , the third cell C13 may be continuously arranged in the first row R11 and the second row R12. In some embodiments, cells continuously arranged in multiple rows (e.g., the first row R11 and the second row R12) may refer to cells continuously extending into the area corresponding to the multiple rows. Figure 1As shown, the height of the third cell C13 can be equal to the sum of the first height D11 of the first row R11 and the second height D12 of the second row R12. In this way, cells arranged continuously in two or more consecutive rows can be referred to as multi-height cells, and in particular, cells arranged continuously in two adjacent rows can be referred to as double-height cells. In other words, a multi-height cell can have a height that is several times the same as the height of a single row (or the height of a single-height cell). Multi-height cells can be used for various purposes. For example, multi-height cells can be used to implement structures in which it is not easy to route signals by extending in the X-axis direction, or can be used as decaps, fillers, etc. Hereinafter, the embodiments of the present invention will mainly refer to double-height cells or double-height cells (for example, Figure 1 The present invention is described with reference to the third cell C13 in FIG, but it will be appreciated that some embodiments may also be applicable to multi-height cells sequentially arranged in three or more consecutive rows.

[0026] The first cell C11, the second cell C12, and the third cell C13 may include an active region and a fin extending in the X-axis direction, and may include a gate line extending in the Y-axis direction. In some embodiments, the active region may include a semiconductor such as silicon (Si) or germanium (Ge), or a compound semiconductor such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP), as well as a conductive region such as an impurity-doped well or impurity-doped structure. In some embodiments, the gate line may include a work function metal-containing layer and / or a gap fill metal layer. For example, the work function metal-containing layer may include titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and / or palladium (Pd), and the gap fill metal layer may include a W layer or an aluminum (Al) layer. In some embodiments, the gate line may include a stacked structure of TiAlC / TiN / W (where N is nitrogen), a stacked structure of TiN / TaN / TiAlC / TiN / W, or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W. In the following figures, for ease of illustration, fins in the active region may not be shown, but it will be understood that embodiments of the present inventive concept are applicable not only to cells including planar transistors but also to cells including fin field-effect transistors (FinFETs).

[0027] In some embodiments, the single-height cells may be arranged in two adjacent rows with a mutually symmetrical structure. Figure 1As shown, the first cell C11 and the second cell C12 can provide the same function as an inverter including an input pin A and an output pin Y, but can have structures that are symmetrical with respect to the boundary between the first row R11 and the second row R12. Therefore, the active region P12 of the p-channel field effect transistor (PFET) and the active region N12 of the n-channel field effect transistor (NFET) for the first cell C11 can be symmetrical with the active region P13 of the PFET and the active region N13 of the NFET for the second cell C12 about the boundary between the first row R11 and the second row R12.

[0028] The power lines extending in the X-axis direction at the boundary between the first row R11 and the second row R12 may be arranged to supply power to the first to third cells C11 to C13. Figure 1 As shown, the first power line PL11 may extend in the X-axis direction at the boundary between the first row R11 and the second row R12, and the first cell C11 and the second cell C12 may share or include corresponding portions of the first power line PL11. Similarly, the third power line PL13 and the fourth power line PL14 may extend in the X-axis direction. Although the power lines are shown and described herein as a pattern of the M1 layer, the embodiments of the present inventive concept are not limited thereto, and in some embodiments, the power lines may be formed as a pattern of a wiring layer above the M1 layer, for example, as a pattern of the M2 layer. In some embodiments, a first power supply voltage may be applied to odd-numbered power lines, and a second power supply voltage may be applied to even-numbered power lines. For example, as Figure 1 As shown, a positive power voltage VDD may be applied to the first power line PL11 , and a negative power voltage VSS is applied to the third and fourth power lines PL13 and PL14 adjacent to the first power line PL11 .

[0029] The third cell C13 may receive power from the fifth power line PL15 and the sixth power line PL16, which are electrically connected to the third power line PL13 supplying power to the first cell C11 and the fourth power line PL14 supplying power to the second cell C12, respectively. The fifth power line PL15 and the sixth power line PL16 may be separately arranged on the boundary of the third cell C13 and may extend in the X-axis direction. In this specification, the power lines (e.g., the fifth power line PL15 and the sixth power line PL16) arranged on the boundary of the multi-height cells may be referred to as outbound power lines. Figure 1 As shown, when the third cell C13 is a double-height cell, the fifth power line PL15 and the sixth power line PL16 may provide the same power voltage, ie, the same negative power voltage VSS.

[0030] The third cell C13 may include a second power line PL12 electrically connected to the first power line PL11 shared by the first cell C11 and the second cell C12, and extending in the X-axis direction in the first row R11. In other words, the second power line PL12 providing the positive power supply voltage VDD may be arranged in one direction starting from the center of the third cell C13, for example, at a position toward the fifth power line PL15, as shown in FIG. Figure 1 As shown. Figure 1 Unlike the example shown in FIG, when the second power line PL12 is arranged at the same position as the first power line PL11 (i.e., at the center of the third cell C13), the area of the M1 layer to which the second power line PL12 belongs can be divided into two in the third cell C13. Figure 1 As shown, the second power line PL12 and the sixth power line PL16 are arranged so that a large area between them can be used to route the input signals, output signals, and internal signals of the third cell C13. Therefore, the structure of multi-height cells such as the third cell C13 can be simplified, and the increased size of the input pins (e.g., A in the third cell C13) and the increased size of the output pins (e.g., Y in the third cell C13) can reduce routing congestion in the integrated circuit.

[0031] In some embodiments, the width D13 of the second power line PL12, i.e., its length in the Y-axis direction, can be greater than the width of a pattern in the same layer as the second power line PL12. The widths (i.e., their lengths in the Y-axis direction) of power lines such as the first power line PL11, third power line PL13, and fourth power line PL14, which supply power to the first and second cells C11 and C12 as single-height cells, can be greater than the width of a pattern in the same layer. The second power line PL12 included in the third cell C13 as a multi-height cell can also have a relatively large width D13. In some embodiments, the width of the second power line PL12 can be the same as the width of the first power line PL11 (in other words, its length in the Y-axis direction).

[0032] The third cell C13 may include active regions such as the active region P11 and the active region N11 extending in the X-axis direction and having different conductivity types. Figure 1As shown, the length of active region P11 for a PFET or p-channel metal oxide semiconductor (PMOS) transistor in the Y-axis direction can be greater than the length of active region P12 for the PFET of the first cell C11, and active region P11 can include at least a portion of the first row R11. Similarly, the length of active region N11 for an NFET or n-channel metal oxide semiconductor (NMOS) transistor in the Y-axis direction can be greater than the length of active region N13 for the NFET of the second cell C12, and active region N11 can include at least a portion of the second row R12. In this way, the third cell C13 can have a structure that is at least partially independent of the structures of the first cell C11 and the second cell C12, and thus can have a more efficient structure.

[0033] Figure 2 A plan view of a first cell C21 and a second cell C22 is shown according to some embodiments. Figure 2 A first cell C21 is shown as a single-height cell and a second cell C22 is shown as a multi-height cell that performs the same function as the first cell C21.

[0034] refer to Figure 2 , the first cell C21 may include an active area P21 for a PFET and an active area N21 for an NFET, which extend in the X-axis direction. The active area P21 and the active area N21 may be spaced or separated from each other by a first distance D21 in the Y-axis direction, and the fin extending in the X-axis direction in the region between the active area P21 and the active area N21 may be referred to as a dummy fin, which does not form or otherwise function as a transistor. In some embodiments, a contact or gate contact connected to a gate according to design rules may be prohibited from being arranged in the active area, and thus the distance between the active area P21 and the active area N21 (i.e., the first distance D21) may be increased to facilitate the arrangement of gate contacts for routing multiple input pins A0, A1, B0, and B1, and the number of dummy fins may be increased. In addition, the area of the active area P21 and the active area N21 may be reduced due to the limited cell height and the increased first distance D21. As a result, the performance (e.g., operating speed) of the first cell C21 may be limited as the size of the transistor decreases. In this way, in the first cell C21 having a limited height equal to the height of a row, a complex configuration of multiple input pins A0, A1, B0 and B1, output pin Y, patterns for routing internal signals (e.g., contact portions), metal patterns and through-holes can be completed according to design rules.

[0035] The second cell C22 can provide the same functionality as the first cell C21 and can include an active area P22 for a PFET and an active area N22 for an NFET, which extend in the X-axis direction. Active areas P22 and N22 can be spaced or separated from each other by a second distance D22 in the Y-axis direction. Contacts (i.e., active contacts) and metal patterns for routing the source and drain of the transistors can be primarily formed on active areas P22 and N22 due to the relatively long lengths of active areas P22 and N22 in the Y-axis direction. Therefore, gate contacts for multiple input pins A0, A1, B0, and B1 can be aligned in the X-axis direction. As a result, the distance between active areas P22 and N22, i.e., second distance D22, can be less than first distance D21, thereby reducing the number of dummy fins in the second cell C22. In this way, compared to the first unit C21, the configuration of multiple input pins A0, A1, B0 and B1, output pin Y, patterns for routing internal signals (e.g., contact portions), metal patterns and through-holes can be simply completed according to design rules or otherwise routed with lower complexity.

[0036] The first power line PL21 applying the positive power supply voltage VDD in the second cell C22 may extend in the X-axis direction at a position spaced apart or separated from the center or central area of the second cell C22 in the Y-axis direction. Figure 2 As shown, the first power line PL21 may be disposed at a position spaced apart or separated from the second power line PL22 applying the negative power voltage VSS such that the conductive pattern M21 of the M1 layer for internal signals is disposed between PL22 and PL21.

[0037] Figure 3 is a plan view illustrating the layout of integrated circuit 30 according to some embodiments. Figure 3 A layout of an integrated circuit 30 is shown including multi-height cells, namely a first cell C31 , a second cell C32 , a third cell C33 and a fourth cell C34 , which have different structures from each other while providing the same function and performance.

[0038] As above reference Figure 1As described above, different power supply voltages can be applied to the odd-numbered power lines and the even-numbered power lines arranged at the boundaries of the rows and extending in the X-axis direction, respectively. Therefore, a plurality of multi-height cells can be defined, which have different structures and provide the same function and performance according to the power supply voltage applied to the power lines, that is, the outgoing power lines can be arranged at the two boundaries of the multi-height cells. In addition, a plurality of multi-height cells can be defined, which have different structures and provide the same function and performance according to the position of the active areas included in the multi-height cells. For example, the first cell C31 and the second cell C32 can be continuously arranged on the first row R31 and the second row R32 (for example, can be continuously extended to the area corresponding to the first row R31 and the second row R32), but can respectively include active areas that are arranged differently. Because the active areas are arranged differently, the first power line PL31, included in the first cell C31 and applied with the positive power supply voltage VDD, can be arranged in the first row R31 of the active area for PFETs, while the second power line PL32, included in the second cell C32 and applied with the positive power supply voltage VDD, can be arranged in the second row R32 of the active area for PFETs. For example, the third cell C33 and the fourth cell C34 can be arranged consecutively in the second row R32 and the third row R33, but can each include an active area arranged differently. Because the active areas are arranged differently, the third power line PL33, included in the third cell C33 and applied with the negative power supply voltage VSS, can be arranged in the third row R33 of the active area for NFETs, while the fourth power line PL34, included in the fourth cell C34 and applied with the negative power supply voltage VSS, can be arranged in the second row R32 of the active area for NFETs.

[0039] As referenced below Figure 11 As described above, the cell library D112 defining the cell layout may define a plurality of layouts of multi-height cells that provide the same function and performance but have different structures, and one of the plurality of layouts may be selected and arranged in a process of generating layout data of an integrated circuit (e.g., placement and routing operations). In the following, reference will be made mainly to the multi-height cells (e.g., Figure 3 An embodiment of the present invention is described using the first cell C31 in FIG, wherein a negative power supply voltage VSS is applied to power lines extending along the X-axis direction at opposite boundaries in the Y-axis direction, active areas for PFETs are arranged along the (+) Y-axis direction, and active areas for NFETs are arranged along the (-) Y-axis direction, but the embodiment is not limited thereto.

[0040] Figures 4A to 4C is a plan view illustrating the layout of integrated circuits 40a, 40b, and 40c according to some embodiments. Figures 4A to 4C An example of an interface between a single height unit and a multi-height unit is shown. Figures 4A to 4C Some unit layers in , and references are omitted Figures 4A to 4C Repeated description of .

[0041] refer to Figure 4A , the integrated circuit 40a may include a first cell C41a arranged in a first row R41, a second cell C42a arranged in a second row R42, and a third cell C43a arranged consecutively in the first row R41 and the second row R42. The first cell C41a and the third cell C43a may be adjacent to each other in the X-axis direction, and the second cell C42a and the third cell C43a may also be adjacent to each other in the X-axis direction. The first cell C41a, the second cell C42a, and the third cell C43a may share a gate line G41a extending in the Y-axis direction along the boundary between the single-height cells C41a, C42a and the multi-height cell C43a. In some embodiments, the gate line G41a may not define or form a transistor, in other words, it may be a dummy gate line. In some embodiments, a single diffusion break (SDB) extending in the Y-axis direction may be formed at the boundary between the first cell C41a and the third cell C43a, and the SDB may be formed below the gate line G41a or in an area where the gate line G41a is removed.

[0042] refer to Figure 4B , the integrated circuit 40b may include a first cell C41b arranged in a first row R41, a second cell C42b arranged in a second row R42, and a third cell C43b arranged continuously in the first row R41 and the second row R42, and may also include a fourth cell C44 arranged continuously in the first row R41 and the second row R42 between the first cell C41b and the third cell C43b and between the second cell C42 and the third cell C43b. In this specification, a cell such as the fourth cell C44 may be referred to as an interface cell, which is arranged between a single-height cell and a multi-height cell and performs a function of connecting (or otherwise being configured to be connected to) a multi-height cell having a structure independent of the single-height cell to the single-height cell. Referring below 5A to 6D etc. to describe examples of the interface unit.

[0043] The length of the fourth cell C44 in the X-axis direction, ie, the width D40, can be determined by the semiconductor process for manufacturing the integrated circuit 40b. Figure 4BAs shown, the active area of the PFET of the third cell C43b may include a portion overlapping with the active area of the NFET of the first cell C41b in the X-axis direction. Therefore, the fourth cell C44 as the interface cell may have a structure in which the active area of the PFET of the third cell C43b and the active area of the NFET of the first cell C41b are separated. The design rules of the semiconductor process may define the minimum separation distance (or minimum space) between active areas of different conductivity types, the minimum separation distance between the gate line and the active area, etc. In addition, in some embodiments, such as Figure 5A and Figure 5B As shown, when the active region for the PFET is formed in a well, the design rules may define a minimum separation distance from the well to the active region of the NFET. Thus, the width D40 of the fourth cell C44 may be determined based on the minimum separation distance between active regions of different conductivity types defined by the design rules. In some embodiments, the cells included in the integrated circuit 40 b may share a gate line extending in the Y-axis direction at the boundary with adjacent cells and may have a width corresponding to a multiple of the pitch between the gate lines (i.e., a multiple of a contact poly pitch (CPP)). The width D40 of the fourth cell C44 may also have a width corresponding to a multiple of the CPP.

[0044] refer to Figure 4C The integrated circuit 40c may include a first cell C41c arranged in a first row R41, a second cell C42c arranged in a second row R42, a third cell C43c arranged in a third row R43 (which are single-height cells), and may include a fourth cell C44c and a fifth cell C45c, which are multi-height cells and are arranged in three consecutive rows (for example, may extend continuously to the areas corresponding to rows R41, R42 and R43), wherein the fifth cell C45c may be used as an interface unit.

[0045] like Figure 4C As shown, the fourth cells C44c arranged consecutively in three rows can receive power from corresponding outgoing power lines to which different power supply voltages are applied. Figure 4C As shown, the first power line PL41 to which the positive power voltage VDD is applied may be arranged at one side boundary, and the second power line PL42 to which the negative power voltage VSS is applied may be arranged at the other side boundary. Figure 4C As shown, in the case where the active region P41 of the PFET of the fourth cell C44c can be arranged adjacent to the first power line PL41 and the active region N41 of the NFET of the fourth cell C44c can be arranged adjacent to the second power line PL42, the power line (e.g., Figure 1 As mentioned above, Figure 4BAs described above, the fifth cell C45c serving as the interface unit may include a portion separating the active regions of the NFETs of the first cell C41c and the second cell C42c from the active region of the PFET of the fourth cell C44c, and may include a portion separating the active regions of the PFETs of the third cell C43c and the second cell C42c from the active region N41 of the NFET of the fourth cell C44c.

[0046] Although respectively Figure 4B and Figure 4C , the interface units (e.g., the fourth unit C44 and the fifth unit C45c) are shown as being arranged on the left side of the multi-height unit (i.e., in the (-) X-axis direction) or on the left side relative to the multi-height unit, but the interface units (e.g., the fourth unit C44 and the fifth unit C45c) may be arranged on the opposite side of the multi-height unit (i.e., in the (+) X-axis direction) or on the opposite side relative to the multi-height unit. Hereinafter, it will be understood that although the example of the interface unit being arranged on the left side of the multi-height unit or on the left side relative to the multi-height unit is mainly described, the embodiments are not limited thereto.

[0047] Figure 5A and Figure 5B is a plan view illustrating the layout of integrated circuits 50a and 50b according to some embodiments. Figure 5A and Figure 5B An example of an interface unit is shown, which differently processes a plurality of fins extending in the X-axis direction and parallel to each other. Reference will be omitted Figure 5A and Figure 5B Overlapping content in the given descriptions.

[0048] refer to Figure 5A , the integrated circuit 50a may include a first cell C51a arranged in a first row R51, a second cell C52a arranged in a second row R52, and a third cell C53a and a fourth cell C54a arranged consecutively in the first row R51 and the second row R52. The fourth cell C54a as an interface cell may cut off a plurality of fins extending in the X-axis direction and parallel to each other. That is, the fourth cell C54a may not have a fin extending in the X-axis direction. In some embodiments, the wells of the first cell C51a and the second cell C52a and the well of the third cell C53a may extend in the X-axis direction into the fourth cell C54a and terminate in the fourth cell C54a. In some embodiments, as Figure 5A As shown, the fourth cell C54a may interconnect the wells of the first cell C51a and the second cell C53a.

[0049] refer to Figure 5B, the integrated circuit 50b may include a first cell C51b arranged in a first row R51, a second cell C52b arranged in a second row R52, and a third cell C53b and a fourth cell C54b arranged consecutively in the first row R51 and the second row R52. The fourth cell C54b as an interface cell may not cut off at least a portion of the plurality of fins extending in the X-axis direction and parallel to each other. For example, as Figure 5B As shown, the first fin F51 and the fifth fin F55 extending above the active area for NFET and the active area for PFET can be cut off in the fourth cell C54b, and the second fin F52 and the sixth fin F56 including the portion extending between the active areas can be cut off in the fourth cell C54b. On the other hand, the third fin F53 and the seventh fin F57 extending above the active area of the same conductivity type can not be cut off in the fourth cell C54b, and the fourth fin F54 (i.e., the dummy fin) can also not be cut off in the fourth cell C54b. That is, the fins F53, F54 and F57 can extend continuously across the boundaries between the single-height cells C51b, C52b and the multi-height cells C53b, C54b.

[0050] In some embodiments, the interface unit may include an active region that connects two active regions of the single-height unit and the multi-height unit in the X-axis direction, wherein the two active regions have the same conductivity type. Figure 5B As shown, the fourth cell C54b may include an active region P51 for a PFET, which overlaps with the active region of the PFET of the first cell C51b and the active region of the PFET of the third cell C53b in the X-axis direction. In addition, the fourth cell C54b may include an active region N51 for an NFET, which overlaps with the active region of the NFET of the second cell C52b and the active region of the NFET of the third cell C53b in the X-axis direction.

[0051] Figures 6A to 6C is a plan view illustrating the layout of integrated circuits 60a, 60b, 60c, and 60d according to some embodiments. 6A to 6D An example of an interface unit that differently connects the power line of a single-height unit to the power line included in a multi-height unit is shown. Figures 6A to 6B Similar or duplicate content in the description.

[0052] Arranged in single height units (e.g. Figure 6A C61a and C62a in ) and multi-height units (e.g. Figure 6A C63a) between the interface unit (for example, Figure 6A C64a in) may include interconnections (e.g., Figure 6AIC60a in the embodiment is used to electrically connect the power lines of the single-height unit to the power lines of the multi-height unit (e.g., Figure 6A PL61a and PL62a in the interface unit). The interconnect included in the interface unit may include at least one conductive pattern extending in the Y-axis direction to electrically connect the power lines arranged at different positions in the Y-axis direction. 6A to 6D As described above, the interconnects included in the interface unit C64a may include various types of conductive patterns, and in some embodiments, 6A to 6D Two or more of the conductive patterns shown in can be arranged in parallel with each other and combined together. Figures 6A to 6D In the example, the interface unit (e.g., Figure 6A C64a in FIG. 1 may be shown as having a spacing, ie, a pair of gate lines (eg, Figure 6A However, it should be understood that embodiments of the inventive concept are applicable to interface cells having widths of two or more CPPs.

[0053] refer to Figure 6A The integrated circuit 60a may include a first cell C61a arranged in a first row R61, a second cell C62a arranged in a second row R62, and a third cell C63a and a fourth cell C64a arranged consecutively in the first row R61 and the second row R62. The third cell C63a, which is a multi-height cell, may include a second power line PL62a extending in the X-axis direction in the active region of the PFET and offset from the first power line PL61a. The positive power supply voltage VDD may be supplied from the second power line PL62a to the source of the transistor formed in the active region of the PFET of the third cell C63a.

[0054] The fourth unit C64a as an interface unit may include an interconnect IC60a that electrically connects the first power line PL61a shared by the first unit C61a and the second unit C62a to the second power line PL62a of the third unit C63a. Figure 6A As shown, interconnect IC60a may include a portion that is patterned as the same M1 layer as the first power line PL61a and the second power line PL62a and extends in the Y-axis direction. Thus, the first power line PL61a can be electrically connected to the second power line PL62a, and a positive power supply voltage VDD can be applied to the second power line PL62a. The first gate line G61a and the second gate line G62a may extend parallel to each other in the Y-axis direction at the boundary of the fourth cell C64a and may be dummy gate lines.

[0055] refer to Figure 6BThe integrated circuit 60b may include a first cell C61b arranged in a first row R61, a second cell C62b arranged in a second row R62, and a third cell C63b and a fourth cell C64b arranged consecutively in the first row R61 and the second row R62. The third cell C63b, which is a multi-height cell, may include a second power line PL62b extending in the X-axis direction in the active region of the PFET and offset from the first power line PL61b. The positive power supply voltage VDD may be supplied from the second power line PL62b to the source of the transistor formed in the active region of the PFET of the third cell C63b.

[0056] The fourth unit C64b as the interface unit may include an interconnection IC60b, and the interconnection IC60b may include a pattern M64 that is a pattern of the M2 layer (or other layer higher than the layers of the first power line PL61b and the second power line PL62b) and extends along the Y-axis direction. Figure 6B As shown, interconnect IC60b may include a pattern of the M1 layer that extends the first power line PL61b in the X-axis direction, and a pattern of the M1 layer that extends the second power line PL62b in the X-axis direction, and may also include a pattern M64 of the M2 layer connected to the pattern of the M1 layer via a conductive via. Thus, the first power line PL61b can be electrically connected to the second power line PL62b, and a positive power supply voltage VDD can be applied to the second power line PL62b. The first gate line G61b and the second gate line G62b may extend parallel to each other in the Y-axis direction at the boundary of the fourth cell C64b and may be dummy gate lines.

[0057] refer to Figure 6C The integrated circuit 60c may include a first cell C61c arranged in a first row R61, a second cell C62c arranged in a second row R62, and a third cell C63c and a fourth cell C64c arranged consecutively in the first row R61 and the second row R62. The third cell C63c, which is a multi-height cell, may include a second power line PL62c extending in the X-axis direction in the active region of the PFET and offset from the first power line PL61c. The positive power supply voltage VDD may be supplied from the second power line PL62c to the source of the transistor formed in the active region of the PFET of the third cell C63c.

[0058] The fourth unit C64c as the interface unit may include an interconnection IC60c, and the interconnection IC60c may include portions of a first gate line G61c and a second gate line G62c extending in parallel at a boundary of the fourth unit C64c in the Y-axis direction. Figure 6CAs shown, interconnect IC 60c may include a pattern of the M1 layer that extends the first power line PL61c in the X-axis direction and a pattern of the M1 layer that extends the second power line PL62c in the X-axis direction, and may include a contact portion and a conductive via that connect the pattern of the M1 layer to the first gate line G61c and the second gate line G62c. Thus, the first power line PL61c can be electrically connected to the second power line PL62c, and the positive power supply voltage VDD can be applied to the second power line PL62c.

[0059] refer to Figure 6D The integrated circuit 60d may include a first cell C61d arranged in a first row R61, a second cell C62d arranged in a second row R62, and a third cell C63d and a fourth cell C64d arranged consecutively in the first row R61 and the second row R62. The third cell C63d, which is a multi-height cell, may include a second power line PL62d extending in the X-axis direction in the active region of the PFET and offset from the first power line PL61d. The positive power supply voltage VDD may be supplied from the second power line PL62d to the transistor formed in the active region of the PFET of the third cell C63d.

[0060] In some embodiments, the unidirectional pattern may be mainly formed in the M1 layer and the M2 layer. Therefore, it may not be easy to form a pattern of the M1 layer extending in the Y-axis direction, where the electric field lines extending in the X-axis direction are as shown in FIG. Figure 6A As shown, it can be formed Figures 6B to 6D The structure shown in .

[0061] The fourth unit C64d as the interface unit may include an interconnection IC60d, and the interconnection IC60d may include a contact portion T64 that is a pattern of a layer lower than the M1 layer of the first power line PL61d and the second power line PL62d and extends in the Y-axis direction. Figure 6D As shown, interconnect IC60d may include a pattern of the M1 layer extending a first power line PL61d in the X-axis direction and a pattern of the M1 layer extending a second power line PL62d in the X-axis direction, and may include a contact portion T64 connected to the pattern of the M1 layer via a conductive via. Thus, the first power line PL61d can be electrically connected to the second power line PL62d, and a positive power supply voltage VDD can be applied to the second power line PL62d. The first gate line G61d and the second gate line G62d may extend parallel to each other in the Y-axis direction at the boundary of the fourth cell C64d and may be dummy gate lines.

[0062] Figure 7A and Figure 7B 7 are a plan view and a perspective view, respectively, illustrating the layout of an integrated circuit 70 according to some embodiments. Figure 7A and Figure 7B An example of the structure of power lines connecting single-height cells and multi-height cells arranged adjacent to each other is shown.

[0063] refer to Figure 7A , the integrated circuit 70 may include first cells C71 arranged in a first row R71, second cells C72 arranged in a second row R72, and third cells C73 arranged consecutively in the first row R71 and the second row R72. The first cells C71 and the second cells C72 may share or include corresponding portions of the first power line PL71. The third cell C73, as a multi-height cell, may include a second power line PL72 extending in the X-axis direction in the active region of the PFET and offset from the first power line PL71. The positive power supply voltage VDD may be supplied from the second power line PL72 to the transistor formed in the active region of the PFET of the third cell C73.

[0064] The first gate line G71 may extend in the Y-axis direction across the first cell C71 and the second cell C72, and the third gate line G73 may extend in the Y-axis direction in the third cell C73. The second gate line G72 may extend in the Y-axis direction along a boundary of the third cell C73 between the first gate line G71 and the third gate line G73, and may connect the first power line PL71 to the second power line PL72.

[0065] refer to Figure 7B , the first power line PL71 can be connected to the second gate line G72 through the first through hole V71 and the first contact portion T71. In addition, the second power line PL72 can be connected to the second gate line G72 through the second through hole V72 and the second contact portion T72. In some embodiments, the contact portion can be divided into an active contact portion connected to the active area and a gate contact portion connected to the gate line. For example, the first contact portion T71 may include an active contact portion CA71 extending in the Y-axis direction and connected to the active area between the first gate line G71 and the second gate line G72, and a gate contact portion CB71 extending in the X-axis direction and connected to the second gate line G72. Similarly, the second contact portion T72 may include an active contact portion CA72 extending in the Y-axis direction and connected to the active area between the second gate line G72 and the third gate line G73, and a gate contact portion CB72 extending in the X-axis direction and connected to the second gate line G72.

[0066] Figure 8A and Figure 8B is a plan view illustrating the layout of integrated circuits 80a and 80b according to some embodiments. Figure 8A and Figure 8BAn example of the pattern of the M2 layer as the upper wiring layer on the single-height cell and the multi-height cell is shown. Reference will be omitted. Figure 8A and Figure 8B Overlapping content in the given descriptions.

[0067] refer to Figure 8A , the integrated circuit 80a may include a first cell C81a and a second cell C82a as single-height cells, and may include a third cell C83a and a fourth cell C84a as multi-height cells. Figure 8A As shown, the M2 layer may include a pattern for routing signals extending in the X-axis direction. Additionally, the M2 layer above the power lines of the M1 layer may include power lines connected to the power lines of the M1 layer via conductive vias and extending in the X-axis direction, and the power lines of the M2 layer may be referred to as upper power lines. For example, the first power line PL81a of the M2 layer may extend in the X-axis direction at the boundary between the first cell C81a and the second cell C82a, and the second power line PL82a of the M2 layer may extend in the X-axis direction in the third cell C83a.

[0068] In some embodiments, the power lines of the M2 layer shared by single-height cells can extend across multiple-height cells. Figure 8A As shown, the first power line PL81a of the M2 layer extending in the X-axis direction at the boundary between the first cell C81a and the second cell C82a may extend in the X-axis direction across the fourth cell C84a (which is an interface cell) and the third cell C83. Figure 8A As shown, in the portion where the first power line PL81a overlaps the third cell C83a in the Z-axis direction, the third cell C83a may not need the power line of the M1 layer to which the positive power supply voltage VDD is applied, and thus no through hole may be formed.

[0069] refer to Figure 8B , the integrated circuit 80b may include a first cell C81b and a second cell C82b as single-height cells, and may include a third cell C83b and a fourth cell C84b as multi-height cells. In some embodiments, the power line of the M2 layer shared by the single-height cells may be cut off in the multi-height cells, and a pattern for routing signals may be formed in the region where the power line of the M2 layer is cut off. For example, Figure 8B As shown, Figure 8B The first power line PL81b in the integrated circuit 80b may have an end in the interface unit C84b, and the area corresponding to the first power line PL81b in the third unit C83c may include a pattern M82 for routing signals. Figure 8A transferability of the positive power supply voltage VDD within the integrated circuit 80a, but can provide Figure 8B Improved routing flexibility of signals within the integrated circuit 80b.

[0070] Figure 9 is a plan view illustrating the layout of integrated circuit 90 according to some embodiments. Figure 9 Examples of patterns forming power grids in single-height cells and multi-height cells are shown. Figure 9 In FIG. 4 , the power mesh is shown as including patterns of the M3 layer, but in some embodiments, the power mesh may include patterns of wiring layers higher than the M3 layer.

[0071] The integrated circuit 90 may include a first cell C91 and a second cell C92 as single-height cells, and may include a third cell C93 and a fourth cell C94 as multi-height cells. Figure 8A and Figure 8B As shown, the first power line PL91 of the M2 layer can extend in the X-axis direction, and the second power line PL92 electrically connected to the first power line PL91 can also extend in the X-axis direction. Figure 9 As shown, the third power line PL93 and the fourth power line PL94 may extend in the X-axis direction.

[0072] A pattern (e.g., first to fourth power grid lines PM91 to PM94) extending in the Y-axis direction for routing power supply voltages on the M3 layer may be formed, and the pattern of the M3 layer may form a power grid. A power grid may refer to a pattern regularly arranged (e.g., at periodic intervals or spacings) to supply power to cells included in the integrated circuit 90, and the patterns included in the power grid may be referred to as power grid lines. The power grid lines may be connected to the power lines of the M2 layer via conductive vias V2.

[0073] In some embodiments, the first power supply voltage may be applied to odd-numbered power grid lines, and the second power supply voltage may be applied to even-numbered power grid lines. Figure 9In the integrated circuit 90, a positive power supply voltage VDD may be applied to the first power grid line PM91 and the third power grid line PM93, while a negative power supply voltage VSS may be applied to the second power grid line PM92 and the fourth power grid line PM94. Thus, odd-numbered power grids (e.g., the first power grid line PM91 and the third power grid line PM93) may be connected to the first power line PL91 and the second power line PL92, to which the positive power supply voltage VDD is applied via vias V2, while even-numbered power grids (e.g., the second power grid line PM92 and the fourth power grid line PM94) may be connected to the third power line PL93 and the fourth power line PL94, to which the negative power supply voltage VSS is applied via vias V2. In this way, the power supply voltage can be applied to the power grid lines of the power grid, and the second power line PL92 included in the third cell C93 (which is a multi-height cell) can be connected to at least one power grid line through the conductive via V2, resulting in that a positive power supply voltage can be stably applied to the second power line PL92 in the third cell C93.

[0074] Figure 10 A plan view of a first cell C101 and a second cell C102 is shown, according to some embodiments. Figure 10 A multi-height unit is shown which provides the same functionality and includes the same pattern as the single-height unit.

[0075] The first cell C101 may function as an inverter including an input pin A and an output pin Y, and may receive a positive power voltage VDD and a negative power voltage VSS from first and second power lines PL101 and PL102 extending in the X-axis direction at a boundary of the first cell C101, respectively.

[0076] When a contact to the gate, i.e., a gate contact in the active region, can be formed, the multi-height cell can include at least some of the same structures as the single-height cell and can include power lines that extend across the multi-height cell as the power lines of the single-height cell extend. Figure 10 As shown, a negative power supply voltage VSS can be supplied to the second cell C102 from the third power line PL103 and the fifth power line PL105, and the fourth power line PL104, which provides the positive power supply voltage VDD, can extend across the second cell C102 in the X-axis direction. In addition, the pattern of the M1 layer formed between the third power line PL103 and the fourth power line PL104 can be the same as the pattern of the M1 layer of the first cell C101, and the pattern of the M1 layer formed between the fourth power line PL104 and the fifth power line PL105 can also be the same as the pattern of the M1 layer of the first cell C101.

[0077] Figure 11 is a flowchart illustrating a method of manufacturing an integrated circuit according to some embodiments.

[0078] The cell library (or standard cell library) D112 may include information about the cell, such as function information, characteristic information, layout information, etc. Figure 11 As shown, the cell library D112 may include data defining the layout of multi-height cells (first data D112_1, second data D112_2, etc.). In some embodiments, for cells providing the same function and performance, the first data D112_1 may define the layout of the cell, such as Figure 3 The first cell C31 and the second cell C32 are arranged between the power lines to which the negative power supply voltage VSS is applied and include the power lines to which the positive power supply voltage VDD is applied, and the second data D112_2 defines the layout of the cell, which is, for example, Figure 3 The third cell C33 and the fourth cell C34 are arranged between the power lines to which the positive power supply voltage VDD is applied and include a power line to which the negative power supply voltage VSS is applied. In addition, the cell library D112 may define an interface cell for connecting a multi-height cell to a single-height cell.

[0079] A logic synthesis operation (S10) may be performed to generate netlist data D113 from register transfer level (RTL) data D111. For example, a semiconductor design tool (e.g., a logic synthesis tool) may generate netlist data D113 including a bitstream or a netlist by performing logic synthesis from RTL data D111 with reference to a cell library D112, which is written in a hardware description language (HDL), such as very high speed integrated circuit (VHSIC) HDL (VHDL) and Verilog. The cell library D112 may include information defining a multi-height cell that provides good performance due to an expanded active area, and thus the multi-height cell may be included in the integrated circuit with reference to the information included in the logic synthesis process.

[0080] A place and route (P&R) operation (S20) of generating layout data D114 from the netlist data D113 may be performed. Figure 11 As shown, the P&R operation S20 may include a plurality of operations S21, S22, and S23.

[0081] A cell placement operation (S21) may be performed. For example, a semiconductor design tool (e.g., a P&R tool) may place a plurality of cells with reference to a cell library D112 from netlist data D113. As described above, the semiconductor design tool may place single-height cells and multi-height cells.

[0082] An operation of generating an interconnection (S22) may be performed. The interconnection may electrically connect the output pin and the input pin of the unit and may include, for example, at least one through hole and at least one conductive pattern. In addition, as described above with reference to Figure 8A 、 Figure 8B and Figure 9 As described above, power lines and power grid lines can be generated, and through holes for connecting them can be generated. As described above, the multi-height cell can provide a large area of input pins and output pins, so routing can be easily performed, and signal delays occurring at the interconnection can be reduced by simplifying the generated interconnection.

[0083] An operation of generating layout data D114 may be performed (S23). The layout data D114 may have a format such as Graphic Database System Information Interchange (GDSII) and may include geometric information about cells and interconnections.

[0084] An optical proximity correction (OPC) operation (S30) may be performed. OPC may refer to a process of forming a pattern shape by correcting distortion phenomena such as refraction caused by light characteristics in photolithography included in a semiconductor process for manufacturing an integrated circuit, and the pattern on the mask may be determined by applying OPC to the layout data D114. In some embodiments, the layout of the integrated circuit may be modified in operation S30, and the limited modification of the integrated circuit in operation S30 may be post-processing for improving or optimizing the structure of the integrated circuit and may be referred to as design polishing.

[0085] An operation of manufacturing a mask (S40) may be performed. For example, a pattern on a mask may be defined to form patterns formed on a plurality of layers by applying OPC to the layout data D114, and at least one mask (or photomask) for forming the pattern of each of the plurality of layers may be manufactured.

[0086] An operation of manufacturing an integrated circuit (S50) may be performed. For example, the integrated circuit may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S40. Figure 11 As shown, operation S50 may include operations S51 and S52.

[0087] A front-end-of-the-line (FEOL) process (S51) may be performed. The FEOL process may be referred to as a process for forming individual components such as transistors, capacitors, and resistors on a substrate in an integrated circuit manufacturing process. For example, the FEOL process may include planarizing and cleaning the wafer, forming trenches, forming wells, forming gate lines, forming source and drain electrodes, and the like.

[0088] Back-end-of-line (BEOL) processes (S52) may be performed. BEOL processes may be referred to as processes in the integrated circuit manufacturing process that interconnect individual components such as transistors, capacitors, and resistors. For example, BEOL processes may include silicide gate, source, and drain regions, adding dielectrics, planarization, forming holes, adding metal layers, forming vias, forming passivation layers, and the like. The integrated circuit may be packaged in a semiconductor package and used as a product for various applications.

[0089] Figure 12 1 is a block diagram illustrating a system on chip (SoC) 120 according to some embodiments. SoC 120 may be a semiconductor device and may include an integrated circuit according to some embodiments. SoC 120 may be a single-chip implementation of complex functional blocks such as intellectual property (IP) that performs various functions, wherein multi-height units according to some embodiments of the present inventive concept are included in each functional block of SoC 120, thereby achieving SoC 120 that provides improved space efficiency and performance.

[0090] refer to Figure 12 , SoC 120 may include a modem 122, a display controller 123, a memory 124, an external memory controller 125, a central processing unit (CPU) 126, a transaction processing unit 127, a power management integrated circuit (PMIC) 128, and a graphics processing unit (GPU) 129, and each functional block of SoC 120 may communicate with each other via a system bus 121.

[0091] The CPU 126, which is capable of controlling the overall operation of the SoC 120, can control the operations of the other functional blocks (122, 123, 124, 125, 127, 128, and 129). The modem 122 can demodulate a signal received from outside the SoC 120, or can modulate a signal generated within the SoC 120 and transmit the modulated signal to the outside (e.g., to an external device). The external memory controller 125 can control the operation of transmitting and receiving data to and from an external memory device connected to the SoC 120. For example, programs and / or data stored in an external memory device can be provided to the CPU 126 or the GPU 129 under the control of the external memory controller 125. The GPU 129 can execute program instructions related to graphics processing. The GPU 129 can receive graphics data via the external memory controller 125 and can transmit the graphics data processed by the GPU 129 to the outside of the SoC 120 via the external memory controller 125. The transaction processing unit 127 may monitor data transactions of each functional block, and the PMIC 128 may control power supplied to each functional block under the control of the transaction processing unit 127. The display controller 123 may transmit data generated inside the SoC 120 to the display by controlling a display (or display device) outside the SoC 120.

[0092] The memory 124 may include non-volatile memory, such as electrically erasable programmable read-only memory (ROM) (EEPROM), flash memory, phase-change random access memory (RAM) (PRAM), resistive RAM (RRAM), nano-floating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), and ferroelectric RAM (FRAM), and volatile memory, such as dynamic RAM (DRAM), static RAM (SRAM), mobile DRAM, double data rate (DDR) synchronous DRAM (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, and / or rambus DRAM (RDRAM).

[0093] Figure 13 1 is a block diagram illustrating a computing system 130 including a memory for storing programs according to some embodiments. The method for manufacturing an integrated circuit according to some embodiments of the present inventive concept (eg, Figure 11 At least some of the operations included in the method).

[0094] The computing system 130 may be a stationary computing system, such as a desktop computer, a workstation, and a server, or a portable computing system, such as a laptop computer. Figure 13 As shown, the computing system 130 may include a processor 131, an input / output device 132, a network interface 133, a RAM 134, a ROM 135, and a storage device 136. The processor 131, the input / output device 132, the network interface 133, the RAM 134, the ROM 135, and the storage device 136 may be connected to a bus 137 and may communicate with each other via the bus 137.

[0095] The processor 131 may be referred to as a processing unit and may include at least one core capable of executing various instruction sets (e.g., Intel Architecture-32 (IA-32), 64-bit extensions to IA-32, x86-64, PowerPC, Scalable Processor Architecture (SPARC), microprocessors without internal interlocked pipeline stages (MIPS), Acorn Reduced Instruction Set Computer Machine (ARM), Intel Architecture-64 (IA-64), etc.), such as a microprocessor, an application processor (AP), a digital signal processor (DSP), and a graphics processing unit (GPU). For example, the processor 131 may access a memory, i.e., a RAM 134 or a ROM 135, via a bus 137 and may execute instructions stored in the RAM 134 or the ROM 135.

[0096] The RAM 134 may store a program 134_1 for manufacturing an integrated circuit according to some embodiments or at least a portion thereof, and the program 134_1 may enable the processor 131 to execute the steps included in the method of manufacturing an integrated circuit (eg, Figure 11 In other words, the program 134_1 may include a plurality of instructions that can be executed by the processor 131, and the plurality of instructions included in the program 134_1 may cause the processor 131 to perform the above-mentioned reference Figure 11 At least some of the operations included in the described flows.

[0097] The storage device 136 may not lose stored data even when the power supplied to the computing system 130 is interrupted. For example, the storage device 136 may include a non-volatile memory device and may include storage media such as tapes, optical disks, and / or magnetic disks. In addition, the storage device 136 may be removable from the computing system 130. The storage device 136 may store a program 134_1 according to some embodiments, and before the processor 131 executes the program 134_1, the program 134_1 or at least a portion thereof may be loaded from the storage device 136 into the RAM 134. Alternatively, the storage device 136 may store a file written in a programming language, and the program 134_1 generated from the file or at least a portion thereof by a compiler or the like may be loaded into the RAM 134. In addition, as Figure 13As shown, the storage device 136 may store a database 136_1, and the database 136_1 may include information required for designing an integrated circuit, such as Figure 11 Cell library D112 in .

[0098] The storage device 136 may store data to be processed by the processor 131 or data that has been processed by the processor 131. In other words, according to the program 134_1, the processor 131 may generate data by processing the data stored in the storage device 136 and may store the generated data in the storage device 136. For example, the storage device 136 may store Figure 11 The RTL data D111, netlist data D113 and / or layout data D114 in the .

[0099] The input / output device 132 may include input devices such as a keyboard and / or a pointing device, and may include output devices such as a display device and / or a printer. For example, a user may trigger the execution of the program 134_1 by the processor 131 through the input / output device 132, and may input Figure 11 RTL data D111 and / or netlist data D113 in, or mark Figure 11 Layout data D114 in.

[0100] Network interface 133 may provide access to a network external to computing system 130. For example, a network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of link.

[0101] As described above, embodiments have been disclosed in the drawings and the specification. For ease of description, spatially relative terms such as "under," "below," "above," "below," "above," "lower," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or features as shown in the drawings. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations shown in the drawings. For example, if the device in the drawings is turned over, an element described as "under" or "under" other elements or features will be oriented "above" or "above" the other elements or features. Thus, the term "under" may include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Although embodiments have been described herein with reference to specific terms, it should be understood that they are intended only to describe the technical ideas of the inventive concept and not to limit the scope of the inventive concept defined in the claims. Therefore, it will be clearly understood by those skilled in the art that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Therefore, the protection scope of the present invention should be determined by the technical ideas of the appended claims.

Claims

1. An integrated circuit comprising: a first cell in a first row, the first row extending in a first horizontal direction; a second cell in a second row adjacent to the first row and extending in the first horizontal direction; as well as a third unit extending continuously in the first row and the second row; wherein the first unit and the second unit include corresponding portions of a first power line extending in the first horizontal direction, wherein the third unit includes a second power line electrically connected to the first power line in the first row and extending in the first horizontal direction, the second power line being offset from the first power line in a second horizontal direction perpendicular to the first horizontal direction, and wherein a portion of the third unit in the second row is free of a fifth power line, The first unit and the third unit include corresponding portions of a third power line extending in the first horizontal direction, and the second unit and the third unit include corresponding portions of a fourth power line extending in the first horizontal direction.

2. The integrated circuit according to claim 1 , further comprising an interface cell comprising interconnects extending continuously in the first row and the second row, the interconnects being adjacent to the third cell and connecting the first power line to the second power line, in, At least a portion of the interconnect extends in the second horizontal direction.

3. The integrated circuit according to claim 2, wherein: The at least a portion of the interconnection includes at least one of a contact, a gate line, or a metal pattern extending in the second horizontal direction.

4. The integrated circuit according to claim 1, wherein: The first cell and the third cell are arranged adjacent to each other and share a gate line extending in the second horizontal direction at a boundary therebetween, the gate line being electrically connected to the first power line and the second power line.

5. The integrated circuit according to claim 1, wherein: The first power line and the second power line are configured to be applied with a first power supply voltage, and the third power line and the fourth power line are configured to be applied with a second power supply voltage.

6. The integrated circuit according to claim 1, wherein: The third unit includes at least one of a transistor, an input pin, or an output pin between corresponding portions of the second power line and the fourth power line.

7. The integrated circuit according to claim 1, wherein: The third unit includes a first active region of a first conductivity type and a second active region of a second conductivity type extending parallel to each other in the first horizontal direction, wherein at least a portion of the first active region is in the first row and at least a portion of the second active region is in the second row.

8. The integrated circuit of claim 7, further comprising: interface cells extending continuously in the first row and the second row between the first cell and the third cell and between the second cell and the third cell, In which, in the interface unit, the first active area of the third unit and the active area of the second conductive type included in the first unit are separated from each other in the first horizontal direction, and the second active area of the third unit and the active area of the first conductive type included in the second unit are separated from each other in the first horizontal direction.

9. The integrated circuit of claim 7, further comprising: interface cells extending continuously in the first row and the second row between the first cell and the third cell and between the second cell and the third cell, The interface unit includes at least one of the third active area or the fourth active area. The third active region connects the first active region to the active region of the first conductivity type included in the first unit. The fourth active region connects the second active region to the active region of the second conductivity type included in the second cell.

10. The integrated circuit of claim 1 , further comprising: a first upper power line electrically connected to the first power line, the first upper power line extending in the first horizontal direction above the first power line; as well as A second upper power line is electrically connected to the second power line, the second upper power line extending in the first horizontal direction above the second power line.

11. The integrated circuit according to claim 10, wherein: The first upper power line extends in the first horizontal direction across the third unit.

12. The integrated circuit of claim 10, further comprising: a power grid line extending in the second horizontal direction above the first upper power line and the second upper power line, The power grid lines include odd-numbered power grid lines electrically connected to the first upper power line and even-numbered power grid lines electrically connected to the second upper power line.

13. The integrated circuit according to claim 1, wherein: A size of the second power line in the second horizontal direction is equal to a size of the first power line in the second horizontal direction.

14. An integrated circuit comprising: a first cell in a first row, the first row extending in a first horizontal direction; a second cell in a second row adjacent to the first row and extending in the first horizontal direction; a third cell extending continuously in the first row and the second row, wherein the third cell includes a first active region of the first conductivity type and a second active region of the second conductivity type extending parallel to each other in the first horizontal direction, and wherein at least a portion of the first active region is in the first row and at least a portion of the second active region is in the second row; and an interface unit extending continuously in the first row and the second row between the first unit and the third unit and between the second unit and the third unit, In which, in the interface unit, the first active area of the third unit and the active area of the second conductive type included in the first unit are separated from each other in the first horizontal direction, and the second active area of the third unit and the active area of the first conductive type included in the second unit are separated from each other in the first horizontal direction.

15. The integrated circuit of claim 14, further comprising: interface cells extending continuously in the first row and the second row between the first cell and the third cell and between the second cell and the third cell, The interface unit includes at least one of the third active area or the fourth active area. The third active region connects the first active region to the active region of the first conductivity type included in the first unit. The fourth active region connects the second active region to the active region of the second conductivity type included in the second cell.

16. The integrated circuit of claim 14, wherein: The first unit and the second unit include corresponding portions of a first power line extending in the first horizontal direction, and the third unit includes a second power line electrically connected to the first power line in the first row and extending in the first horizontal direction, and wherein the second row does not have the second power line.

17. An integrated circuit comprising: a first cell in a first row, the first row extending in a first horizontal direction; a second cell in a second row adjacent to the first row and extending in the first horizontal direction; a third cell extending continuously in the first and second rows, wherein the third cell includes a first active region of a first conductivity type and a second active region of a second conductivity type, the first active region of the first conductivity type and the second active region of the second conductivity type extending parallel to each other in the first horizontal direction, and wherein at least a portion of the first active region is in the first row, and at least a portion of the second active region is in the second row; and an interface unit extending continuously in the first row and the second row between the first unit and the third unit and between the second unit and the third unit, The interface unit includes at least one of the third active area or the fourth active area. wherein the third active region connects the first active region and the active region of the first conductivity type included in the first unit, and The fourth active region connects the second active region and the active region of the second conductivity type included in the second unit.

18. The integrated circuit of claim 17, wherein: The third unit includes a second power line electrically connected to the first power line, wherein the first power line extends in the first horizontal direction at a boundary between the first row and the second row, wherein the second power line extends in the first horizontal direction in the first row, and wherein the second row does not have the second power line.

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