High voltage resistant component and manufacturing process based on planar S-type junction

Abstract

The present invention discloses a high-voltage resistant component based on a planar S-type junction and a manufacturing process, and relates to the field of semiconductor technology. The component is characterized in that it at least comprises: a single crystal silicon wafer, a second conductive type lightly doped layer located on the upper surface of the single crystal silicon wafer, a first conductive type heavily doped layer located at one end of the second conductive type lightly doped layer, a second conductive type heavily doped layer located at the other end of the second conductive type lightly doped layer, a first electrode connected to the first conductive type heavily doped layer, and a second electrode connected to the second conductive type heavily doped layer; a first insulating layer is provided between two adjacent conductive type lightly doped layers; both sides of each conductive type lightly doped layer are provided with the first insulating layer; the second conductive type lightly doped layer, the first insulating layer, the first conductive type heavily doped layer and the second conductive type heavily doped layer are located in the same plane; the first electrode is parallel to the above conductive type lightly doped layer; the second electrode is parallel to the above conductive type lightly doped layer; and the first insulating layer is located on the plane.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-voltage resistant component based on a planar S-type junction and a manufacturing process. Background Art

[0002] According to Poisson's equation, the spatial gradient of electric potential is equal to the spatial intensity of the electric field, and the spatial gradient of the electric field is equal to the spatial charge concentration. For a structure that needs to withstand voltage, the maximum voltage that can be borne by both ends of its electrodes is limited by the critical electric field of the material itself and the electric field distribution inside it after the voltage is applied. In the usual voltage-resistant structure design, the direction of the electric field line is in a certain direction. To obtain a higher voltage resistance, thicker materials are required. This results in a larger volume of high-voltage-resistant devices and higher material costs.

[0003]

[0004] is the electric potential, ρ is the charge density, ε 0 is the vacuum dielectric constant, ε r is the relative dielectric constant.

[0005] By designing the structure of the doped region and the insulating region, the electric field lines are distributed in the direction of the fastest potential drop, that is, in an S-shaped path. By extending the length of the space charge region, the length of the electric field line path is increased, and the purpose of withstanding high voltage can be achieved. The traditional method of obtaining a higher voltage resistance characteristic for high-voltage components is to change the thickness of the material or directly replace the material with different properties. The traditional method has several disadvantages. First, the depletion region is narrow, which easily forms regional charge accumulation, causing the local junction temperature to be too high, which easily leads to breakdown and leakage, and shortens the service life of the device. Second, increasing the material thickness leads to higher costs, and also increases the difficulty of device manufacturing. The electric field lines of traditional devices are as follows: Figure 1 .

[0006] Since the application of semiconductors, many experts and scholars have been committed to improving the above problems, trying to obtain better pressure resistance characteristics by continuously increasing the thickness of materials or directly replacing materials with better performance. However, the above methods always only achieve the purpose of greater pressure resistance by changing the physical properties of the material itself, and do not solve the problem efficiently. Summary of the invention

[0007] The present invention aims at the above-mentioned technical problems existing in the prior art, and provides a high-voltage-resistant component and manufacturing process based on a planar S-type junction, which realizes the extension of the depletion region length through the internal structure of the device, thereby achieving the purpose of attenuating the electric field and withstanding high voltage, thereby more efficiently achieving the goal of withstanding stronger high voltage under the same material thickness, and the electric field line forms a folded curve. In the PN junction, the length of the depletion region is extended by increasing the path of the electric field line, thereby improving the withstand voltage characteristics of the device.

[0008] The technical solution adopted by the present invention to solve the technical problems existing in the known technology is:

[0009] The first object of the present invention is to provide a high voltage resistant component based on a planar S-type junction, comprising at least:

[0010] A single crystal silicon wafer (1013), wherein the thickness of the single crystal silicon wafer (1013) is in the range of 400 to 600 um;

[0011] A second conductive type lightly doped layer (1022) is located on the upper side of the single crystal silicon wafer (1013); the second conductive type lightly doped layer (1022) comprises M conductive type lightly doped layers parallel to each other, the conductive type lightly doped layers are in a strip structure, wherein: the tail of the Nth conductive type lightly doped layer is connected to the tail of the N+1th conductive type lightly doped layer; the head of the N+1th conductive type lightly doped layer is connected to the head of the N+2th conductive type lightly doped layer; M is a natural number greater than 2, and N is an odd number; N is less than M; both sides of each conductive type lightly doped layer are first insulating layers (1011);

[0012] A first conductive type heavily doped layer (1021) located at one end of the second conductive type lightly doped layer (1022);

[0013] A second conductive type heavily doped layer (1023) located at the other end of the second conductive type lightly doped layer (1022);

[0014] A first electrode connected to the first conductive type heavily doped layer (1021);

[0015] a second electrode connected to the second conductive type heavily doped layer (1023); the second conductive type lightly doped layer (1022), the first insulating layer (1011), the first conductive type heavily doped layer (1021) and the second conductive type heavily doped layer (1023) are located in the same plane; the first electrode is parallel to the conductive type lightly doped layer; and the second electrode is parallel to the conductive type lightly doped layer;

[0016] A first insulating layer (1012) is located on the plane.

[0017] Further: the first conductive type heavily doped layer (1021) is a P-type or N-type or Schottky metal layer.

[0018] Further: the second conductive type heavily doped layer (1023) is a P-type or N-type or Schottky metal layer.

[0019] Further: the second conductive type lightly doped layer (1022) is P type or N type.

[0020] Further: the first electrode and / or the second electrode is Al or Ti or Ni or Ag or Cu or Au or W or a combination of the above.

[0021] The second object of the present invention is to provide a manufacturing process of a high voltage resistant component based on a planar S-type junction, comprising the following steps:

[0022] Step 1: Select a single crystal silicon wafer (1013);

[0023] Step 2: using thermal oxidation or chemical vapor deposition to grow a 200 nm first insulating layer (1011) on the upper surface of the single crystal silicon wafer;

[0024] Step 3: photolithography a groove A on the upper surface of the first insulating layer, and then bombarding the groove A by wet method or plasma, wherein the shape of the groove A is the same as the shape of the second conductive type lightly doped layer (1022); the position of the groove A coincides with the position of the second conductive type lightly doped layer (1022);

[0025] Step 4: Using thermal diffusion, ion implantation or epitaxial process, a lightly doped P-type or N-type second conductivity type lightly doped layer (1022) is grown in the groove A, with a doping concentration of 1.5×10 13 ~1.5×10 15 ;

[0026] Step 5: Photolithography grooves B are formed at both ends of the second conductive type lightly doped layer (1022), and then the grooves B are bombarded by wet method or plasma;

[0027] Step 6: Using thermal diffusion, ion implantation or epitaxial process, a heavily doped N-type or P-type first conductivity type heavily doped layer (1021) is grown in a groove B, with a doping concentration of about 1.5×10 19 ;

[0028] Step 7: Using thermal diffusion, ion implantation or epitaxial process, grow a 50nm-100nm P-type or N-type second conductivity type heavily doped layer (1023) in another groove B, with a doping concentration of 1.5×10 13 ~1.5×10 15 ;

[0029] Step 8: growing a second insulating layer (1012) on the first conductivity type heavily doped layer (1021) and the second conductivity type heavily doped layer (1023) as a protective layer by thermal oxidation or chemical vapor deposition;

[0030] Step nine: making the first electrode and the second electrode.

[0031] The advantages and positive effects of the present invention are:

[0032] By adopting the above technical scheme, the present invention can obtain different withstand voltage values ​​by changing the process line width, length and period of the doping layer and extending the equivalent length of the depletion region. In the present invention, the part of the device connecting the electrode has the function of heavily doping to provide a large number of composite carriers to expand the length of the depletion layer, which can quickly deplete the free carriers of the lightly doped layer and extend the length of the depletion region or the part of the device connecting the electrode is a Schottky metal. Since the work function is larger than that of the semiconductor, the free carriers of the lightly doped layer can be quickly depleted and the length of the depletion region can be extended; the present invention controls the doping concentration and the structure of the doped semiconductor material to extend the length of the space charge region in the semiconductor, thereby realizing the control of the direction of the electric field line, and realizing a wider space charge region on a limited chip length to obtain a larger withstand voltage. Different from the traditional withstand voltage device that changes the thickness of the material to obtain a high withstand voltage, this patent can use the ion implantation between the substrate into the lightly doped layer to make a groove to fill the insulating layer; or horizontally stack the doping layer and the insulating layer to form an equivalent wider S-type space charge region. The S-type planar conductive path connects the sidewall electrode (such as Ti Ni Cu Au, etc.) to achieve a faster response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is the electric field line diagram of the traditional device;

[0034] Figure 2 is a device electric field line diagram of a preferred embodiment of the present invention;

[0035] Figure 3 is a structural diagram of a preferred embodiment of the present invention;

[0036] Figure 4 The present invention Figure 3 AA cross-section diagram;

[0037] Figure 5 The present invention Figure 3 BB cross-section diagram;

[0038] Figure 6 The present invention Figure 3 CC cross-section diagram;

[0039] Figure 7 It is a product structure diagram obtained in step 1 of the present invention;

[0040] Figure 8 It is the product structure diagram obtained in step 2 of the present invention;

[0041] Fig. 9 It is the product structure diagram obtained in step 3 of the present invention;

[0042] Fig.10 It is the product structure diagram obtained in step 5 of the present invention;

[0043] Fig.11 This is the product structure diagram obtained in step 6 of the present invention;

[0044] Fig.12 This is the product structure diagram obtained in step seven of the present invention;

[0045] Fig.13 This is the product structure diagram obtained in step nine of the present invention; DETAILED DESCRIPTION

[0046] In order to further understand the content, features and effects of the present invention, the following embodiments are given as examples and described in detail with reference to the accompanying drawings:

[0047] like Figures 2 to 6 As shown, the present invention discloses a high voltage resistant component based on a planar S-type junction, comprising:

[0048] A single crystal silicon wafer 1013, wherein the thickness of the single crystal silicon wafer is in the range of 400 to 600 um;

[0049] A second conductive type lightly doped layer 1022 is located on the upper surface of the single crystal silicon wafer 1013; the second conductive type lightly doped layer 1022 includes M conductive type lightly doped layers parallel to each other, and the conductive type lightly doped layers are strip-shaped structures, wherein: the tail of the Nth conductive type lightly doped layer is connected to the tail of the N+1th conductive type lightly doped layer; the head of the N+1th conductive type lightly doped layer is connected to the head of the N+2th conductive type lightly doped layer; M is a natural number greater than 2, and N is an odd number; N is less than M; a first insulating layer 1011 is between two adjacent conductive type lightly doped layers; both sides of each conductive type lightly doped layer are the first insulating layer 1011;

[0050] A first conductivity type heavily doped layer 1021 located at one end of the second conductivity type lightly doped layer 1022;

[0051] A second conductivity type heavily doped layer 1023 located at the other end of the second conductivity type lightly doped layer 1022;

[0052] A first electrode connected to the first conductive type heavily doped layer 1021;

[0053] a second electrode connected to the second conductive type heavily doped layer 1023; the second conductive type lightly doped layer 1022, the first insulating layer 1011, the first conductive type heavily doped layer 1021 and the second conductive type heavily doped layer 1023 are located in the same plane; the first electrode is parallel to the above conductive type lightly doped layer; the second electrode is parallel to the above conductive type lightly doped layer;

[0054] A first insulating layer 1012 is located on the plane.

[0055] In the above preferred embodiment:

[0056] The cross section of the second conductive type lightly doped layer 1022 is rectangular or trapezoidal, and the bottom of the second conductive type lightly doped layer 1022 can be a straight line or an arc;

[0057] The material of the first insulating layer 1011 is not limited to silicon oxide, silicon nitride, etc.;

[0058] The material of the second insulating layer 1012 is not limited to silicon oxide, silicon nitride, etc.;

[0059] The first conductive type heavily doped layer 1021 is a P-type or N-type or Schottky metal layer;

[0060] The second conductive type lightly doped layer 1022 is N-type or P-type or a second conductive type lightly doped layer (P-type);

[0061] The second conductive type heavily doped layer 1023 is a P-type or N-type or a second Schottky metal layer;

[0062] The material of the metal electrode 103 (the first electrode and the second electrode) is Al, Ti, Ni, Ag, Cu, Au, W or a combination thereof.

[0063] The present invention can obtain different withstand voltage values ​​by changing the process line width, length and period of the doping layer and extending the equivalent length of the depletion region. In the present invention, the part of the device connecting the electrode has the function of providing a large number of composite carriers to expand the length of the depletion layer by heavy doping, which can quickly deplete the free carriers of the lightly doped layer and extend the length of the depletion region. Or the part of the device connecting the electrode is a Schottky metal. Since the work function is larger than that of the semiconductor, the free carriers of the lightly doped layer can be quickly depleted and the length of the depletion region can be extended. The present invention controls the doping concentration and the structure of the doped semiconductor material to extend the length of the space charge region in the semiconductor, thereby achieving control of the direction of the electric field line and realizing a wider space charge region on a limited chip length to obtain a larger withstand voltage. Different from the traditional withstand voltage device that changes the thickness of the material to obtain a high withstand voltage, this patent can use the ion implantation between the substrate into the lightly doped layer to make a groove to fill the insulating layer; or horizontally stack the doping layer and the insulating layer to form an equivalent wider S-type space charge region. The S-type planar conductive path connects the sidewall electrode (such as Ti Ni CuAu, etc.) to achieve a faster response speed.

[0064] See also Figures 7 to 13 , a manufacturing process of a high voltage resistant component based on a planar S-type junction, comprising the following steps:

[0065] Step 1: Select a single crystal silicon wafer 1013;

[0066] Step 2: using thermal oxidation or chemical vapor deposition to grow a 200 nm thick first insulating layer 1011 on the upper surface of the single crystal silicon wafer;

[0067] Step 3: photolithography a groove A on the upper surface of the first insulating layer, and then bombarding the groove A by wet method or plasma, wherein the shape of the groove A is the same as the shape of the second conductive type lightly doped layer 1022; the position of the groove A coincides with the position of the second conductive type lightly doped layer 1022;

[0068] Step 4: Using thermal diffusion, ion implantation or epitaxial process, a lightly doped P-type or N-type second conductivity type lightly doped layer 1022 is grown in the groove A, with a doping concentration of 1.5×10 13 ~1.5×10 15 ;

[0069] Step 5: Photolithography grooves B are formed at both ends of the second conductive type lightly doped layer 1022, and then the grooves B are bombarded by wet method or plasma;

[0070] Step 6: Using thermal diffusion, ion implantation or epitaxial process, a heavily doped N-type or P-type first conductivity type heavily doped layer 1021 is grown in a groove B, with a doping concentration of about 1.5×10 19 ;

[0071] Step 7: Using thermal diffusion, ion implantation or epitaxial process, grow a 50nm-100nm P-type or N-type second conductivity type heavily doped layer 1023 in another groove B, with a doping concentration of 1.5×10 13 ~1.5×10 15 ;

[0072] Step 8: using thermal oxidation or chemical vapor deposition, growing a second insulating layer 1012 on the first conductivity type heavily doped layer 1021 and the second conductivity type heavily doped layer 1023 as a protective layer;

[0073] Step nine: manufacturing the electrode 103, wherein the electrode 103 comprises a first electrode and a second electrode.

[0074] The embodiments of the present invention are described in detail above, but the contents are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made according to the scope of application of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A high voltage resistant component based on a planar S-type junction, characterized in that: At least: A single crystal silicon wafer (1013), wherein the thickness of the single crystal silicon wafer (1013) is in the range of 400 to 600 um; A second conductive type lightly doped layer (1022) is located on the upper side of the single crystal silicon wafer (1013); the second conductive type lightly doped layer (1022) comprises M parallel second conductive type lightly doped layers, the second conductive type lightly doped layer is a strip structure, wherein: the tail of the Nth second conductive type lightly doped layer is connected to the tail of the N+1th second conductive type lightly doped layer; the head of the N+1th second conductive type lightly doped layer is connected to the head of the N+2th second conductive type lightly doped layer; M is a natural number greater than 2, N is an odd number; N is less than M; Both sides of each second conductivity type lightly doped layer are first insulating layers (1011); A first conductive type heavily doped layer (1021) located at one end of the second conductive type lightly doped layer (1022); A second conductive type heavily doped layer (1023) located at the other end of the second conductive type lightly doped layer (1022); A first electrode connected to the first conductive type heavily doped layer (1021); a second electrode connected to the second conductive type heavily doped layer (1023); the second conductive type lightly doped layer (1022), the first insulating layer (1011), the first conductive type heavily doped layer (1021) and the second conductive type heavily doped layer (1023) are located in the same plane; the first electrode is parallel to the second conductive type lightly doped layer; and the second electrode is parallel to the second conductive type lightly doped layer; A second insulating layer (1012) is located on the plane.

2. The high voltage resistant component based on planar S-type junction according to claim 1, characterized in that: The first conductive type heavily doped layer (1021) is of P type or N type.

3. The high voltage resistant component based on planar S-junction according to claim 1, characterized in that: The second conductive type heavily doped layer (1023) is of P type or N type.

4. The high voltage resistant component based on planar S-type junction according to claim 1, characterized in that: The second conductive type lightly doped layer (1022) is P type or N type.

5. The high voltage resistant component based on planar S-junction according to claim 1, characterized in that: The first electrode and / or the second electrode is Al, Ti, Ni, Ag, Cu, Au or W.

6. A process for manufacturing a high voltage resistant component based on a planar S-type junction as claimed in claim 1, characterized in that: The steps include: Step 1: Select a single crystal silicon wafer (1013); Step 2: using thermal oxidation or chemical vapor deposition to grow a 200 nm first insulating layer (1011) on the upper surface of the single crystal silicon wafer; Step 3: photolithography a groove A on the upper surface of the first insulating layer, and then bombarding the groove A by wet method or plasma, wherein the shape of the groove A is the same as the shape of the second conductive type lightly doped layer (1022); the position of the groove A coincides with the position of the second conductive type lightly doped layer (1022); Step 4: Using thermal diffusion, ion implantation or epitaxial process, a lightly doped P-type or N-type second conductivity type lightly doped layer (1022) is grown in the groove A, with a doping concentration of 1.5×10 13 ~1.5×10 15 ; Step 5: Photolithography grooves B are formed at both ends of the second conductive type lightly doped layer (1022), and then the grooves B are bombarded by wet method or plasma; Step 6: Using thermal diffusion, ion implantation or epitaxial process, a heavily doped N-type or P-type first conductivity type heavily doped layer (1021) is grown in a groove B, with a doping concentration of 1.5×10 19 ; Step 7: Using thermal diffusion, ion implantation or epitaxial process, grow a 50nm-100nm P-type or N-type second conductivity type heavily doped layer (1023) in another groove B, with a doping concentration of 1.5×10 13 ~1.5×10 15 ; Step 8: growing a second insulating layer (1012) on the first conductivity type heavily doped layer (1021) and the second conductivity type heavily doped layer (1023) as a protective layer by thermal oxidation or chemical vapor deposition; Step nine: making the first electrode and the second electrode.

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