Storage device including write buffer memory and method of operating the storage device

Abstract

A storage device includes: a nonvolatile memory including a plurality of nonvolatile storage cells; a write buffer memory storing first data and second data received from a host; and a storage controller storing the first data and second data stored in the write buffer memory into the nonvolatile memory. The storage controller performs a first programming operation and a second programming operation on a plurality of first storage cells connected to a first word line group to store the first data, and performs a first programming operation and a second programming operation on a plurality of second storage cells connected to a second word line group to store the second data. When the storage controller performs the first programming operation on the plurality of second storage cells, the first data is written into the write buffer memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0061134 filed on May 29, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a memory device including a nonvolatile memory and a method of operating the memory device. Background Art

[0004] Flash memory, as a nonvolatile memory, can retain data stored therein even when power is turned off. Recently, storage devices including flash memory such as solid state drives (SSDs) and memory cards are widely used and are useful for storing or moving large amounts of data. Summary of the invention

[0005] The inventive concept provides a memory device for efficiently performing a plurality of program operations by including a large-capacity write buffer memory, and a method of operating the memory device.

[0006] According to some embodiments of the present invention, there is provided a storage device, comprising: a nonvolatile memory including a plurality of nonvolatile storage cells; a write buffer memory configured to store first data and second data received from a host; and a storage controller configured to store the first data and second data stored in the write buffer memory into the nonvolatile memory. The storage controller is configured to perform a first programming operation and a second programming operation on a plurality of first storage cells connected to a first word line group including a plurality of first word lines to store the first data, and to perform a first programming operation and a second programming operation on a plurality of second storage cells connected to a second word line group including a plurality of second word lines to store the second data. When the storage controller is configured to perform the first programming operation on the plurality of second storage cells, the first data is written into the write buffer memory.

[0007] According to some embodiments of the present invention, there is provided a storage device, comprising: a nonvolatile memory including a plurality of nonvolatile memory cells; and a storage controller configured to store first data and second data received from a host in the nonvolatile memory, the storage controller comprising a write buffer memory. The storage controller is configured to perform a first programming operation and a second programming operation on a plurality of first memory cells connected to a first word line group to store the first data, and to perform a first programming operation and a second programming operation on a plurality of second memory cells connected to a second word line group to store the second data. When the storage controller is configured to perform the first programming operation on the plurality of second memory cells, the first data is written into the write buffer memory.

[0008] According to some embodiments of the present invention, there is provided a method of operating a memory device, the memory device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory, the method of operating the memory device including: performing a first programming operation on a plurality of first memory cells connected to a first word line group based on first data; performing a first programming operation on a plurality of second memory cells connected to a second word line group different from the first word line group based on second data; performing a second programming operation on the plurality of first memory cells based on the first data; and performing a second programming operation on the plurality of second memory cells based on the second data. Some of the plurality of first memory cells and some of the plurality of second memory cells store multi-bit data, and performing the first programming operation on the plurality of first memory cells, performing the first programming operation on the plurality of second memory cells, performing the second programming operation on the plurality of first memory cells, and performing the second programming operation on the plurality of second memory cells are sequentially performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1A is a block diagram illustrating a storage system according to some embodiments of the present inventive concept;

[0011] Figure 1B is a block diagram illustrating a storage device according to some embodiments of the inventive concept;

[0012] Figure 2 is a block diagram illustrating a storage system according to some embodiments of the present inventive concept;

[0013] Figure 3 is a block diagram illustrating a storage device according to some embodiments of the inventive concept;

[0014] Figure 4 is a diagram showing some embodiments of the present invention. Figure 3 A diagram showing a distribution of threshold voltages of memory cells programmed in a memory cell array shown in FIG.

[0015] Figure 5 is a flowchart of a method of programming a memory device according to some embodiments of the inventive concept;

[0016] FIG. 6A to FIG. 6C It is used to illustrate Figure 5 , i.e., for explaining a plurality of first storage units and a plurality of second storage units according to some embodiments of the inventive concept;

[0017] Figure 7 is a block diagram illustrating a write buffer memory included in a storage device according to some embodiments of the inventive concept;

[0018] Figure 8 The present invention schematically illustrates some embodiments of the present invention. Figure 7 A circuit diagram of a memory cell array in;

[0019] FIG. 9A to FIG. 9C is a diagram showing some embodiments of the present invention. Figure 8 Circuit diagrams of different embodiments of a plurality of storage cells in;

[0020] Fig.10 is a diagram for explaining the operation of a write buffer memory according to some embodiments of the inventive concept;

[0021] Fig.11A and Fig. 11B is a timing diagram of a write operation of a write buffer memory according to some example embodiments of the inventive concept;

[0022] Fig.12 is a block diagram illustrating a configuration of an error checking and correction (ECC) circuit included in a memory device according to some embodiments of the inventive concept; and

[0023] Fig.13 is a flowchart of an operation of a memory controller included in a memory device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0024] It should be noted that the various aspects of the inventive concept described with respect to one embodiment may be combined in different embodiments, although not specifically described with respect to it. That is to say, all embodiments and / or the features of any embodiment may be combined in any manner and / or combination. These and other purposes and / or aspects of the inventive concept are described in detail in the specification set forth below. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Expressions such as "at least one" when preceding a list of elements modify the entire list of elements without modifying the individual elements of the list.

[0025] Hereinafter, embodiments of the inventive concept are described in detail with reference to the accompanying drawings.

[0026] Figure 1A 1 is a block diagram showing a storage system 10 according to some embodiments. The storage system 10 may be implemented as, for example, a personal computer (PC), a laptop computer, a mobile phone, a smart phone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a video camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, or an electronic book. In addition, the storage system 10 may be implemented as, for example, an electronic device such as a wearable device such as a watch or a head mounted display (HMD).

[0027] See also Figure 1A , the storage system 10 may include a storage device 100 and a host 200. The storage device 100 may include a storage controller 110 and a non-volatile memory (NVM) 120. Figure 1A The illustrated storage device 100 may also include a write buffer memory 130 .

[0028] The host 200 may provide an access request for data to the storage device 100. In some embodiments, the host 200 provides a write request or a read request for data to the storage device 100, and the storage device 100 may write the data to the NVM 120 in response to the access request from the host 200, or may read the data from the NVM 120 and provide the read data to the host 200. In addition, the storage device 100 may perform an erase operation on the data in the area indicated by the host 200 in response to an erase request for data from the host 200.

[0029] The host 200 may communicate with the storage device 100 via various interfaces. The host 200 may include various types of devices capable of performing data access to the storage device 100. For example, the host 200 may be an application processor (AP) that communicates with the flash memory-based storage device 100. The host 200 may communicate with the storage device 100 via various interfaces.

[0030] NVM 120 may include a memory cell array including a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Below, an embodiment will be described for a case where the plurality of memory cells are NAND flash memory cells. However, the technical idea of ​​the present invention is not limited thereto, and the plurality of memory cells may be various NVM cells. In some embodiments, the plurality of memory cells may be resistance-based memory cells, such as resistive random access memory (RAM) (RRAM), phase change RAM (PRAM), and magnetic RAM (MRAM). In some embodiments, the plurality of memory cells may be ferroelectric RAM (FRAM) cells, spin transfer torque RAM (STT-RAM) cells, and the like.

[0031] The NVM 120 may be implemented in a three-dimensional array structure. The inventive concept may be applied not only to a flash memory device in which a charge storage layer includes a conductive floating gate, but also to a charge trap flash memory (CTF) in which a charge storage layer includes an insulating film.

[0032] The memory controller 110 may control the NVM 120 to write data to the NVM 120 in response to a write request received from the host 200. At this time, in the NVM 120, a plurality of programming operations may be performed on a plurality of word lines so that data is written, and each of the plurality of programming operations may be performed by an incremental step pulse programming (ISPP) method. In some embodiments, the plurality of programming operations may include at least one coarse programming operation and at least one fine programming operation.

[0033] A plurality of programming operations may include a first programming operation and a second programming operation performed sequentially. In the first programming operation and the second programming operation, the increment of the programming pulse in the first programming operation and the increment of the programming pulse in the second programming operation may be different. The time interval between the programming pulses in the first programming operation and the time interval between the programming pulses in the second programming operation may be different. In the storage device 100 according to the concept of the present invention, the threshold voltage dispersion width can be formed narrowly by performing a plurality of programming operations on a plurality of word lines. It should be understood that although the terms first, second, third, etc. can be used here to describe various elements, the elements should not be limited by these terms. On the contrary, these terms are only used to distinguish one element from another element. Therefore, without departing from the scope of the concept of the present invention, the first element discussed below may be referred to as the second element.

[0034] While a plurality of program operations are being performed, data to be written to a plurality of memory cells may be stored in the write buffer memory 130. For example, data to be written to a plurality of memory cells connected to a plurality of word lines may be stored in the write buffer memory 130 at the same time.

[0035] In some embodiments, the write buffer memory 130 may be a resistance-based memory such as RRAM, PRAM, and MRAM. In some embodiments, the write buffer memory 130 may be FRAM, STT-RAM, etc. In some embodiments, the write buffer memory 130 may be a NAND flash memory including a single-level cell (SLC). In some embodiments, the write buffer memory 130 may be a memory of a different type than the NVM 120.

[0036] When the delay time between the time when the first program operation is completed and the time when the second program operation is started is not sufficiently ensured, the threshold voltage distributions between different program states may overlap. The memory device 100 according to the inventive concept can ensure the delay time by performing program operations on a plurality of different word lines between performing the first program operation and performing the second program operation. Figure 4 Threshold voltage distributions according to first and second program operations are described.

[0037] The write buffer memory 130 may store first data DATA1 to be written to the first memory cell during a delay time in which a second programming operation starts after a first programming operation on a plurality of first memory cells connected to the first word line group is completed. The write buffer memory 130 may store second data DATA2 to be written to the second memory cell so that the first programming operation is performed on a plurality of second memory cells connected to the second word line group during the delay time. The first word line group and the second word line group may each include a plurality of word lines.

[0038] In other words, the write buffer memory 130 may have the ability to store the first data DATA1 and the second data DATA2 simultaneously. When the first data DATA1 is stored in the plurality of first memory cells, the first data DATA1 in the write buffer memory 130 may be erased.

[0039] In some embodiments, the storage device 100 may be an internal memory embedded in an electronic device. For example, the storage device 100 may be an embedded universal flash memory (UFS) memory device, an embedded multimedia card (eMMC), or a solid-state drive (SSD). The storage device 100 and the host 200 may be mounted on the same substrate. In some embodiments, the storage device 100 may be an external memory removable from an electronic device. For example, the storage device 100 may include at least one of a UFS memory card, a compact flash memory (CF) memory card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme digital (XD) card, and a memory stick.

[0040] Figure 1Bis a block diagram illustrating a storage device 100 according to some embodiments.

[0041] See also Figure 1B , the storage device 100 may include a storage controller 110, an NVM 120, and a write buffer memory 130. The storage controller 110 may include a processor 111, an error checking and correction (ECC) circuit 112, a mapping table 113, a RAM 114, a host interface (I / F) 115, a buffer manager 116, and an NVM I / F 117, which can communicate with each other via a bus 118. In addition, the storage controller 110 may further include other peripheral devices.

[0042] The processor 111 may control the overall operation of the storage controller 110. The processor 111 may also include a central processing unit, a microprocessor, etc. The processor 111 may drive firmware to drive the storage controller 110. The firmware may be loaded into the RAM 114 and driven, and may include a flash translation layer (FTL).

[0043] The mapping table 113 may map and store physical address information of a page of the write buffer memory 130 corresponding to a logical address of each page of the NVM 120. Each time data received from the host 200 is stored in the write buffer memory 130, the mapped physical address information may be updated. Figure 1B The mapping table 113 is shown separately in FIG. 1 , but according to some embodiments, the mapping table 113 may be implemented in the RAM 114 .

[0044] The RAM 114 may operate under the control of the processor 111 and may be used as a working memory, a buffer memory, a cache memory, etc. Software and firmware for controlling the memory controller 110 may be loaded into the RAM 114. The RAM 114 may be implemented as a volatile memory such as a dynamic RAM (DRAM) and a static RAM (SRAM). In some embodiments, the RAM 114 may be implemented as a resistance-based memory such as an RRAM, a PRAM, or an MRAM.

[0045] The host I / F 115 may provide an interface between the host 200 and the storage controller 110. The host 200 and the storage controller 110 may be connected to each other via at least one of various standard interfaces. The standard interface may include various interfaces such as a universal serial bus (USB), an embedded multimedia card (eMMC), a multimedia card (MMC), a PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), an external SATA (e-SATA), a parallel ATA (PATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), IEEE1394 and / or a card interface.

[0046] The buffer manager 116 may provide an interface between the storage controller 110 and the write buffer memory 130. Data to be written to the NVM 120 may be temporarily stored in the write buffer memory 130 via the buffer manager 116.

[0047] The NVM I / F 117 may provide an interface between the memory controller 110 and the NVM 120. For example, the memory controller 110 may transmit and receive data to and from the NVM 120 via the NVM I / F 117.

[0048] The NVM 120 may store data or read stored data under the control of the memory controller 110. The NVM 120 may include a plurality of NVM chips including a memory cell array, and may be connected to the NVM I / F 117 via a plurality of channels Ch. The NVM 120 may include a three-dimensional memory cell array in which a memory cell string to which the memory cell is connected is formed vertically to the substrate. However, the embodiment is not limited thereto, and may include a planar memory cell array.

[0049] Figure 2 is a block diagram illustrating a storage system 10a according to some embodiments.

[0050] See also Figure 2 , the storage system 10a may include a storage device 100a and a host 200. The storage device 100a may include a storage controller 110a and an NVM 120. Figure 1A and Figure 1B The storage device 100 in the embodiment includes a write buffer memory 130 separated from the storage controller 110, but Figure 2 The storage device 100a in may include a write buffer memory 130a embedded therein.

[0051] The memory controller 110 a may include a buffer manager, and data to be written to the NVM 120 may be temporarily stored in the write buffer memory 130 a via the buffer manager.

[0052] Therefore, the write buffer memory 130a can store the first data DATA1 to be written to the first memory cell during the delay time in which the second programming operation starts after the first programming operation on the plurality of first memory cells connected to the first word line group is completed. In addition, the write buffer memory 130a can store the second data DATA2 to be written to the second memory cell so that the first programming operation is performed on the plurality of second memory cells connected to the second word line group during the delay time. Therefore, the write buffer memory 130a can have the ability to store the first data DATA1 and the second data DATA2 at the same time.

[0053] It is obvious that the following description of writing to the buffer memory 130 can be applied to Figure 2 The write buffer memory 130a in.

[0054] Figure 3 is a block diagram illustrating a storage device 100 according to some embodiments.

[0055] See also Figure 3 , the storage device 100 may include an NVM 120 and a storage controller 110 for controlling the NVM 120 .

[0056] NVM 120 may include a memory cell array 121, an address decoder (ADDR DEC) 122, an input / output circuit 123, and a control logic 124. NVM 120 may be implemented in a three-dimensional array structure. Hereinafter, for ease of explanation, NVM 120 will be referred to as a NAND flash memory device.

[0057] The memory cell array 121 may be connected to the ADDR DEC 122 via first to m-th word lines WL1 to WLm, at least one string selection line SSL, and at least one ground selection line GSL, and may be connected to the input / output circuit 123 via first to n-th bit lines BL1 to BLn. The memory cell array 121 may include a plurality of memory blocks. Figure 3 In the embodiment, for the convenience of explanation, only one storage block is shown. In this case, m may be an integer of 5 or more, and n may be an integer of 4 or more, and thus, the number of first to m-th word lines WL1 to WLm and the number of first to n-th bit lines BL1 to BLn may be variously configured. In some embodiments, a storage block may correspond to a unit that performs an erase operation.

[0058] The memory block may include a plurality of strings. Here, each of the plurality of strings may include at least one string selection transistor, a plurality of memory cells MC, and at least one ground selection transistor. Each of the plurality of memory cells MC may store multi-bit data. Each of the plurality of memory cells MC may store k-bit data (k is an integer of 2 or more). For example, each of the plurality of memory cells MC may store 4 or more bits of data.

[0059] The memory block may include a first page Page_1 to an mth page Page_m. Each of the first page Page_1 to the mth page Page_m may correspond to a write unit or a read unit of data in one memory block. Each of the first page Page_1 to the mth page Page_m may be connected to one of the first word line WL1 to the mth word line WLm. For example, the first page Page1 may be connected to the first word line WL1, and the mth page Page_m may be connected to the mth word line WLm.

[0060] The ADDR DEC 122 may be connected to the memory cell array 121 via the first to m-th word lines WL1 to WLm, at least one string selection line SSL, and at least one ground selection line GSL. The ADDR DEC 122 may select the first to m-th word lines WL1 to WLm, the string selection line SSL, and the ground selection line GSL by using the decoded row address. In addition, the ADDR DEC 122 may decode the column address in the input address ADDR. Here, the decoded column address may be sent to the input / output circuit 123. In some embodiments, the ADDR DEC 122 may include a row decoder, a column decoder, an address buffer, and the like.

[0061] The input / output circuit 123 may be connected to the memory cell array 121 via the first to nth bit lines BL1 to BLn. The input / output circuit 123 may be implemented to receive a decoded column address from the ADDR DEC 122. The input / output circuit 123 may select the first to nth bit lines BL1 to BLn by using the decoded column address ADDR.

[0062] The input / output circuit 123 may include first to n-th page buffers PB1 to PBn connected to the first to n-th bit lines BL1 to BLn, respectively. The first to n-th page buffers PB1 to PBn may receive data from the outside (e.g., the memory controller 110) during a program operation and store the input data in the memory cell array 121. In addition, the first to n-th page buffers PB1 to PBn may read data from the memory cell array 121 during a read operation and output the read data to the outside. Each of the first to n-th page buffers PB1 to PBn may include a plurality of latches.

[0063] The control logic 124 may control the overall operation of the NVM 120 (e.g., a plurality of programming operations, read operations, and erase operations). The control logic 124 may operate in response to an externally input control signal. The control logic 124 may control the ADDRDEC 122 and the input / output circuit 123 to perform the first programming operation and the second programming operation.

[0064] Figure 4 It is shown in Figure 3 FIG. 1 is a diagram showing the distribution of threshold voltages of memory cells MC programmed in the memory cell array 121. Figure 4 In the embodiment, for the convenience of explanation, it is assumed that a 4-bit programming operation is performed on the memory cell MC. Therefore, the memory cell MC can be programmed with at least one of 16 threshold voltage distributions.

[0065] See also Figure 4 , through the first program operation, the first PGM to the ath program operation, the ath PGM, the memory cell MC may be programmed with at least one of the erase state E and the program state (e.g., the first state Pa_1 to the fifteenth state Pa_15). Here, the program state (e.g., Pa_1 to Pa_15) may be a final state storing 4-bit data.

[0066] A plurality of programming operations may perform a first programming operation first PGM and then perform an ath programming operation ath PGM. Here, a may be a natural number of 2 or more. The number of programming operations may vary according to circumstances. During the first programming operation first PGM, the threshold voltage distribution of the memory cell MC may be programmed using at least one of the erase state E and the first programming state P1_1 to the fifteenth programming state P1_15. The level of the threshold voltage may gradually increase from the first programming state P1_1 to the fifteenth programming state P1_15. During the ath programming operation ath PGM, the threshold voltage distribution of the memory cell MC may be programmed using at least one of the erase state E and the first programming state Pa_1 to the fifteenth programming state Pa_15. At least one distribution width of the first programming state Pa_1 to the fifteenth programming state Pa_15 of the ath programming operation ath PGM may be narrower than the distribution width of the first programming state P1_1 to the fifteenth programming state P1_15 of the corresponding first programming operation first PGM.

[0067] For example, "a" may be equal to 2, and after performing the first program operation 1PGM, the second program operation 2PGM may be performed so that the threshold voltage distribution of the memory cells MC is programmed using the erase state E and at least one of the first to fifteenth program states P2_1 to P2_15.

[0068] The memory device according to the present inventive concept can perform multiple program operations so that the width of the threshold voltage distribution of the memory cell is formed narrower than when a single program operation is performed. Therefore, the threshold voltage distributions of different program states can be formed without overlapping each other.

[0069] Figure 5 is a flow chart of a method of programming a memory device according to some embodiments.

[0070] See also Figure 5 , a first programming operation first PGM may be performed on a plurality of first memory cells connected to a first word line group (S10). For example, the first word line group may include Figure 3 At least some of the first word lines WL_1 to the mth word lines WL_m included in the same memory block in FIG. When performing the first programming operation PGM, the first word line WL_1 to the mth word line WL_m may be as described in reference to FIG. Figure 4 The threshold voltage distribution of the plurality of first memory cells is changed.

[0071] Next, a first programming operation first PGM (S20) may be performed on a plurality of second memory cells connected to the second word line group. For example, the second word line group may include at least some of the first word lines WL_1 to the m-th word line WL_m, and may not include any of the first word lines WL_1 to the m-th word line WL_m included in the first word line group. In some embodiments, the second word line group may include any word line other than the first word line group among the first word lines WL_1 to the m-th word line WL_m included in the memory block. Therefore, the plurality of first memory cells and the plurality of second memory cells may be different memory cells MC. In operation S20, the first programming operation first PGM may be performed on the plurality of second memory cells. Thereafter, since the second programming operation second PGM is performed on the plurality of first memory cells, a state in which the first data DATA1 is written to the write buffer memory 130 may be maintained in operation S20.

[0072] Next, a second programming operation 2 PGM may be performed on the plurality of first memory cells connected to the first word line group (S30). The width of the threshold voltage distribution of the plurality of first memory cells formed by the first programming operation 1 PGM may be further reduced by the second programming operation 2 PGM. When the first data DATA1 is stored in the plurality of first memory cells, the first data DATA1 written in the buffer memory 130 may be erased.

[0073] Next, a second program operation 2 PGM may be performed on the plurality of second memory cells connected to the second word line group (S40). The width of the threshold voltage distribution of the plurality of second memory cells formed by the first program operation 1 PGM may be further reduced by the second program operation 2 PGM.

[0074] The method for programming a storage device according to the present invention may perform a first programming operation first PGM (S20) on a plurality of second storage cells instead of a plurality of first storage cells between a first programming operation first PGM (S10) on a plurality of first storage cells and a second programming operation second PGM (S30) on the plurality of first storage cells, thereby obtaining a delay time between a first programming operation first PGM and a second programming operation second PGM on the plurality of first storage cells. The delay time between the first programming operation first PGM and the second programming operation second PGM may be obtained by performing a second programming operation second PGM (S30) on the first storage cells between a first programming operation first PGM (S20) on the second storage cells and a second programming operation second PGM (S40) on the second storage cells.

[0075] In addition, some embodiments of the method for programming a storage device according to the present invention can obtain a longer delay time than the following situation: a first programming operation first PGM is performed on memory cells MC connected to one word line, and a first programming operation first PGM is performed on memory cells MC connected to another word line, and then, a second programming operation second PGM is performed again on the memory cells MC connected to one word line.

[0076] FIG. 6A to FIG. 6C It is used to illustrate Figure 5 , that is, for explaining a plurality of first storage units and a plurality of second storage units according to some embodiments.

[0077] See also Figure 3 and Fig. 6A , the first word line group WG1 may include the mth word line WLm to the m-3th word line WLm-3, and the second word line group WG2 may include the m-4th word line WLm-4 to the m-7th word line WLm-7. In some embodiments, the word lines included in the first word line group WG1 may be word lines adjacent to each other, and the second word line group WG2 may include word lines adjacent to each other.

[0078] A plurality of first memory cells C1 connected to the first word line group WG1 may constitute the mth page Page_m to the m-3th page Page_m-3, and a first programming operation 1 PGM and a second programming operation 2 PGM may be performed in units of pages. A plurality of second memory cells C2 connected to the second word line group WG2 may constitute the m-4th page Page_m-4 to the m-7th page Page_m-7, and a first programming operation 1 PGM and a second programming operation 2 PGM may be performed in units of pages.

[0079] Although each of the first word line group WG1 and the second word line group WG2 is illustrated as including four word lines, the embodiment is not limited thereto, and the number of word lines respectively included in the first word line group WG1 and the second word line group WG2 may vary. In addition, although the plurality of first memory cells C1 and the plurality of second memory cells C2 are illustrated as being included in the first memory block BLKa included in the memory cell array 121, the plurality of first memory cells C1 and the plurality of second memory cells C2 may be included in different memory blocks.

[0080] See also Figure 3 and Figure 6B , the first word line group WG1' may include the mth word line WLm, the m-2th word line WLm-2, the m-4th word line WLm-4, and the m-6th word line WLm-6, and the second word line group WG2' may include the m-1th word line WLm-1, the m-3th word line WLm-3, the m-5th word line WLm-5, and the m-7th word line WLm-7. In some embodiments, the word lines included in the first word line group WG1' may not be adjacent to each other, but may be adjacent to the word lines included in another word line group. The word lines included in the second word line group WG2' may not be adjacent to each other, but may be adjacent to the word lines included in another word line group.

[0081] The plurality of first memory cells C1' connected to the first word line group WG1' may constitute the mth page Page_m, the m-2nd page Page_m-2, the m-4th page Page_m-4, and the m-6th page Page_m-6, and the first programming operation First PGM and the second programming operation Second PGM may be performed in units of pages. The plurality of second memory cells C2' connected to the second word line group WG2' may be the m-1th page Page_m-1, the m-3rd page Page_m-3, the m-5th page Page_m-5, and the m-7th page Page_m-7, and the first programming operation First PGM and the second programming operation Second PGM may be performed in units of pages.

[0082] Although each of the first word line group WG1' and the second word line group WG2' is illustrated as including four word lines, the embodiment is not limited thereto, and the number of word lines respectively included in the first word line group WG1' and the second word line group WG2' may vary. In addition, although the plurality of first memory cells C1' and the plurality of second memory cells C2' are illustrated as being included in the first memory block BLKa' included in the memory cell array 121, the plurality of first memory cells C1' and the plurality of second memory cells C2' may be included in different memory blocks.

[0083] See also Figure 3 and Figure 6C, the first word line group WG1 ″ may include first to m-th word lines WL1 to WLm connected to the first memory block BLKa ″. The second word line group WG2 ″ may include first to m-th word lines WL1 to WLm connected to the second memory block BLKb.

[0084] A plurality of first storage cells C1" connected to the first word line group WG1" may constitute a first storage block BLKa", and a first programming operation first PGM and a second programming operation second PGM may be performed in units of pages. A plurality of first storage cells C2" connected to the second word line group WG2" may constitute a second storage block BLKb, and a first programming operation first PGM and a second programming operation second PGM may be performed in units of pages.

[0085] See also FIG. 6A to FIG. 6C , the method of programming a memory device according to the present invention may be configured such that a first programming operation first PGM and a second programming operation second PGM are performed on a plurality of first memory cells (C1, C1', and C1") in the order of word lines included in a first word line group (WG1, WG1', and WG1") (i.e., in units of pages). The first programming operation and the second programming operation may be performed on a plurality of second memory cells (C2, C2', and C2") in the order of word lines included in a second word line group (WG2, WG2', and WG2") (i.e., in units of pages). Since the second programming operation second PGM is performed on the plurality of first memory cells (C1, C1', and C1") in the order of word lines included in the first word line group (WG1, WG1', and WG1") after the first programming operation first PGM on the plurality of second memory cells (C2, C2', and C2") is completed, a delay time between the execution of the first programming operation first PGM and the second programming operation second PGM may be extended.

[0086] The method of programming a storage device according to the present inventive concept is not limited to FIG. 6A to FIG. 6C Before performing the second programming operation 2 PGM on the first memory cells (C1, C1' and C1"), the first programming operation 1 PGM (e.g., Figure 5 In some embodiments, before performing the second programming operation 2 PGM on the second memory cells (C2, C2', and C2"), a first programming operation 1 PGM (e.g., Figure 5 Operation S40 in FIG.

[0087] Therefore, after programming the plurality of first memory cells and the plurality of second memory cells, an overlapping phenomenon of threshold voltage distributions between different program states can be prevented.

[0088] Figure 7 is a block diagram illustrating a write buffer memory 130 included in a storage device according to some embodiments. Figure 7 In the present invention, for convenience of explanation, the write buffer memory 130 is described as being implemented with a resistance memory, but the inventive concept is not limited thereto.

[0089] See also Figure 7 , the write buffer memory 130 may include a memory cell array 131 and a control circuit 133. The write buffer memory 130 may also include a row decoder for decoding a row address to select a word line, a column decoder for decoding a column address to set the selected column switch to an on state, a sense amplifier, a read data latch, a write driver, and a write data latch. The memory cell array 131 may include a plurality of memory banks, and each of the plurality of memory banks may be connected to a row decoder, a column decoder, a sense amplifier, a read data latch, a write driver, and a write data latch, which may be different from each other.

[0090] The memory cell array 131 may include a plurality of memory cells MC. The plurality of memory cells MC may be arranged at the intersection of a plurality of bit lines and a plurality of word lines. In some embodiments, each memory cell MC may be an SLC storing one bit of data. For example, depending on the data stored therein, the memory cell MC may have two resistance distributions. However, the write buffer memory 130 according to the present invention is not limited thereto, and each memory cell MC may be a multi-level cell capable of storing 2 bits of data, or a three-level cell capable of storing 3 bits of data. In this case, each memory cell MC may have four or eight resistance distributions, depending on the data stored therein. However, the present invention is not limited thereto, and the memory cell array 131 may include memory cells MC each capable of storing 4 or more bits of data. In addition, the memory cell array 131 may include an SLC as well as a multi-level cell and / or a three-level cell.

[0091] In some embodiments, the plurality of memory cells MC may include a resistance-based memory cell including a variable resistance element having a resistance that varies depending on data to be stored therein, or may include a resistance memory cell. In some embodiments, when the variable resistance element has a resistance that varies with temperature as a phase change material (i.e., germanium-antimony-tellurium (Ge-Sb-Te or GST)), the write buffer memory 130 may be a PRAM. As another example, when the variable resistance element includes a composite metal oxide arranged at a top electrode, a bottom electrode, and therebetween, the buffer memory 130 may be an RRAM. As another example, in some embodiments, when the write buffer memory 130 includes a top electrode of a magnetic substance, a bottom electrode of a magnetic substance, and a dielectric material therebetween, the write buffer memory 130 may be an MRAM.

[0092] The memory controller 110 may control the write buffer memory 130 to read the data DATA after temporarily storing the data DATA in response to a write request from the host 200. The memory controller 110 may control a write operation or a read operation of the write buffer memory 130 by providing a command CMD and an address ADDR to the write buffer memory 130. In addition, data DATA to be written and read may be transmitted and received between the memory controller 110 and the write buffer memory 130.

[0093] The control circuit 133 may control write and read operations on the memory cell array 131 in response to a command CMD received from the memory controller 110. The control circuit 133 may control a bank activation state of the memory cell array 131 based on an address ADDR including a bank address and / or a row address received together with an activation command ACT. The control circuit 133 may activate a circuit associated with a bank to be activated in response to a bank address in the bank activation state, activate a selected word line by decoding a row address in the activated bank, and perform a read data recognition operation of reading and latching data of a memory cell MC of the memory cell array 131 connected to the selected word line.

[0094] The control circuit 133 may perform a read operation in response to a read command CMD. The control circuit 133 may output data read from the memory cell array 131 in a bank activated state to the memory controller 110 as output data DATA. The control circuit 133 may perform a read operation in response to a read command CMD. The control circuit 133 may write the received data DATA to the memory cell array 131 in a bank activated state.

[0095] The write buffer memory 130 according to the inventive concept may write first data DATA1 and second data DATA2 into the memory cell array 131 in a bank active state according to a write command CMD, and may read the first data DATA1 and second data DATA2 according to a read command CMD.

[0096] Figure 8 It is schematically shown Figure 7 Circuit diagram of the memory cell array 131 in FIG.

[0097] See also Figure 8 , the memory cell array 131 may be a two-dimensional memory of a horizontal structure and include first to b-th word lines WL1 to WLb, first to c-th bit lines BL1 to BLc, and a plurality of memory cells BMC. In this case, a and b may be integers of 5 or more, and the number of word lines WL, the number of bit lines BL, and the number of memory cells BMC may be variously changed according to some embodiments. Figure 8 Unlike that shown in FIG. 1 , the memory cell array 131 may be a vertical three-dimensional memory. The memory cell array 131 may include a plurality of memory blocks. Figure 8 In the figure, for the convenience of explanation, only one memory block is shown. The memory block may include multiple pages Page_b. Each of the multiple pages Page_b may correspond to a write unit or a read unit of data in one memory block. Each of the multiple pages Page_b may be connected to one of the first word line WL1 to the b-th word line WLb.

[0098] In some embodiments, each of the plurality of memory cells BMC may be a diode-one resistor (1D1R) type memory cell including a variable resistance element R and a selection element D. Here, the variable resistance element R may be referred to as a variable resistance material, and the selection element D may be referred to as a switching element.

[0099] In some embodiments, the variable resistance element R may be connected between one of the first bit line BL1 to the c-th bit line BLc and the selection element D, and the selection element D may be connected between the variable resistance element R and one of the first word line WL1 to the b-th word line WLb. However, embodiments are not limited thereto, and the selection element D may be connected between one of the first bit line BL1 to the c-th bit line BLc and the variable resistance element R, and the variable resistance element R may be connected to the selection element D and one of the first word line WL1 to the b-th word line WLb.

[0100] Due to the applied electric pulse, the variable resistor R can have one of multiple resistance states. In some embodiments, the variable resistor element R may include a phase change material, wherein the crystal state changes according to the amount of current. The phase change material may include various materials, such as GaSb, InSb, InSe, Sb2Te3 and / or GeTe in each combination of 2 elements, GeSbTe, GaSeTe, InSbTe, SnSb2Te4 and / or InSbGe in each combination of 3 elements, and / or AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and / or Te81Ge15Sb2S2 in each combination of 4 elements.

[0101] In some examples, instead of a phase change material, the variable resistance element R may include a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0102] The selection element D may be connected between any one of the first to b-th word lines WL1 to WLb and the corresponding variable resistance element R, and may control the current supply to the variable resistance element R according to the voltage applied to the connected word line WL and the connected bit line BL. Figure 8 In FIG. 1 , the selection element D is shown as a diode, but this is merely an example embodiment of the inventive concept, and in some embodiments, the selection element D may be changed to another switchable element.

[0103] FIG. 9A to FIG. 9C It is shown Figure 8 Circuit diagram of different embodiments of multiple storage cells BMC in FIG.

[0104] See also Fig. 9A , the memory cell MCa may include a variable resistance element Ra, and the variable resistance element Ra may be connected between the bit line BL and the word line WL. The memory cell MCa may store data by voltages respectively applied to the bit line BL and the word line WL.

[0105] See also Fig. 9B , the memory cell MCb may include a variable resistance element Rb and a bidirectional diode Db. The variable resistance element Rb may include a resistance material for storing data. The bidirectional diode Db may be connected between the variable resistance element Rb and the bit line BL, and the variable resistance element Rb may be connected between the word line WL and the bidirectional diode Db. The positions of the bidirectional diode Db and the variable resistance element Rb may be reversed. The leakage current flowing to the unselected resistance unit through the bidirectional diode Db may be cut off.

[0106] See also Fig. 9C, the memory cell MCc may include a variable resistance element Rc and a transistor TR. The transistor TR may be a selection element, that is, a switching element that supplies or cuts off current to the variable resistor Rc according to the voltage of the word line WL. Fig. 9C In an embodiment of the present invention, a source line SL for adjusting the voltage level at both ends of the variable resistance element Rc may be additionally provided. The transistor TR may be connected between the variable resistance element Rc and the bit line BL, and the variable resistance element R may be connected between the source line SL and the transistor TR. The source line SL may be a ground voltage line. The positions of the transistor TR and the variable resistance element Rc may be switched with each other. The memory cell MCc may be selected or not selected depending on whether the transistor TR driven by the word line WL is turned on or off.

[0107] Fig.10 1 is a diagram for explaining a write operation of the write buffer memory 130 according to some embodiments. Fig. 6A As shown in FIG. 1 , a case where the first data DATA1 is stored in the m-th page Page_m to the m-3-th page Page_m-3 of the first memory block BLKa of the NVM 120 is explained.

[0108] See also Fig. 6A and Fig.10 , the capacity of the first page data PD1 stored in one page of the NVM 120 may be greater than the capacity of the second page data PD2 stored in one page of the write buffer memory 130. Fig.10 , the first page data PD1 is shown to be four times the second page data PD2, but this is for ease of understanding, and the embodiment is not limited thereto.

[0109] When the first data DATA1 is written to the NVM 120, the first data DATA1 may be sequentially written to the mth page Page_m to the m-3rd page Page_m-3 in units of pages. In other words, the first program operation 1PGM or the second program operation 2PGM may be sequentially performed on the mth word line WLm to the m-3rd word line WLm-3. Therefore, the write buffer memory 130 may output the first data DATA1 in a manner of sequentially outputting data of the mth page Page_m to the m-3rd page Page_m-3 of the first memory block BLKa of the NVM 120, respectively. For example, the write buffer memory 130 may sequentially output data (DATA_Page_b11, DATA_Page_b12, DATA_Page_b13, and DATA_Page_b14) stored in each of the plurality of pages of the write buffer memory 130, so that the write buffer memory 130 outputs data DATA_BLKa_Page_m corresponding to the mth page Page_m of the first memory block BLK1 of the NVM 120. In addition, the write buffer memory 130 can sequentially output data (DATA_Page_b21, DATA_Page_b22, DATA_Page_b23 and DATA_Page_b24) stored in each of the multiple pages of the write buffer memory 130, so that the write buffer memory 130 outputs data DATA_BLKa_Page_m-1 corresponding to the m-1th page Page_m-1 of the first storage block BLK1 of the NVM 120.

[0110] The memory cell array 131 of the write buffer memory 130 may include a zeroth memory bank Bank0 to a third memory bank Bank3, and although Fig.10 In some embodiments, data (DATA_Page_b11, DATA_Page_b12, DATA_Page_b13, and DATA_Page_b14) stored in each of the plurality of pages of the write buffer memory 130 may be data stored in different memory banks, respectively.

[0111] In the mapping table (for example, Figure 1BIn the mapping table 113 in the write buffer memory 130, information about the logical address of each of the multiple pages of the NVM 120 and information about the physical address of each of the multiple pages of the write buffer memory 130 corresponding to the logical address may be stored. For example, information about the physical address of each of the multiple pages (Page_b11, Page_b12, Page_b13, and Page_b14) of the write buffer memory 130 corresponding to the logical address of the mth page Page_m of the first storage block BLKa of the NVM 120 may be stored. Therefore, when a request to write data to the mth page Page_m of the first storage block BLKa of the NVM 120 is received from the host 200, in the write buffer memory 130, the data may be temporarily written to the multiple pages (e.g., Page_b11, Page_b12, Page_b13, and Page_b14) of the first storage block BLKa based on the mapping table 113, and thereafter, the data may be written to the mth page Page_m of the first storage block BLKa.

[0112] Fig.11A and Fig. 11B is a timing diagram of a write operation of the write buffer memory 130 according to an example embodiment. Fig.10 As shown and referenced in Fig.10 What is described gives a description.

[0113] See also Figure 7 , Fig.10 and Fig.11A In some embodiments, the write buffer memory 130 may be a resistive memory device. The read operation of the write buffer memory 130 may be performed by an activation command Act and a plurality of read commands (Read_P11, Read_P12, Read_P13, and Read_P14) received in succession.

[0114] Each of the plurality of read commands (Read_P11, Read_P12, Read_P13, and Read_P14) may be used to read a Fig.10In the write buffer memory 130, the storage controller 110 outputs a command for reading data stored in a plurality of pages (Page_b11, Page_b12, Page_b13, and Page_b14) of the write buffer memory 130. At this time, since the data stored in the plurality of pages (Page_b11, Page_b12, Page_b13, and Page_b14) is one page of the NVM 120 (for example, data DATA_BLKa_Page_m to be stored in the mth page Page_m of the first storage block BLKa), the data stored in the plurality of pages (Page_b11, Page_b12, Page_b13, and Page_b14) of the write buffer memory 130 may be read in full without partial reading. Therefore, when the storage controller 110 outputs each of the plurality of read commands (Read_P11, Read_P12, Read_P13, and Read_P14) to the write buffer memory 130, the activation command Act may not be output separately between the read commands (Read_P11, Read_P12, Read_P13, and Read_P14). After outputting the activation command Act to the write buffer memory 130, the storage controller 110 may sequentially output a plurality of read commands (Read_P11, Read_P12, Read_P13, and Read_P14). The write buffer memory 130 may be in an activated state by the activation command Act, and may read data based on corresponding addresses corresponding to the plurality of read commands (Read_P11, Read_P12, Read_P13, and Read_P14). Therefore, the write buffer memory 130 according to the exemplary embodiment of the inventive concept may output data to be stored in one page of the NVM 120 without providing the activation command Act multiple times, so its data reading speed may be improved.

[0115] See also Figure 7 , Fig.10 and Fig. 11B, the read operation of the write buffer memory 130 may be performed by a plurality of activation commands Act and a plurality of read commands (Read_P11, Read_P12, Read_P13, and Read_P14) provided at different times (t1, t2, t3, and t4). The addresses ADDR corresponding to the plurality of read commands (Read_P11, Read_P12, Read_P13, and Read_P14), respectively, may represent pages included in different banks of the memory cell array 131 of the write buffer memory 130. The durations of performing activation operations for reading data stored in pages included in different banks may overlap with each other, and the read operations may be performed overlapping with each other. In other words, the total time for reading the data DATA_BLKa_Page_m may be shortened by the bank interleaving operation, and therefore, the data reading speed may be improved.

[0116] Fig.12 is a block diagram showing a configuration of an ECC circuit included in a storage device according to some embodiments, and is Figure 1B 1. A block diagram of the ECC circuit 112 in FIG.

[0117] See also Fig.12 , the ECC circuit 112 may include a buffer memory ECC decoder 112 a and an NVM ECC encoder 112 b.

[0118] The buffer memory ECC decoder 112a may sequentially receive the first data DATA1 and the second data DATA2 from the write buffer memory 130. At this time, the first data DATA1 may include a first ECC parity code P11 generated based on the first data DATA1, and the second data DATA2 may include a first ECC parity code P12 generated based on the second data DATA2. The buffer memory ECC decoder 112a may detect an error contained in each of the first data DATA1 and the second data DATA2 by decoding each of the first ECC parity codes (P11 and P12). The first ECC parity codes (P11 and P12) may be used to correct errors generated in the first data DATA1 and the second data DATA2. For example, an error occurring in one or more bits of data in a read process of the first data DATA1 and the second data DATA2 may be corrected by an error correction operation using the first ECC parity codes (P11, P12).

[0119] The NVM ECC encoder 112b may generate a second parity code P21 by ECC encoding the error-corrected first data DATA1, and may generate a second parity code P22 by ECC encoding the error-corrected second data DATA2. The NVM ECC encoder 112b may output the first data DATA1′ including the second parity code P21 and the second data DATA2′ including the second parity code P22 to the NVM I / F 117.

[0120] At this time, the first data DATA1' and the second data DATA2' provided to the NVM 120 may be data in which errors of the first data DATA1 and the second data DATA2 have been corrected. Each of the first ECC parity codes (P11 and P12) may be different from each of the second ECC parity codes (P21 and P22).

[0121] In some embodiments, NVM 120 may be a NAND flash memory and write buffer memory 130 may be a PRAM. When write buffer memory 130 is a PRAM, the time taken for decoding by buffer memory ECC decoder 112a may be reduced compared to when write buffer memory 130 is a NAND flash memory.

[0122] Fig.13 is a flowchart of an operation of a memory controller included in a memory device according to example embodiments.

[0123] See also Figure 1B , Fig.12 and Fig.13 , the first data DATA1 to be stored in the plurality of first storage cells including the first ECC parity code (P11) generated based on the first data DATA1 may be stored in the write buffer memory 130 (S100). At this time, the second data DATA2 to be stored in the plurality of second storage cells including the first ECC parity code (P12) generated based on the second data DATA2 may be stored in the write buffer memory 130 together with the first data DATA1.

[0124] The first data DATA1 may be output from the write buffer memory 130 ( S200 ).

[0125] The buffer memory ECC decoder 112a may decode the first ECC parity code (P11) and correct an error of the first data DATA1 (S300). The buffer memory ECC decoder 112a may output the error-corrected first data DATA1.

[0126] The NVM ECC encoder 112 b may receive the error-corrected first data DATA1 and encode a second ECC parity code ( P21 ) based on the error-corrected first data DATA1 .

[0127] The NVM ECC encoder 112b may output the first data DATA1' including the second ECC parity code (P21) to the NVM 120 via the NVM I / F 117 (S500).

[0128] After performing operation S500, an operation on the second data DATA2 stored in the write buffer memory 130 may be performed. For example, the second data DATA2 including the first ECC parity code (P12) may be output from the write buffer memory 130, and an error of the second data DATA2 may be corrected by decoding the first ECC parity code (P12). The NVM ECC encoder 112b may receive the error-corrected second data DATA2 and encode the second ECC parity code (P22) based on the error-corrected second data DATA2. The NVM ECC encoder 112b may output the second data DATA2' including the second ECC parity code (P22) to the NVM 120 via the NVM I / F 117.

[0129] When the write buffer memory is implemented as a NAND flash memory including an SLC and is included in the NVM, the first data and the second data are input to the write buffer memory (once), the first ECC parity code is decoded and the second ECC parity code is encoded based on the first data and the second data output from the write buffer memory (twice), and the first data and the second data including the first ECC parity code are written to the NVM 120 (three times). Since the first data and the second data are stored in the memory controller (e.g., Figure 1A and / or Figure 1B The data input / output operation may take a certain amount of time because the data input / output operation is input and output three times between the NVM 110) and the NVM 120.

[0130] However, the memory device according to the inventive concept may include a write buffer memory 130 provided separately from the NVM 120 so that each of the first data DATA1′ and the second data DATA2′ is output once between the memory controller 110 and the NVM 120. Therefore, the time required to write the first data DATA1′ and the second data DATA2′ to the NVM 120 may be reduced.

[0131] Embodiments of the inventive concept have been described in detail with reference to the accompanying drawings. On the other hand, although a detailed description of the present disclosure has been provided with reference to specific embodiments, various modifications may be made without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be interpreted as being limited to the above-described embodiments, and may be limited by the claims of the present disclosure and the equivalents of the appended claims.

Claims

1. A storage device, comprising: A non-volatile memory, comprising a plurality of non-volatile storage units; a write buffer memory configured to store first data and second data received from a host; as well as a storage controller configured to store the first data and the second data stored in the write buffer memory in the nonvolatile memory, wherein the memory controller is configured to perform a first programming operation and a second programming operation on a plurality of first memory cells connected to a first word line group including a plurality of first word lines to store first data, wherein the memory controller is configured to perform a first programming operation and a second programming operation on a plurality of second memory cells connected to a second word line group including a plurality of second word lines to store second data, wherein when the storage controller is configured to perform a first programming operation on the plurality of second storage cells, the first data is written into the write buffer memory, and The storage controller is configured to sequentially provide a plurality of read commands corresponding to different addresses to the write buffer memory after providing an activation command to the write buffer memory.

2. The storage device according to claim 1, wherein: A plurality of word lines in the first word line group are adjacent to each other.

3. The storage device according to claim 1, in, At least one of the plurality of second word lines is between different first word lines among the plurality of first word lines.

4. The storage device according to claim 1, wherein: The plurality of first storage units include a first storage block.

5. The storage device according to claim 1, wherein: The write buffer memory includes a plurality of resistance memory cells.

6. The storage device according to claim 1, wherein: A first size of data stored in a single page of the nonvolatile memory is greater than a second size of data stored in a single page of the write buffer memory.

7. The storage device according to claim 1, in, The memory controller includes an error checking and correction (ECC) circuit including a buffer memory ECC decoder and a non-volatile memory (NVM) ECC encoder, wherein the buffer memory ECC decoder is configured to detect errors by decoding a first ECC parity code in the first data and a second ECC parity code in the second data, and The NVM ECC encoder is configured to encode a first ECC parity code of the first data in which errors have been corrected and a second ECC parity code of the second data.

8. A storage device, comprising: A non-volatile memory, comprising a plurality of non-volatile storage units; as well as a storage controller configured to store first data and second data received from a host in a nonvolatile memory, the storage controller comprising a write buffer memory, wherein the memory controller is configured to perform a first programming operation and a second programming operation on a plurality of first memory cells connected to a first word line group to store first data, and wherein the memory controller is configured to perform a first programming operation and a second programming operation on a plurality of second memory cells connected to a second word line group to store second data, wherein when the storage controller is configured to perform a first programming operation on the plurality of second storage cells, the first data is written into the write buffer memory, and The storage controller is configured to sequentially provide a plurality of read commands corresponding to different addresses to the write buffer memory after providing an activation command to the write buffer memory.

9. The storage device according to claim 8, wherein: A plurality of word lines in at least one of the first word line group and the second word line group are adjacent to each other.

10. The storage device according to claim 8, wherein: At least one second word line in the second word line group is between first word lines in the first word line group.

11. The storage device according to claim 8, wherein: The plurality of first storage units include a first storage block, and the plurality of second storage units include a second storage block different from the first storage block.

12. The storage device according to claim 8, wherein: The write buffer memory and the nonvolatile memory are different memories from each other.

13. The storage device of claim 12, wherein: The write buffer memory is a phase change random access memory (PRAM).

14. The storage device according to claim 8, wherein: An increment of the plurality of first program pulses in the first program operation is different from an increment of the plurality of second program pulses in the second program operation.

15. The storage device according to claim 8, wherein: Some of the plurality of nonvolatile memory cells are configured to store multi-bit data.

16. A method for operating a storage device, the storage device comprising a non-volatile memory and a storage controller configured to control the non-volatile memory, the method for operating the storage device comprising: performing a first programming operation on a plurality of first memory cells connected to a first word line group based on first data; performing a first programming operation on a plurality of second memory cells connected to a second word line group different from the first word line group based on second data; performing a second programming operation on the plurality of first memory cells based on the first data; as well as performing a second programming operation on the plurality of second memory cells based on second data, wherein some of the plurality of first storage units and some of the plurality of second storage units store multi-bit data, and wherein performing a first programming operation on the plurality of first storage cells, performing a first programming operation on the plurality of second storage cells, performing a second programming operation on the plurality of first storage cells, and performing a second programming operation on the plurality of second storage cells are performed sequentially, After the activate command is supplied to the write buffer memory, a plurality of read commands corresponding to different addresses are sequentially supplied to the write buffer memory.

17. The method for operating a storage device according to claim 16, further comprising: decoding, by the storage controller, a first error checking and correction (ECC) parity code in the first data; Correcting errors of the first data by the storage controller based on decoding of the first ECC parity code to generate error-corrected first data; encoding, by the storage controller, a second ECC parity code based on the error-corrected first data; as well as The first data and the second ECC parity code are output to the nonvolatile memory by the memory controller.

18. The method for operating a storage device according to claim 16, wherein: Some of the plurality of first memory cells and some of the plurality of second memory cells store data of 4 bits or more.

19. A storage device comprising: A non-volatile memory, comprising a plurality of non-volatile storage units; a write buffer memory configured to store first data and second data received from a host; as well as a storage controller configured to store the first data and the second data stored in the write buffer memory in the nonvolatile memory, wherein the memory controller is configured to perform a first programming operation and a second programming operation on a plurality of first memory cells connected to a first word line group including a plurality of first word lines to store first data, wherein the memory controller is configured to perform a first programming operation and a second programming operation on a plurality of second memory cells connected to a second word line group including a plurality of second word lines to store second data, wherein, when the storage controller is configured to perform a first programming operation on the plurality of second storage cells, the first data is written into the write buffer memory, wherein the storage controller is configured to subsequently provide a plurality of activate commands to the write buffer memory, and The durations of performing activation operations on the write buffer memory due to the plurality of activation commands overlap with each other.

20. The storage device of claim 19, wherein: A plurality of word lines in the first word line group are adjacent to each other.

21. The storage device according to claim 19, in, At least one of the plurality of second word lines is between different first word lines among the plurality of first word lines.

22. The storage device of claim 19, wherein: The plurality of first storage units include a first storage block.

23. The storage device of claim 19, wherein: The write buffer memory includes a plurality of resistance memory cells.

24. The storage device of claim 19, wherein: A first size of data stored in a single page of the nonvolatile memory is greater than a second size of data stored in a single page of the write buffer memory.

25. The storage device of claim 19, in, The memory controller includes an error checking and correction (ECC) circuit including a buffer memory ECC decoder and a non-volatile memory (NVM) ECC encoder, wherein the buffer memory ECC decoder is configured to detect errors by decoding a first ECC parity code in the first data and a second ECC parity code in the second data, and The NVM ECC encoder is configured to encode a first ECC parity code of the first data in which errors have been corrected and a second ECC parity code of the second data.

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