System and method for reducing write buffer size in non-volatile memory device

Abstract

The invention relates to a system and method for reducing write buffer size in a non-volatile storage device. A system may include a controller, a write buffer, and a device. An apparatus may include a non-volatile memory (NVM), a first data buffer, and a second data buffer. The controller may be configured to transfer data from the write buffer to the first data buffer and the second data buffer, and determine whether a power failure has occurred. In response to determining that the power failure does not occur, the controller may configure the device to program data stored in at least one of the first data buffer or the second data buffer to the NVM in a first mode. In response to determining that the power failure has occurred, the controller may configure the device to program data stored in at least one of the first data buffer or the second data buffer to the NVM in a second mode different from the first mode.

Description

Technical Field

[0001] Arrangements described herein generally relate to operating a data storage device using a write buffer for transferring data to a nonvolatile memory, and more particularly to using a buffer in a nonvolatile memory device to reduce the size of the write buffer. Background Art

[0002] The storage device may read a data block from a nonvolatile memory or write a data block to a nonvolatile memory via a volatile memory buffer. When a power failure is detected, the storage device may perform power loss protection (PLP), for example, writing data to be persisted that is temporarily stored in a buffer to a nonvolatile memory. Given that time and power are limited during a power failure, improvements in time-energy efficient PLP operations are still desired. Summary of the invention

[0003] The present arrangements relate to systems and methods for using a buffer in a non-volatile memory device to reduce the size of a write buffer in a data storage device.

[0004] According to some arrangements, a system includes a controller, a write buffer, and a device. The device may include a non-volatile memory NVM, a first data buffer, and a second data buffer. The controller may be configured to determine whether a power failure occurs. In response to determining that a power failure does not occur, the controller may configure the device to program the data stored in at least one of the first data buffer or the second data buffer to the NVM in a first mode. In response to determining that the power failure occurs, the controller may configure the device to program the data stored in at least one of the first data buffer or the second data buffer to the NVM in a second mode different from the first mode.

[0005] According to some arrangements, a method includes transferring data from a write buffer to a first data buffer of a device and a second data buffer of the device by a controller. The method includes determining by the controller whether a power failure has occurred. The method may include, in response to determining that a power failure has not occurred, configuring the device by the controller to program the data stored in at least one of the first data buffer or the second data buffer to a non-volatile memory NVM of the device in a first mode. The method may include, in response to determining that the power failure has occurred, configuring the device by the controller to program the data stored in at least one of the first data buffer or the second data buffer to the NVM of the device in a second mode different from the first mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and other aspects and features of the present arrangement will become apparent to those of ordinary skill in the art after reading the following description of the specific arrangement in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a block diagram illustrating an example computer system including a solid state drive (SSD);

[0008] Figure 2 is a block diagram illustrating an example computer system including a controller system on chip (SoC) in an SSD according to some arrangements;

[0009] Figure 3 is a block diagram illustrating an example computer system including a controller SoC and a buffer in a NAND subsystem in an SSD according to some arrangements;

[0010] Figure 4A and Figure 4B is a graph illustrating performance of a write buffer using a buffer in a NAND subsystem according to some arrangements; and

[0011] Figure 5 is a flow chart illustrating an example method of reducing the size of a write buffer using a buffer in a NAND subsystem according to some arrangements. DETAILED DESCRIPTION

[0012] Some arrangements of the present disclosure relate to techniques for using a buffer in a non-volatile memory device to reduce the size of a write buffer in a data storage device.

[0013] In some arrangements, data centers and enterprise servers may have PLP capacitors for use during sudden external power outages (e.g., power outages, power failures). The PLP capacitors can ensure that when the solid-state drive (SSD) is powered off, for all host write commands that have been confirmed, the write data temporarily saved and / or buffered in the volatile memory is persisted to the non-volatile memory (NAND) using the PLP capacitor power. Many PLP capacitors are used to store the amount of write data that can be stored in the volatile memory. "Write buffer" may refer to an area in the volatile memory where write data is temporarily stored. The size of the write buffer may sometimes limit the performance of the storage device (e.g., SSD) and affect the latency of the host writing data. Figure 1 and Figure 2 A configuration is shown in which an SSD uses one or more write buffers to transfer data to non-volatile memory.

[0014] Figure 1 is a block diagram illustrating an example computer system according to some arrangements. Figure 1, the computer system 1000 may include a host 10 and an SSD 100, which is a storage device and may be used as a main storage device of an information processing device (eg, the host 10). The SSD 100 may be incorporated into the information processing device or may be connected to the information processing device via a cable or a network.

[0015] The host 10 may be an information processing device (computing apparatus) that accesses the SSD 100. The host 10 may be a server (storage server) that stores a large amount of various data in the SSD 100, or may be a personal computer. The host includes a file system 15 for controlling file operations (e.g., creation, saving, updating, or deletion). For example, ZFS, Btrfs, XFS, ext4, or NTFS may be used as the file system 15. Alternatively, a file object system (e.g., Ceph Object Storage Daemon), a key value storage system (e.g., RocksDB) may be used as the file system 15.

[0016] The SSD 100 includes, for example, a controller 120 and a flash memory 180 (for example, a NAND-type flash memory) as a non-volatile memory. The SSD 100 may include a random access memory as a volatile memory, for example, a DRAM (Dynamic Random Access Memory) 110. In some arrangements, the controller 120 may include a random access memory such as an SRAM (Static Random Access Memory). The random access memory such as the DRAM 110 has, for example, a read buffer, which is a buffer area for temporarily storing data read from the flash memory 180; a write buffer 112, which is a buffer area for temporarily storing data written in the flash memory 180, and a buffer for garbage collection. In some arrangements, the controller 120 may include the DRAM 110.

[0017] In some arrangements, the flash memory 180 may include a memory cell array including a plurality of flash memory blocks (e.g., NAND blocks) 180-1 to 180-m. Each of the blocks 180-1 to 180-m may be used as an erase unit. Each of the blocks 180-1 to 180-m includes a plurality of physical pages. In some arrangements, in the flash memory 180, data reading and data writing may be performed on a page basis, and data erasure may be performed on a block basis.

[0018] In some arrangements, the controller 120 may be a memory controller configured to control the flash memory 180. The controller 120 includes, for example, a processor (e.g., CPU) 150, a flash memory interface 140, and a DRAM interface 130, a host interface 190, all of which may be interconnected via a bus 128. The DRAM interface 130 may function as a DRAM controller configured to control access to the DRAM 110. The flash memory interface 140 may function as a flash memory control circuit (e.g., a NAND control circuit) configured to control the flash memory 180 (e.g., a NAND-type flash memory).

[0019] The host interface 190 may be used as a circuit for receiving various requests from the host 15 and sending responses to the requests to the host 10. The request may include various commands, such as I / O commands and control commands. The I / O command may include, for example, a write command, a read command, a trim command (unmap command), a format command, and a flush command. The write command is also referred to as a programming command. The format command may be a command for unmapping the entire memory system (SSD 100).

[0020] The processor 150 may be configured to control the flash memory interface 140 and the DRAM interface 130. The processor 150 may be configured to perform various processes by executing a control program (e.g., firmware) stored in, for example, a ROM (not shown). In some arrangements, the processor 150 may execute a command control 160 to perform command processing to process various commands received from an information processing device (e.g., a host computer). In some arrangements, the processor 150 may execute a power failure control 152 to detect a power failure and / or perform a PLP operation, for example, using PLP capacitor power to write and / or persist write data temporarily saved and / or buffered in the write buffer 112 to a non-volatile memory (e.g., NAND). The processor 150 may be configured to serve as a flash translation layer (FTL) 170 to perform data management and block management of the flash memory 180. The FTL 170 may include a lookup table control 172, a garbage collection control 174, a wear leveling control 176, and a flash memory control 178. Data management may include management of mapping information indicating a correspondence between a logical address (e.g., LBA (Logical Block Address)) and a physical address of the flash memory 180. In some arrangements, the lookup table control 172 may perform management of mapping between (1) each logical block address (LBA) or each logical page address and (2) each physical address using an address translation table (logical / physical address translation table). The garbage collection control unit 174 may perform garbage collection (GC), which is a process performed to generate a free block as a data writing destination block. The wear leveling control 176 may perform wear leveling, which is a process of balancing the number of times a block is erased, so that the possibility of failure of the SSD 100 can be reduced by preventing the occurrence of blocks with a large number of erases. The flash memory control unit 178 may perform control of the flash memory interface 140.

[0021] Figure 2 2 is a block diagram illustrating an example computer system 2000 including a controller system on chip (SoC) 220 in an SSD 200 according to some arrangements. The computer system 2000 may include a host 20, which may have a connection with the host 10 (see Figure 1) is a configuration similar to that of the host 20. The SSD 200 is a storage device and can be used as a main storage device of an information processing device (e.g., the host 20). The SSD 200 can be incorporated into the information processing device or can be connected to the information processing device via a cable or a network. The SSD 200 can include a DRAM 210 and a NAND array 280. The DRAM 210 has a configuration similar to that of the DRAM 110. For example, the DRAM 210 can include a write buffer 212. The NAND array 280 can include a plurality of NAND-type flash memories 280-1, 280-2, ..., 280-N (e.g., N=16, ..., 128, etc.). The controller SoC 220 can read data from the NAND array or write data to the NAND array through a NAND bus 290 (e.g., an 8-bit or 16-bit data bus).

[0022] The controller SoC 220 may be a system on chip or an integrated circuit that integrates the NAND controller 220, the memory controller 230, the host I / F controller 240, and a volatile memory including the write buffer 260. A typical write buffer size (including the write buffers 212 and 260) may be at least 6MB (as a minimum). Each of the NAND controller 220, the memory controller 230, the host I / F controller 240 may be implemented or executed by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.

[0023] The NAND controller 250 may communicate with the processor 150 and / or the flash memory I / F 140 (see Figure 1) functions similarly. For example, the NAND controller may execute command control 260 to perform command processing for processing various commands received from an information processing device (e.g., a host computer). In some arrangements, the NAND controller may execute power failure control 252 to detect power failures (e.g., by monitoring voltage) and / or perform PLP operations, for example, using PLP capacitor power to write and / or persist write data temporarily saved and / or buffered in the write buffer 260 to a non-volatile memory (e.g., NAND). The NAND controller may be configured to function as a flash translation layer (FTL) 270 to perform data management and block management of a flash memory (e.g., a NAND-type flash memory) in a NAND array 280. The NAND controller 250 may be configured to control the flow of data in a plurality of channels (e.g., 16 channels) to or from the transmission of the NAND array 280 connected in parallel (via a NAND bus 290). The NAND controller 250 may be configured to perform error correction to extract correct data from data read from the NAND array 280.

[0024] The memory controller 230 can communicate with the DRAM I / F 130 (see Figure 1 ) functions similarly. For example, the memory controller may manage temporary data buffers (e.g., write buffer 212) to transfer read / write data, and manage lookup table (LUT) data (which may account for 90% of DRAM data). The host interface controller 240 may communicate with the host I / F 190 (see Figure 1 ) functions similarly. In some arrangements, the host interface controller 240 may implement one or more storage access protocols including Peripheral Component Interconnect Express (PCIe) and / or NVMe (Non-Volatile Memory Express).

[0025] In one aspect, a write buffer (e.g., Figure 2 The size of the write buffer 260 in the SSD may be a limitation (e.g., Figure 2 The NVMe SSD 200 is a key element of the host I / O write command performance of the NVMe SSD 200. For example, a smaller write buffer may reduce write performance. Different storage access protocols may use write buffers of different sizes. For example, an NVMe multi-stream SSD may use a larger write buffer than a standard NVMe SSD to achieve the same aggregate I / O write performance.

[0026] Typically, as the capacity of the SSD increases, the size of the write buffer also increases to improve write performance. However, in the event of a power outage or power failure, a smaller write buffer uses fewer PLP capacitors to achieve power-off protection. In addition, the data stored in the write buffer can be programmed in the NAND subsystem (e.g., TLC programming), and once the data has been transferred to the NAND (e.g., using a method called "fire-and-forget FTL"), the data can be deleted from the write buffer. In the event of a power outage, the data transferred from the write buffer to the NAND must complete TLC programming, which consumes a lot of energy. Therefore, using a larger write buffer may consume more energy than using a smaller write buffer. The write buffer can be made smaller, which may reduce write performance. It is a common problem to reduce the size of the write buffer to reduce the energy used to store in-flight host write command data without affecting write performance.

[0027] To address this problem, according to certain aspects, the arrangements of the present disclosure relate to such techniques for limiting or reducing the size of a write buffer in a non-volatile storage device (e.g., an SSD) to reduce the energy used to store in-transit write commands when a power failure occurs without affecting the I / O write command performance of the SSD. In some arrangements, the SSD may include one or more write buffers and a flash memory controller system-on-chip (SoC) (e.g., a NAND controller SoC). Most of the one or more write buffers may be located within the NAND controller SoC to improve the performance of the SSD. In some arrangements, the SSD may be a multi-stream (or multi-stream) SSD that can write data in a stream together to a physically related NAND flash memory space (e.g., a block or erase unit) and also separate the data from other streams. The size of the write buffer is critical to the host I / O write command performance of the SSD (e.g., a data center SSD) - especially an NVMe multi-stream SSD.

[0028] In some arrangements, the storage device may include one or more flash memory devices (e.g., NAND subsystems). The NAND subsystem may include at least one of the following types of NAND: single-layer cell (SLC) type, multi-layer cell (MLC) type, triple-layer cell (TLC) type, or quad-layer cell (QLC) type. The NAND subsystem may support or maintain at least two data buffers—(1) a program data buffer (also referred to as a "program buffer," "P buffer," "current program full sequence programming (FSP) data buffer") and (2) an additional data buffer (also referred to as an "additional buffer," "A buffer," "queue program FSP data buffer"). For example, each NAND subsystem may have a 192KB A buffer. If the number of NAND subsystems is 128, the total size of the A buffer will be 24MB. Each NAND subsystem may include a NAND memory, one or more P buffers, and one or more A buffers. In some arrangements, each NAND subsystem may be an integrated circuit or chip. The use of the P buffer and the A buffer can allow data to be transferred quickly from the controller (e.g., a NAND controller SoC), so that the write buffer can be as small as possible without affecting the I / O write command performance of the storage device. The use of the P buffer and the A buffer can reduce the size of the write buffer, thereby reducing the energy used to store in-transit host write command data without affecting the I / O write performance. The use of the A buffer can also reduce the time between completing one NAND program command and starting the next programming operation because the data for the program has been received from the host and transferred to the NAND.

[0029] In some arrangements, the P buffer may include multiple P buffers. The A buffer may include multiple A buffers. The P buffer and the A buffer may form a buffer queue (e.g., a first-in, first-out (FIFO) queue). The P buffer and the A buffer may form a ping pong buffer (or multi-buffer) so that data in one of the P buffer and the A buffer may be written to the NAND while the other of the P buffer and the A buffer receives data.

[0030] In some arrangements, the storage device may support a "power-off reset" command to immediately stop all programming of a NAND subsystem or a NAND array including multiple NAND subsystems. For example, upon receiving a "power-off reset" command, the storage device may stop all programming of the NAND array in SLC mode, MLC mode, TLC mode, or QLC mode.

[0031] In some arrangements, the storage device may support a "power-off flush" command to trigger or start programming any host in-transit data stored in the P-buffer and / or A-buffer of the NAND subsystem to the NAND memory of the NAND subsystem. For example, upon receiving the "power-off flush" command, the storage device may program (or control each NAND subsystem to program) the host in-transit data stored in the P-buffer and / or A-buffer to an empty block in a pseudo single-layer cell (pSLC) mode. The pSLC mode programs data significantly faster than other modes (e.g., MLC, TLC, or QLC modes), thereby reducing the energy used to store the host in-transit data in the NAND array. The P-buffer and / or A-buffer of the NAND subsystem may be used to program the data, thereby (1) allowing the controller (e.g., controller SoC) to not process or transmit the data to the NAND subsystem, and (2) saving energy used to create NAND parity and transmit the data to the NAND subsystem.

[0032] In some arrangements, a storage device may add an A buffer to a NAND subsystem (e.g., each NAND subsystem in a NAND array), and add additional NAND commands (e.g., "power off reset" followed by "power off flush") to allow data stored in the P buffer and the A buffer to be programmed into empty blocks in pSLC mode without having to transfer data from a write buffer (e.g., a write buffer in an SSD controller SoC) to the NAND subsystem across a NAND bus through a controller (e.g., an SSD controller SoC). In this way, the storage device may divide the buffer size (e.g., the size of the write buffer) between (1) the controller and DRAM and (2) the NAND subsystem. When there is a power outage (or a power outage is detected), the storage device may allow the controller to immediately stop all programming in the NAND array (in MLC, TLC, or QLC mode) while identifying which data stored in the NAND buffers (e.g., the P buffer and / or the A buffer) is to be programmed in pSLC mode. In some arrangements, data stored in the P buffer and / or A buffer and then programmed in pSLC mode may include host write data and may not include garbage collection data. Immediately stopping the process program (in MLC, TLC, or QLC mode) can maximize the amount of data programmed in pSLC mode, and programming from the internal NAND buffer (e.g., P buffer and / or A buffer) can reduce the energy used to store the data compared to methods that allow in-process programming to complete and then transfer the remaining data from the controller and / or write buffers in DRAM. In some arrangements, when power is restored, the storage device can read the data programmed in pSLC mode and write (e.g., reprogram) the data in the original programming mode (e.g., TLC mode).

[0033] In some arrangements, the storage device may transfer data to one of the P-buffer and the A-buffer in the NAND subsystem while running the current NAND programming (e.g., in TLC / QLC mode) in the other of the P-buffer and the A-buffer, thereby maximizing the NAND programming rate and freeing up space in the write buffer of the controller and / or internal memory (e.g., DRAM), which can improve write performance with a small amount or a small size of internal RAM. The use of the P-buffer and the A-buffer for each NAND subsystem can have the following effect: the size of the write buffer is automatically increased as the number of NAND subsystems increases. That is, the more NAND subsystems become, the larger the write buffer can be achieved, obtained, or completed (in the volatile memory in the NAND subsystem) through the P-buffer and the A-buffer.

[0034] In one approach, a system may include a controller, a write buffer, and a device. The device may include a non-volatile memory (NVM), a first data buffer, and a second data buffer. The controller may be configured to transfer data from the write buffer to the first data buffer and the second data buffer, and determine whether a power failure has occurred. In response to determining that a power failure has not occurred, the controller may configure the device to program data stored in at least one of the first data buffer or the second data buffer to the NVM in a first mode. In response to determining that a power failure has occurred, the controller may configure the device to program data stored in at least one of the first data buffer or the second data buffer to the NVM in a second mode different from the first mode.

[0035] In some arrangements, the first mode may be at least one of a single-layer cell (SLC) mode, a multi-layer cell (MLC) mode, a triple-layer cell (TLC) mode, or a quad-layer cell (QLC) mode. The second mode may be a pseudo single-layer cell (pSLC) mode. The controller may include a write buffer. For example, in response to determining that a power failure has occurred, remaining in-transit write data may be transferred from the write buffer to the NAND buffer (e.g., first buffer, second buffer) in parallel with a flush operation to a special pSLC storage area of ​​other NAND buffers (e.g., first buffer, second buffer). In some arrangements, a flush operation may be performed and then the remaining in-transit data in the write buffer may be transferred to the NAND to be programmed into the special pSLC storage area.

[0036] In some arrangements, the device may include multiple subsystems, each subsystem including a corresponding NVM. The first data buffer may include one or more program data buffers in each of the multiple subsystems. The second data buffer may include one or more additional buffers in each of the multiple subsystems. In some arrangements, the controller is a solid state drive (SSD) controller system on chip (SoC).

[0037] In some arrangements, the controller may be configured to transfer data from the write buffer to one or more program data buffers and one or more additional data buffers of a first subsystem of the plurality of subsystems. In response to determining that a power failure has not occurred, the controller may configure the first subsystem to program data stored in at least one of the one or more program data buffers or the one or more additional data buffers of the first subsystem of the plurality of subsystems to the NVM of the first subsystem in a first mode. In response to determining that a power failure has occurred, the controller may configure the first subsystem to program data stored in at least one of the one or more program data buffers or the one or more additional data buffers of the first subsystem to the NVM of the first subsystem in a second mode.

[0038] In some arrangements, in response to transferring data from the write buffer to the first data buffer and the second data buffer, the controller may be configured to delete the data from the write buffer. In response to determining that a power failure has occurred, the device may be configured to stop programming in the first mode and then start programming the data stored in the first data buffer to the NVM in the second mode. In response to determining that a power failure has occurred, the controller is configured to program the data stored in the write buffer to the NVM in the second mode while programming the data stored in at least one of the first data buffer or the second data buffer to the NVM in the second mode.

[0039] The arrangement of the present disclosure has at least the following advantages and benefits. First, the arrangement of the present disclosure can provide a useful technique for reducing the size of a write buffer in a storage device. The use of NAND buffers (e.g., P buffers and A buffers) can allow data to be quickly transferred from a controller (e.g., a NAND controller SoC), thereby making the write buffer as small as possible without affecting the I / O write command performance of the storage device. The use of NAND buffers (e.g., P buffers and A buffers) can also allow data to be transferred from the P buffer and A buffer to the pSLC primitives, thereby providing lower power, because there is no need to transfer from the write buffer to the NAND through the NAND controller SoC via an external bus (e.g., NAND bus).

[0040] Second, the arrangement of the present disclosure can provide a useful technique for reducing the energy used to store host in-transit data in a NAND array. First, the use of a P buffer and an A buffer can reduce the size of the write buffer, thereby reducing the energy used to store in-transit host write command data without affecting I / O write command performance. Second, the storage device can program the host in-transit data stored in a NAND buffer (e.g., a P buffer and / or an A buffer) into an empty block in pSLC mode. The pSLC mode programs data significantly faster than other modes (e.g., MLC, TLC, or QLC modes), thereby reducing the energy used to store host in-transit data in a NAND array.

[0041] Figure 3 3 is a block diagram illustrating an example computer system 3000 including a controller SoC 320 and a buffer (e.g., a program buffer, an additional buffer) in a NAND subsystem (e.g., NAND subsystems 380-1, 380-2, ..., 380-N in a NAND array (or NAND device or NAND subsystem) 380) in an SSD 300 according to some arrangements. The computer system 3000 may include a host 20, which may have a connection with the host 20 (see Figure 2) is a configuration similar to that of the host computer 300. SSD 300 is a storage device and can be used as a main storage device of an information processing device (e.g., host 30). SSD 300 can be incorporated into the information processing device or can be connected to the information processing device via a cable or a network. SSD 300 can include DRAM 310 and NAND array (or NAND device) 380. DRAM 310 has a configuration similar to that of DRAM 210. For example, DRAM 310 can include a write buffer 312. NAND array 380 can include multiple subsystems (e.g., NAND subsystems 380-1, 380-2, ..., 380-N; N=16, ..., 128, etc.). Each device may include a corresponding NAND-type flash memory 382-1, 382-2, ..., 382-N, a corresponding program buffer ("P buffer") 384-1, 384-2, ..., 384-N, and a corresponding additional buffer ("A buffer") 386-1, 386-2, ..., 386-N. The corresponding P buffer and the corresponding A buffer may be included in a volatile memory. In some arrangements, each device may include a corresponding processor (e.g., a CPU) and / or a corresponding non-volatile memory (not shown), and the corresponding P buffer and the corresponding A buffer may be included in a corresponding volatile memory. The controller SoC 320 may read data from the NAND array 380 or write data to the NAND array 380 via a NAND bus 390 (e.g., an 8-bit or 16-bit data bus).

[0042] The controller SoC 320 may be a system on chip or an integrated circuit that integrates a NAND controller 320, a memory controller 330, a host I / F controller 340, and a volatile memory including a write buffer 360, wherein each of the NAND controller 320, the memory controller 330, the host I / F controller 340, and the volatile memory including the write buffer 360 may be implemented by a general purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.

[0043] NAND controller 350 can be connected to NAND controller 250 (see Figure 2) functions similarly. For example, similar to NAND controller 250 that respectively performs command control 260, power failure control 252, and flash translation layer (FTL) 270, NAND controller 350 can perform command control 360, power failure control 352, and FTL 370. In some arrangements, NAND controller 350 can be configured to perform buffer control 354 to manage and / or control data buffers (e.g., write buffer 312, write buffer 360, P buffer 384, A buffer 386). Memory controller 330 can be connected to memory controller 230 (see Figure 2 ) functions similarly. The host interface controller 340 may be connected to the host interface controller 240 (see Figure 2 ) works similarly.

[0044] refer to Figure 3, SSD 300 can limit or reduce the size of the write buffer (e.g., write buffer 360 or 312) to reduce the energy used to store in-transit write commands during a power failure (e.g., when a power failure is detected by power failure control 352) without affecting the I / O write command performance of the SSD. SSD 300 can include one or more write buffers (e.g., write buffer 360 or 312) and a NAND controller SoC 320. In some arrangements, most of the one or more write buffers can be located within the NAND controller SoC (e.g., within the write buffer 360) to improve the performance of the SSD. SSD 300 can be a multi-stream (or multi-stream) SSD. NAND subsystems 380-1, 380-2, ..., 380-N in NAND array 380 can include NAND 382 of at least one of the following types: SLC type, MLC type, TLC type, or QLC type. The NAND subsystem may support or maintain at least two data buffers—(1) a program data buffer (P buffer) 384 and (2) an additional data buffer (A buffer) 386. For example, each NAND subsystem may have a 192KB A buffer. If the number of NAND subsystems is 128, the total size of the A buffer will be 24MB. Each NAND subsystem 380-1, 380-2, ..., 380-N may include a corresponding NAND memory 382-1, 382-2, ..., 382-N, corresponding one or more P buffers 384-1, 384-2, ..., 384-N, and corresponding one or more A buffers 386-1, 386-2, ..., 386-N. Each NAND subsystem may be an integrated circuit or chip. The use of the P buffer and the A buffer may allow data to be quickly transferred from the NAND controller SoC 320, thereby making the write buffer 360 or 312 as small as possible without affecting the I / O write command performance of the SSD 300. The use of the P buffer and the A buffer can reduce the size of the write buffer, thereby reducing the energy used to store in-transit host write command data without affecting the I / O write performance.

[0045] In some arrangements, the P buffer (P buffer 384-1) may include multiple P buffers. The A buffer (A buffer 386-1) may include multiple A buffers. The P buffer and the A buffer may form a buffer queue (e.g., a FIFO queue). The P buffer and the A buffer may form a ping-pong buffer (or multi-buffer) so that data in one of the P buffer and the A buffer may be written to the NAND while the other of the P buffer and the A buffer receives data.

[0046] In some arrangements, the SSD 300 (e.g., controller SoC 320, NAND controller 350, command control 360, buffer control 354) may support a "power-off reset" command to immediately stop all programming of the NAND array 380 including multiple NAND subsystems 380-1, 380-2, ..., 380-N. For example, upon receiving the "power-off reset" command, the SSD 300 may stop all programming of the NAND array in SLC mode, MLC mode, TLC mode, or QLC mode. The SSD 300 (e.g., NAND controller 350, command control 360, buffer control 354) may support a "power-off flush" command to trigger or start programming any host in-transit data stored in the P-buffer 384 and / or A-buffer 386 of the NAND subsystem to the NAND memory 382 of the NAND subsystem. For example, upon receiving a "power-off flush" command, the SSD 300 may program (or control each NAND subsystem to program) the host in-transit data stored in the P buffer 384 and / or the A buffer 386 into an empty block in pSLC mode. The pSLC mode programs data significantly faster than other modes (e.g., MLC, TLC, or QLC mode), thereby reducing the energy used to store the host in-transit data in the NAND array 380. The P buffer and / or A buffer of the NAND subsystem may be used to program the data, thereby (1) allowing the controller SoC 320 to not process or transfer the data to the NAND device (or NAND array) 380, and (2) saving energy used to create NAND parity and transfer data to the NAND device 380.

[0047] By adding an A buffer to the NAND subsystem (e.g., each NAND subsystem in a NAND array), and adding additional NAND commands (e.g., “power off reset” followed by “power off flush”), data stored in both the A buffer and the P buffer can be programmed into empty blocks in pSLC mode without having to transfer the data from the write buffers 360, 312 to the NAND devices (or NAND array) 380 across the NAND bus 390 through the controller SoC 320. In this way, the SSD 300 can divide the buffer size (e.g., the size of the write buffer) between (1) the controller 320 and DRAM 310 and (2) the NAND subsystem 380. When there is a power outage (or a power outage is detected), the SSD 300 (e.g., controller SoC 320, NAND controller 350, command control 360, buffer control 354) may allow the controller 320 to immediately stop all programming in the NAND array 380 (in MLC, TLC, or QLC mode) while identifying which data stored in the NAND buffers (e.g., P buffer 384 and / or A buffer 386) is to be programmed in pSLC mode. The data stored in the P buffer and / or A buffer and then programmed in pSLC mode may include host write data and may not include garbage collection data. Immediately stopping an in progress program (in MLC, TLC, or QLC mode) may maximize the amount of data programmed in pSLC mode and is more convenient than an SSD that allows in progress programming to complete and then transfers the remaining data from the controller and / or write buffers in DRAM (e.g., Figure 2 Programming from the internal NAND buffers (e.g., P-buffer and / or A-buffer) can reduce the energy used to store the data compared to SSD 200 in the SSD 200. In some arrangements, when power is restored, SSD 300 (e.g., controller SoC 320, NAND controller 350, command control 360, buffer control 354) can read the data programmed in pSLC mode and write (e.g., reprogram) the data in the original programming mode (e.g., TLC mode).

[0048] In some arrangements, the SSD 300 may transfer data to one of the P-buffer 384 and the A-buffer 386 of the NAND subsystem 380 while running the current NAND programming (e.g., in TLC / QLC mode) in the other of the P-buffer and the A-buffer, thereby maximizing the NAND programming rate and freeing up space in the write buffer in the controller 320 and / or the internal memory (e.g., DRAM 310), which can improve write performance with a small amount or a small size of internal memory. The use of the P-buffer and the A-buffer for each NAND subsystem may have the following effect: the size of the write buffer is automatically increased as the number of NAND subsystems increases. That is, the more NAND subsystems become, the larger the write buffer can be achieved, obtained, or completed by the P-buffer and the A-buffer (in the volatile memory in the NAND subsystem). For example, if the size of the A-buffer is 192KB and the number of NAND subsystems is 128, this may have the effect of increasing the total size of the write buffer by 24MB.

[0049] Figure 4A and Figure 4B is a graph illustrating the performance of a write buffer using a buffer in a NAND subsystem according to some arrangements. Figure 4A shows that in the case of using a storage device (e.g., Figure 3 The performance of the write buffer samples over time when transferring multiple data streams (e.g., 16 streams) for an SSD 300 in FIG. 1 (which uses a NAND buffer (e.g., A buffer) and pSLC programming during power failure). Figure 4A In FIG. 4 , line 401 represents the performance of a write buffer for transmitting independent 16 streams, while line 402 represents the performance of a write buffer for transmitting an aggregate stream that aggregates the 16 streams. Figure 4B shows that in the case of using a storage device (e.g., Figure 3 The performance of the write buffer samples over time when transferring multiple data streams (e.g., 16 streams) for an SSD 300 in FIG. 1 (which does not use a NAND buffer (e.g., A buffer) and does not use pSLC programming during power failure). Figure 4B In FIG. 4 , line 451 represents the performance of a write buffer for transmitting independent 16 streams, while line 452 represents the performance of a write buffer for transmitting an aggregate stream of 16 streams. Figure 4A The performance shown is higher than Figure 4B Shown performance. Figure 4A and Figure 4B The following diagram shows the difference between a smaller write buffer and a storage device that does not use an additional A buffer (see Figure 4B ) by using an additional A buffer in NAND that can effectively increase the size of the write buffer (see Figure 4A ) improves performance. One advantage is that as the number of NAND subsystems increases, the write buffer effectively increases; and the additional NAND subsystems allow for higher write performance without increasing the size of the write buffer in the internal SoC memory. If the buffer in the NAND is not used and the write buffer is only in the internal SoC memory, the size of the internal memory must be designed to the maximum SSD size, which will increase the power and cost of the SoC.

[0050] Figure 5 Flowchart showing an example method of reducing the size of a write buffer (e.g., write buffer 312, 360) using a buffer (e.g., P buffer 384, A buffer 386) in a NAND subsystem (e.g., NAND subsystem 380-1, 380-2, ..., 380-N) according to some arrangements. In this example, the process begins at S502 by transferring data from a write buffer (e.g., write buffer 360, 312) to a first data buffer (e.g., P buffer 384-1, ..., 384-N) and a second data buffer (e.g., A buffer 386-1, ..., 386-N) of a device (e.g., NAND device or NAND array 380) by a controller (e.g., controller SoC 320, NAND controller 350, power failure control 352). In some arrangements, the controller is a solid state drive (SSD) controller system on chip (SoC) (e.g., controller SoC 320). In some arrangements, in response to transferring the data from the write buffer to the first data buffer and the second data buffer, the controller may be configured to delete the data from the write buffer.

[0051] In some arrangements, the device may include multiple subsystems (e.g., NAND subsystems 380-1, 380-2, ..., 380-N), each subsystem including a corresponding NVM (e.g., NAND 382-1, 382-2, ..., 382-N). The first data buffer may include one or more program data buffers (e.g., P buffers 384-1, ..., 384-N) in each of the multiple subsystems. The second data buffer may include one or more additional buffers (e.g., A buffers 386-1, ..., 386-N) in each of the multiple subsystems. In some arrangements, the controller may be configured to transfer data from the write buffer to one or more program data buffers and one or more additional data buffers of a first subsystem of the multiple subsystems.

[0052] In S504 , in some arrangements, the controller (eg, controller SoC 320 , NAND controller 350 , power failure control 352 ) may determine whether a power failure has occurred.

[0053] In S506, in some arrangements, in response to determining that a power failure has not occurred, the controller may configure the device to program data stored in at least one of the first data buffer (e.g., P buffer 384) or the second data buffer (e.g., A buffer 386) to the NVM in a first mode. In some arrangements, the first mode may be at least one of a single-layer cell (SLC) mode, a multi-layer cell (MLC) mode, a triple-layer cell (TLC) mode, or a quad-layer cell (QLC) mode. In some arrangements, in response to determining that a power failure has not occurred, the controller may configure the first subsystem to program data stored in at least one of one or more program data buffers (e.g., P buffer 384-1) or one or more additional data buffers (e.g., A buffer 386-1) of the first subsystem among the plurality of subsystems in the first mode to the NVM (e.g., NAND 382-1) of the first subsystem (e.g., NAND subsystem 380-1).

[0054] In S508, in some arrangements, in response to determining that a power failure has occurred, the controller may configure the device to program data stored in at least one of the first data buffer (e.g., P buffer 384) or the second data buffer (e.g., A buffer 386) to the NVM in a second mode (e.g., pSLC mode) different from the first mode (e.g., SLC / TLC / QLC mode). The second mode may be a pseudo single-layer cell (pSLC) mode. In response to determining that a power failure has occurred, the controller may configure the first subsystem to program data stored in at least one of the one or more program data buffers (e.g., P buffer 384-1) or the one or more additional data buffers (e.g., A buffer 386-1) of the first subsystem in the second mode (e.g., pSLC mode) to the NVM (e.g., NAND 382-1) of the first subsystem (e.g., NAND subsystem 380-1).

[0055] In some arrangements, in response to determining that a power failure has occurred, the device can be configured to stop programming in a first mode and then begin programming the data stored in the first data buffer to the NVM in a second mode (e.g., a "power-off reset" followed by a "power-off flush"). For example, a power-off reset will stop any ongoing TLC / QLC program, while a power-off flush will program any contents of the first data buffer (e.g., P-buffer) and the second data buffer (e.g., A-buffer) to the NAND in pSLC mode. In response to determining that a power failure has occurred, the controller can be configured to program the data stored in the write buffer (e.g., other remaining uncommitted but acknowledged data stored in the write buffer 360) to the NVM in a second mode (e.g., pSLC mode), while programming the data stored in at least one of the first data buffer or the second data buffer (e.g., P-buffer or A-buffer) to the NVM in the second mode.

[0056] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but should be given the full scope consistent with the language claims, wherein unless otherwise specified, references to singular elements are not intended to mean "one and only one", but to "one or more". Unless otherwise specifically stated, the term "some" refers to one or more. All structural and functional equivalents of elements throughout the various aspects described in the previous description that are known or will be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be exclusively disclosed, regardless of whether such disclosure is expressly recorded in the claims. Any claim element is not interpreted as a device plus function unless the element is expressly recorded using the phrase "device for...".

[0057] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an illustrative approach. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged while remaining within the scope of the previous description. The accompanying method claims present elements of the various steps in an example order, and are not meant to be limited to the specific order or hierarchy presented.

[0058] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the disclosed subject matter. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the previous description. Therefore, the previous description is not intended to be limited to the embodiments shown herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

[0059] The various examples illustrated and described are provided as examples only to illustrate the various features of the claims. However, the features shown and described with respect to any given example are not necessarily limited to the associated example, and may be used or combined with other examples shown and described. In addition, the claims are not intended to be limited by any one example.

[0060] The foregoing method descriptions and process flow charts are provided only as illustrative examples and are not intended to require or imply that the steps of the various examples must be performed in the order presented. As will be appreciated by those skilled in the art, the order of the steps in the foregoing examples may be performed in any order. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of the steps; these words are only used to guide the reader through the description of the method. In addition, any reference to a claim element in the singular form, such as the use of the article "a," "an," or "the" should not be construed as limiting the element to the singular.

[0061] The various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the examples disclosed herein may be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. The technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0062] Hardware for implementing the various illustrative logic devices, logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but, in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some steps or methods may be performed by circuits specific to a given function.

[0063] In some exemplary examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. Functions implemented in software may be stored as one or more instructions or codes on a non-transitory computer-readable storage medium or a non-transitory processor-readable storage medium. The steps of the method or algorithm disclosed herein may be embodied in a processor-executable software module, which may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium accessible by a computer or processor. As an example and not limitation, such a non-transitory computer-readable or processor-readable storage medium may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other medium that may be used to store the required program code in the form of an instruction or data structure and accessible by a computer. As used herein, disks and optical disks include compact disks (CDs), laser optical disks, optical optical disks, digital versatile disks (DVDs), floppy disks, and Blu-ray disks, wherein disks typically reproduce data magnetically, and optical disks reproduce data optically using lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and / or instructions on a non-transitory processor-readable storage medium and / or computer-readable storage medium that may be incorporated into a computer program product.

[0064] The previous description of the disclosed examples is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these examples will be apparent to those skilled in the art, and the general principles defined herein may be applied to some examples without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples shown herein, but should be given the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. A system comprising: Controller; Write buffer; as well as A device comprising a non-volatile memory NVM, a first data buffer and a second data buffer, Wherein, the controller is configured as: transferring data from the write buffer to the first data buffer and the second data buffer; Determine if a power failure has occurred; In response to determining that a power failure has not occurred, configuring the device to program data stored in at least one of the first data buffer or the second data buffer to the NVM in a first mode; as well as In response to determining that the power failure has occurred, the device is configured to program data stored in at least one of the first data buffer or the second data buffer to the NVM in a second pattern different from the first pattern.

2. The system according to claim 1, wherein: The first mode is at least one of a single-layer cell SLC mode, a multi-layer cell MLC mode, a triple-layer cell TLC mode, or a quad-layer cell QLC mode.

3. The system according to claim 1, wherein: The second mode is a pseudo single layer cell pSLC mode.

4. The system according to claim 1, wherein: The controller includes the write buffer.

5. The system according to claim 1, wherein: The device includes a plurality of subsystems, each subsystem including a corresponding NVM, The first data buffer includes one or more program data buffers in each of the plurality of subsystems, and The second data buffer includes one or more additional buffers in each of the plurality of subsystems.

6. The system according to claim 5, wherein: The controller is configured to: transferring data from the write buffer to the one or more program data buffers and the one or more additional data buffers of a first subsystem of the plurality of subsystems; In response to determining that the power failure has not occurred, configuring the first subsystem to program data stored in at least one of the one or more program data buffers or the one or more additional data buffers of the first subsystem among the plurality of subsystems to the NVM of the first subsystem in the first mode; as well as In response to determining that the power failure occurs, the first subsystem is configured to program data stored in at least one of the one or more program data buffers or the one or more additional data buffers of the first subsystem to the NVM of the first subsystem in the second mode.

7. The system according to claim 1, wherein: The controller is configured to: In response to transferring the data from the write buffer to the first data buffer and the second data buffer, deleting the data from the write buffer.

8. The system according to claim 1, wherein: In response to determining that the power failure occurs, the apparatus is configured to: The programming in the first mode is stopped, and then the data stored in at least one of the first data buffer or the second data buffer is started to be programmed to the NVM in the second mode.

9. The system according to claim 1, wherein: In response to determining that the power failure occurs, the controller is configured to program the data stored in the write buffer to the NVM in the second mode while programming the data stored in at least one of the first data buffer or the second data buffer to the NVM in the second mode.

10. The system according to claim 1, wherein: The controller is a solid state drive SSD controller system on chip SoC.

11. A method comprising: transferring, by the controller, data from the write buffer to a first data buffer of the device and a second data buffer of the device; determining, by the controller, whether a power failure occurs; In response to determining that a power failure has not occurred, configuring the device, by the controller, to program the data stored in at least one of the first data buffer or the second data buffer to a non-volatile memory NVM of the device in a first mode; as well as In response to determining that the power failure occurs, the device is configured, by the controller, to program data stored in at least one of the first data buffer or the second data buffer to the NVM of the device in a second mode different from the first mode.

12. The method according to claim 11, wherein: The first mode is at least one of a single-layer cell SLC mode, a multi-layer cell MLC mode, a triple-layer cell TLC mode, or a quad-layer cell QLC mode.

13. The method according to claim 11, wherein: The second mode is a pseudo single layer cell pSLC mode.

14. The method according to claim 11, wherein: The controller includes the write buffer.

15. The method according to claim 11, wherein: The device includes a plurality of subsystems, each subsystem including a corresponding NVM, The first data buffer includes one or more program data buffers in each of the plurality of subsystems, and The second data buffer includes one or more additional buffers in each of the plurality of subsystems.

16. The method according to claim 15, further comprising: transferring data from the write buffer to the one or more program data buffers and the one or more additional data buffers of a first subsystem of the plurality of subsystems; In response to determining that the power failure has not occurred, configuring the first subsystem to program data stored in at least one of the one or more program data buffers or the one or more additional data buffers of the first subsystem to the NVM of the first subsystem in the first mode; as well as In response to determining that the power failure occurs, the first subsystem is configured to program data stored in at least one of the one or more program data buffers or the one or more additional data buffers of the first subsystem to the NVM of the first subsystem in the second mode.

17. The method according to claim 11, further comprising: In response to transferring the data from the write buffer to the first data buffer and the second data buffer, deleting the data from the write buffer.

18. The method according to claim 11, further comprising: In response to determining that the power failure occurs, the programming in the first mode is stopped, and then the data stored in at least one of the first data buffer or the second data buffer is started to be programmed to the NVM in the second mode.

19. The method according to claim 11, further comprising: The data stored in the write buffer is programmed to the NVM in the second mode, while the data stored in at least one of the first data buffer or the second data buffer is programmed to the NVM in the second mode.

20. The method according to claim 11, wherein: The controller is a solid state drive SSD controller system on chip SoC.

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