Intelligent throughput router

Abstract

The invention relates to an intelligent throughput router. The memory system may monitor a parameter associated with a received write command. The memory system may select whether to write data to a first block type (e.g., a high density cell block) or a second block type (e.g., a single level cell block) of a non-volatile memory device based on the parameter. The memory system may store data associated with a write command in a volatile storage region, such as a write buffer, and monitor a size of the write buffer. The memory system may select the first block type or the second block type based on a threshold associated with use of the write buffer. The memory system may estimate a throughput of data associated with the write command and select the first block type or the second block type based on a threshold associated with the throughput of the data.

Description

[0001] Cross-reference

[0002] This patent application claims the benefit of priority of U.S. Patent Application No. 18 / 955,713, filed on November 21, 2024, entitled "INTELLIGENT THROUGHPUT ROUTER" by Porzio et al., and U.S. Patent Application No. 63 / 603,551, filed on November 28, 2023, entitled "INTELLIGENT THROUGHPUT ROUTER" by Porzio et al., each of which is assigned to its assignee and each of which is hereby incorporated by reference in its entirety.

[0003] The technical field relates to an intelligent throughput router. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, which are typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states and any one of them can be stored. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) the state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described as being in a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain the stored logical state for an extended period even in the absence of an external power supply. Memory cells configured in a volatile configuration may lose the stored state when disconnected from an external power supply. Summary of the Invention

[0006] Describe a device. The device may include: a controller associated with a memory device, wherein the controller is configured to cause the device to: receive a plurality of write commands for writing data to a non-volatile memory device; monitor parameters associated with the received plurality of write commands; select, at least in part based on monitoring the parameters, to store data associated with the plurality of write commands in a first type of block of the non-volatile memory device; and transfer, at least in part based on selecting to store the data associated with the plurality of write commands, the data associated with the plurality of write commands from a write buffer of a volatile memory device to the first type of block of the non-volatile memory device.

[0007] Describe a non-transitory computer-readable medium storing code. The code may include instructions executable by a processor to: receive a plurality of write commands for writing data to a non-volatile memory device; monitor parameters associated with the received plurality of write commands; select, at least in part based on monitoring the parameters, to store data associated with the plurality of write commands in a first type of block of the non-volatile memory device; and transfer, at least in part based on selecting to store the data associated with the plurality of write commands, the data associated with the plurality of write commands from a write buffer of a volatile memory device to the first type of block of the non-volatile memory device.

[0008] Describe a method. The method may include: receiving a plurality of write commands for writing data to a non-volatile memory device; monitoring parameters associated with the received plurality of write commands; selecting, at least in part based on monitoring the parameters, to store data associated with the plurality of write commands in a first type of block of the non-volatile memory device; and transferring, at least in part based on selecting to store the data associated with the plurality of write commands, the data associated with the plurality of write commands from a write buffer of a volatile memory device to the first type of block of the non-volatile memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Show an example of a system supporting an intelligent throughput router according to an example disclosed herein.

[0010] Figure 2 Show an example of a system supporting an intelligent throughput router according to an example disclosed herein.

[0011] Figure 3 Show an example of a system supporting an intelligent throughput router according to an example disclosed herein.

[0012] Figure 4A block diagram showing a memory system supporting an intelligent throughput router according to an example disclosed herein.

[0013] Figure 5 A flowchart showing one or more methods for supporting an intelligent throughput router according to an example disclosed herein. Detailed Description

[0014] Some memory systems may include a write enhancer mode. The write enhancer mode may allow the memory system to write information faster than in a normal mode (e.g., a non-write enhancer mode). During the write enhancer mode, the memory system may write data to single-level cell (SLC) blocks of a memory device and then move the data to higher density blocks, such as multi-level cells (MLC), triple-level cells (TLC), or quad-level cells (QLC), at a later time (e.g., as part of a background or administrative operation). During normal mode, the memory system may write information to higher density cell blocks (e.g., MLC, TLC, QLC), which may take more time than writing information to SLC blocks. In some cases, the memory device may transfer data from SLC blocks to higher density blocks in response to the memory system entering an idle or sleep mode. Although the write enhancer mode may temporarily improve the speed of write operations, its use may also shorten the life of the memory system at least in part due to an increase in write amplification. Even when operating in a low or idle mode, some memory systems may default to using the write enhancer mode. This situation may further shorten the life of the memory system.

[0015] Describes techniques for improving the use of write booster mode and SLC blocks in a memory system. In some cases, in response to the write booster mode being active, the memory system may monitor parameters associated with a write command received by the memory system. The memory system may select whether to write data to a first block type (e.g., high-density cell block) or a second block type (e.g., single-level cell block) of a non-volatile memory device based on the monitored parameters. In some cases, even when the memory system is not in the write booster mode, the memory system may perform this monitoring and selection. In such cases, the memory system may dynamically select to write to an SLC block to improve the write speed based on the monitored parameters. Some examples of monitored parameters may include the memory system storing data associated with a write command in a volatile storage area such as a write buffer and monitoring the size of the write buffer used. The memory system may select to use the first block type or the second block type based on meeting a threshold associated with the use of the write buffer. Some examples of monitored parameters may include the memory system estimating the throughput of data based on monitoring parameters associated with a write command (e.g., transfer size (i.e., data size)). The memory system may select to use the first block type or the second block type based on meeting a threshold associated with the throughput of the data. By using an SLC block to store data based on meeting various thresholds, write amplification can be reduced and the lifespan of the memory system can be extended.

[0016] First described in the context of systems, apparatuses, and circuits of reference Figure 1 、 2 and 3. These and other features of the present disclosure are further illustrated and described in the context of device diagrams and flowcharts related to the intelligent throughput router of reference Figure 4 and 5 .

[0017] Figure 1 Shows an example of a system 100 supporting an intelligent throughput router according to an example disclosed herein. System 100 includes a host system 105 coupled to a memory system 110. System 100 may be included in a computing device such as a desktop computer, laptop computer, network server, mobile device, vehicle (e.g., train, car, or other transportation vehicle), an Internet of Things (IoT) capable device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or networked commercial device), or any other computing device that includes memory and a processing device.

[0018] The memory system 110 may be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multi-Media Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), and other devices.

[0019] The system 100 may include a host system 105 that may be coupled to the memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to enable the host system 105 to perform various operations in accordance with the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to and read data from the memory system 110. Although Figure 1 one memory system 110 is shown, the host system 105 may be coupled to any number of memory systems 110.

[0020] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of the physical host interface may include, but are not limited to, SATA interface, UFS interface, eMMC interface, PCIe interface, USB interface, Fibre Channel interface, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interface, DIMM interface (e.g., DIMM slot interface supporting DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interface. In some instances, one or more such interfaces may be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some instances, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0021] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cell (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 two memory devices 130-a and 130-b are shown in the example, the memory system 110 may include any number of memory devices 130. Additionally, if the memory system 110 includes more than one memory device 130, the different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0022] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations in accordance with examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130 - and other such operations - which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to perform such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive a command or operation from the host system 105 and may convert the command or operation into an instruction or appropriate command to effect the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to a command from the host system 105 or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may convert a response (e.g., a data packet or other signal) associated with the memory device 130 into a corresponding signal for the host system 105.

[0023] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between a logical address (e.g., a logical block address (LBA)) associated with a command from the host system 105 and a physical address (e.g., a physical block address) associated with memory cells within the memory device 130.

[0024] The memory system controller 115 may include hardware such as, for example, one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard - coded) logic for performing the operations ascribed to the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field - programmable gate array (FPGA), an application - specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0025] Memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that may store operation codes (e.g., executable instructions) that can be executed by memory system controller 115 to perform the functions attributed to memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by memory system controller 115 for internal storage or computations related to, for example, the functions attributed to memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache for memory system controller 115. For example, data may be stored in local memory 120 in the case of reading from or writing to memory device 130, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., update) by host system 105 according to a cache policy (e.g., with reduced latency relative to memory device 130).

[0026] Although Figure 1 the example of memory system 110 in

[0027] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0028] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that may perform operations on one or more memory cells of the corresponding memory device 130. Local controller 135 may operate in conjunction with memory system controller 115 or may perform one or more functions ascribed herein to memory system controller 115. For example, as Figure 1 illustrated, memory device 130-a may include local controller 135-a and memory device 130-b may include local controller 135-b.

[0029] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more dies 160. In some instances, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0030] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as SLC. Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as MLC when configured to each store two bits of information, TLC when configured to each store three bits of information, QLC when configured to each store four bits of information, or more generally as multi-level memory cells. The multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity of the supporting circuitry.

[0031] In some cases, a plane 165 may refer to a number of groups of blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170 as long as the different blocks 170 are in different planes 165. In some cases, an individual block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d that are in planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes that include memory devices 130-a and memory device 130-b). In some cases, the blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, and so on). In some cases, performing concurrent operations on different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0032] In some cases, a block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, the memory cells within the same page 175 may share a common word line (e.g., be coupled to a common word line), and the memory cells within the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., be coupled to a common digit line).

[0033] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at a page granularity level, or a portion thereof) but can be erased at a second granularity level (e.g., at a block granularity level). That is, page 175 can be the smallest unit (e.g., a group of memory cells) of the memory that can be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit (e.g., a group of memory cells) of the memory that can be independently erased (e.g., concurrently erased as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Thus, for example, in some cases, a used page 175 cannot be updated until the entire block 170 containing the page 175 is erased.

[0034] In some cases, memory system 110 can utilize memory system controller 115 to provide a managed memory system, which can include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0035] System 100 can include any number of non-transitory computer-readable media that support an intelligent throughput router. For example, host system 105 (e.g., host system controller 106), memory system 110 (e.g., memory system controller 115), or memory device 130 (e.g., local controller 135) can include or otherwise be accessible to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to host system 105, memory system 110, or memory device 130. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), by memory system 110 (e.g., by memory system controller 115), or by memory device 130 (e.g., by local controller 135), can cause host system 105, memory system 110, or memory device 130 to perform the associated functions as described herein.

[0036] According to the disclosed examples, the use of the write enhancer mode and SLC blocks can be improved in the memory system 110. In response to the write enhancer mode being active, the memory system 110 can monitor parameters associated with write commands received from the host system 105. The memory system 110 can select whether to write data to a first block type (e.g., high-density cell block) or a second block type (e.g., single-level cell block) of the non-volatile memory device included in the memory device 130 based on the monitored parameters. As previously discussed, the memory device 130 can include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof.

[0037] In some examples, the memory system 110 can select to write data to the first block type in response to the second block type being in use. In some cases, these selections can be made when operating in the write enhancer mode. In some cases, these selections can be made when operating in the normal mode. In some examples, the memory system 110 can store data associated with a write command in a volatile memory device (e.g., SRAM) that includes a portion allocated as a write buffer and monitor the size of the write buffer for storing the data. The memory system 110 can select to use the first block type or the second block type based on meeting a threshold associated with the use of the write buffer. In some examples, the memory system 110 can estimate the throughput of the data based on monitoring parameters associated with the write command (e.g., transfer size (i.e., data size)). The memory system 110 can select to use the first block type or the second block type based on meeting a threshold associated with the throughput of the data.

[0038] In addition to its applicability in the memory systems described herein, techniques for intelligent throughput routers can generally be implemented to improve the performance of various electronic devices and systems, including games. Some electronic device applications, including games and other high-performance applications, can be associated with relatively high processing requirements while also benefiting from relatively fast response times to improve the user experience. Thus, there may be a need to increase processing speed, reduce response time, or otherwise improve the performance of the electronic device. Implementing the techniques described herein can improve the performance of the electronic device by storing data in SLC blocks in response to meeting conditions, thereby improving memory access speed, which can reduce latency time, improve response time, or otherwise improve the user experience, among other benefits.

[0039] Figure 2 An example of a system 200 that supports intelligent throughput routing in accordance with an example as disclosed herein is shown. In some examples, system 200 may implement aspects of system 100 illustrated in Figure 1 For example, system 200 may include a host system 205 and a memory system 220, which may be an example of the host system 105 or the memory system 110 as described with reference to Figure 1 or may include aspects of the host system 105 or the memory system 110 as described with reference to Figure 1 The host system 205 may also include a host system controller 210, which may be an example of the host system controller 106 described with reference to Figure 1 System 200 may further include a bus 215 for enabling communication between the host system 205 and the memory system 220.

[0040] The memory system 220 may include a memory system controller 225 for controlling various operations, such as executing commands received from the host system 205, controlling data path components when moving data, etc. The memory system controller 225 may be an example of the memory system controller 115 described with reference to Figure 1 As illustrated in Figure 2 the memory system 220 may include one or more memory devices 230 (only one is shown) for storing data transferred between the memory system 220 and the host system 205. The memory device 230 may include as described with reference to Figure 1One or more volatile and / or non-volatile memory devices as described. For example, memory device 230 may include NAND memory, PCM, self-selecting memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM. For example, data may be transferred to one or more memory devices 230 in response to receiving an access command from host system 205. In some instances, memory system controller 225 may control operations, including but not limited to storing data, retrieving data, determining memory locations for storing / retrieving data, etc. In some instances, memory system controller 225 may communicate directly with memory device 230. In other instances, memory system controller 225 may communicate with memory device 230 via a memory device interface (not shown) using a protocol specific to the type of memory device 230.

[0041] Memory system 220 may include command queue 235 to control access commands received from host system 205 and the processing of data associated with such access commands. In some instances, memory system controller 225 may process access commands passed from host system 205 to memory system 220. Commands may be received via bus 215 according to a protocol (e.g., UFS protocol or eMMC protocol). In some cases, memory system controller 225 may determine, based on communication from bus 215, that an access command has been received, for example. Memory system controller 225 may add commands passed from host system 205 to command queue 235. Memory system 220 may include circuitry 240, a portion of which is configured to process commands passed from command queue 235 via a command path. In some instances, circuitry 240 may be configured to process access commands from command queue 235 and determine whether they include an indication of a write operation. Circuitry 240 may also determine whether memory system 220 is in write enhancer mode. The circuitry may also determine whether to write data to an SLC block or to a higher density cell block.

[0042] The memory system 220 may also include a write buffer 245 that is partially configured to store data associated with commands stored in the command queue 235. The host system 205 may transfer data along with write commands, where the data is to be stored in the memory system 220. In some instances, the write buffer 245 may be part of a local memory (e.g., the local memory 120) and may be used to temporarily store data associated with the commands being processed, thereby reducing the latency between commands and allowing the transfer of any data size (e.g., transfer size) associated with the commands. The write buffer 245 may include relatively fast memory (e.g., volatile memory such as SRAM or DRAM), a hardware accelerator, or both to allow for fast storage and retrieval of data. According to some instances, the write buffer 245 may be part of a larger volatile memory component. For example, the memory system 220 may include SRAM that includes at least one allocated portion configured to operate as the write buffer 245 as illustrated in Figure 2 . In other instances, the memory system 220 may include a dedicated volatile memory device (e.g., the local memory 120) configured as the write buffer 245. The temporary storage of data in the write buffer 245 allows the access commands to be executed with low latency by temporarily storing data associated with some access commands until the data can be moved (or transferred) to the memory device 230. For example, writing to a non-volatile memory device may take longer compared to writing to SRAM or DRAM.

[0043] According to the disclosed instances, the memory system 220 may be configured to support multiple access modes for transferring data from the write buffer 245 to the memory device 230 (e.g., a non-volatile memory device). The access modes may correspond to the block types used to store data in the memory device 230. The memory device 230 may use a first block type 250 to store data from the write buffer 245. The memory device 230 may also use a second block type 255 to store data from the write buffer 245. In some instances, the first block type 250 may be an example of a higher density cell block, such as an MLC block, a TLC block, or a QLC block, and other examples of blocks. For example, two information bits may be written to a corresponding memory cell of the memory device 230 in response to operating in the MLC access mode, three information bits may be written to a corresponding memory cell of the memory device 230 in response to operating in the TLC access mode, and four information bits may be written to a corresponding memory cell of the memory device 230 in response to operating in the QLC access mode. According to the disclosed instances, the term multi-level cell may refer to a block (e.g., an MLC block, a TLC block, a QLC block) that stores two or more information bits in a single memory cell of the memory device 230.

[0044] In some instances, the second block type 255 can be an instance of an SLC block. For example, in response to operating in an SLC access mode, one information bit can be written to a corresponding memory cell of the memory device 230. Access to the SLC block may be relatively faster than that of higher density cell blocks and the error tolerance on the data stored in the SLC block may be relatively greater than that of higher density cell blocks. In additional instances, the first block type 250 can be associated with the SLC access mode, and the second block type 255 can be associated with an MLC, TLC, or QLC access mode. According to various instances, the circuitry 240 can be configured to determine whether to use the first block type 250 or the second block type 255 of the memory device 230 to store data from the write buffer 245. In some cases, the first block type 250 can be designated as the default block type for storing data from the write buffer 245. However, in other cases, the second block type 255 can be designated as the default block type for storing data from the write buffer 245.

[0045] In some instances, the system 200 can be configured to have a default access mode that utilizes a default block type (e.g., the first block type 250). In the default access mode, the memory system 220 can use the first block type 250 to store data from the write buffer 245 to the memory device 230. The system 200 can be configured to transition from the default access mode based on conditions such as, for example, a received command (e.g., write enhancer enabled), data traffic, storage requirements, system performance, a threshold associated with a command queue, a threshold associated with the write buffer, etc. In response to satisfying the conditions, the system 200 can be configured to use the second block type 255 to store data from the write buffer 245 to the memory device 230.

[0046] According to the disclosed examples, the host system 205 may indicate an access mode of the memory system 220. For example, the host system 205 may include a write enhancer component. The host system 205 may initiate the write enhancer component by transmitting one or more commands for one or more operations to the memory system 220. Additionally or alternatively, the host system 205 may transmit a write enhancer signal to the memory system 220. In some examples, the write enhancer signal may provide an indication as to whether the memory system 220 is going to perform an access operation (e.g., transfer data from the write buffer 245) using a first block type 250 or a second block type 255. As an illustrative example, if the write enhancer is deactivated (e.g., the host device transmits a signal indicating deactivation of the write enhancer), then the memory device 230 may use the first block type 250 (e.g., a higher density cell block) to transfer data from the write buffer 245. As another example, if the write enhancer is activated (e.g., the host device transmits a signal indicating activation of the write enhancer), then the memory device 230 may use the second block type 255 (e.g., an SLC block) to transfer data from the write buffer 245.

[0047] In some memory systems, determining whether to write data to a first block type 250 (e.g., a higher density cell block) or a second block type 255 (e.g., an SLC block) is based on whether the write enhancer mode is enabled or disabled. If the write enhancer mode is activated, then data is initially written to the second block type 255 (e.g., an SLC block). If the write enhancer mode is deactivated, then data is initially written to the first block type 250 (e.g., a higher density cell block). The write enhancer mode includes initially writing to an SLC block to reduce the time spent initially writing data into the memory device 230, and then folding the data into a higher density cell block at a later time as part of a media management operation. Such procedures may increase the write amplification of the memory system 220 and may shorten the overall lifespan of the memory system 220 (compared to writing into a higher density cell block) because a higher amount of writes are performed in response to received host commands. Some host systems may overuse the write enhancer mode (e.g., even when there is little performance benefit from using the write enhancer mode) and thereby shorten the lifespan of the memory system 220. Other host systems may underuse the write enhancer mode (e.g., resulting in performance latency in writing data). Techniques are described for enabling the memory system 220 to monitor parameters associated with the memory system 220 and dynamically select whether to write data to an SLC block or a higher density cell block. In some cases, such techniques may be used as part of operating the write enhancer mode. In some cases, such techniques may be used in response to deactivating the write enhancer mode.

[0048] System 200 can identify a block type (e.g., first block type 250 or second block type 255) for storing data into the memory device 230 based on various conditions. In some instances, the circuitry 240 can monitor parameters associated with a write command received from the host system 205. The circuitry 240 can monitor the size of the write buffer 245 that is used to store data associated with the write command relative to the total size of the write buffer 245. In other words, the portion of the write buffer 245 that is currently used to store data. In some instances, the circuitry 240 can select the block type for storing data based at least in part on determining that a threshold size of the write buffer 245 has been met. Depending on the particular type of the memory device 230, the threshold can be based on a percentage of the total size of the write buffer 245. The threshold can also be based on a specific amount, e.g., 256K, 384K, 512K, etc.

[0049] In some instances, the memory system 220 can operate in a mode where the first block type 250 is used to store data, and the first block type 250 indicates an MLC, TLC, or QLC access mode. The circuitry 240 can determine that the threshold has been met and transmit a signal indicating this state. The signal can provide an indication of the block type to be used for storing subsequent data. For example, the signal can indicate that the second block type 255 will be used to store data. The second block type 255 can indicate an SLC access mode that can provide improved performance (e.g., improved speed) for write operations. Thus, the memory device 230 can transition from storing data using the first block type 250 to storing data using the second block type 255.

[0050] The techniques described herein are related to using the utilization of a write buffer to trigger whether to write to a higher density cell block or an SLC block. The present invention provides a technique for determining whether the first block type 250 (e.g., higher density cell block) or the second block type 255 (e.g., SLC block) will be used to write data in response to enabling a write enhancer mode. Such techniques involve monitoring the utilization of the write buffer 245 of the memory system 220. When a write command is received, the memory system 220 can temporarily store the data in the write buffer 245. The circuitry 240 can monitor the utilization of the write buffer 245 and determine whether to use the first block type 250 (e.g., higher density cell block) or the second block type 255 (e.g., SLC block) to write the data.

[0051] In some instances of monitoring the utilization of write buffer 245, memory system 220 may determine whether write buffer 245 can be emptied before the next data packet from host system 205 arrives. In such instances, memory system 220 may store data in memory device 230 using first block type 250 (e.g., higher density cell block). Such a situation may mean that there is little performance benefit in initially writing data into second block type 255 (e.g., SLC block). In such cases, memory system 220 may determine to write data into first block type 250 (e.g., higher density cell block) to reduce write amplification. However, if write buffer 245 cannot be emptied before memory system 220 stores the next data from host system 205, then memory system 220 may determine to store data in second block type 255 (e.g., SLC block).

[0052] When transitioning to using second block type 255 (e.g., SLC block), memory system 220 may use second block type 255 until an exit condition is recognized. Examples of exit conditions include memory system 220 determining that it is operating in an idle mode (e.g., detecting that memory system 220 is in an idle time). In such cases, memory system 220 may fallback to using first block type 250 (e.g., higher density cell block) to store data in memory device 230 for the next write stream. Being in the idle mode may indicate that write buffer 245 is empty or almost empty. Another example of an exit condition may include memory system 220 determining whether the information stored in write buffer 245 meets a threshold (e.g., below a threshold amount). In such cases, memory system 220 may fallback to using first block type 250 (e.g., higher density cell block) to store data in memory device 230 for the next write stream. Being in the idle mode may indicate that command queue 235 is empty. Another example of an exit condition may include memory system 220 determining whether the number of commands in command queue 235 meets a threshold (e.g., below a threshold amount). In such cases, memory system 220 may fallback to using first block type 250 (e.g., higher density cell block) to store data in memory device 230 for the next write stream.

[0053] In some instances, circuit system 240 may determine that memory device 230 is in an idle mode. Additionally or alternatively, circuit system 240 may further determine information regarding the size or content of command queue 235. For example, the circuit system may determine that command queue 235 is empty or contains write commands at a low threshold (e.g., 5, 10, 20, etc.). Circuit system 240 may determine that memory device 230 is idle and / or the command queue is empty or meets the low threshold. Based on this determination, circuit system 240 may provide an indication that a transition will be made to use first block type 250 to store data. Accordingly, memory device 230 may transition from storing data using second block type 255 to storing data using first block type 250.

[0054] As previously discussed, system 200 may be configured to operate in a write enhancer mode. The write enhancer mode may be initiated (e.g., enabled) by host system 205. For example, host system 205 may transmit one or more commands for operations that require the write enhancer mode to memory system 220 via bus 215. Additionally or alternatively, host system 205 may transmit a write enhancer signal to memory system 220. If the write enhancer mode is initiated, then circuit system 240 may provide an indication that second block type 255 (e.g., SLC access mode) will be used to store data. Accordingly, memory device 230 may transition from storing data using first block type 250 to storing data using second block type 255. In some instances, memory device 230 may already be using second block type 255 and thus may not need to transition.

[0055] In some instances, circuit system 240 may also adjust the size of write buffer 245 based on whether data is being written to a first block type 250 or a second block type 255. If the blocks contain a fixed number of memory cells, then a TLC block may be able to store three times as much data as an SLC block because each memory cell in a TLC block stores three data bits instead of one. In such a case, write buffer 245 may be able to be smaller in response to writing data into an SLC block because less buffering is used between receiving data from host system 205 and writing the data into memory device 230. In addition to determining whether to use a higher density cell block or an SLC block, circuit system 240 may also use a second threshold to determine whether to change the size of write buffer 245. For example, circuit system 240 may determine a threshold to be 384K and a second threshold to be 448K (i.e., 384K + 64K). Circuit system 240 may wait until it is determined that the first threshold and / or the second threshold has been met before indicating that the second block type 255 will be used to store data. According to the examples disclosed herein, the threshold and the second threshold may be fixed or selected based on storage requirements, system performance, data traffic, cyclic (e.g., time of day, hourly, daily, weekly, etc.) usage patterns, and the like. In some cases, host system 205 may select the threshold or the second threshold or both. Memory device 230 may change from storing data using the first block type 250 to storing data using the second block type 255 in response to circuit system 240 determining that the threshold, the second threshold, or both have been met.

[0056] According to the examples disclosed herein, circuit system 240 may continue to monitor the parameters associated with the write command and the size of write buffer 245. Circuit system 240 may further determine that a third threshold has been met. In some instances, the third threshold may be less than the threshold. As previously discussed, writing to the second block type 255 may cause data from write buffer 245 to be transferred to memory device 230 faster than writing to a higher density cell block. Therefore, the size of write buffer 245 used to store data may be reduced when using the second block type 255. Accordingly, the third threshold may indicate a reduction in the size of write buffer 245. Circuit system 240 may determine that the third threshold has been met and provide an indication of the block type to be used to store subsequent data. For example, circuit system 240 may provide an indication to change back to using the first block type 250 to store data. Accordingly, memory device 230 may change from storing data using the second block type 255 to storing data using the first block type 250.

[0057] Some benefits of such techniques may include improving the total bytes written (TBW) of memory system 220, improving latency quality of service (QoS) management, and reducing battery consumption. By writing more content to the first block type 250 (e.g., higher density cell block) without using the second block type 255 (e.g., SLC block), even in response to being in the write enhancer mode, memory system 220 can reduce its use of the second block type 255 (e.g., SLC block), thereby improving the overall TBW statistics. Additionally, since memory system 220 can fold less data from the second block type 255 (e.g., SLC block) into the first block type 250 (e.g., higher density cell block), such techniques can result in fewer media management operations that may affect the performance of executing commands from host system 205. For example, memory system 220 can transfer data from the second block type 255 (e.g., SLC block) to the first block type 250 (e.g., higher density cell block) during periods of lower utilization. However, if host system 205 sends multiple commands while memory system 220 is performing these transfers, it may increase the latency incurred by memory system 220 in executing commands from host system 205. Thus, such techniques can have a smaller impact on incoming write traffic and can improve latency QoS management. Additionally, reducing the number of write operations to the second block type 255 and the associated folding activities can cause memory system 220 to consume less energy, thereby improving battery life.

[0058] Figure 3 An example of a system 300 that supports intelligent throughput routing in accordance with an example as disclosed herein is shown. In some examples, system 300 may implement Figure 1 aspects of system 100 illustrated in. For example, system 300 may include a host system 305 and a memory system 320, which may be an example of host system 105 or memory system 110 as described with reference to Figure 1 or may include aspects of host system 105 or memory system 110 as described with reference to Figure 1 Host system 305 may further include a host system controller 310, which may be an example of host system controller 106 as described with reference to Figure 1 System 300 may further include a bus 315 for enabling communication between host system 305 and memory system 320.

[0059] Memory system 320 may include a memory system controller 325 for controlling various operations (e.g., executing commands received from host system 305, controlling data path components when moving data, etc.). Memory system controller 325 may be an example of memory system controller 115 as described with reference to Figure 1 As Figure 3As described, the memory system 320 may include one or more memory devices 330 (only one is shown) for storing data transferred between the memory system 320 and the host system 305. The memory device 330 may include one or more volatile and / or non-volatile memory devices as described with reference to Figure 1 For example, the memory device 330 may include NAND memory, PCM, self-selecting memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM. For example, in response to receiving an access command from the host system 305, data may be passed to the one or more memory devices 330. In some instances, the memory system controller 325 may control operations including but not limited to storing data, retrieving data, determining the memory location for storing / retrieving data, etc. In some instances, the memory system controller 325 may communicate directly with the memory device 330. In other instances, the memory system controller 325 may communicate with the memory device 330 via a memory device interface (not shown) using a protocol specific to the type of the memory device 330.

[0060] The memory system 320 may include a command queue 335 to control the processing of access commands received from the host system 305 and data associated with such access commands. In some instances, the memory system controller 325 may determine whether an access command has been received based on communication from the bus 315 and add the received access command to the command queue 335. The memory system 320 may include a throughput detector 348 configured in part to monitor the throughput of commands in the command queue 335. The throughput detector 348 may be configured to monitor access commands from the command queue 335, determine whether they include an indication of a write operation, and identify the transfer size of data associated with the write operation.

[0061] The memory system 320 may also include a write buffer 345 configured in part to store data transferred from the command queue 335 via a data path. In some instances, the write buffer 345 may be used to temporarily store data while processing commands, thereby reducing the latency between commands and allowing the movement of any data size associated with the commands. The write buffer 345 may include relatively fast memory (e.g., some types of volatile memory such as SRAM or DRAM), a hardware accelerator, or both to allow for fast storage and retrieval of data. According to some instances, the write buffer 345 may be part of a larger volatile memory component. For example, the memory system 320 may include including configured to act as Figure 3SRAM for at least an allocation portion of the write buffer 345 operations as described. In other instances, the memory system 320 may include a dedicated volatile memory chip configured as the write buffer 345.

[0062] System 300 may be an example of a controller-based solution for determining whether to use a first block type 350 or a second block type 355. System 300 may include a block type selector 340 and a throughput detector 348. In some instances, the throughput detector 348 may monitor the content of the command queue 335 to determine the throughput of data associated with received write commands. For example, the throughput detector 348 may examine the commands in the command queue 335 to determine whether they are associated with write access operations (e.g., write commands). The throughput detector 348 may further determine the transfer size associated with each write command. For example, the throughput detector 348 may determine that a write command is associated with a transfer block of 4K, 16K, 32K, 64K, etc. In some instances, the throughput detector 348 may determine the throughput (or amount) of data to be written within a certain time interval. The time interval may be selected based on various factors including the type of the memory device 330, the number of write commands contained in the command queue 335, etc. According to at least one instance, the throughput detector 348 may determine the throughput based on Equation 1.

[0063]

[0064] In Equation 1, WriteTransferSize(i) is the size of the data block associated with each write command, T is the selected time interval, and t is the current time.

[0065] The throughput detector 348 may determine whether the amount of data associated with the write commands currently in the command queue 335 is at a high level or a low level based on the estimated throughput value. The throughput detector 348 may provide an indication of the level (e.g., high or low) to the block type selector 340. The block type selector 340 may select the first block type 350 or the second block type 355 to store the data from the write buffer 345.

[0066] In some instances, the memory system 320 may operate in a mode where the first block type 350 is used to store data from the write buffer 345. The first block type 350 may indicate an MLC, TLC, or QLC access mode. The throughput detector 348 may determine that the throughput (e.g., estimated throughput) of the data associated with the write commands in the command queue 335 is at a high level. In some instances, the throughput detector 348 may determine whether the throughput is at a high level or a low level based on meeting a threshold. The throughput detector 348 may provide an appropriate indication to the block type selector 340. The block type selector 340 may select a second block type 355 for storing data into the memory device 330 based on the indication from the throughput detector 348. In such instances, the second block type 355 may indicate an SLC access mode that can provide improved performance for write operations. Thus, the memory device 330 may transition from storing data using the first block type 350 to storing data using the second block type 355.

[0067] The throughput detector 348 may continue to monitor parameters associated with the write commands in the command queue 335, such as the throughput of the data. The throughput detector 348 may further determine that the throughput level no longer meets the threshold (e.g., the throughput level is below the threshold). Thus, the throughput detector 348 may determine that the throughput is at a low level and provide an appropriate indication to the block type selector 340. The block type selector 340 may select the first block type 350 (e.g., MLC, TLC, or QLC access mode) for storing data into the memory device 330 based on the indication from the throughput detector 348. Thus, the memory device 330 may transition from storing data using the second block type 355 to storing data using the first block type 350.

[0068] In some instances, the throughput detector 348 may further examine the transfer sizes associated with one or more write commands. If a threshold number of write commands have transfer sizes that exceed a set value (64K, 128K, etc.), then the throughput detector 348 may provide an indication of high-level throughput to the block type selector 340. In some instances, the throughput detector 348 may provide an indication of high-level throughput based on the throughput (e.g., estimated throughput) of the data associated with the write commands over an interval and the transfer sizes associated with the write commands exceeding the set value.

[0069] In some instances, throughput detector 348 may estimate the throughput capacity of memory system 320. In operation, if the estimated throughput value is within the throughput capacity of a first block type 350 (e.g., a higher density cell block), then throughput detector 348 may indicate to block type selector 340 to use the first block type 350 (e.g., a higher density cell block) to store write data. On the other hand, if the estimated throughput value is higher than the throughput capacity of the first block type 350 (e.g., a higher density cell block), then throughput detector 348 may indicate to block type selector 340 to use a second block type 355 (e.g., an SLC block) to store write traffic. In some cases, throughput detector 348 may also determine whether to enable or disable a write enhancer mode. In some instances of such cases, throughput detector 348 may be configured to make these determinations in response to enabling the write enhancer mode. In some instances of such cases, throughput detector 348 may be configured to make these determinations whether the write enhancer mode is enabled or disabled.

[0070] Figure 4 FIG. 400 is a block diagram showing a memory system 420 supporting an intelligent throughput router in accordance with an example as disclosed herein. Memory system 420 may be an example of aspects of a memory system as described with reference to Figures 1 to 3 Memory system 420 or its various components may be examples of components for performing various aspects of the intelligent throughput router as described herein. For example, memory system 420 may include a bus interface 425, a command monitoring component 430, a block type selection component 435, a write circuitry 440, a command storage component 445, a throughput monitoring component 450, a write enhancer component 455, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0071] Bus interface 425 may be configured to or otherwise support components for receiving a plurality of write commands for writing data to a non-volatile memory device. Command monitoring component 430 may be configured to or otherwise support components for monitoring parameters associated with the received plurality of write commands. Block type selection component 435 may be configured to or otherwise support components for selecting a first type of block in the non-volatile memory device to store data associated with the plurality of write commands based at least in part on the monitored parameters. Write circuitry 440 may be configured to or otherwise support components for transferring data associated with the plurality of write commands from a write buffer of a volatile memory device to the first type of block in the non-volatile memory device based at least in part on the selection to store the data associated with the plurality of write commands.

[0072] In some instances, the block type selection component 435 may be configured to or otherwise support components for transitioning from writing data to a first type of block of the non-volatile memory device to writing data to a second type of block of the non-volatile memory device at least in part based on monitoring parameters associated with multiple write commands.

[0073] In some instances, the block type selection component 435 may be configured to or otherwise support components for transitioning from writing data to a second type of block of the non-volatile memory device to writing data to a first type of block of the non-volatile memory device at least in part based on monitoring parameters associated with multiple write commands.

[0074] In some instances, to support transferring data associated with multiple write commands, the command storage component 445 may be configured to or otherwise support components for storing data into a write buffer of a volatile memory device.

[0075] In some instances, the first type of block of the non-volatile memory device includes a multi-level cell block, a triple-level cell block, or a quadruple-level cell block. In some instances, the second type of block of the non-volatile memory device includes a single-level cell block.

[0076] In some instances, the first type of block of the non-volatile memory device includes a single-level cell block. In some instances, the second type of block of the non-volatile memory device includes a multi-level cell block, a triple-level cell block, or a quadruple-level cell block.

[0077] In some instances, to support monitoring parameters associated with multiple write commands, the throughput monitoring component 450 may be configured to or otherwise support components for determining the throughput of data associated with multiple write commands within a certain time interval, where selecting to store data associated with multiple write commands is at least in part based on the throughput of data associated with multiple write commands within the time interval meeting a threshold.

[0078] In some instances, the throughput of data is at least in part based on the transfer size associated with each of the multiple write commands.

[0079] In some instances, to support selecting to store data associated with multiple write commands, the command monitoring component 430 may be configured to or otherwise support components for transitioning from a first type of block to a second type of block or from a second type of block to a first type of block at least in part based on the throughput of data associated with multiple write commands within the time interval meeting a second threshold.

[0080] In some instances, to support monitoring parameters associated with multiple received write commands, the command monitoring component 430 may be configured to or otherwise support components for determining the size of a write buffer for storing data associated with multiple write commands, where the selection to store data associated with multiple write commands is at least partially based on the size of the write buffer for storing data meeting a threshold.

[0081] In some instances, the command monitoring component 430 may be configured to or otherwise support components for selecting to store data associated with multiple write commands at least partially based on the size of a write buffer for storing data exceeding a second threshold greater than the threshold.

[0082] In some instances, the block type selection component 435 may be configured to or otherwise support components for transitioning from a first type of block to a second type of block or from a second type of block to a first type of block at least partially based on the size of a write buffer for storing data meeting a third threshold.

[0083] In some instances, to support monitoring parameters associated with multiple received write commands, the command monitoring component 430 may be configured to or otherwise support components for determining whether a non - volatile memory device is in an idle mode. In some instances, to support monitoring parameters associated with multiple received write commands, the command monitoring component 430 may be configured to or otherwise support components for determining whether a command queue associated with a write buffer is free of multiple write commands, where the selection to store data in a first type of block is at least partially based on determining whether the non - volatile memory device is in an idle mode and determining whether the write buffer is empty.

[0084] In some instances, the command monitoring component 430 may be configured to or otherwise support components for determining whether a command queue meets a threshold, where the selection to store data in a first type of block is at least partially based on determining whether the command queue meets the threshold.

[0085] In some instances, the block type selection component 435 may be configured to or otherwise support components for determining whether the amount of data in a write buffer meets a threshold, where the selection to store data in a first type of block is at least partially based on determining whether the amount of data in the write buffer meets the threshold.

[0086] In some instances, the write enhancer component 455 may be configured to or otherwise support components for initiating a write enhancer mode of a non - volatile memory device, where monitoring parameters are at least partially based on initiating the write enhancer mode.

[0087] Figure 5FIG. 0 shows a flowchart of a method 500 for supporting an intelligent throughput router according to an example as disclosed herein. Operations of method 500 may be implemented by a memory system or components thereof as described herein. For example, operations of method 500 may be performed by a memory system as described with reference to Figures 1 to 4 The memory system described. In some examples, the memory system may execute a set of instructions to control functional elements of a device to perform the described functions. Additionally or alternatively, a wireless memory system may use dedicated hardware to perform aspects of the described functions.

[0088] At 505, the method may include receiving a plurality of write commands for writing data to a non-volatile memory device. Operations of 505 may be performed according to an example as disclosed herein. In some examples, aspects of operations of 505 may be performed by a bus interface 425 as described with reference to Figure 4 The bus interface 425 described.

[0089] At 510, the method may include monitoring parameters associated with the received plurality of write commands. Operations of 510 may be performed according to an example as disclosed herein. In some examples, aspects of operations of 510 may be performed by a command monitoring component 430 as described with reference to Figure 4 The command monitoring component 430 described.

[0090] At 515, the method may include selecting to store data associated with the plurality of write commands in a first type of block of the non-volatile memory device at least in part based on the monitored parameters. Operations of 515 may be performed according to an example as disclosed herein. In some examples, aspects of operations of 515 may be performed by a block type selection component 435 as described with reference to Figure 4 The block type selection component 435 described.

[0091] At 520, the method may include transferring data associated with the plurality of write commands from a write buffer of the volatile memory device to the first type of block of the non-volatile memory device at least in part based on the selection to store the data associated with the plurality of write commands. Operations of 520 may be performed according to an example as disclosed herein. In some examples, aspects of operations of 520 may be performed by a write circuitry 440 as described with reference to Figure 4 The write circuitry 440 described.

[0092] In some examples, a device as described herein may execute one or several methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0093] Aspect 1: A method, apparatus, or non-transitory computer-readable medium that includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a plurality of write commands for writing data to a non-volatile memory device; monitoring parameters associated with the received plurality of write commands; selecting, at least in part based on monitoring the parameters, to store the data associated with the plurality of write commands in a first type of block of the non-volatile memory device; and transferring, at least in part based on selecting to store the data associated with the plurality of write commands, the data associated with the plurality of write commands from a write buffer of a volatile memory device to the first type of block of the non-volatile memory device.

[0094] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for transitioning, at least in part based on monitoring the parameters associated with the plurality of write commands, from writing the data to the first type of block of the non-volatile memory device to writing the data to a second type of block of the non-volatile memory device.

[0095] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 2, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for transitioning, at least in part based on monitoring the parameters associated with the plurality of write commands, from writing the data to the second type of block of the non-volatile memory device to writing the data to the first type of block of the non-volatile memory device.

[0096] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, wherein transferring the data associated with the plurality of write commands further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for storing the data in the write buffer of the volatile memory device.

[0097] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, wherein the first type of block of the non-volatile memory device includes a multi-level cell block, a triple-level cell block, or a quadruple-level cell block and the second type of block of the non-volatile memory device includes a single-level cell block.

[0098] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, wherein the first type of block of the non-volatile memory device comprises single-level cell blocks and the second type of block of the non-volatile memory device comprises multi-level cell blocks, triple-level cell blocks, or quadruple-level cell blocks.

[0099] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, wherein monitoring the parameter associated with the plurality of write commands further comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for determining a throughput of the data associated with the plurality of write commands over a time interval, wherein selecting to store the data associated with the plurality of write commands is at least partially based on the throughput of the data associated with the plurality of write commands over the time interval meeting a threshold.

[0100] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to Aspect 7, wherein the throughput of the data is at least partially based on a transfer size associated with each of the plurality of write commands.

[0101] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 7 to 8, wherein selecting to store the data associated with the plurality of write commands further comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for transitioning from the first type of block to the second type of block or from the second type of block to the first type of block at least partially based on the throughput of the data associated with the plurality of write commands over the time interval meeting a second threshold.

[0102] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, wherein monitoring the parameter associated with the received plurality of write commands further comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for determining a size of a write buffer for storing the data associated with the plurality of write commands, wherein selecting to store the data associated with the plurality of write commands is at least partially based on the size of the write buffer for storing the data meeting a threshold.

[0103] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to Aspect 10, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for selecting to store the data associated with the plurality of write commands at least partially based on the size of the write buffer for storing the data exceeding a second threshold greater than the threshold.

[0104] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 10 to 11, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for transitioning from the first type of block to the second type of block or from the second type of block to the first type of block at least in part based on the size of the write buffer used to store the data satisfying a third threshold.

[0105] Aspect 13: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 12, wherein monitoring the parameters associated with the plurality of received write commands further comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for determining whether the non-volatile memory device is in an idle mode and determining whether the command queue associated with the write buffer is free of the plurality of write commands, wherein selecting to store the data in the first type of block is at least in part based on determining whether the non-volatile memory device is in the idle mode and determining whether the write buffer is empty.

[0106] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to aspect 13, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for determining whether the command queue satisfies a threshold, wherein selecting to store the data in the first type of block is at least in part based on determining whether the command queue satisfies the threshold.

[0107] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 14, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for determining whether the amount of data in the write buffer satisfies a threshold, wherein selecting to store the data in the first type of block is at least in part based on determining whether the amount of data in the write buffer satisfies the threshold.

[0108] Aspect 16: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 15, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for initiating a write enhancer mode of the non-volatile memory device, wherein monitoring the parameters is at least in part based on initiating the write enhancer mode.

[0109] Note that the described techniques include possible embodiments, and the operations and steps may be rearranged or otherwise modified and other embodiments are possible. Additionally, portions from two or more of the methods may be combined.

[0110] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0111] The terms "electrically connected", "electrically contacting", "connected", and "coupled" may refer to the relationship between components that supports the flow of signals between the components. Components are considered to be electrically connected (or electrically contacting or connected or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device that includes the connected components, the conductive path between components that are electrically connected (or electrically contacting or connected or coupled to each other) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some instances, the flow of signals between the connected components may be interrupted for a period of time using, for example, one or more intermediate components (such as switches or transistors).

[0112] The term "coupled" (e.g., "electrically coupled") may refer to a state that moves from an open-circuit relationship between components (where signals cannot currently be passed between the components through the conductive path) to a closed-circuit relationship between components (where signals can be passed between the components through the conductive path). If a component, such as a controller, couples other components together, then the component causes a change that allows signals to flow between the other components through a conductive path that previously did not permit signal flow.

[0113] The term "isolated" refers to the relationship between components where signals cannot currently flow between the components. If there is an open circuit between the components, then the components are isolated from each other. For example, if a switch located between two components is open, then the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents signals from flowing between the components through a conductive path that previously permitted signal flow.

[0114] The terms "if", "when", "based on", or "at least partially based on" may be used interchangeably. In some instances, the terms may be interchangeable if the terms "if", "when", "based on", or "at least partially based on" are used to describe the connection between conditional actions, conditional processes, or parts of a process.

[0115] The term "in response to" can refer to a condition or action that occurs at least in part (if not entirely) as a result of a previous condition or action. For example, a first condition or action can be performed and a second condition or action can occur at least in part as a result of the previous condition or action occurring (whether occurring immediately after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0116] Additionally, the term "directly in response to" can refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action can be performed and a second condition or action can occur directly as a result of the previous condition or action occurring, regardless of whether other conditions or actions occur. In some instances, a first condition or action can be performed and a second condition or action can occur directly as a result of the previous condition or action occurring such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on", "at least in part based on", or "in response to" some other step, action, event, or condition can additionally or alternatively (e.g., in an alternative instance) be performed "directly in response to" this other condition or action.

[0117] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical species (including but not limited to phosphorus, boron, or arsenic). The doping can be performed by ion implantation or by any other doping means during the initial formation or growth of the substrate.

[0118] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be “on” or “activated”. If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be “off” or “deactivated”.

[0119] The description set forth herein in connection with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or that are within the scope of the claims. The term “exemplary” as used herein is intended to mean “serving as an example, instance, or illustration” and not “preferred” or “advantageous over other examples”. The detailed description includes specific details for providing an understanding of the described technology. However, the technology may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0120] In the figures, like components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that differentiates among the like components. If only the first reference label is used in the specification, the description applies to any one of the like components having the same first reference label regardless of the second reference label.

[0121] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described may be implemented using software, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located in various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0122] For example, various illustrative blocks and components described in connection with the present disclosure may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0123] As used herein, including in the claims, the term "or" as used in a list of items (e.g., a list of items prefaced by phrases such as "at least one of..." or "one or more of...") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0124] Computer-readable media includes both non-transitory computer storage media and communication media, where the communication media includes any media that facilitates transfer of a computer program from one place to another. The non-transitory storage media may be any available media that can be accessed by a general or special purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code instructions or data structures in the form of and that can be accessed by a general or special purpose computer or a general or special purpose processor. Also, any connection is properly termed a computer-readable media. For example, if software is transmitted using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave from a website, server, or other remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0125] The description provided herein enables a person of ordinary skill in the art to make or use the present disclosure. Those of ordinary skill in the art will understand various modifications to the present disclosure, and the general principles defined herein can be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a controller associated with the memory device, wherein the controller is configured to cause the apparatus to: receiving a plurality of write commands for writing data to a non-volatile memory device; monitoring parameters associated with the plurality of received write commands; selecting to store data associated with the plurality of write commands in a first type of block of the non-volatile memory device based at least in part on monitoring the parameter; and The data associated with the plurality of write commands is transferred from a write buffer of a volatile memory device to the first type of block of the non-volatile memory device based at least in part on selecting to store the data associated with the plurality of write commands.

2. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: Transitioning from writing the data to the first type of blocks of the nonvolatile memory device to writing the data to a second type of blocks of the nonvolatile memory device based at least in part on monitoring the parameters associated with the plurality of write commands.

3. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: Transitioning from writing the data to a second type of block of the nonvolatile memory device to writing the data to the first type of block of the nonvolatile memory device is based at least in part on monitoring the parameter associated with the plurality of write commands.

4. The apparatus of claim 1 , wherein transmitting the data associated with the plurality of write commands is further configured to cause the apparatus to: The data is stored to the write buffer of the volatile memory device.

5. The apparatus of claim 1, wherein: The first type block of the nonvolatile memory device comprises a multi-level cell block, a three-level cell block or a four-level cell block; and The second type block of the nonvolatile memory device includes a single level cell block.

6. The apparatus of claim 1, wherein: The first type block of the non-volatile memory device comprises a single level cell block; and The second type block of the nonvolatile memory device includes a multi-level cell block, a three-level cell block, or a four-level cell block.

7. The apparatus of claim 1 , wherein monitoring the parameters associated with the plurality of write commands is further configured to cause the apparatus to: A throughput of the data associated with the plurality of write commands within a time interval is determined, wherein selecting to store the data associated with the plurality of write commands is based at least in part on the throughput of the data associated with the plurality of write commands within the time interval satisfying a threshold.

8. The apparatus of claim 7, wherein the throughput of the data is based at least in part on a transfer size associated with each of the plurality of write commands.

9. The apparatus of claim 7, wherein selecting to store the data associated with the plurality of write commands is further configured to cause the apparatus to: Transitioning from the first type of block to the second type of block or from the second type of block to the first type of block based at least in part on the throughput of the data associated with the plurality of write commands within the time interval satisfying a second threshold.

10. The apparatus of claim 1, wherein monitoring the parameters associated with the received plurality of write commands is further configured to cause the apparatus to: A size of the write buffer for storing the data associated with the plurality of write commands is determined, wherein selecting to store the data associated with the plurality of write commands is based at least in part on the size of the write buffer for storing the data satisfying a threshold.

11. The apparatus of claim 10, wherein the controller is further configured to cause the apparatus to: The data associated with the plurality of write commands is selected for storage based at least in part on the size of the write buffer for storing the data exceeding a second threshold that is greater than the threshold.

12. The apparatus of claim 10, wherein the controller is further configured to cause the apparatus to: Transitioning from the first type of block to the second type of block or from the second type of block to the first type of block based at least in part on the size of the write buffer used to store the data satisfying a third threshold.

13. The apparatus of claim 1 , wherein monitoring the parameters associated with the received plurality of write commands is further configured to cause the apparatus to: determining whether the non-volatile memory device is in an idle mode; and Determining whether a command queue associated with the write buffer is empty of the plurality of write commands, wherein selecting to store the data in the first type of block is based at least in part on determining whether the nonvolatile memory device is in the idle mode and determining whether the write buffer is empty.

14. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: A determination is made as to whether the command queue satisfies a threshold, wherein selecting to store the data in the first type of block is based at least in part on determining whether the command queue satisfies the threshold.

15. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: A determination is made as to whether an amount of data in the write buffer satisfies a threshold, wherein selecting to store the data in the first type of block is based at least in part on determining whether the amount of data in the write buffer satisfies the threshold.

16. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: A write intensifier mode of the non-volatile memory device is enabled, wherein monitoring the parameter is based at least in part on enabling the write intensifier mode.

17. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: receiving a plurality of write commands for writing data to a non-volatile memory device; monitoring parameters associated with the plurality of received write commands; selecting to store data associated with the plurality of write commands in a first type of block of the nonvolatile memory device based at least in part on monitoring the parameter; and The data associated with the plurality of write commands is transferred from a write buffer of a volatile memory device to the first type of block of the non-volatile memory device based at least in part on selecting to store the data associated with the plurality of write commands.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processor to: Transitioning from writing the data to the first type of blocks of the nonvolatile memory device to writing the data to a second type of blocks of the nonvolatile memory device based at least in part on monitoring the parameters associated with the plurality of write commands.

19. The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processor to: Transitioning from writing the data to a second type of block of the nonvolatile memory device to writing the data to the first type of block of the nonvolatile memory device is based at least in part on monitoring the parameter associated with the plurality of write commands.

20. A method comprising: receiving a plurality of write commands for writing data to a non-volatile memory device; monitoring parameters associated with the plurality of received write commands; selecting to store data associated with the plurality of write commands in a first type of block of the nonvolatile memory device based at least in part on monitoring the parameter; and The data associated with the plurality of write commands is transferred from a write buffer of a volatile memory device to the first type of block of the non-volatile memory device based at least in part on selecting to store the data associated with the plurality of write commands.

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