Solid-state imaging device, imaging device, and control method for solid-state imaging device

Abstract

A solid-state imaging device, an imaging device, and a control method of a solid-state imaging device are provided. A failure site is determined in a solid-state imaging device in which a arbiter coordinates requests. A plurality of pixels generate requests to transmit a prescribed detection signal in a case where a prescribed event is detected. A test circuit outputs the requests of the plurality of pixels as output requests in a case where a test is not instructed, and generates a new plurality of requests and outputs the respective requests as the output requests in a case where a test is instructed. The arbiter coordinates the output requests. A communication circuit transmits the detection signal according to a result of the coordination by the arbiter. A failure determination section determines whether the arbiter is faulty according to the detection signal in a case where a test is instructed.

Description

Technical Field

[0001] This technology relates to solid-state imaging elements, imaging devices, and control methods for solid-state imaging elements. Specifically, it relates to solid-state imaging elements, imaging devices, and control methods for solid-state imaging elements that detect changes in brightness exceeding a threshold as address events. Background Technology

[0002] Currently, synchronous solid-state imaging elements that capture image data (frames) in sync with synchronization signals such as vertical synchronization signals are used in imaging devices. However, these typical synchronous solid-state imaging elements can only acquire image data per cycle of the synchronization signal (e.g., 1 / 60th of a second). Therefore, they are unsuitable for applications requiring higher processing speeds, such as user interfaces for autonomous driving or wearable devices. Therefore, asynchronous solid-state imaging elements (e.g., see Patent Document 1) have been proposed, which include multiple pixels that detect and send requests in real time when changes in brightness exceed a threshold as address events, and a arbiter that coordinates these requests. As a method for testing the operation of such solid-state imaging elements, an example is a test method that involves placing a modulated light source that emits pulsed light and analyzing the detection results during pulsed light illumination.

[0003] Existing technical documents

[0004] Patent Document 1: Japanese Patent Publication No. 2016-533140

[0005] In the aforementioned asynchronous testing method, defective pixels are identified by analyzing the detection results during pulsed light illumination. However, since this detection result is output by a judge that coordinates requests from pixels, even if a defective pixel is detected, it remains difficult to determine whether the fault lies in the circuitry within the pixel or in the judge. Summary of the Invention

[0006] This technology is proposed in view of this situation, with the aim of identifying the fault location in the solid-state imaging element that the arbitrator coordinates the request.

[0007] To address the aforementioned problems, the first aspect of this technology is a solid-state imaging element and its control method. The solid-state imaging element includes: multiple pixels that, upon detecting a predetermined event, generate requests to send a predetermined detection signal; a test circuit that, when no test is indicated, outputs the requests from each of the multiple pixels as output requests, and when the test is indicated, generates multiple new requests and outputs each of these requests as output requests; a decision maker that coordinates the output requests; a communication circuit that sends the detection signal based on the coordination result of the decision maker; and a fault determination unit that, when the test is indicated, determines whether the decision maker is faulty based on the detection signal. Thus, it has the function of determining whether the decision maker is faulty.

[0008] Furthermore, in this first aspect, the test circuit includes a transistor that, when the test is indicated, supplies a predetermined potential to a signal line connected to the detector, and the request is output via the signal line. Thus, it has the function of forcibly outputting a predetermined potential request.

[0009] Furthermore, in this first aspect, the test circuit includes an AND gate that performs a logical AND operation on the request and the control signal instructing the test, outputting the request as the output. This prevents a short circuit between the signal line transmitting the request and the ground terminal.

[0010] Furthermore, in this first aspect, different addresses are assigned to the aforementioned plurality of pixels, and the test circuit outputs the new request corresponding to a portion of the aforementioned addresses as the output request. This serves to further determine the location of the fault within the fault detector.

[0011] Furthermore, in this first aspect, the pixel array containing the aforementioned plurality of pixels is partially divided into a predetermined number of regions, and the analyzer includes an analyzer block in each of the aforementioned regions. The fault determination unit determines, based on the aforementioned detection signal, which analyzer block has malfunctioned. This further facilitates the identification of the fault location within the analyzer.

[0012] Furthermore, in this first aspect, a portion of the aforementioned pixels is disposed on a photosensitive film, and the remaining portion of the aforementioned pixels is disposed on a circuit sheet, with the photosensitive film stacked on top of the circuit sheet. This effectively suppresses the increase in film area.

[0013] Furthermore, a second aspect of this technology is a camera device comprising: a plurality of pixels that, upon detecting a predetermined event, generate a request to send a predetermined detection signal; a test circuit that, when no test is instructed, outputs the requests of each of the plurality of pixels as output requests, and when the test is instructed, generates new plurality of requests and outputs each of these requests as output requests; a decision maker that coordinates the output requests; a communication circuit that sends the detection signal based on the coordination result of the decision maker; a fault determination unit that, when the test is instructed, determines whether the decision maker is faulty based on the detection signal; and a signal processing unit that performs predetermined processing on the detection signal. Thus, it has the function of determining whether the decision maker is faulty and performing predetermined processing.

[0014] Furthermore, a third aspect of this technology is a control method for a solid-state imaging element, comprising: a request generation step, wherein, when multiple pixels detect a specified event, a request is generated to send a specified detection signal; a testing step, wherein, when no test is indicated, the requests of each of the multiple pixels are output as output requests, and when the test is indicated, multiple new requests are generated and each request is output as the output request; a coordination step, wherein the output requests are coordinated; a communication step, wherein the detection signal is sent according to the coordination result of the resolver; and a fault determination step, wherein, when the test is indicated, the resolver is determined to be faulty based on the detection signal.

[0015] According to this technology, in a solid-state imaging element that is coordinated and requested by a malfunctioning arbiter, an excellent effect can be achieved in determining whether the arbiter is faulty. Furthermore, the effect described herein is not limited and can be any of the effects described in this invention. Attached Figure Description

[0016] Figure 1 This is a block diagram illustrating a structural example of a camera device in the first embodiment of the present technology.

[0017] Figure 2 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element in the first embodiment of the present technology.

[0018] Figure 3 This is a block diagram illustrating a structural example of a solid-state imaging element in the first embodiment of the present technology.

[0019] Figure 4 This is a circuit diagram illustrating a structural example of a pixel in the first embodiment of this technology.

[0020] Figure 5 This is a diagram illustrating an example of the input-output characteristics of the comparator in the first embodiment of this technology.

[0021] Figure 6 This is a block diagram illustrating a structural example of the AER (Address Event Representation) logic circuit in the first embodiment of this technology.

[0022] Figure 7 This is a circuit diagram illustrating a structural example of the line test circuit in the first embodiment of the present technology.

[0023] Figure 8 This is a diagram illustrating an example of the operation of the line test circuit in the first embodiment of this technology.

[0024] Figure 9 This is a circuit diagram illustrating a structural example of a test circuit in the first embodiment of this technology.

[0025] Figure 10 This is a block diagram illustrating a structural example of a row AER circuit in the first embodiment of this technology.

[0026] Figure 11 This is a circuit diagram illustrating a structural example of a row AER block in the first embodiment of this technology.

[0027] Figure 12 This is a block diagram illustrating a structural example of the column AER circuit in the first embodiment of this technology.

[0028] Figure 13 This is a block diagram illustrating a structural example of a column AER block in the first embodiment of this technology.

[0029] Figure 14 This is a block diagram illustrating a structural example of the row sorting algorithm in the first embodiment of this technology.

[0030] Figure 15 This is a timing diagram illustrating an example of a handshake in the first embodiment of this technology.

[0031] Figure 16 This is a flowchart illustrating an example of the operation of a solid-state imaging element in the first embodiment of this technology.

[0032] Figure 17 This is a circuit diagram illustrating a structural example of a line test circuit in a first variation of the first embodiment of the present technology.

[0033] Figure 18 This is a circuit diagram illustrating a structural example of an AND (Logical AND) gate in a first variation of the first embodiment of the present technology.

[0034] Figure 19 This is a diagram illustrating an example of the operation of the line test circuit in a first variation of the first embodiment of the present technology.

[0035] Figure 20 This is a circuit diagram illustrating a structural example of a test circuit in a first variation of the first embodiment of the present technology.

[0036] Figure 21 This is a circuit diagram illustrating a structural example of a pixel in a second variation of the first embodiment of the present technology.

[0037] Figure 22 This is a circuit diagram illustrating a structural example of a second variation of the first embodiment of the present technology, up to the buffer being disposed on the pixel of the photosensitive film.

[0038] Figure 23 This is a circuit diagram illustrating a structural example of a second variation of the first embodiment of the present technology, up to the pixel of the photosensitive film where the comparator is disposed.

[0039] Figure 24 This is a circuit diagram illustrating a structural example of a pixel at a connection position in a second variation of the first embodiment of the present technology.

[0040] Figure 25 This is a block diagram illustrating a structural example of the test control circuit in the second embodiment of the present technology.

[0041] Figure 26 This is a circuit diagram illustrating a structural example of the line test circuit in the second embodiment of the present technology.

[0042] Figure 27 This is a diagram illustrating an example of the operation of the line-side decoder in the second embodiment of this technology.

[0043] Figure 28 This is a circuit diagram illustrating a structural example of a test circuit in the second embodiment of this technology.

[0044] Figure 29 This is a diagram illustrating the test method in the second embodiment of the present technology.

[0045] Figure 30 This is a diagram illustrating a method for further segmenting the region and narrowing the fault location in a second embodiment of the present technology.

[0046] Figure 31 This is a diagram illustrating an example of detecting a faulty location in the second embodiment of this technology.

[0047] Figure 32 This is a block diagram illustrating a general structural example of a vehicle control system.

[0048] Figure 33 This is an explanatory diagram showing an example of the camera unit's installation location.

[0049] Explanation of reference numerals in the attached figures

[0050] 100 camera devices

[0051] 110 Optics Department

[0052] 120 DSP circuit

[0053] 130 Display Section

[0054] 140 Operations Department

[0055] 150 bus

[0056] 160-frame memory

[0057] 170 Storage Department

[0058] 180 Power Supply Section

[0059] 200 solid-state imaging elements

[0060] 201 Photosensitive Film

[0061] 202 Circuit Chip

[0062] 213 Rank Optimizer

[0063] 214 Column Address Encoder

[0064] 215 State Machine

[0065] 216-line address encoder

[0066] 220-column AER circuit

[0067] 221 AER blocks

[0068] 222 H side column AER block

[0069] 223 L-side AER block

[0070] 224, 415, 417, 426 OR (Logical OR) gates

[0071] 260-line AER circuit

[0072] 270 lines of AER block

[0073] 271, 324, 331, 332, 342, 344, 351, 353, 364, 369, 422-1, 422-2, 422-3 pMOS transistors

[0074] 272, 273, 321, 323, 345, 352, 354, 361-363, 365-368, 370, 371, 411, 412, 421, 422-4, 422-5, 422-6 nMOS transistors

[0075] Inverters 274, 275, 601, and 602

[0076] 276 NOR (Logical NOR) gates

[0077] 300-pixel array

[0078] 310 pixels

[0079] 320 Logarithmic Response Unit

[0080] 322 photodiode

[0081] 330 buffer

[0082] 340 Differential Circuit

[0083] Capacitors 341, 343, and 372

[0084] 350 comparator

[0085] 360 AER Logic Circuit

[0086] 410 test circuits

[0087] 413, 414, 422 AND (Logical AND) gates

[0088] Column-side decoders 416 and 418

[0089] 420-line test circuit

[0090] 427 line-side decoder

[0091] 430 Test Control Circuit

[0092] 431, 433 Control Signal Supply Department

[0093] Fault Determination Department 432, 434

[0094] 600-line optimization analyzer

[0095] 610, 650-654 Analyzer Block

[0096] 12031 Camera Department Detailed Implementation

[0097] The following describes the method for implementing this technology (hereinafter referred to as the implementation method).

[0098] The instructions are as follows.

[0099] 1. First Implementation Method (Example of outputting a request to the test circuit during testing)

[0100] 2. Second Implementation Method (Example of outputting a request for a specific address to the test circuit during testing)

[0101] 3. Examples of applications for moving bodies

[0102] <1. First Implementation Method>

[0103] [Example of camera device structure]

[0104] Figure 1 This is a block diagram illustrating a structural example of the camera device 100 in the first embodiment of the present technology. The camera device 100 is a device for capturing image data and includes: an optical unit 110, a solid-state imaging element 200, and a DSP (Digital Signal Processing) circuit 120. Furthermore, the camera device 100 also includes: a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. The camera device 100 is envisioned as a camera mounted on an industrial robot, a vehicle-mounted camera, etc.

[0105] The optical unit 110 collects light from the subject and directs it to the solid-state imaging element 200. The solid-state imaging element 200 detects an address event as when the absolute value of the change in brightness of each pixel exceeds the absolute value of a threshold. The solid-state imaging element 200 generates a detection signal indicating the presence or absence of an address event for each pixel and supplies it to the DSP circuit 120 via signal line 209.

[0106] The DSP circuit 120 performs prescribed signal processing on the image data composed of the detection signals. The DSP circuit 120 outputs the processed image data and event data to the frame memory 160, etc., via the bus 150. Furthermore, the DSP circuit 120 is an example of the signal processing unit described in the claims.

[0107] Display unit 130 displays image data and event data. Display unit 130 may be, for example, a liquid crystal panel or an organic EL (Electroluminescence) panel. Operation unit 140 generates operation signals according to user commands.

[0108] Bus 150 is a shared path for the optical unit 110, solid-state imaging element 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170 and power supply unit 180 to exchange data with each other.

[0109] The frame memory 160 holds image data. The storage unit 170 stores various data, including image data. The power supply unit 180 supplies power to the solid-state imaging element 200, the DSP circuit 120, or the display unit 130.

[0110] [Example of solid-state imaging element structure]

[0111] Figure 2 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element 200 in the first embodiment of the present technology. The solid-state imaging element 200 includes: a photosensitive film 201 and a circuit chip 202 stacked on the photosensitive film 201.

[0112] Figure 3 This is a block diagram illustrating a structural example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes: a column optimizer 213, a column AER circuit 220, a column address encoder 214, a pixel array unit 300, and a state machine 215. Furthermore, the solid-state imaging element 200 includes: a row address encoder 216, a row AER circuit 260, a row optimizer 600, a column test circuit 410, a row test circuit 420, and a test control circuit 430. The test control circuit 430 includes a control signal supply unit 431 and a fault determination unit 432. Additionally, the pixel array unit 300 has a plurality of pixels 310 arranged in a two-dimensional grid. Hereinafter, the set of pixels arranged in a predetermined direction in the pixel array unit 300 is referred to as a "row," and the set of pixels arranged in a direction perpendicular to the rows is referred to as a "column."

[0113] Pixel 310 generates a differential signal representing the voltage change corresponding to the photocurrent and compares the level of this signal with a predetermined threshold. The comparison result represents the detection result of an address event. Here, the threshold used for comparison with the differential signal includes two different thresholds, with the larger threshold set as the upper limit threshold and the smaller threshold set as the lower limit threshold. Furthermore, address events include on events and off events, and the detection result includes a 1-bit on event detection result and a 1-bit off event detection result. An on event is detected when the differential signal exceeds the upper limit threshold, and a off event is detected when the differential signal is below the lower limit threshold.

[0114] When an address event is detected, pixel 310 exchanges requests and responses with row test circuit 420 (hereinafter referred to as a "handshake"). Here, the request is an external signal sent to state machine 215 requesting the detection signal of the address event. Next, pixel 310 and column test circuit 410 perform a handshake.

[0115] The column test circuit 410 and the column AER circuit 220 exchange requests and responses. When the control signal from the test control circuit 430 does not indicate a test, the column test circuit 410 outputs the requests from all rows to the column AER circuit 220 as is. Conversely, when a test is indicated, the column test circuit 410 generates new requests for all columns and outputs them to the column AER circuit 220. Furthermore, the column test circuit 410 outputs the responses from the column AER circuit 220 to the pixel 310 as is.

[0116] The row test circuit 420 and the row AER circuit 260 exchange requests and responses. When the control signal from the test control circuit 430 does not indicate a test, the row test circuit 420 outputs all requests from all rows to the row AER circuit 260 as is. Conversely, when a test is indicated, the row test circuit 420 generates new requests for all rows and outputs them to the row AER circuit 260. Furthermore, the row test circuit 420 outputs the responses from the row AER circuit 260 to the pixel 310 as is.

[0117] In addition, the circuit including column test circuit 410 and row test circuit 420 is an example of the test circuit described in the claims.

[0118] The column optimizer 213 coordinates requests from the column AER circuit 220 and sends a response to the column AER circuit 220 based on the coordination result.

[0119] The column AER circuit 220 sends and receives requests and responses (handshakes) with each column, column arbiter 213, and state machine 215.

[0120] The column address encoder 214 encodes the address of the column where the address event occurred and sends it to the state machine 215.

[0121] The row address encoder 216 encodes the address of the row where the address event occurred and sends it to the state machine 215.

[0122] Row resolver 600 coordinates requests from row AER circuit 260 and sends a response to row AER circuit 260 based on the coordination result. Additionally, column resolver 213 and row resolver 600 are examples of resolvers described in the claims.

[0123] The row AER circuit 260 sends and receives requests and responses (handshakes) with each row, row classifier 600 and state machine 215.

[0124] State machine 215 sends a detection signal based on the coordination result of column optimizer 213 and row optimizer 600. When state machine 215 receives a request from column AER circuit 220 and row AER circuit 260, it decodes the data from column address encoder 214 and row address encoder 216 and determines the address of the detected address event. Image data is generated by arranging the detection signals of the address events of each pixel into a two-dimensional grid. State machine 215 sends its image data to DSP circuit 120 and fault determination unit 432. Furthermore, state machine 215 is an example of the communication circuit described in the claims.

[0125] When a test is indicated by the mode signal MODE, the control signal supply unit 431 supplies control signals to the column test circuit 410 and the row test circuit 420 respectively. Here, the mode signal MODE is a signal that indicates either a test mode in which the solid-state imaging element 200 is tested or a normal mode in which no test is performed. This mode signal MODE is generated by user operation or the execution of a specified application.

[0126] When instructed to perform a test, the fault determination unit 432 determines whether the column optimizer 213 or the row optimizer 600 is faulty based on the detection signal from the state machine 215. During the test, the column test circuit 410 and the row test circuit 420 are used to request the output of all pixels for all rows and all columns. Therefore, if the state machine 215 is not faulty, and neither the column optimizer 213 nor the row optimizer 600 is faulty, the state machine 215 sends the detection signal for all pixels. On the other hand, if the state machine 215 is not faulty, but the column optimizer 213 or the row optimizer 600 is faulty, the detection signal for some pixels may not be output. Therefore, the fault determination unit 432 can determine whether the column optimizer 213 or the row optimizer 600 is faulty by whether the detection signal for all pixels has been sent.

[0127] Furthermore, by combining a modulated light source that illuminates all pixels with pulsed light with a test method that analyzes the detection results when the pulsed light is applied, it is possible to determine which pixel or the arbiter is faulty.

[0128] Alternatively, without using a modulated light source, it can be discussed later. Figure 4 A selector is added after the logarithmic response unit 320, buffer 330, or differentiating circuit 340 for testing. This selector selects the test signal and the signal from the preceding stage and outputs it to the following stage. When combined with this testing method, it is possible to determine which circuit or arbiter within a pixel is faulty.

[0129] Alternatively, the test control circuit 430 can be configured inside the solid-state imaging element 200, but some or all of the circuitry within the test control circuit 430 can also be configured outside the solid-state imaging element 200 (DSP circuit 120, etc.).

[0130] [Example of pixel structure]

[0131] Figure 4 This is a circuit diagram illustrating a structural example of pixel 310 in a first embodiment of the present technology. Pixel 310 includes: a logarithmic response unit 320, a buffer 330, a differentiating circuit 340, a comparator 350, and an AER logic circuit 360.

[0132] The logarithmic response unit 320 includes: nMOS (negative channel MOS) transistors 321 and 323, photodiode 322, and pMOS (positive channel MOS) transistor 324.

[0133] Photodiode 322 generates photocurrent by photoelectric conversion of incident light. pMOS transistor 324 and nMOS transistor 323 are connected in series between the power supply and ground terminals. Furthermore, the gate of nMOS transistor 321 is connected to the junction of pMOS transistors 324 and 323, its source is connected to photodiode 322, and its drain is connected to the power supply terminal. A bias voltage Vblog is applied to the gate of pMOS transistor 324. Through this connection, the photocurrent flowing to photodiode 322 is logarithmically converted into a voltage Vp.

[0134] Furthermore, a photodiode 322 is disposed on the photosensitive film 201, and other circuitry is disposed on the circuit board 202. Additionally, the grounding of the photosensitive film 201 and the grounding of the circuit board 202 are separated to avoid interference.

[0135] Furthermore, the buffer 330 includes pMOS transistors 331 and 332 connected in series between the power supply and ground terminals. The gate of the ground-side pMOS transistor 332 is connected to the logarithmic response section 320, and a bias voltage Vbsf is applied to the gate of the power supply-side pMOS transistor 331. Additionally, the connection point of pMOS transistors 331 and 332 is connected to the differentiating circuit 340. This connection enables impedance transformation relative to Vp.

[0136] The differentiating circuit 340 includes: capacitors 341 and 343, pMOS transistors 342 and 344, and nMOS transistor 345.

[0137] One end of capacitor 341 is connected to buffer 330, and the other end is connected to one end of capacitor 343 and the gate of pMOS transistor 344. A reset signal xrst is input to the gate of pMOS transistor 342, with its source and drain connected across capacitor 343. PMOS transistor 344 and nMOS transistor 345 are connected in series between the power supply and ground terminals. Furthermore, the other end of capacitor 343 is connected to the junction of pMOS transistor 344 and nMOS transistor 345. A bias voltage Vba is applied to the gate of nMOS transistor 345 on the ground side, and the junction of pMOS transistor 344 and nMOS transistor 345 is also connected to comparator 350. Through this connection, a differential signal is generated and output to comparator 350. The differential signal is initialized by the reset signal xrst.

[0138] Comparator 350 includes pMOS transistors 351 and 353 and nMOS transistors 352 and 354. pMOS transistors 351 and 352 are connected in series between a power supply terminal and a ground terminal, and pMOS transistors 353 and 354 are also connected in series between a power supply terminal and a ground terminal. Furthermore, the gates of pMOS transistors 351 and 353 are connected to differentiating circuit 340. A predetermined upper threshold value Von is applied to the gate of nMOS transistor 352, and a predetermined lower threshold value Voff is applied to the gate of nMOS transistor 354.

[0139] The connection point of pMOS transistor 351 and nMOS transistor 352 is connected to AER logic circuit 360, and the voltage at this connection point is output as the comparison result VCH. The connection point of pMOS transistor 353 and nMOS transistor 354 is also connected to AER logic circuit 360, and the voltage at this connection point is output as the comparison result VCL. With this connection, when the differential signal exceeds the upper threshold Von, comparator 350 outputs a high-level comparison result VCH, and when the differential signal is below the lower threshold Voff, it outputs a low-level comparison result VCL. The comparison result VCH represents the detection result of an on event, and the comparison result VCL represents the detection result of an off event.

[0140] Alternatively, comparator 350 can detect both enable and disable events, but it can also detect only one of them. For example, when only enabling events are detected, only the corresponding pMOS transistor 351 and nMOS transistor 352 are configured.

[0141] The AER logic circuit 360 performs a handshake based on the comparison results VCH and VCL. In the event of an address event, the AER logic circuit 360 performs a handshake with the row AER circuit 260. Next, the AER logic circuit 360 performs a handshake with the column AER circuit 220 and uses the reset signal xrst to reset the differentiating circuit 340.

[0142] Figure 5 This is a graph illustrating an example of the input-output characteristics of the comparator 350 in the first embodiment of this technology. The vertical axis of the graph represents the level of the output signal (VCH or VCL) of the comparator 350, and the horizontal axis represents the level of the input signal (differential signal) of the comparator 350. Furthermore, the solid line represents the trajectory of the comparison result VCH, and the dashed line represents the trajectory of the comparison result VCL.

[0143] If the change in voltage corresponding to brightness (i.e., the differential signal) exceeds the upper threshold Von, the comparison result VCH changes from low to high, detecting an on event. On the other hand, if the differential signal is below the lower threshold Voff, the comparison result VCL changes from high to low, detecting an off event.

[0144] [Example of AER logic circuit structure]

[0145] Figure 6 This is a block diagram illustrating a structural example of the AER logic circuit 360 in the first embodiment of the present technology. The AER logic circuit 360 includes: nMOS transistors 361 to 363, 365 to 368, 370 and 371, pMOS transistors 364 and 369, and capacitor 372.

[0146] nMOS transistors 361 and 362 are connected in series. The comparison result VCH is input to the gates of nMOS transistors 362 and 363, and the response AckYp1 is input to the gate of nMOS transistor 361. Furthermore, the sources of nMOS transistors 362 and 363 are grounded, and a request ReqHXp1 is output from the drain of nMOS transistor 361 to the column test circuit 410. A request ReqYp1 ​​is output from the drain of nMOS transistor 363 to the row test circuit 420.

[0147] pMOS transistor 364 and nMOS transistor 365 are connected in series between the power supply and ground terminals. Furthermore, a comparison result VCL is input to the gate of pMOS transistor 364, and a bias voltage Vbaer is applied to the gate of nMOS transistor 365.

[0148] nMOS transistors 366 and 367 are connected in series. The gates of nMOS transistors 367 and 368 are connected to the junction of pMOS transistors 364 and nMOS transistor 365. A response AckYp1 is input to the gate of nMOS transistor 366. Furthermore, the sources of nMOS transistors 367 and 368 are grounded, and a request ReqLXp1 is output from the drain of nMOS transistor 366 to the column test circuit 410. A request ReqYp1 ​​is output from the drain of nMOS transistor 368 to the row test circuit 420.

[0149] pMOS transistor 369 is connected in series with nMOS transistors 370 and 371 between the power supply and ground terminals. Furthermore, a bias voltage Vbrst is applied to the gate of pMOS transistor 369. The gate input of nMOS transistor 370 receives the response AckYp1, and the gate input of nMOS transistor 371 receives the response AckXp1. One end of capacitor 372 is connected to the power supply, and the other end is connected to the junction of pMOS transistors 369 and nMOS transistors 370. Additionally, the voltage at the junction of pMOS transistors 369 and nMOS transistors 370 is output to differentiating circuit 340 as a reset signal xrst.

[0150] According to the above structure, when a high-level comparison result VCH (i.e., an enable event is detected) is input, the AER logic circuit 360 sends a low-level request ReqYp1 ​​to the row AER circuit 260. Furthermore, when a high-level response AckYp1 is received from the row test circuit 420, the AER logic circuit 360 sends a low-level request ReqHXp1 to the column AER circuit 410. Next, when a high-level response AckXp1 is received from the column test circuit 410, the AER logic circuit 360 outputs a low-level reset signal xrst to the differentiating circuit 340.

[0151] Furthermore, when a low-level comparison result VCL (i.e., a closed event is detected) is input, the AER logic circuit 360 sends a low-level request ReqYp1 ​​to the row test circuit 420. Moreover, when a high-level response AckYp1 is received from the row test circuit 420, the AER logic circuit 360 sends a low-level request ReqLXp1 to the column test circuit 410. Next, when a high-level response AckXp1 is received from the column test circuit 410, the AER logic circuit 360 outputs a low-level reset signal xrst to the differentiating circuit 340.

[0152] Figure 7 This is a circuit diagram illustrating a structural example of the row test circuit 420 in the first embodiment of this technology. In this row test circuit 420, nMOS transistors 421 are arranged row by row.

[0153] The nMOS transistor 421 supplies a specified potential to the signal line used to transmit the corresponding row request according to the control signal T_ReqY from the test control circuit 430. In the case of requesting the transmission of a low-level signal, a low level (such as ground potential) is supplied to the signal line.

[0154] When a test is indicated, the test control circuit 430 sends a high-level control signal T_ReqY. Consequently, regardless of the request ReqYp1 ​​in the first row of the pixel array section 300, the signal line is forcibly controlled to a low level, and a low-level request ReqYq1 is output to the row AER circuit 260. The same applies to the second row and thereafter. Furthermore, request ReqYp1 ​​is an example of the output request described in the claims.

[0155] On the other hand, without a test instruction, the test control circuit 430 sends a low-level control signal T_ReqY. As a result, the request ReqYp1 ​​of the first row of the pixel array section 300 is output as request ReqYq1 to the row AER circuit 260. The same applies to the second row and thereafter.

[0156] Furthermore, the response AckYp1 from the first row of the row AER circuit 260 is supplied to the pixel array section 300 in its original state. The same applies to the second row and thereafter.

[0157] Figure 8 This diagram illustrates an example of the operation of the line test circuit 420 in the first embodiment of this technology. When the control signal T_ReqY is low, the line test circuit 420 directly outputs the original state of request ReqYp1 ​​as request ReqYq1.

[0158] On the other hand, when the control signal T_ReqY is high, the line test circuit 420 will force the output of the request ReqYq1, which indicates a low level, regardless of the request ReqYp1.

[0159] [Example of a test circuit structure]

[0160] Figure 9 This is a circuit diagram illustrating a structural example of the column test circuit 410 in the first embodiment of the present technology. In this column test circuit 410, nMOS transistors 411 and 412 are arranged in rows.

[0161] nMOS transistor 411 supplies a specified potential (such as ground potential) to the signal line used to transmit the request for the corresponding column according to the control signal T_ReqLXp from the test control circuit 430. nMOS transistor 412 supplies a specified potential to the signal line used to transmit the request for the corresponding column according to the control signal T_ReqHXp from the test control circuit 430.

[0162] When a test is indicated, the test control circuit 430 sets one of the control signals T_ReqLXp and T_ReqHXp to a high level and the other to a low level. When a detection signal for an output enable event is received, the control signal T_ReqHXp is controlled to a high level; when a detection signal for an output disable event is received, the control signal T_ReqLXp is controlled to a high level. Using these control signals, a low-level request ReqLXq1 or a low-level ReqHXq1 is output to the column AER circuit 220. The same applies to rows 2 and beyond. Furthermore, request ReqLXq1 and ReqHXq1 are examples of the output requests described in the claims.

[0163] On the other hand, without a test instruction, the test control circuit 430 sends low-level control signals T_ReqLXp and T_ReqHXp. As a result, the request ReqLXp1 and ReqHXp1 of the first row of the pixel array section 300 are output to the column AER circuit 220 as request ReqLXq1 and ReqHXq1. The same applies to the second row and thereafter.

[0164] Furthermore, as described above, the column test circuit 410 and the row test circuit 420 forcibly set their potentials to low even when the signal line for transmitting the request is not low. If a response (AckYp1, etc.) is returned at this time, even though no request was originally sent, the unexpected pixel state caused by the return response could lead to a deadlock or other state. Therefore, in test mode, it is preferable that the test control circuit 430 sets all pixels to a reset state. For example, the test control circuit 430 in Figure 6 In the illustrated AER logic circuit 360, the circuit is set to a reset state by inputting a high-level bias voltage Vbrst.

[0165] [Example of a row AER circuit structure]

[0166] Figure 10 This is a block diagram illustrating a structural example of the row AER circuit 260 in the first embodiment of the present technology. The row AER circuit 260 includes row AER blocks 270 per row. The row AER blocks 270 perform handshakes with the corresponding row, row optimizer 600 and state machine 215.

[0167] [Example of the structure of a row AER block]

[0168] Figure 11 This is a circuit diagram illustrating a structural example of a row AER block 270 in a first embodiment of the present technology. The row AER block 270 includes: pMOS transistor 271, nMOS transistors 272 and 273, NOR gate 276, and inverters 274 and 275.

[0169] pMOS transistors 271, 272, and 273 are connected in series between the power supply and ground terminals. Furthermore, a control signal LOAD from state machine 215 is input to the gates of pMOS transistors 271 and 272. This control signal LOAD is a signal indicating the detection result of a read address event. Additionally, xCHIP_ACK, which is the inverted response CHIP_ACK from state machine 215, is input to the gate of nMOS transistor 273.

[0170] NOR gate 276 outputs the logical OR of two input values ​​as a request ReqYa1 to row decomposer 600. One input to the NOR gate 276 is the response CHIP_ACK from state machine 215. The other input to the NOR gate 276 is connected to the junction of pMOS transistor 271 and nMOS transistor 272, and to the signal line that transmits the request ReqYq1 from row test circuit 420.

[0171] Inverter 275 inverts the response AckYa1 from the self-determiner 600 and outputs it to inverter 274. Inverter 274 inverts the signal from inverter 275 and outputs it as the response AckYp1 to the horizontal test circuit 420.

[0172] With the above structure, when the row AER block 270 receives a low-level request ReqYq1, if the response CHIP_ACK is high, it outputs a low-level request ReqYa1. Furthermore, the row AER block 270 delays the high-level response AckYa1 and outputs it as the response AckYp1.

[0173] [Example of AER circuit structure]

[0174] Figure 12 This is a block diagram illustrating a structural example of the column AER circuit 220 in the first embodiment of the present technology. The column AER circuit 220 includes column AER blocks 221 column by column. The column AER blocks 221 handshake with the corresponding column, state machine 215, and column optimizer 213.

[0175] [Example of the structure of a column AER block]

[0176] Figure 13 This is a block diagram illustrating a structural example of column AER block 221 in the first embodiment of the present technology. The column AER block 221 includes: H-side column AER block 222, L-side column AER block 223, and OR (logic OR) gate 224.

[0177] H-side AER block 222 performs a handshake when a low-level request ReqHXq1 is input. This H-side AER block 222 outputs a signal to OR gate 224 that delays the high-level response AckHXa1. L-side AER block 223 performs a handshake when a low-level request ReqLXq1 is input. This L-side AER block 223 outputs a signal to OR gate 224 that delays the high-level response AckLXa1. Furthermore, the low-level request from pixel array section 300 is inverted using H-side AER block 222 and L-side AER block 223. The structure of the H-side AER block 222 and L-side AER block 223 is similar to... Figure 11 The example row AER block 270 is the same. Furthermore, the structure of the AER blocks in the above rows or columns is not limited to any specific structure, as long as it enables handshaking. Figure 12 Example circuit.

[0178] OR gate 224 performs a logical OR operation on the signals from the H-side AER block 222 and the L-side AER block 223, and outputs AckXp1 as a response.

[0179] [Example of the structure of a row sorting optimizer]

[0180] Figure 14 This is a block diagram illustrating a structural example of a row optimizer 600 in the first embodiment of this technology. The row optimizer 600 includes optimizer blocks 610, 650 to 654, and inverters 601 and 602. Furthermore, this diagram shows the row optimizer when the number of vertical event-driven pixels is set to 7 pixels. For example, if the number of vertical event-driven pixels is 1000 pixels, a 10th-order optimizer covering up to 2^10 (= 1024 pixels) is configured.

[0181] Discriminator block 610 coordinates the requests from line 1 and line 2. Discriminator block 610 performs a handshake with discriminator block 652 and outputs the response to line 1 or line 2 based on the coordination result.

[0182] Discriminator block 650 coordinates the requests from line 3 and line 4. Discriminator block 650 performs a handshake with discriminator block 652 and outputs the response to line 3 or line 4 based on the coordination result.

[0183] Discriminator block 651 coordinates the requests from line 5 and line 6. Discriminator block 651 performs a handshake with discriminator block 653 and outputs the response to line 5 or line 6 based on the coordination result.

[0184] Discriminator block 652 coordinates requests from discriminator block 610 and discriminator block 650. Discriminator block 652 performs a handshake with discriminator block 654 and outputs a response to discriminator block 610 or 650 based on the coordination result.

[0185] Discriminator block 653 coordinates the requests from discriminator block 651 and from line 7. Discriminator block 653 performs a handshake with discriminator block 654 and outputs a response to discriminator block 651 or line 7 based on the coordination result.

[0186] Discriminator block 654 coordinates requests from discriminator block 652 and requests from discriminator block 653. Discriminator block 654 uses inverters 601 and 602 to delay the response to the earlier request and supply it to discriminator block 652 or 653.

[0187] Furthermore, the structure of column resolver 213 is the same as that of row resolver 600. Moreover, the structure of the aforementioned resolvers is only required to coordinate requests and is not limited to the structure shown in this illustration.

[0188] Figure 15 This is a timing diagram illustrating an example of a handshake in the first embodiment of this technology. If pixel 310 outputs a low-level request ReqYp1, then row AER block 270 returns a high-level response AckYp1 when the response CHIP_ACK is high.

[0189] If the response AckYp1 is received, pixel 310 outputs a low-level request ReqHXp1 in the event of an on event. Additionally, in the event of a off event, it outputs a low-level request ReqLXp1.

[0190] If request ReqHXp1 is received, column AER block 221 returns a high-level response AckXp1 when the response CHIP_ACK is high. If response AckXp1 is received, pixel 310 generates a low-level reset signal xrst and initializes requests ReqYp1 ​​and ReqHXp1 to high.

[0191] Furthermore, if the output response is AckXp1, then column AER block 221 outputs a low-level request CHIP_REQ. If the request CHIP_REQ is received, state machine 215 transmits the detection result of the address event to DSP circuit 120 and returns a low-level response CHIP_ACK.

[0192] If a CHIP_ACK response is received, row AER block 270 initializes the response AckYp1 to low when requesting ReqYp1 ​​to be high. Furthermore, if a CHIP_ACK response is received, column AER block 221 initializes the response AckXp1 to low when requesting ReqHXp1 to be high.

[0193] If the response AckXp1 is initialized, pixel 310 initializes the reset signal xrst to high, and column AER block 221 initializes the request CHIP_REQ to high. Furthermore, state machine 215 initializes the response CHIP_ACK to high.

[0194] [Example of solid-state camera element operation]

[0195] Figure 16 This is a flowchart illustrating an example of the operation of the solid-state imaging element 200 in the first embodiment of this technology. This operation begins, for example, when a test is indicated by the mode signal MODE.

[0196] The test control circuit 430 within the solid-state imaging element 200 controls the column test circuit 410 and the row test circuit 420 to forcibly output requests to all rows and all columns (step S901). Furthermore, the column optimizer 213 and the row optimizer 600 coordinate these requests (step S902).

[0197] State machine 215 sends a detection signal to each pixel based on the coordination result (step S903). Test control circuit 430 determines whether column optimizer 213 and row optimizer 600 are faulty based on the detection signals (step S904). After step S904, solid-state imaging element 200 stops its testing operation.

[0198] Thus, according to the first embodiment of this technology, since the column test circuit 410 and the row test circuit 420 generate requests and supply them to the detector during testing, the presence or absence of a fault in the detector can be determined based on the coordination result of the requests from the detector. Therefore, it is possible to determine which of the pixels or the detector is faulty, and thus the location of the fault within the solid-state imaging element including them can be identified.

[0199] [First Variation]

[0200] In the first embodiment described above, the test control circuit 430 outputs a low-level request by switching nMOS transistors 411 and 421 to the on state during testing. However, in this structure, since the signal line transmitting the request is short-circuited to the ground terminal during testing, power consumption may increase. This first variation of the first embodiment differs from the first embodiment in that it uses an AND gate instead of nMOS transistors 411 to suppress the increase in power consumption.

[0201] Figure 17 This is a circuit diagram illustrating a structural example of the row test circuit 420 in a first variation of the first embodiment of the present technology. The row test circuit 420 in this variation of the first embodiment differs from the first embodiment in that it uses an AND gate 422 instead of an nMOS transistor 421.

[0202] AND gate 422 performs a logical AND operation between the request (ReqYp1, etc.) from the corresponding row in the pixel array section 300 and the control signal T_ReqY from the test control circuit 430, and outputs it to the row AER circuit 260.

[0203] Figure 18 This is a circuit diagram illustrating a structural example of the AND gate 422 in a first variation of the first embodiment of the present technology. The AND gate 422 includes pMOS transistors 422-1 to 422-3 and nMOS transistors 422-4 to 422-6. pMOS transistor 422-1 and nMOS transistors 422-4 and 422-5 are connected in series between a power supply terminal and a ground terminal. Furthermore, pMOS transistor 422-3 and nMOS transistor 422-6 are connected in series between a power supply terminal and a ground terminal. The source of nMOS transistor 422-2 is connected to the power supply terminal. The drain of nMOS transistor 422-2 is connected to the junction of pMOS transistors 422-1 and 422-4 and the gates of pMOS transistors 422-3 and 422-6.

[0204] Furthermore, requests (ReqYp1, etc.) for the corresponding rows within the pixel array section 300 are input to the gates of nMOS transistor 422-4 and pMOS transistor 422-2. A control signal T_ReqY from the test control circuit 430 is input to the gates of pMOS transistor 422-1 and nMOS transistor 422-5. Requests (ReqYq1, etc.) for the corresponding rows are output from the connection point of pMOS transistor 422-3 and nMOS transistor 422-6.

[0205] Figure 19 This diagram illustrates an example of the operation of the line test circuit 420 in a first variation of the first embodiment of this technology. When the control signal T_ReqY is low, the line test circuit 420 forces a low-level output for the request ReqYq1 regardless of the request ReqYp1.

[0206] On the other hand, when the control signal T_ReqY is high, the line test circuit 420 directly outputs the original state of request ReqYp1 ​​as request ReqYq1.

[0207] like Figure 18 and Figure 19 For example, during testing, a low-level control signal T_ReqY is used to turn off the nMOS transistor 425. Therefore, it is not necessary to charge and discharge the signal line and ground terminal for transmitting requests during testing, thus suppressing the increase in power consumption compared to the first embodiment.

[0208] Figure 20 This is a circuit diagram illustrating a structural example of the column test circuit 410 in a first variation of the first embodiment of the present technology. The aspect in which AND gates 413 and 414 are configured instead of nMOS transistors 411 and 412 in the column test circuit 410 of this first variation differs from that of the first embodiment. The circuit structures of the aforementioned AND gates 413 and 414 are the same as those of AND gate 422.

[0209] Thus, in the first variation of the first embodiment of this technology, since the logical AND of the output request (ReqYp1, etc.) of the AND gate 422 and the control signal T_ReqY is performed, a short circuit between the signal line transmitting the request and the ground terminal can be prevented. As a result, an increase in power consumption can be suppressed.

[0210] [Second variation]

[0211] In the first embodiment described above, components other than the photodiode 322 are disposed on the circuit board 202. However, as the number of pixels increases, the circuit size of the circuit within the circuit board 202 may increase. The solid-state imaging element 200 of the second variation of this first embodiment differs from the first embodiment in that nMOS transistors 321 and 323 are disposed on the photosensitive film 201.

[0212] Figure 21 This is a circuit diagram illustrating a structural example of pixel 310 in a second variation of the first embodiment of the present technology. The second variation of this first embodiment differs from the first embodiment in that pixel 310 is further configured with nMOS transistors 321 and 323 on the photosensitive film 201 in addition to the photodiode 322.

[0213] By arranging nMOS transistors 321 and 323 on the photosensitive film 201, the circuit size of the corresponding circuit chip 202 can be reduced. Furthermore, by using only N-type transistors within the photosensitive film 201, compared to a mixture of N-type and P-type transistors, the number of steps involved in transistor fabrication can be reduced. This reduces the manufacturing cost of the photosensitive film 201.

[0214] Furthermore, a portion of the logarithmic response unit 320 is disposed on the photosensitive film 201, and the remainder is disposed on the circuit chip 202, but the circuitry disposed on each chip is not limited thereto. For example, as Figure 22For example, the logarithmic response unit 320 and the buffer 330 can also be disposed on the photosensitive film 201, and otherwise disposed on the circuit board 202. Furthermore, as... Figure 23 For example, the logarithmic response unit 320, buffer 330, differentiator circuit 340 and comparator 350 can also be arranged on the photosensitive film 201, and otherwise arranged on the circuit board 202.

[0215] In addition, Figure 21 In the cascaded constructions shown, such as Figure 24 For example, the ground of the photosensitive film 201 can also be connected to the ground of the circuit chip 202 without separation. Figure 4 and Figure 23 The illustrated structure can also be grounded in the same way.

[0216] Thus, according to the second variation of the first embodiment of the present technology, in addition to the photodiode 322, since nMOS transistors 321 and 323 are also arranged on the photosensitive film 201, the circuit size of the circuit chip 202 can be reduced.

[0217] <2. Second Implementation Method>

[0218] In the first embodiment described above, it is determined which of the pixels and the optimizer is faulty, and the location of the fault within the solid-state imaging element 200 is identified. However, in the first embodiment, the solid-state imaging element 200 cannot further determine which of the multiple optimizer blocks within the optimizer is faulty. The solid-state imaging element 200 of this second embodiment differs from the first embodiment in that it requests specific rows or columns for output and further determines the location of the fault.

[0219] Figure 25 This is a block diagram illustrating a structural example of the test control circuit 430 in the second embodiment of the present technology. The test control circuit 430 of this second embodiment includes a control signal supply unit 433 and a fault determination unit 434.

[0220] When an instruction test is performed, the control signal supply unit 433 uses control signals to force all rows and all columns to output a request.

[0221] On the other hand, when a test is indicated, the fault determination unit 434 divides the pixel array unit 300 into multiple regions and calculates the detection frequency of address events as a statistic for each region. Furthermore, the fault determination unit 434 calculates the average detection frequency for each region. Moreover, the fault determination unit 434 extracts regions with detection frequencies below the average as regions corresponding to faulty decision-makers and supplies the address range of these regions to the control signal supply unit 433.

[0222] The control signal supply unit 433 forces the output of the row and column of the area extracted by the fault determination unit 434.

[0223] Furthermore, the fault determination unit 434 further divides the extracted area into multiple regions and calculates the detection frequency for each region. The fault determination unit 434 also extracts regions where the detection frequency is below the average value and supplies the address range of these regions to the control signal supply unit 433. Thereafter, the fault determination unit 434 and the control signal supply unit 433 repeat the same control process and narrow down the region corresponding to the faulty decision block. However, when the region is narrowed down to the smallest unit that can detect the fault (e.g., a 2-row × 2-column region), the fault determination unit 434 outputs a fault signal to the DSP circuit 120, indicating the fault location of the decision block corresponding to that region.

[0224] Here, the decision makers can be classified into equal decision makers and non-equal decision makers. An equal decision maker is a circuit that can maintain and prioritize signals input simultaneously as internal states. After priority processing, the priority of subsequent input signals decreases, and inputs are received after processing of other high-priority parts is completed. On the other hand, a non-equal decision maker, because it does not maintain the internal states of simultaneous inputs, responds quickly. However, if a request is immediately input after processing, it is processed regardless of priority order, and circuits capable of high-speed response due to manufacturing unevenness are processed first. Therefore, in an equal decision maker, when all pixels are requested to output, the detection points of address events are not concentrated in specific rows, columns, or pixels but are dispersed. On the other hand, in a non-equal decision maker, it is possible to concentrate the detection points in specific rows or columns. When narrowing down fault locations, it is preferable that the detection points are not concentrated; therefore, as the column decision maker 213 and row decision maker 600 of the second embodiment, equal decision makers are preferably used.

[0225] Figure 26 This is a circuit diagram illustrating a structural example of the row test circuit 420 in the second embodiment of this technology. The row test circuit 420 of this second embodiment differs from the first embodiment in that it also includes an OR (Logical OR) gate 426 and a row-side decoder 427. The aforementioned OR gate 426 and row-side decoder 427 are arranged row by row. Furthermore, the row-side decoder 427 of all rows receives a control signal Y_Ctrl from the test control circuit 430. This control signal Y_Ctrl encodes the row address and mode signal MODE of the output request.

[0226] The horizontal decoder 427 decodes the control signal Y_Ctrl. Based on the decoded horizontal address and mode signal MODE, the horizontal decoder 427 generates control signals T_ReqY and EN, and supplies control signal T_ReqY to the gate of nMOS transistor 421 and control signal EN to OR gate 426.

[0227] OR gate 426 performs a logical OR operation between the control signal EN and the corresponding row request (ReqYp1, etc.), and outputs it to the row AER circuit 260.

[0228] Figure 27 This diagram illustrates an example of the operation of the line-side decoder 427 in the second embodiment of this technology. When the mode signal MODE is a value representing the normal mode (e.g., logic value "0"), the line-side decoder 427 outputs low-level control signals T_ReqY and EN.

[0229] On the other hand, when the mode signal MODE is a value representing the test mode (e.g., the logic value "1"), the row-side decoder 427 determines whether the decoded row address is consistent with its own corresponding row address.

[0230] When the request is consistent, the line-side decoder 427 outputs a high-level control signal T_ReqY and a low-level control signal EN. This forces a low-level request to be output from that line. Conversely, when the request is inconsistent, the line-side decoder 427 outputs a low-level control signal T_ReqY and a high-level control signal EN. This forces a high-level request to be output from that line and blocks the request.

[0231] Thus, the test control circuit 430 can output only requests for specific row addresses and block requests for other row addresses by controlling the Y_Ctrl signal. The same applies to column addresses.

[0232] Figure 28 This is a circuit diagram illustrating a structural example of the column test circuit 410 in the second embodiment of the present technology. The column test circuit 410 of this second embodiment differs from the first embodiment in that it also includes OR gates 415 and 417, and column-side decoders 416 and 418 per column.

[0233] The column-side decoders 416 and 418 have the same structure as the row-side decoder 427. However, column-side decoder 416 decodes the control signal X_CtrlL, and column-side decoder 418 decodes the control signal X_CtrlH. These control signals encode the column address and the mode signal MODE. When an output enable event detection signal is received, the test control circuit 430 uses the control signal X_CtrlH to output a request from a specific column address and uses the control signal X_CtrlL to block requests from all column addresses. Conversely, when an output disable event detection signal is received, the test control circuit 430 uses the control signal X_CtrlL to output a request from a specific column address and uses the control signal X_CtrlH to block requests from all column addresses.

[0234] The structures of OR gates 415 and 417 are the same as those of OR gate 426.

[0235] Figure 29 This is a diagram illustrating the testing method in the second embodiment of this technology. In the diagram, the vertical axis represents the detection frequency of address events, and the horizontal axis represents addresses. In the diagram, 'a' represents an example of the detection result for region B1, 'b' represents an example of the detection result for region B2 adjacent to region B1, and 'c' represents an example of the detection result for region B3 adjacent to region B2.

[0236] When instructed to perform a test, the fault determination unit 434 calculates the detection frequency of region B1 as illustrated in figure a. Furthermore, the fault determination unit 434 calculates the detection frequencies of regions B2 and B3 as illustrated in figures b and c. The detection frequency is also calculated for each region other than B1 to B3 in the same manner.

[0237] Here, the detection frequency of region B3 is lower than the average of all addresses. In this case, the fault determination unit 434 extracts this region as the region corresponding to the faulty decision block. The control signal supply unit 433 forcibly outputs requests for the rows and columns of the extracted region B3, while blocking requests for the remaining regions.

[0238] Figure 30 This diagram illustrates a method for further segmenting the region and narrowing down the fault location in the second embodiment of this technology. In the same figure, a represents an example of the detection result of region B31 after segmenting region B3. In the same figure, b represents an example of the detection result of region B32, which is adjacent to region B31, after segmenting region B3. In the same figure, c represents an example of the detection result of any one of the regions after segmenting region B32.

[0239] The fault determination unit 434 calculates the detection frequency of regions B31 and B32 in the multiple regions obtained by further dividing the extracted region B3, as illustrated in a and b in the figure.

[0240] Here, the detection frequency of region B32 is lower than the average. In this case, the fault determination unit 434 extracts this region as the region corresponding to the faulty decision block. The control signal supply unit 433 forces the output of requests for the rows and columns of the extracted region B32, and blocks the requests for the remaining rows and columns.

[0241] The fault determination unit 434 calculates the detection frequency of any one of the multiple regions after further subdividing the extracted region B32, as illustrated in example c of the figure. Solid-state imaging element 200 repeats... Figure 29 and Figure 30 The example process refines the area and narrows down the location of the fault.

[0242] Figure 31 This diagram illustrates an example of fault location detection in the second embodiment of this technology. In a portion of the refined region B32, the detection frequency becomes extremely low. The fault determination unit 434 determines that the block arbiter corresponding to this region is faulty.

[0243] Thus, according to the second embodiment of this technology, the test control circuit 430 can output a request corresponding to a portion of all addresses and narrow down the address that causes the request output, thereby identifying the fault location within the fault detector.

[0244] <3. Examples of applications for moving bodies>

[0245] The technology involved in this invention (the Technology) can be applied to a variety of products. For example, the Technology involved in this invention can also be implemented as a device mounted on any mobile body such as a car, electric car, hybrid electric car, autonomous two-wheeler, bicycle, personal mobile device, airplane, drone, ship, robot, etc.

[0246] Figure 32 This is a block diagram illustrating a schematic structural example of a vehicle control system, which is an example of a mobile body control system to which the technology of the present invention can be applied.

[0247] The vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. Figure 32 In the example shown, the vehicle control system 12000 includes: a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, the functional structure diagram of the comprehensive control unit 12050 includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network I / F 12053.

[0248] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a drive force generating device such as an internal combustion engine or drive motor for generating the vehicle's driving force, a drive force transmission mechanism for transmitting the driving force to the wheels, a control mechanism for adjusting the vehicle's steering angle, and a braking device for generating the vehicle's braking force.

[0249] The vehicle body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the vehicle body system control unit 12020 functions as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves or signals from various switches emitted by a portable device that replaces the key can be input to the vehicle body system control unit 12020. The vehicle body system control unit 12020 receives the input of the aforementioned radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0250] The external information detection unit 12030 detects external information of the vehicle equipped with the vehicle control system 12000. For example, a camera unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the camera unit 12031 to capture images of the outside of the vehicle and receives the captured images. The external information detection unit 12030 can also perform object detection processing or distance detection processing based on the received images, such as people, vehicles, obstacles, signs, or text on the road surface.

[0251] The camera unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light it is sensitive to. The camera unit 12031 can output the electrical signal as an image and also as distance measurement information. Furthermore, the light received by the camera unit 12031 can be either visible light or non-visible light such as infrared light.

[0252] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041, which detects, for example, the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. The in-vehicle information detection unit 12040 can also calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, and can also determine whether the driver is drowsy.

[0253] Based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can calculate the control target values ​​for the drive force generating device, the control mechanism, or the braking device, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for the purpose of realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following distance based on vehicle distance, maintaining vehicle speed, collision warning, or lane departure warning.

[0254] Furthermore, the microcomputer 12051 controls the drive force generating device, the control mechanism, or the braking device based on the vehicle's surrounding information obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby enabling coordinated control for purposes such as autonomous driving without relying on the driver's operation.

[0255] Furthermore, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on the external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights based on the position of the vehicle in front or oncoming vehicles detected by the external information detection unit 12030, and can perform coordinated control for purposes such as switching high beams to low beams to reduce glare.

[0256] The audio-visual output unit 12052 sends at least one output signal, consisting of audio and visual signals, to an output device that can provide visual or auditory notification to vehicle occupants or outside the vehicle. Figure 32 In the example, a speaker 12061, a display unit 12062, and a mounting panel 12063 are shown as output devices. The display unit 12062 may also include at least one of, for example, an in-vehicle display and a head-up display.

[0257] Figure 33 This diagram shows an example of the installation location of the camera unit 12031.

[0258] Figure 33 In the middle, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104, and 12105.

[0259] Cameras 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, exterior rearview mirrors, rear bumper, rear door, and the upper part of the windshield inside the vehicle 12100. Camera 12101 mounted on the front nose and camera 12105 mounted on the upper part of the windshield inside the vehicle primarily acquire images of the front of the vehicle 12100. Cameras 12102 and 12103 mounted on the exterior rearview mirrors primarily acquire images of the sides of the vehicle 12100. Camera 12104 mounted on the rear bumper or rear door primarily acquires images of the rear of the vehicle 12100. Camera 12105 mounted on the upper part of the windshield inside the vehicle is mainly used to detect vehicles or pedestrians, obstacles, traffic lights, traffic signs, or lane markings ahead.

[0260] in addition, Figure 33This is an example illustrating the shooting range of camera units 12101 to 12104. Shooting range 12111 refers to the shooting range of camera unit 12101 mounted on the front nose; shooting ranges 12112 and 12113 refer to the shooting ranges of camera units 12102 and 12103 mounted on the exterior rearview mirrors, respectively; and shooting range 12114 refers to the shooting range of camera unit 12104 mounted on the rear bumper or rear door. For example, by overlapping the image data captured by camera units 12101 to 12104, a top-down view of vehicle 12100 is obtained.

[0261] At least one of the camera units 12101 to 12104 may also have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera composed of multiple camera elements, or a camera element having pixels for phase difference detection.

[0262] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 calculates the distances between the camera and each three-dimensional object within the shooting range 12111 to 12114, and the time change of these distances (relative speed to vehicle 12100). This allows it to particularly identify three-dimensional objects located closest to vehicle 12100 on its path, and those traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher), as preceding vehicles. Furthermore, microcomputer 12051 sets a pre-defined distance to be maintained in front of the preceding vehicle and can perform automatic braking control (including follow-stop control) or automatic acceleration control (including follow-start control), etc. Thus, coordinated control for purposes such as autonomous driving can be performed without relying on driver operation.

[0263] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can classify and extract three-dimensional object data related to three-dimensional objects into categories such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, etc., and use this information for automatic obstacle avoidance. For example, microcomputer 12051 can identify obstacles around vehicle 12100 as obstacles that are identifiable to the driver of vehicle 12100 and obstacles that are difficult to identify. Furthermore, microcomputer 12051 determines the collision risk, indicating the degree of danger of colliding with each obstacle. When the collision risk is above a set value and there is a possibility of collision, it outputs an alarm to the driver via speaker 12061 or display unit 12062, or performs forced deceleration or evasive steering via drive system control unit 12010, thereby enabling driving assistance for collision avoidance.

[0264] At least one of the camera units 12101 to 12104 can also be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. The pedestrian identification is performed by the following steps: extracting feature points from the images captured by the camera units 12101 to 12104, which are, for example, infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the camera units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to overlay a square outline for emphasis on the identified pedestrian. Alternatively, the audio-visual output unit 12052 can also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired position.

[0265] The above describes an example of a vehicle control system to which the technology of the present invention can be applied. The technology of the present invention can be applied to the camera unit 12031 in the structure described above. Specifically, for example, Figure 1 The camera device 100 can be used in the camera unit 12031. By applying the technology of the present invention to the camera unit 12031, the location of its failure can be determined, thereby improving the safety and reliability of the system.

[0266] Furthermore, the above-described embodiments represent one example of the specific implementation of this technology, and the elements in the embodiments correspond to the specific elements of the claims. Similarly, the specific elements of the claims and the elements in the embodiments of this technology bearing the same name correspond to each other. However, this technology is not limited to the embodiments, and can be specifically implemented by various modifications to the embodiments without departing from its main idea.

[0267] Furthermore, the effects described in this instruction manual are merely illustrative and not intended to limit the scope of the invention; other effects may also be present.

[0268] In addition, this technology can form the following structure.

[0269] (1) A solid-state imaging element, comprising:

[0270] Multiple pixels, upon detecting a specified event, generate a request to send a specified detection signal;

[0271] The test circuit outputs the requests of each of the plurality of pixels as output requests when no test is indicated, and generates a plurality of new requests and outputs each of the requests as the output requests when the test is indicated.

[0272] The decision-maker coordinates the output requests;

[0273] The communication circuit sends the detection signal based on the coordination result of the decision-maker;

[0274] The fault determination unit determines whether the fault calibrator is faulty based on the detection signal when the test is instructed.

[0275] (2) Among the solid-state imaging elements described in (1) above,

[0276] The test circuit includes a transistor that, when the test is indicated, supplies a predetermined potential to a signal line connected to the resolver.

[0277] The request is output via the signal line.

[0278] (3) In the solid-state imaging element described in (1) above, the test circuit includes a logic AND gate, which outputs the logic AND of the request and the control signal indicating the test as the output request.

[0279] (4) Among the solid-state imaging elements described in (1) to (3) above,

[0280] Each of the multiple pixels is assigned a different address.

[0281] The test circuit outputs the new request corresponding to a portion of the address as the output request.

[0282] (5) In the solid-state imaging element described in (4) above, the pixel array portion in which the plurality of pixels are arranged is divided into a predetermined number of regions.

[0283] The decision-maker includes a decision-maker block in each of the regions.

[0284] The fault determination unit determines which of the decision-makers blocks has malfunctioned based on the detection signal.

[0285] (6) Among the solid-state imaging elements described in (1) to (5) above,

[0286] A portion of the pixel is disposed on the photosensitive film.

[0287] The remaining portion of the pixel is disposed on a circuit chip.

[0288] The photosensitive film is stacked on the circuit chip.

[0289] (7) A camera device comprising:

[0290] Multiple pixels, upon detecting a specified event, generate a request to send a specified detection signal;

[0291] The test circuit outputs the requests of each of the plurality of pixels as output requests when no test is indicated, and generates a plurality of new requests and outputs each of the requests as the output requests when the test is indicated.

[0292] The decision-maker coordinates the output requests;

[0293] The communication circuit sends the detection signal based on the coordination result of the decision-maker;

[0294] The fault determination unit determines whether the fault calibrator is faulty based on the detection signal when the test is instructed.

[0295] The signal processing unit performs prescribed processing on the detection signal.

[0296] (8) A method for controlling a solid-state imaging element, comprising:

[0297] The request generation step generates a request to send a specified detection signal when multiple pixels detect a specified event.

[0298] The testing procedure is as follows: if no test is indicated, the requests of each of the plurality of pixels are output as output requests; if the test is indicated, multiple new requests are generated and each request is output as the output request.

[0299] The coordination step coordinates the output request;

[0300] In the communication step, the detection signal is sent according to the coordination result of the arbiter;

[0301] The fault determination step involves determining whether the fault calibrator is faulty based on the detection signal when the test is instructed.

Claims

1. A solid-state imaging element, characterized in that, include: Multiple pixels, upon detecting a specified event, generate a request to send a specified detection signal; The test circuit outputs the requests of each of the plurality of pixels as output requests without indicating a test, and generates a plurality of new requests and outputs each of the new requests as output requests when the test is indicated. The decision-maker coordinates the output requests; The communication circuit sends the detection signal based on the coordination result of the decision-maker; The fault determination unit determines whether the fault calibrator is faulty based on the detection signal when the test is instructed.

2. The solid-state imaging element according to claim 1, characterized in that, The test circuit includes a transistor that, when the test is indicated, supplies a predetermined potential to a signal line connected to the resolver. The request is output via the signal line.

3. The solid-state imaging element according to claim 1, characterized in that, The test circuit includes an AND gate that performs a logical AND operation on the request and the control signal instructing the test as the output request.

4. The solid-state imaging element according to claim 1, characterized in that, Each of the multiple pixels is assigned a different address. The test circuit outputs the new request corresponding to a portion of the address as the output request.

5. The solid-state imaging element according to claim 4, characterized in that, The pixel array containing the plurality of pixels is divided into a predetermined number of regions. The decision-maker includes a decision-maker block in each of the regions. The fault determination unit determines which of the decision-makers blocks has malfunctioned based on the detection signal.

6. The solid-state imaging element according to claim 1, characterized in that, A portion of the pixel is disposed on the photosensitive film. The remaining portion of the pixel is disposed on a circuit chip. The photosensitive film is stacked on the circuit chip.

7. A camera device, characterized in that, include: Multiple pixels, upon detecting a specified event, generate a request to send a specified detection signal; The test circuit outputs the requests of each of the plurality of pixels as output requests without indicating a test, and generates a plurality of new requests and outputs each of the new requests as output requests when the test is indicated. The decision-maker coordinates the output requests; The communication circuit sends the detection signal based on the coordination result of the decision-maker; The fault determination unit determines whether the fault calibrator is faulty based on the detection signal when the test is instructed. The signal processing unit performs prescribed processing on the detection signal.

8. A control method for a solid-state imaging element, characterized in that, include: The request generation step generates a request to send a specified detection signal when multiple pixels detect a specified event. The testing procedure is as follows: if no test is indicated, the requests of each of the plurality of pixels are output as output requests as is; if the test is indicated, multiple new requests are generated and each of the new requests is output as the output request. The coordination step involves coordinating the output request through a decision-maker. In the communication step, the detection signal is sent according to the coordination result of the arbiter; The fault determination step involves determining whether the fault calibrator is faulty based on the detection signal when the test is instructed.

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