Image Sensor

Abstract

An image sensor includes: a substrate including a sensor region for receiving light and generating image data and a pad region adjacent to the sensor region; an insulating layer on the substrate; a lower transparent electrode on the insulating layer in the sensor region; and an etch stop layer on the insulating layer in the sensor region and the pad region. The etch stop layer may include silicon nitride. The height of the uppermost surface of the lower transparent electrode relative to the substrate may be substantially equal to the height of the upper surface of the etch stop layer relative to the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0064721 filed on June 5, 2018 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments of the present disclosure relate to image sensors and / or methods of manufacturing the same. For example, at least some example embodiments relate to image sensors including transparent electrodes and / or methods of manufacturing the same. Background Art

[0004] Image sensors are devices for converting optical images into electrical signals. With the development of the computer industry and the communication industry, the demand for image sensors with improved performance is increasing in various fields such as digital cameras, video cameras, personal communication systems (PCS), gaming devices, security cameras, and medical miniature cameras. Image sensors can be classified into charge coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensors. CMOS image sensors can be easily driven and include signal processing circuits integrated therein, thereby reducing the size of the image sensor. The power consumption of CMOS image sensors is also very low, so they can be easily applied to devices with limited battery capacity. In addition, CMOS image sensors can be manufactured by CMOS process technology, thereby reducing manufacturing costs. Therefore, since high resolution can be achieved, the use of CMOS image sensors is growing rapidly. Summary of the invention

[0005] According to an example embodiment of the present invention, an image sensor may include a substrate including a sensor area and a pad area adjacent to the sensor area; an insulating layer on the substrate; a lower transparent electrode on the insulating layer within the sensor area; and an etch stop layer on the insulating layer within both the sensor area and the pad area, wherein a height of an uppermost portion of an upper surface of the lower transparent electrode relative to the substrate is substantially equal to a height of an upper surface of the etch stop layer relative to the substrate.

[0006] According to an example embodiment of the present invention, an image sensor may include a substrate including a sensor area and a pad area, the sensor area including a first pixel area and a second pixel area; an insulating layer on the substrate; a first lower transparent electrode on the insulating layer in the first pixel area; a second lower transparent electrode on the insulating layer in the second pixel area; a first etch stop layer on the insulating layer in the sensor area and the pad area, such that in the sensor area, the first etch stop layer is located on the insulating layer between the first lower transparent electrode and the second lower transparent electrode, wherein an upper surface of the first lower transparent electrode relative to an uppermost portion of the substrate is substantially coplanar with an upper surface of the first etch stop layer relative to the substrate.

[0007] According to an example embodiment of the present invention, an image sensor may include a substrate including a sensor area and a pad area adjacent to the sensor area; a first photoelectric conversion layer in a portion of the substrate associated with the sensor area; an interlayer insulating structure on the substrate, the interlayer insulating structure including an insulating layer and an etch stop layer on the insulating layer; a groove in a portion of the interlayer insulating structure associated with the sensor area; a lower transparent electrode in the groove; and a second photoelectric conversion layer on the lower transparent electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an image sensor according to example embodiments.

[0009] Figure 2 yes Figure 1 Equivalent circuit of the sensor array.

[0010] Figure 3 is a schematic plan view of an image sensor according to example embodiments.

[0011] Figure 4 It is shown Figure 3 Layout diagram of the first area S1.

[0012] Figure 5 is along Figure 3 A cross-sectional view taken along lines AA' and BB'.

[0013] Figure 6 and Figure 7 yes Figure 5 FIG. 1 is an enlarged view of the second area S2.

[0014] Figure 8 is a schematic cross-sectional view of an image sensor according to example embodiments.

[0015] Fig. 9 yes Figure 8An enlarged view of the third area S3.

[0016] Figures 10 to 17 are views illustrating stages in a method of manufacturing an image sensor according to example embodiments.

[0017] Figures 18 to 20 are views illustrating stages in a method of manufacturing an image sensor according to example embodiments. DETAILED DESCRIPTION

[0018] Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings.Throughout the application, like reference numerals may refer to like elements.

[0019] Figure 1 is a block diagram of an image sensor according to example embodiments. Figure 2 yes Figure 1 Equivalent circuit of the sensor array. Figure 3 is a schematic plan view of an image sensor according to example embodiments. Figure 4 It is shown Figure 3 Layout diagram of the first area S1. Figure 5 is along Figure 3 A cross-sectional view taken along lines AA' and BB'. Figure 6 and Figure 7 yes Figure 5 FIG. 1 is an enlarged view of the second area S2.

[0020] refer to Figure 1 , an image sensor according to example embodiments may include an active pixel sensor array 10, a row decoder 20, a row driver 30, a column decoder 40, a timing generator 50, a correlated double sampler (CDS) 60, an analog-to-digital converter (ADC) 70, and an input / output buffer 80.

[0021] The active pixel sensor array 10 may include a plurality of unit pixels arranged in two dimensions and may convert an optical signal into an electrical signal. The active pixel sensor array 10 may be driven by a plurality of driving signals, such as a selection signal, a reset signal, and a transfer signal from a row driver 30. The electrical signal converted by the active pixel sensor array 10 may be provided to a correlated double sampler 60.

[0022] The row driver 30 may provide a plurality of driving signals for driving a plurality of unit pixels to the active pixel sensor array 10 according to the result of decoding in the row decoder 20. In the case where the unit pixels are arranged along rows and columns, a driving signal may be provided to each row.

[0023] The timing generator 50 may provide timing signals and control signals to the row decoder 20 and the column decoder 40 .

[0024] The correlated double sampler 60 may receive the electric signal generated by the active pixel sensor array 10, and may hold and sample the electric signal. The correlated double sampler 60 may double-sample a reference level including specific noise and a signal level of the electric signal, and may output a differential level corresponding to the difference between the reference level and the signal level.

[0025] The analog-to-digital converter 70 may convert an analog signal corresponding to the differential level output from the correlated double sampler 60 into a digital signal and may output the digital signal.

[0026] The input / output buffer 80 may latch the digital signal and may sequentially output the digital signal to the video signal processing unit according to the result of decoding in the column decoder 40 .

[0027] refer to Figure 2 , the unit pixels P may be arranged along rows and columns to form an active pixel array (see, for example, Figure 1 10). Each unit pixel P may include a phototransistor 11, a floating diffusion region (FD) 13, a charge transfer transistor 15, a drive transistor 17, a reset transistor 18, and a selection transistor 19. Their functions will be described with reference to the i-th row pixels (P(i, j), P(i, j+1), P(i, j+2), P(i, j+3), ...) as an example.

[0028] The phototransistor 11 may receive incident light to accumulate charges corresponding to the amount of light. The phototransistor 11 may include, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), an organic photodiode (OPD), a quantum dot (QD), or a combination thereof.

[0029] The phototransistor 11 may be coupled to the charge transfer transistor 15, thereby transmitting the accumulated charges to the floating diffusion region 13. The floating diffusion region 13 may convert the charges into a voltage and may have a parasitic capacitance, thereby accumulatively storing the charges.

[0030] In the figure, it is shown that the unit pixel P includes one charge transfer transistor 15 , but the inventive concept is not limited thereto. For example, the unit pixel P may include a plurality of charge transfer transistors 15 .

[0031] For example, a plurality of phototransistors 11 may be provided in the unit pixel P. Therefore, a charge transfer transistor 15 corresponding to each of the plurality of phototransistors 11 may be provided in the unit pixel. In some example embodiments, when a plurality of charge transfer transistors 15 are provided in the unit pixel P, the floating diffusion region 13 may be shared.

[0032] The drive transistor 17 may be, for example, a source follower amplifier. Therefore, the drive transistor 17 may amplify the change in the potential of the floating diffusion region 13 that has received the accumulated charge from the phototransistor 11, and may output the amplified result to the output line Vout.

[0033] The reset transistor 18 can periodically reset the floating diffusion region 13. The reset transistor 18 can be composed of a MOS transistor driven by a reset line (RX(i)) to which a predetermined bias (i.e., a reset signal) is applied. When the reset transistor 18 is turned on by the bias provided by the reset line (RX(i)), a desired (or alternatively, predetermined) potential (e.g., a power supply voltage (VDD)) provided to the drain of the reset transistor 18 can be sent to the floating diffusion region 13.

[0034] The selection transistor 19 can be used to select the pixel unit P to be read in units of rows. The selection transistor 19 can be composed of a MOS transistor, wherein the MOS transistor is driven by a row selection line (SEL (i)) to which a desired (or alternatively, predetermined) bias (i.e., a row selection signal) is applied. When the selection transistor 19 is turned on by the bias provided by the row selection line (SEL (i)), the desired (or alternatively, predetermined) potential (e.g., power supply voltage (VDD)) provided to the drain of the selection transistor 19 can be sent to the drain region of the drive transistor 17.

[0035] The transfer line (TX(i)) that applies bias to the charge transfer transistor 15, the reset line (RX(i)) that applies bias to the reset transistor 18, and the row selection line (SEL(i)) that applies bias to the selection transistor 19 can be arranged along the row direction to extend basically parallel to each other.

[0036] refer to Figure 3 and Figure 4 , an image sensor according to example embodiments may include a sensor region SENSOR and a pad region PAD.

[0037] Arranged with unit pixels (see, for example, Figure 2 The sensor area SENSOR of the P) may include a light receiving area LRR that receives light to generate image data and a light shielding area LSR that does not receive light. The light shielding area LSR may be disposed between the light receiving area LRR and the pad area PAD. However, the inventive concept is not limited thereto. For example, the light receiving area LRR and the light shielding area LSR may be arranged in various forms.

[0038] In the sensor region SENSOR, an electrical signal generated by incident light may be output. In the sensor region SENSOR, for example, a plurality of unit pixel regions PX may be arranged in a matrix form.

[0039] The unit pixel region PX may include an active pixel region AP and a reference pixel region RP. The light receiving region LRR may be disposed in the active pixel region AP to convert incident light into an electrical signal. The reference pixel region RP may be disposed in the light shielding region LSR to output an electrical signal generated from an area on which light is not incident.

[0040] The unit pixel region PX may include a first pixel region PX1 and a second pixel region PX2 adjacent to each other. In the figure, it is shown that the first pixel region PX1 and the second pixel region PX2 are active pixel regions AP, but the inventive concept is not limited thereto. For example, one of the first pixel region PX1 and the second pixel region PX2 may be a reference pixel region RP, or both of the first pixel region PX1 and the second pixel region PX2 may be a reference pixel region RP.

[0041] In some example embodiments, the first pixel region PX1 may sense red light, and the second pixel region PX2 may sense blue light. For example, a first color filter 170a as a red color filter R may be disposed in the first pixel region PX1, and a second color filter 170b as a blue color filter B may be disposed in the second pixel region PX2. Figure 4 , the red filters R and the blue filters B can be arranged alternately.

[0042] The pad area PAD may include a conductive pad (see, for example, Figure 5 315), which is used to input the control signal and the photoelectric signal into the sensor area SENSOR and output the control signal and the photoelectric signal from the sensor area SENSOR.

[0043] The pad region PAD may be disposed around the light receiving region LRR to easily electrically connect to an external device. For example, the pad region PAD may be disposed along the periphery of the sensor region SENSOR. However, the inventive concept is not limited thereto. For example, the sensor region SENSOR and the pad region PAD may be arranged in various forms.

[0044] refer to Figures 3 to 7 , an image sensor according to example embodiments may include a substrate 100, a first photoelectric conversion layer 110, a well impurity layer 120, a first device isolation layer 132, a second device isolation layer 134, a storage node region 140, an anti-reflection layer 160, a first interlayer insulating structure 200, a first color filter 170a, a second color filter 170b, a first lower transparent electrode 410a, a second lower transparent electrode 410b, a second photoelectric conversion layer 420, an upper transparent electrode 430, a microlens 440, a conductive pad 315, and a second interlayer insulating structure 300.

[0045] The substrate 100 may include a first surface 100a and a second surface 100b opposite to each other. Hereinafter, light incident on the first surface 100a of the substrate 100 will be described.

[0046] The substrate 100 may be a structure in which a base substrate and an epitaxial layer are stacked. The substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a display glass substrate, and / or a semiconductor on insulator (SOI) substrate. However, the inventive concept is not limited thereto.

[0047] The first photoelectric conversion layer 110 may be formed on the substrate 100. The first photoelectric conversion layer 110 may generate photocharges proportional to the amount of light incident from the outside. For example, the first photoelectric conversion layer 110 may receive light and may convert the light into an electrical signal. The first photoelectric conversion layer 110 may include, for example, a photodiode.

[0048] The first photoelectric conversion layer 110 may be formed by doping the substrate 100 with impurities. For example, the first photoelectric conversion layer 110 may be formed by implanting n-type impurities into the substrate 100. In addition, there may be a difference in impurity concentration between the upper portion of the first photoelectric conversion layer 110 and the lower portion thereof, so that the first photoelectric conversion layer 110 may have a potential gradient. For example, the first photoelectric conversion layer 110 may be formed of a plurality of stacked impurity regions.

[0049] For ease of description, various transistors connected to the first photoelectric conversion layer 110 to process electrical signals are not shown in the figure. However, a portion of the substrate 100 may be a region in which various transistors are provided to process electrical signals generated from the first photoelectric conversion layer 110. For example, a transfer transistor (see, e.g., Figure 2 15), reset transistor (see, for example, Figure 2 18), a driving transistor (see, for example, Figure 2 17) or select transistors (see, for example, Figure 2 19 ) may be disposed in some portions of the first pixel region PX1 and the second pixel region PX2 to process an electrical signal generated from the first photoelectric conversion layer 110 .

[0050] The well impurity layer 120 may be formed adjacent to the first photoelectric conversion layer 110. For example, the well impurity layer 120 may be formed in a portion of the substrate 100 adjacent to the second surface 100b of the substrate 100. The well impurity layer 120 may be formed by doping the substrate 100 with impurities. For example, the well impurity layer 120 may be formed by doping the substrate 100 with impurities having a conductivity type opposite to that of the first photoelectric conversion layer 110. For example, the well impurity layer 120 may be formed by implanting p-type impurities.

[0051] The first device isolation layer 132 may define a unit pixel region PX in the sensor region SENSOR. That is, the first pixel region PX1 and the second pixel region PX2 may be defined by the first device isolation layer 132. The first device isolation layer 132 may extend from the first surface 100a of the substrate 100 to the second surface 100b of the substrate 100. The first device isolation layer 132 may surround each of the first pixel region PX1 and the second pixel region PX2. Therefore, the first pixel region PX1 and the second pixel region PX2 may be spaced apart from each other by the first device isolation layer 132.

[0052] The first device isolation layer 132 may be formed by patterning the substrate 100 to form a deep trench and then filling the deep trench with an insulating material. Therefore, the first device isolation layer 132 may extend from the first surface 100a of the substrate 100 to the second surface 100b of the substrate 100. In some example embodiments, the width of the first device isolation layer 132 may vary in a direction from the first surface 100a of the substrate 100 to the second surface 100b of the substrate 100 according to a patterning process.

[0053] The first device isolation layer 132 may be formed of an insulating material having a lower refractive index than the substrate 100. For example, when the substrate 100 is formed of silicon, the first device isolation layer 132 may be formed of a silicon oxide layer, a silicon nitride layer, an undoped polysilicon layer, air, or a combination thereof.

[0054] Therefore, the first device isolation layer 132 can refract light obliquely incident on the first photoelectric conversion layer 110. In addition, the first device isolation layer 132 can prevent the photocharge generated from a specific pixel due to the incident light from moving to an adjacent pixel region due to random drift. As a result, the first device isolation layer 132 can improve the light receiving efficiency of the first photoelectric conversion layer 110, and thus can improve the quality of image data.

[0055] The second device isolation layer 134 may define an active region in the unit pixel region PX. For example, the second device isolation layer 134 may be formed in a portion of the substrate 100 adjacent to the second surface 100 b of the substrate 100. In addition, the second device isolation layer 134 may be formed in the well impurity layer 120. Therefore, the second device isolation layer 134 may define a portion of the well impurity layer 120 in which the second device isolation layer 134 is not formed as an active region.

[0056] For example, the second device isolation layer 134 may define an active region, such as a storage node region 140, in the well impurity layer 120. The storage node region 140 may be formed by doping impurities having a conductivity opposite to that of the well impurity layer 120. For example, the storage node region 140 may be formed by implanting n-type impurities. The storage node region 140 may be connected to the second photoelectric conversion layer 420, and may store an electrical signal generated by the second photoelectric conversion layer 420.

[0057] The second device isolation layer 134 may be formed by patterning a substrate to form a shallow trench and then filling the shallow trench with an insulating material. The depth of the second device isolation layer 134 may be less than the depth of the first device isolation layer 132.

[0058] The anti-reflection layer 160 may be formed on the first surface 100a of the substrate 100. In some example embodiments, the anti-reflection layer 160 may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD. The anti-reflection layer 160 may reduce (or alternatively, prevent) reflection of light incident from the first surface 100a of the substrate 100 to the inside of the substrate 100.

[0059] refer to Figure 5 , the anti-reflection layer 160 may be conformally formed along the first surface 100a of the substrate 100, but the inventive concept is not limited thereto. For example, the anti-reflection layer 160 may cover the lower surface and sidewalls of the first color filter 170a and the second color filter 170b. The anti-reflection layer 160 may be formed of a single layer or multiple layers. In some embodiments, the anti-reflection layer 160 may be omitted.

[0060] The first interlayer insulating structure 200 may be formed on the first surface 100a of the substrate 100. The first interlayer insulating structure 200 may include a first insulating layer 210 and a first etch stop layer 220 sequentially stacked on the first surface 100a of the substrate 100.

[0061] The first insulating layer 210 may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD. The first insulating layer 210 may be formed to cover an upper surface of the anti-reflection layer 160.

[0062] The first insulating layer 210 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material having a dielectric constant lower than that of silicon oxide. The low-k dielectric material may include flowable oxide (FOX), doline silazane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphorescent glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorinated silicate glass (FSG), carbon-doped silicon oxide (CDO), dry gel, aerogel, amorphous fluorinated carbon, organic silicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymeric material, or a combination thereof. Hereinafter, the first insulating layer 210 will be described as including a low temperature oxide (LTO) as a silicon oxide. LTO refers to silicon oxide that can be formed at a low temperature of, for example, 100° C. to 200° C.

[0063] The first etch stop layer 220 may be formed on the first insulating layer 210. The first etch stop layer 220 may be formed on the first insulating layer 210 in the sensor region SENSOR and the pad region PAD.

[0064] The first etch stop layer 220 may include a material having an etching selectivity relative to the first lower transparent electrode 410a and the second lower transparent electrode 410b. For example, the first etch stop layer 220 may include silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or a combination thereof. Hereinafter, the first etch stop layer 220 will be described as including silicon nitride.

[0065] The first interlayer insulating structure 200 may include a first trench T1 and a second trench T2 formed in the first interlayer insulating structure 200 in the sensor region SENSOR. For example, the first trench T1 may be formed in the first interlayer insulating structure 200 in the first pixel region PX1, and the second trench T2 may be formed in the first interlayer insulating structure 200 in the second pixel region PX2.

[0066] The first trench T1 and the second trench T2 may be formed by etching a portion of the first interlayer insulating structure 200 in the sensor region SENSOR. In some embodiments, the bottom surface of the first trench T1 and the bottom surface of the second trench T2 may be lower than the lower surface of the first etch stop layer 220 relative to the first surface 100a of the substrate 100. Therefore, the sidewall of the first trench T1 may be defined by the inner sidewall of the first insulating layer 210 and the sidewall of the first etch stop layer 220. The first etch stop layer 220 may not be formed on the upper surface of the first insulating layer 210 defining the first trench T1 and the second trench T2.

[0067] The first color filter 170a and the second color filter 170b may be formed on the first surface 100a of the substrate 100. For example, the first color filter 170a may be formed in the first insulating layer 210 in the first pixel region PX1, and the second color filter 170b may be formed in the first insulating layer 210 in the second pixel region PX2.

[0068] In some example embodiments, the first color filter 170a and the second color filter 170b may absorb light of different wavelengths. Figure 4 As described above, the first color filter 170 a may be a red color filter R, and the second color filter 170 b may be a blue color filter B.

[0069] The first lower transparent electrode 410a and the second lower transparent electrode 410b may be formed on the first interlayer insulating structure 200. Therefore, the first color filter 170a may be interposed between the substrate 100 and the first lower transparent electrode 410a, and the second color filter 170b may be interposed between the substrate 100 and the second lower transparent electrode 410b.

[0070] In addition, the first lower transparent electrode 410a and the second lower transparent electrode 410b may be spaced apart from each other. For example, the first lower transparent electrode 410a may be formed on the first interlayer insulating structure 200 in the first pixel region PX1, and the second lower transparent electrode 410b may be formed on the first interlayer insulating structure 200 in the second pixel region PX2. The first etch stop layer 220 may be interposed between the first lower transparent electrode 410a and the second lower transparent electrode 410b.

[0071] The first lower transparent electrode 410a may fill the first trench T1 in the first interlayer insulating structure 200. The second lower transparent electrode 410b may fill the second trench T2 in the first interlayer insulating structure 200. The first etch stop layer 220 may contact the sidewalls of the first lower transparent electrode 410a and the sidewalls of the second lower transparent electrode 410b. In addition, the first etch stop layer 220 may be formed on the first insulating layer 210 between the first lower transparent electrode 410a and the second lower transparent electrode 410b. With respect to the first surface 100a of the substrate 100, the upper surface of the first lower transparent electrode 410a and the upper surface of the second lower transparent electrode 410b may be higher than the lower surface of the first etch stop layer 220.

[0072] With respect to the first surface 100a of the substrate 100, the height of the upper surface of the first lower transparent electrode 410a and the height of the upper surface of the second lower transparent electrode 410b may be substantially equal to the height of the upper surface of the first etch stop layer 220. Figure 6, a first height H1 from the first surface 100 a of the substrate 100 to the upper surface of the first lower transparent electrode 410 a may be substantially equal to a second height H2 from the first surface 100 a of the substrate 100 to the upper surface of the first etch stop layer 220 .

[0073] The first lower transparent electrode 410a and the second lower transparent electrode 410b may be formed by a planarization process using the first etch stop layer 220 as a barrier layer. Figures 14 to 16 Describe in detail.

[0074] The first lower transparent electrode 410a and the second lower transparent electrode 410b may include a material having an etching selectivity with respect to the first etch stop layer 220. The first lower transparent electrode 410a and the second lower transparent electrode 410b may include a transparent conductive material. For example, the first lower transparent electrode 410a and the second lower transparent electrode 410b may include indium tin oxide (ITO), zinc oxide (ZnO), tin dioxide (SnO 2 ), antimony-doped tin oxide (ATO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), titanium dioxide (TiO 2 ), fluorine-doped tin oxide (FTO), or a combination thereof. Hereinafter, it will be described that the first lower transparent electrode 410a and the second lower transparent electrode 410b include ITO.

[0075] The first lower transparent electrode 410a and the second lower transparent electrode 410b may be formed at the same process stage. Therefore, the first lower transparent electrode 410a and the second lower transparent electrode 410b may include the same material. For example, the first lower transparent electrode 410a and the second lower transparent electrode 410b may include the same ITO.

[0076] The composition ratio of the elements constituting the first lower transparent electrode 410a and the second lower transparent electrode 410b can be adjusted according to the etching selectivity of the first lower transparent electrode 410a and the second lower transparent electrode 410b. For example, the composition ratio of indium (In), tin (Sn) and oxygen (O) in ITO included in the first lower transparent electrode 410a and the second lower transparent electrode 410b can be variously adjusted.

[0077] In some example embodiments, the thickness of the first lower transparent electrode 410a and the thickness of the second lower transparent electrode 410b may be greater than the thickness of the first etch stop layer 220. For example, referring to Figure 6 , a first thickness D1 of the first lower transparent electrode 410 a may be greater than a second thickness D2 of the first etch stop layer 220 .

[0078] The second thickness D2 of the first etch stop layer 220 may be In some example embodiments, the second thickness D2 of the first etch stop layer 220 may be to within the range.

[0079] In some example embodiments, the upper surfaces of the first lower transparent electrode 410a and the second lower transparent electrode 410b may be concave. Figure 7 , the upper surface 410US of the first lower transparent electrode 410a may have an upward concave shape (or a downward convex shape). This may be caused by the characteristics of the planarization process used to form the first lower transparent electrode 410a and the second lower transparent electrode 410b. For example, due to the depression phenomenon generated during the planarization process, the upper surface 410US of the first lower transparent electrode 410a may be concave.

[0080] In some example embodiments, the height of the uppermost surface of the first lower transparent electrode 410a and the height of the uppermost surface of the second lower transparent electrode 410b relative to the first surface 100a of the substrate 100 may be substantially equal to the height of the upper surface of the first etch stop layer 220. Figure 7 , a third height H3 from the first surface 100a of the substrate 100 to the highest point of the upper surface 410US of the first lower transparent electrode 410a adjacent to the first etch stop layer 220 may be substantially equal to a second height H2 from the first surface 100a of the substrate 100 to the upper surface of the first etch stop layer 220.

[0081] The second photoelectric conversion layer 420 may be formed on the first lower transparent electrode 410a and the second lower transparent electrode 410b. For example, the second photoelectric conversion layer 420 may extend along the upper surface of the first lower transparent electrode 410a, the upper surface of the second lower transparent electrode 410b, and the upper surface of the first etch stop layer 220 in the sensor region SENSOR.

[0082] The second photoelectric conversion layer 420 may generate photocharges in proportion to the amount of light incident from the outside. The second photoelectric conversion layer 420 may receive light and may convert the light into an electrical signal.

[0083] The second photoelectric conversion layer 420 may be Figure 2 The second photoelectric conversion layer 420 corresponds to the phototransistor 11. For example, the second photoelectric conversion layer 420 may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), an organic photodiode (OPD), a quantum dot (QD) or a combination thereof. Hereinafter, the second photoelectric conversion layer 420 will be described as including an organic photodiode.

[0084] Upper transparent electrode 430 may be formed on second photoelectric conversion layer 420. Thus, second photoelectric conversion layer 420 may be interposed between first lower transparent electrode 410a and upper transparent electrode 430 and between second lower transparent electrode 410b and upper transparent electrode 430.

[0085] The upper transparent electrode 430 may extend across the first pixel region PX1 and the second pixel region PX2 , but the inventive concept is not limited thereto. For example, the upper transparent electrode 430 may be formed in each of the first pixel region PX1 and the second pixel region PX2 , respectively.

[0086] The upper transparent electrode 430 may include a transparent conductive material. For example, the upper transparent electrode 430 may include indium tin oxide (ITO), zinc oxide (ZnO), tin dioxide (SnO 2 ), antimony-doped tin oxide (ATO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), titanium dioxide (TiO 2 ), fluorine-doped tin oxide (FTO), or a combination thereof. The upper transparent electrode 430 may include the same material as the first and second lower transparent electrodes 410a and 410b or a different material.

[0087] The microlens 440 may be formed on the upper transparent electrode 430. The microlens 440 may have a convex shape and may have a predetermined radius of curvature. Thus, the microlens 440 may collect light incident on the first pixel region PX1 and the second pixel region PX2.

[0088] The microlens 440 may include an organic material such as a light-transmitting resin, but is not limited thereto.

[0089] In some example embodiments, the second photoelectric conversion layer 420 may sense green light. For example, light of a green wavelength in incident light collected by the microlens 440 may be adsorbed in the second photoelectric conversion layer 420. Thus, the second photoelectric conversion layer 420 may provide an electrical signal for green light. Light of other wavelengths except green light may pass through the second photoelectric conversion layer 420.

[0090] In some example embodiments, the first photoelectric conversion layer 110 may sense red light or blue light. For example, light passing through the second photoelectric conversion layer 420 may pass through the first color filter 170a and may provide red light to the first photoelectric conversion layer 110 in the first pixel region PX1. In addition, for example, light passing through the second photoelectric conversion layer 420 may pass through the second color filter 170b and may provide blue light to the first photoelectric conversion layer 110 in the second pixel region PX2. Therefore, the first photoelectric conversion layer 110 in the first pixel region PX1 may provide an electrical signal for red light, and the first photoelectric conversion layer 110 in the second pixel region PX2 may provide an electrical signal for blue light.

[0091] The conductive pad 315 may be formed on the substrate 100 in the pad area PAD. For example, the conductive pad 315 may be formed on the first wiring 305 formed on the first surface 100a of the substrate 100 in the pad area PAD.

[0092] The conductive pad 315 and the first wiring 305 may include metal, such as copper (Cu) or aluminum (Al), but are not limited thereto.

[0093] In some embodiments, the conductive pad 315 may fill the third trench T3 in the substrate 100 of the pad region PAD. Figure 5 The first wiring 305 may conformally extend along the sidewall and bottom surface of the third trench T3 , and the conductive pad 315 may fill the third trench T3 . The first wiring 305 may be disposed on the anti-reflection layer 160 .

[0094] The second interlayer insulating structure 300 may be formed on the second surface 100b of the substrate 100. The second interlayer insulating structure 300 may include three insulating layers, for example, a second insulating layer 310, a third insulating layer 320, and a fourth insulating layer 330 sequentially stacked on the second surface 100b of the substrate 100. In some example embodiments, the second interlayer insulating structure 300 may include more or less than three insulating layers. The second insulating layer 310, the third insulating layer 320, and the fourth insulating layer 330 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material having a dielectric constant lower than that of silicon oxide.

[0095] The image sensor according to example embodiments may further include a through hole 150. The through hole 150 may extend through the substrate 100 to electrically connect a corresponding one of the first lower transparent electrode 410a and the second lower transparent electrode 410b to the storage node region 140. For example, the through hole 150 may be electrically connected to the storage node region 140 through the second contact 340 and the second wiring 350 in the second interlayer insulating structure 300. Thus, the electrical signal generated by the second photoelectric conversion layer 420 may be stored in the storage node region 140.

[0096] In some example embodiments, the through hole 150 may include a conductor 152 and a fifth insulating layer 154. The conductor 152 of the through hole 150 may pass through the substrate 100 to extend from the first surface 100a of the substrate 100 to the second surface 100b of the substrate 100. The fifth insulating layer 154 of the through hole 150 may cover the sidewall of the conductor 152 to insulate the conductor 152 from the substrate 100.

[0097] In some example embodiments, the first lower transparent electrode 410a and the second lower transparent electrode 410b may be electrically connected to the storage node region 140 through a contact that does not pass through the substrate 100. For example, in the case where the well impurity layer 120 or the storage node region 140 is formed in a portion of the substrate 100 adjacent to the first surface 100a of the substrate 100, the first lower transparent electrode 410a and the second lower transparent electrode 410b may be electrically connected to the storage node region 140 through the first contact 230 or the like.

[0098] Figure 8 is a schematic cross-sectional view of an image sensor according to example embodiments. Fig. 9 yes Figure 8 The third region S3 of FIG. will not be described in detail or will only be briefly mentioned with reference to FIG. Figures 1 to 7 The same elements as those described.

[0099] refer to Figure 8 and Fig. 9 , the image sensor according to example embodiments may further include a second etch stop layer.

[0100] The second etch stop layer 240 may be formed in the first insulating layer 210. The second etch stop layer 240 may be formed in the first insulating layer 210 in the sensor region SENSOR and the first insulating layer 210 in the pad region PAD.

[0101] For example, the first insulating layer 210 may include a first layer 210a below the second etch stop layer 240 and a second layer 210b above the second etch stop layer 240. The first layer 210a and the second layer 210b of the first insulating layer 210 may include the same material or different materials.

[0102] The second etch stop layer 240 may include a material having an etch selectivity relative to the first insulating layer 210. For example, the second etch stop layer 240 may include silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or a combination thereof. Hereinafter, the second etch stop layer 240 will be described as including silicon nitride.

[0103] With respect to the first surface 100a of the substrate 100, the height of the lower surface of the first lower transparent electrode 410a and the height of the lower surface of the second lower transparent electrode 410b may be the same as the height of the lower surface of the second etch stop layer 240. Fig. 9 , a fourth height H4 from the first surface 100 a of the substrate 100 to the lower surface of the first lower transparent electrode 410 a may be substantially equal to a fifth height H5 from the first surface 100 a of the substrate 100 to the lower surface of the second etch stop layer 240 .

[0104] In some embodiments, the fourth height H4 may be different from the fifth height H5. For example, the fourth height H4 may be smaller than or larger than the fifth height H5 according to the etching selectivity of the second etch stop layer 240 relative to the first insulating layer 210. For example, the fourth height H4 may be smaller than or larger than the fifth height H5 according to the characteristics of the etching process used to form the first trench T1.

[0105] Figures 10 to 17 1 is a diagram showing various stages in a method of manufacturing an image sensor according to an example embodiment. Figures 1 to 7 The same elements as those described.

[0106] refer to Fig.10 , a substrate 100 including a sensor area SENSOR and a pad area PAD may be provided, and a first layer 210 a may be formed on the substrate 100 .

[0107] For example, first, a through hole 150 and a first device isolation layer 132 passing through the substrate 100, a first photoelectric conversion layer 110 and a well impurity layer 120 located in the substrate 100, a second device isolation layer 134 adjacent to the second surface 100 b of the substrate 100, a storage node region 140 in the well impurity layer 120, a second interlayer insulating structure 300 on the second surface 100 b of the substrate 100, and a second contact 340 and a second wire 350 located in the second interlayer insulating structure 300 and connected to the storage node region 140 can be formed.

[0108] Thereafter, the first layer 210a may be formed on the first surface 100a of the substrate 100. The first layer 210a may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD.

[0109] The first layer 210a may include an insulating material. For example, the first layer 210a may include a low temperature oxide (LTO).

[0110] In some example embodiments, the first layer 210a may be formed to cover the first color filter 170a and the second color filter 170b. For example, the first color filter 170a may be formed in the first layer 210a in the first pixel region PX1, and the second color filter 170b may be formed in the first layer 210a in the second pixel region PX2.

[0111] In some example embodiments, before forming the first layer 210a, an anti-reflection layer 160 may be formed on the first surface 100a of the substrate 100. The anti-reflection layer 160 may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD.

[0112] In some example embodiments, before forming the first layer 210a, a conductive pad 315 may be formed on the substrate 100 in the pad region PAD. The conductive pad 315 may be formed on the first wiring 305 formed on the first surface 100a of the substrate 100 in the pad region PAD (i.e., on the anti-reflection layer 160). Therefore, the first layer 210a may be formed to cover the conductive pad 315.

[0113] In some example embodiments, after forming the first layer 210a, the first contact 230 may be formed. The first contact 230 may pass through the first layer 210a to be connected to the via 150.

[0114] refer to Fig.11 , the second layer 210 b and the first etch stop layer 220 may be sequentially formed on the first layer 210 a .

[0115] The second layer 210b may be formed on the first layer 210a. The second layer 210b may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD. Therefore, the first insulating layer 210 including the first layer 210a and the second layer 210b may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD. In some example embodiments, the first insulating layer 210 may cover the first contact 230.

[0116] The second layer 210b may include an insulating material. For example, the second layer 210b may include LTO.

[0117] The first etch stop layer 220 may be formed on the first insulating layer 210. The first etch stop layer 220 may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD. Therefore, the first interlayer insulating structure 200 including the first insulating layer 210 and the first etch stop layer 220 may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD.

[0118] The first etch stop layer 220 may include a material having an etch selectivity with respect to a transparent electrode layer 410 to be formed later. For example, the first etch stop layer 220 may include silicon nitride.

[0119] The first etch stop layer 220 may have a sufficient thickness to be used as a barrier layer in a subsequent planarization process. For example, the second thickness D2 of the first etch stop layer 220 may be In some example embodiments, the second thickness D2 of the first etch stop layer 220 may be to within the range.

[0120] refer to Fig.12 and Fig.13 , first trenches T1 and second trenches T2 may be formed in the first interlayer insulating structure 200 . Fig.13 yes Fig.12 An enlarged view of the fourth region S4.

[0121] For example, a portion of the first interlayer insulating structure 200 in the first pixel region PX1 may be etched to form a first trench T1 , and a portion of the first interlayer insulating structure 200 in the second pixel region PX2 may be etched to form a second trench T2 .

[0122] In some example embodiments, etching of a portion of the first interlayer insulating structure 200 may be performed until the first contact 230 is exposed. Thus, the first trench T1 and the second trench T2 exposing the first contact 230 may be formed.

[0123] In some example embodiments, the bottom surface of the first trench T1 and the bottom surface of the second trench T2 may be lower than the lower surface of the first etch stop layer 220 relative to the first surface 100a of the substrate 100. Fig.13 , a fourth height H4 from the first surface 100a of the substrate 100 to the bottom surface of the first trench T1 may be smaller than a fifth height H5 from the first surface 100a of the substrate 100 to the bottom surface of the first etch stop layer 220. Therefore, the first trench T1 and the second trench T2 may pass through the first etch stop layer 220.

[0124] refer to Fig.14 , a transparent electrode layer 410 may be formed on the first interlayer insulating structure 200 .

[0125] The transparent electrode layer 410 may be formed on the first interlayer insulating structure 200 in the sensor region SENSOR and the first interlayer insulating structure 200 in the pad region PAD.

[0126] The transparent electrode layer 410 may be formed to completely fill the first trench T1 and the second trench T2. For example, the transparent electrode layer 410 may be formed on the first interlayer insulating structure 200 so that the lowermost portion of the upper surface of the transparent electrode layer 410 is located higher than the upper surface of the first etch stop layer 220 relative to the first surface 100a of the substrate 100.

[0127] The transparent electrode layer 410 may include a material having an etching selectivity with respect to the first etch stop layer 220. The transparent electrode layer 410 may include a transparent conductive material. For example, the transparent electrode layer 410 may include indium tin oxide (ITO).

[0128] refer to Figures 15 to 17 , a planarization process using the first etch stop layer 220 as a barrier layer may be performed. Fig.16 and Fig.17 yes Fig.15 An enlarged view of the fifth region S5.

[0129] For example, a planarization process may be performed on the transparent electrode layer 410 until the first etch stop layer 220 is exposed, so that a first lower transparent electrode 410 a filling the first trench T1 and a second lower transparent electrode 410 b filling the second trench T2 may be formed.

[0130] Therefore, the height of the upper surface of the first lower transparent electrode 410a and the height of the upper surface of the second lower transparent electrode 410b relative to the first surface 100a of the substrate 100 may be substantially equal to the height of the upper surface of the first etch stop layer 220. Fig.16 , a height H1 of an upper surface of the first lower transparent electrode 410 a may be substantially equal to a second height H2 of an upper surface of the first etch stop layer 220 .

[0131] The planarization process may include, for example, a chemical mechanical polishing (CMP) process. In some example embodiments, the etching selectivity of the transparent electrode layer 410 relative to the first etch stop layer 220 may be 20 or more. Therefore, during the formation of the first lower transparent electrode 410a and the second lower transparent electrode 410b, it may be difficult to etch the first etch stop layer 220.

[0132] The CMP process may be performed using a slurry having different removal rates with respect to the first etch stop layer 220 and the transparent electrode layer 410. The slurry may include ceria, silicon dioxide, aluminum oxide, etc., but is not limited thereto.

[0133] The CMP process can be performed in an environment of pH 1 to pH 5.

[0134] In some example embodiments, the thickness of the first lower transparent electrode 410a and the thickness of the second lower transparent electrode 410b may be greater than the thickness of the first etch stop layer 220. For example, referring to Fig.16 , a first thickness D1 of the first lower transparent electrode 410 a may be greater than a second thickness D2 of the first etch stop layer 220 .

[0135] In some example embodiments, after the planarization process is performed, the second thickness D2 of the first etch stop layer 220 may be to within the range.

[0136] In some example embodiments, the upper surface of the first lower transparent electrode 410a and the upper surface of the second lower transparent electrode 410b may be concave. Fig.17 , the upper surface 410US of the first lower transparent electrode 410a may have an upward concave shape (or a downward convex shape). For example, due to a recess phenomenon generated during a planarization process, the upper surface 410US of the first lower transparent electrode 410a may be concave.

[0137] In some example embodiments, the height of the uppermost surface of the first lower transparent electrode 410a and the height of the uppermost surface of the second lower transparent electrode 410b relative to the first surface 100a of the substrate 100 may be substantially equal to the height of the upper surface of the first etch stop layer 220. Fig.17 , relative to the first surface 100 a of the substrate 100 , a third height H3 of the uppermost surface of the first lower transparent electrode 410 a may be substantially equal to a second height H2 of the upper surface of the first etch stop layer 220 .

[0138] Reference again Figure 5 , a second photoelectric conversion layer 420, an upper transparent electrode 430, and a microlens 440 may be formed on the first lower transparent electrode 410a and the second lower transparent electrode 410b.

[0139] The second photoelectric conversion layer 420 may be formed to extend along the upper surfaces of the first lower transparent electrode 410a, the second lower transparent electrode 410b, and the first etch stop layer 220 in the sensor region SENSOR. The second photoelectric conversion layer 420 may include, for example, an organic photodiode.

[0140] An upper transparent electrode 430 may be formed on the second photoelectric conversion layer 420. The upper transparent electrode 430 may include, for example, ITO.

[0141] The microlens 440 may be formed on the upper transparent electrode 430. The microlens 440 may include an organic material, such as a light-transmitting resin.

[0142] In order to form a transparent electrode in the groove formed in the sensor area, a transparent electrode layer may be formed to fill the groove, and then a planarization process may be performed. However, since the transparent electrode layer only fills the groove formed in the sensor area, a step may be formed between the sensor area and the pad area. In the subsequent planarization process of forming the lower transparent electrode, a residue of the transparent electrode layer may remain in the pad area due to the step.

[0143] In order to reduce (or alternatively, prevent) the above problems, the transparent electrode layer in the pad region may be first removed by a photolithography process. However, this method may increase the number of processing steps and, therefore, may reduce the productivity of the image sensor.

[0144] In contrast, in the image sensor and the method of manufacturing the same according to example embodiments, the first etch stop layer 220 may be used as a barrier layer to reduce or remove the step between the sensor region SENSOR and the pad region PAD in the planarization process of the transparent electrode layer 410. Therefore, the process for manufacturing the image sensor may be simplified, so that the productivity of the image sensor may be improved.

[0145] Figures 18 to 20 1 is a diagram showing various stages in a method of manufacturing an image sensor according to an example embodiment. Figures 1 to 17 The same elements as those described.

[0146] Fig.18 Shows Fig.10 The process stage following the process stage shown in .

[0147] refer to Fig.18 , the second etch stop layer 240 , the second layer 210 b , and the first etch stop layer 220 may be sequentially formed on the first layer 210 a .

[0148] The second etch stop layer 240 may be formed on the first layer 210 a . The second etch stop layer 240 may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD. In some embodiments, the second etch stop layer 240 may cover the first contact 230 .

[0149] Therefore, the first insulating layer 210 may include a first layer 210a below the second etch stop layer 240 and a second layer 210b above the second etch stop layer 240. A first interlayer insulating structure 200 including the first insulating layer 210, the first etch stop layer 220, and the second etch stop layer 240 may be formed on the substrate 100 of the sensor region SENSOR and the substrate 100 of the pad region PAD.

[0150] The second etch stop layer 240 may include a material having an etch selectivity with respect to the first insulating layer 210. For example, the second etch stop layer 240 may include silicon nitride.

[0151] refer to Fig.19 and Fig. 20 , the first trench T1 and the second trench T2 may be formed in the first interlayer insulating structure 200 in the sensor region SENSOR. Fig. 20 yes Fig.19 An enlarged view of the sixth region S6.

[0152] For example, a portion of the first interlayer insulating structure 200 may be etched through an etching process using the second etch stop layer 240 as a barrier layer to form the first trench T1 and the second trench T2 .

[0153] With respect to the first surface 100a of the substrate 100, the height of the bottom surface of the first trench T1 and the height of the bottom surface of the second trench T2 may be equal to the height of the lower surface of the second etch stop layer 240. Fig.19 , relative to the first surface 100 a of the substrate 100 , a fourth height H4 of the bottom surface of the first trench T1 may be substantially equal to a fifth height H5 of the lower surface of the second etch stop layer 240 .

[0154] In some embodiments, the fourth height H4 may be different from the fifth height H5. For example, the fourth height H4 may be smaller than or larger than the fifth height H5 according to the etching selectivity of the second etch stop layer 240 relative to the first insulating layer 210. In addition, the fourth height H4 may be smaller than or larger than the fifth height H5 according to the characteristics of the etching process used to form the first trench T1.

[0155] While example embodiments of the inventive concept have been shown and described with reference to certain example embodiments of the inventive concept, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. An image sensor, comprising: A substrate, comprising a sensor area and a pad area adjacent to the sensor area; an insulating layer on the substrate; a lower transparent electrode located on the insulating layer in the sensor region; as well as an etch stop layer, located on the insulating layer in both the sensor region and the pad region, the etch stop layer comprising a material having an etching selectivity relative to the lower transparent electrode, wherein: The height of the uppermost portion of the lower transparent electrode relative to the upper surface of the substrate is equal to the height of the etch stop layer relative to the upper surface of the substrate, and the lower surface of the lower transparent electrode is arranged to be lower than the lower surface of the etch stop layer.

2. The image sensor according to claim 1, wherein: A height of a portion of an upper surface of the lower transparent electrode adjacent to the etch stop layer is equal to a height of the etch stop layer relative to an upper surface of the substrate.

3. The image sensor according to claim 1, wherein: The thickness of the lower transparent electrode is greater than the thickness of the etching stop layer.

4. The image sensor according to claim 1, wherein: The etch stop layer contacts a sidewall of the lower transparent electrode.

5. The image sensor according to claim 1, wherein: The insulating layer includes low temperature oxide (LTO).

6. The image sensor according to claim 1, wherein: The lower transparent electrode includes indium tin oxide (ITO).

7. The image sensor according to claim 1, further comprising: A photoelectric conversion layer, on the lower transparent electrode; an upper transparent electrode, on the photoelectric conversion layer; as well as A microlens is on the upper transparent electrode.

8. The image sensor according to claim 1, further comprising: A color filter is located in the insulating layer below the lower transparent electrode.

9. An image sensor, comprising: A substrate, comprising a sensor area and a pad area, wherein the sensor area comprises a first pixel area and a second pixel area; an insulating layer on the substrate; a first lower transparent electrode, located on the insulating layer in the first pixel area; a second lower transparent electrode, located on the insulating layer in the second pixel area; as well as a first etch stop layer, located on the insulating layer in the sensor region and the pad region, so that in the sensor region, the first etch stop layer is located on the insulating layer between the first lower transparent electrode and the second lower transparent electrode, and the first etch stop layer includes a material having an etching selectivity relative to the first lower transparent electrode and the second lower transparent electrode, wherein An uppermost portion of each of the first lower transparent electrode and the second lower transparent electrode relative to an upper surface of the substrate is coplanar with an upper surface of the first etch stop layer relative to the substrate, and a lower surface of each of the first lower transparent electrode and the second lower transparent electrode is arranged to be lower than a lower surface of the first etch stop layer.

10. The image sensor according to claim 9, wherein: The first etch stop layer includes silicon nitride.

11. The image sensor according to claim 9, further comprising: a first color filter located in the insulating layer below the first lower transparent electrode; as well as A second color filter is located in the insulating layer below the second lower transparent electrode, wherein: The second color filter absorbs light having a wavelength different from the wavelength of light absorbed by the first color filter.

12. The image sensor according to claim 9, wherein: The insulating layer includes silicon oxide.

13. The image sensor according to claim 12, further comprising: A second etch stop layer, in the insulating layer, the second etch stop layer comprises silicon nitride, wherein: The insulating layer includes a first layer below the second etch stop layer relative to the substrate and a second layer above the second etch stop layer.

14. An image sensor, comprising: A substrate, comprising a sensor area and a pad area adjacent to the sensor area; a first photoelectric conversion layer in a portion of the substrate associated with the sensor region; an interlayer insulating structure, on the substrate, the interlayer insulating structure comprising an insulating layer and an etch stop layer on the insulating layer, the etch stop layer being located on the insulating layer in both the sensor region and the pad region; a trench in a portion of the interlayer insulating structure associated with the sensor region; a lower transparent electrode in the groove, wherein a height of an uppermost portion of the lower transparent electrode relative to an upper surface of the substrate is equal to a height of the etch stop layer relative to an upper surface of the substrate, and a lower surface of the lower transparent electrode is arranged to be lower than a lower surface of the etch stop layer; and A second photoelectric conversion layer, on the lower transparent electrode, Wherein, the etching stop layer includes a material having etching selectivity relative to the lower transparent electrode.

15. The image sensor according to claim 14, wherein: The upper surface of the lower transparent electrode relative to the substrate is higher than the lower surface of the etching stop layer relative to the substrate.

16. The image sensor according to claim 14, wherein: The upper surface of the lower transparent electrode is concave.

17. The image sensor according to claim 14, wherein: The second photoelectric conversion layer includes an organic photodiode.

18. The image sensor according to claim 14, further comprising: A color filter is located in the insulating layer below the lower transparent electrode.

19. The image sensor according to claim 18, wherein: The trench is located in the interlayer insulating structure on the color filter.

20. The image sensor according to claim 14, further comprising: A through hole passes through the substrate and is electrically connected to the lower transparent electrode.

Images