Compensation circuit for generating read / program / erase voltages

Abstract

The compensation circuit may include a reference current generating circuit including a first transistor configured to transmit a first width of a first current. The reference generating circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generating circuit including a second transistor configured to transmit a second width of a second current. The second transistor may be selected from a first group of transistors based on a code. The first group of transistors may have a width proportional to the first width. The compensation current generating circuit may output a compensation current having an amplitude selected in proportion to the amplitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage whose amplitude is based on the amplitude of the second current and the second width.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0066044 filed on June 8, 2018 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the inventive concepts disclosed herein relate to electronic circuits, and more particularly, to electronic circuits included in a memory device. Background Art

[0004] As information devices such as computers, mobile phones, and smartphones develop and progress, a large amount of information may be stored in and processed by the information devices. Therefore, higher performance memory devices may be used as components of information devices. Since semiconductor memories can operate at low power, semiconductor memories can be used in memory devices.

[0005] Examples of semiconductor memory include volatile memory and non-volatile memory. Examples of volatile memory may include static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. Examples of non-volatile memory include flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), etc.

[0006] A semiconductor memory may include a memory cell for storing data. The data stored in the memory cell may be read as a voltage of a specific magnitude is supplied to the memory cell. The characteristics of the memory cell may be affected by conditions such as temperature. Therefore, in order to accurately sense (read / program / erase) the data stored in the memory cell, the magnitude of the voltage supplied has a magnitude that may be determined in consideration of the conditions that have an influence on the memory cell. Summary of the invention

[0007] Some embodiments of the inventive concept may provide an electronic circuit configured to generate a voltage for sensing data stored in a memory device.

[0008] According to some embodiments, a compensation circuit may be provided. The compensation circuit may include a reference current generating circuit, a compensation current generating circuit, a current mirror circuit, and an output transistor. The reference current generating circuit may include a first transistor configured to transmit a first width of a first current, and may be configured to output a reference current based on the first current. The compensation current generating circuit may include a second transistor of a first width selected from a first group of transistors based on a code. The first group of transistors may have a width proportional to the first width. The compensation current generating circuit may be configured to output a compensation current having an amplitude selected in proportion to the amplitude of the reference current based on the second current. The current mirror circuit may be configured to output a compensation voltage having an amplitude based on the amplitude of the second current. The output transistor may be configured to output a sensing voltage based on the compensation voltage. The code may have a first value, a second value, and a third value. The difference between the first value and the second value may be the same as the difference between the second value and the third value. The difference between the first amplitude of the voltage output based on the first value and the second amplitude of the voltage output based on the first value may correspond to the difference between the second amplitude and the third amplitude of the voltage output based on the third value.

[0009] According to some embodiments, a compensation circuit may be provided. The compensation circuit may include a compensation current generating circuit, wherein the compensation current generating circuit is configured to output a reference current generating circuit of a fixed amplitude. The compensation circuit may include a compensation current generating circuit, wherein the compensation current generating circuit is configured to output a compensation current having an amplitude selected in proportion to the amplitude of the reference current based on the code. The compensation circuit may include a current mirror circuit, which is configured to output a first current to the reference current generating circuit based on the reference current, output a second current based on the compensation current, and output a compensation voltage based on the first current and the second current. The compensation circuit may include an output transistor configured to output a sensing voltage based on the compensation voltage. The amplitude of the sensing voltage may be associated with the amplitude of the second current, so that when the code is a reference value, the amplitude of the sensing voltage is the reference amplitude, and when the value of the code increases the reference value, the amplitude of the second current increases the reference amplitude.

[0010] According to some embodiments, a voltage generating circuit may be provided. The voltage generating circuit may include a compensation circuit configured to output a compensation voltage having an amplitude based on the code based on the first temperature-dependent voltage and based on the second temperature-dependent voltage. The first temperature-dependent voltage may have an amplitude that varies with temperature, and the second temperature-dependent voltage may have an amplitude that is uniform regardless of temperature. The voltage generating circuit may include an output transistor configured to output a sensing voltage having an amplitude based on the amplitude of the compensation voltage. The voltage generating circuit may be configured to generate a sensing voltage having an amplitude that is proportional to the code value and associated with a difference between the amplitude of the first temperature-dependent voltage and the amplitude of the second temperature-dependent voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present inventive concept will become apparent by describing in detail example embodiments of the present inventive concept with reference to the attached drawings.

[0012] Figure 1 is a circuit diagram illustrating a read voltage generating circuit according to some embodiments of the inventive concept.

[0013] Figure 2 is a diagram showing some embodiments of the present invention. Figure 1 A block diagram of an example configuration of a compensation circuit.

[0014] Figure 3 is a diagram showing some embodiments of the present invention. Figure 1 A circuit diagram of an example configuration of a compensation circuit.

[0015] Figure 4 is a circuit diagram illustrating a read voltage generating circuit according to some embodiments of the inventive concept.

[0016] Figure 5 is a diagram showing some embodiments of the present invention. Figure 4 A block diagram of an example configuration of a compensation circuit.

[0017] Figure 6 is a diagram showing some embodiments of the present invention. Figure 4 A circuit diagram of an example configuration of a compensation circuit.

[0018] Figure 7 is a diagram showing some embodiments of the present invention. Figure 4 A circuit diagram of an example configuration of a compensation circuit.

[0019] Figure 8 is a diagram showing some embodiments of the present invention. Figure 7 A circuit diagram of an example configuration of a compensation current generating circuit.

[0020] Fig. 9 It is used to describe some embodiments of the present invention. Figure 8 A circuit diagram of an example operation of a compensation current generating circuit.

[0021] Fig.10 It is used to describe some embodiments of the present invention. Figure 8 A circuit diagram of an example operation of a compensation current generating circuit.

[0022] Fig.11 It is used to describe some embodiments of the present invention. Figure 8 A circuit diagram of an example operation of a compensation current generating circuit.

[0023] Fig.12 is a diagram showing some embodiments of the present invention. Figure 4 A graph of the voltage received by the compensation circuit.

[0024] Fig.13 FIG. 1 is a diagram showing a method of performing a selection operation according to some embodiments of the present invention. Figure 4 A graph of the read voltage.

[0025] Fig.14 The following are some examples of the present invention. Figure 1 and / or Figure 4 A graph of the voltage output by the read voltage generating circuit.

[0026] Fig.15 The following are some examples of the present invention. Figure 1 and / or Figure 4 A graph of the voltage output by the read voltage generating circuit.

[0027] Fig.16 Some embodiments of the present invention include Figure 1 and / or Figure 4 Block diagram of an example memory system with a read voltage generation circuit. DETAILED DESCRIPTION

[0028] Some embodiments of the inventive concept may be described in detail and clearly to such an extent that those having ordinary skill in the art can easily implement the inventive concept.

[0029] As used herein, the term "width" may refer to the width of a transistor channel. That is, the width may refer to the length in a direction (e.g., a vertical direction) that intersects the direction in which charge is transferred in the transistor channel. A transistor may be configured to have a width of a particular size.

[0030] As used herein, the term "code" may refer to data represented in the form of a binary number. An n-bit code may be represented by "n" consecutive logical values ​​(logical value "1" or logical value "0"). For example, the values ​​of a 2-bit code may include "00", "01", "10", and "11".

[0031] As used herein, the expression “the voltage level is proportional to the code value” or “the voltage level varies linearly with the code value” may be used. The voltage level being proportional to the code value or varying linearly with the code value may refer to the difference between the voltage amplitude corresponding to the value of the “qth” code of the “n” codes and the voltage amplitude corresponding to the value of the “q+1th” code being substantially equal to the difference between the voltage amplitude corresponding to the value of the “q+1th” code and the voltage amplitude corresponding to the value of the “q+2th” code (q is a natural number).

[0032] For example, in an embodiment where the difference between the magnitude of the voltage corresponding to the code value "000" and the magnitude of the voltage corresponding to the code value "001" is substantially equal to the difference between the magnitude of the voltage corresponding to the code value "001" and the magnitude of the voltage corresponding to the code value "010", the voltage magnitude may be proportional to the code value in the range of code values ​​"000" to "010". Alternatively, the voltage magnitude may vary linearly with the code value in the range of code values ​​"000" to "010". However, the two values ​​being substantially equal to each other may include an embodiment where the two values ​​are not completely equal to each other but there is only a slight difference between the two values, as well as an embodiment where the two values ​​are completely equal to each other.

[0033] Figure 1 is a circuit diagram showing a read voltage generating circuit according to some embodiments of the inventive concept. Figure 1 The read voltage generating circuit 1000 configured to generate a read voltage Vread1 for reading data is described, however, it can be understood that the read voltage generating circuit 1000 can generate not only the read voltage Vread1, but also other voltages for various purposes in some embodiments. For example, the read voltage generating circuit 1000 can generate a voltage for sensing (reading, programming, erasing, etc.) data.

[0034] Reference Figure 1 , the read voltage generating circuit 1000 may include a compensation circuit 1100 , a transistor TR0 , a resistor R1 , and a resistor R2 .

[0035] The compensation circuit 1100 can receive codes TC1 and TC2, voltages Vztc, Vntc, Vpwr and Vss, a reference voltage Vref and a feedback voltage Vfb. Fig.16 As described, the compensation circuit 1100 may be a component of a memory device included in a memory system. The memory system may include a logic circuit for generating the codes TC1 and TC2. For example, the logic circuit may be included in a component such as a memory controller. The compensation circuit 1100 may receive the codes TC1 and TC2 from the logic circuit.

[0036] For example, the memory system may include a voltage generator. The voltage generator may generate voltages Vztc, Vntc, and Vpwr and a reference voltage Vref, which may be used to operate the read voltage generating circuit 1000. The compensation circuit 1100 may receive voltages Vztc, Vntc, and Vpwr and a reference voltage Vref from the voltage generator. The compensation circuit 1100 may be electrically connected to a node between the resistor R1 and the resistor R2. The compensation circuit 1100 may receive a feedback voltage Vfb from a node between the resistor R1 and the resistor R2. The voltage Vss may be a voltage of an equipotential terminal. For example, the voltage Vss may be a ground voltage.

[0037] The compensation circuit 1100 may output a voltage Vout1 based on the codes TC1 and TC2 and the voltages Vztc, Vntc, Vref, Vpwr, and Vss. The compensation circuit 1100 may output the voltage Vout1 to the gate terminal of the transistor TR0. Figure 2 and Figure 3 The configuration and operation of compensation circuit 1100 is described.

[0038] The transistor TR0 may include a gate terminal receiving a voltage Vout1 from the compensation circuit 1100. The transistor TR0 may include a first end receiving a voltage Vpwr. The second end of the transistor TR0 may be electrically connected to a first end of the resistor R1. The read voltage Vread1 may be output from a node between the transistor TR0 and the first end of the resistor R1. The second end of the resistor R1 may be electrically connected to a first end of a resistor R2. The second end of the resistor R2 may be electrically connected to an equipotential terminal providing a voltage Vss.

[0039] When voltage Vout1 is applied to the gate terminal of transistor TR0, current may flow through transistor TR0. When current flows through transistor TR0, a read voltage Vread1 may be formed at a node between transistor TR0 and resistor R1. The magnitude of voltage Vread1 may be associated with the magnitude of voltage Vout1. Read voltage generating circuit 1000 may output read voltage Vread1 to another component of a memory system (e.g., a memory cell in a memory device). The memory device may output a data signal (refer to FIG. 1 ) indicating data stored in the memory cell based on read voltage Vread1. Fig.16 ).

[0040] The voltage Vread1 can be divided by the resistor R1 and the resistor R2. In an embodiment where the amplitude of the voltage Vss is "Vss", the amplitude of the voltage Vread1 is "Vread1", the amplitude of the resistor R1 is "R1", and the amplitude of the resistor R2 is "R2", the amplitude of the feedback voltage Vfb can be expressed by the formula "(Vread1-Vss)*R2 / (R1+R2)". In an embodiment where the amplitude of the feedback voltage Vfb is "Vfb" and the amplitude of the voltage Vss is "0", the amplitude of the voltage Vread1 can be expressed by the formula "(1+(R1 / R2))*Vfb". Therefore, the amplitude of the feedback voltage Vfb can be associated with the amplitude of the voltage Vread1, and the amplitude of the feedback voltage Vfb can be associated with the amplitude of the voltage Vout1.

[0041] Each of the codes TC1 and TC2 may be represented as being composed of "n" bits (n is a natural number). In some embodiments, the codes TC1 and TC2 may have complementary values ​​to each other. For example, when the value of the code TC1 is "000000", the value of the code TC2 may be "111111". The code TC1 may include the least significant bit TC1 <0> To the most significant bit TC1 <n-1>The code TC2 may include the least significant bit TC2 <0> To the most significant bit TC2 <n-1>For example, in an embodiment where code TC1 and code TC2 are each 6-bit codes, code TC1 and code TC2 may respectively have one of values ​​from "000000" to "111111" and a complementary value of a value from "000000" to "11111".

[0042] The logic circuit can generate codes TC1 and TC2 based on various conditions associated with the memory device of the memory system. The memory device can provide a read voltage of a specific amplitude for the purpose of reading data stored in the memory cell. The amplitude of the threshold voltage of the memory cell can vary with various conditions (e.g., temperature and stress, etc.). Therefore, the amplitude of the read voltage used to accurately read data can also vary with various conditions. As used herein, temperature can refer to the temperature of the memory system including the read voltage generation circuit 1000.

[0043] For example, the magnitude of the threshold voltage of the memory cell may increase as the temperature decreases. The read voltage of the increased magnitude may be used to accurately read the data stored in the memory cell having the threshold voltage of the increased magnitude. The logic circuit may track the threshold voltage of the memory cell. The logic circuit may determine the magnitude of the read voltage that can be used to accurately read the data stored in the memory cell based on the tracked threshold voltage. The logic circuit may determine the magnitude of the voltage Vout1 based on the relationship between the read voltage Vread1 and the voltage Vout1. The logic circuit may determine the codes TC1 and TC2 so that the read voltage Vread1 having the determined magnitude is output from the read voltage generating circuit 1000.

[0044] One or more of the amplitudes of the voltages Vztc and / or Vntc may be associated with temperature. For example, the amplitude of the voltage Vztc may be uniform regardless of temperature variations. The amplitude of the voltage Vntc may decrease as the temperature increases. In the specification, for ease of description, an ideal embodiment may be described with respect to a voltage Vztc whose amplitude is uniform regardless of temperature variations and a voltage Vntc whose amplitude is proportional to the temperature. However, in some embodiments, the actual amplitudes of the voltages Vztc and Vntc may be slightly different from the amplitudes of the voltages Vztc and Vntc of the ideal embodiment. Reference will be made to Fig.12 Describe the relationship between the voltages Vztc and Vntc and temperature.

[0045] Figure 2 is a diagram showing some embodiments of the present invention. Figure 1 A block diagram of an example configuration of a compensation circuit.

[0046] Reference Figure 2 The compensation circuit 1100 may include a current mirror circuit 1110, a reference current generating circuit 1120, and a compensation current generating circuit 1130. The current mirror circuit 1110 may receive a voltage Vpwr. The current mirror circuit 1110 may output a voltage Vout1 to Figure 1 The current mirror circuit 1110 may be electrically connected to the reference voltage generating circuit 1120. The current mirror circuit 1110 may be electrically connected to the compensation current generating circuit 1130.

[0047] The reference current generating circuit 1120 may receive a reference voltage Vref, a feedback voltage Vfb, and a code TC1. The compensation current generating circuit 1130 may receive a voltage Vztc, a voltage Vntc, and a code TC2. The reference current generating circuit 1120 and the compensation current generating circuit 1130 may be electrically connected to an equipotential terminal providing a voltage Vss.

[0048] The reference current generating circuit 1120 may generate a reference current Iref1 based on the received reference voltage Vref, the received feedback voltage Vfb, and the received code TC1. The reference current generating circuit 1120 may output the reference current Iref1 to the equipotential terminal. The compensation current generating circuit 1130 may generate a compensation current ITC1 based on the received voltage Vztc, the received voltage Vntc, and the received code TC2. The compensation current generating circuit 1130 may output the compensation current ITC1 to the equipotential terminal.

[0049] When the reference current Iref1 is generated by the reference current generating circuit 1120, the reference current generating circuit 1120 may receive the current I1 from the current mirror circuit 1110. When the compensation current ITC1 is generated by the compensation current generating circuit 1130, the compensation current generating circuit 1130 may receive the current I2 from the current mirror circuit 1110. When the current I1 and the current I2 are output from the current mirror circuit 1110, a voltage Vout1 may be formed in the current mirror circuit 1110. The current mirror circuit 1110 may output the voltage Vout1 to Figure 1 of transistor TR0.

[0050] The current mirror circuit 1110 may be a first stage amplifier configured to output the voltage Vout1 . The transistor TR0 may be a second stage amplifier configured to output the read voltage Vread1 .

[0051] The magnitude of the voltage Vout1 may be associated with the temperature. Also, the magnitude of the voltage Vout1 may be associated with the code TC1 and the code TC2. Therefore, the magnitude of the read voltage Vread1 may be associated with the temperature and the codes TC1 and TC2. Figure 3 The operations of the current mirror circuit 1110 , the reference current generating circuit 1120 , and the compensation current generating circuit 1130 are described.

[0052] Figure 3 is a diagram showing some embodiments of the present invention. Figure 1 A circuit diagram of an example configuration of a compensation circuit.

[0053] Reference Figure 3 , the current mirror circuit 1110 may include a transistor TR1 and a transistor TR2. The reference current generating circuit 1120 may include a transistor TR3, a transistor TR4, and a current source CS1. The compensation current generating circuit 1130 may include a transistor TR5, a transistor TR6, and a current source CS2.

[0054] Transistor TR1 may include a first terminal receiving voltage Vpwr. A second terminal of transistor TR1 may be electrically connected to node N1. Transistor TR2 may include a first terminal receiving voltage Vpwr. A gate terminal of transistor TR1 may be electrically connected to a gate terminal of transistor TR2, a second terminal of transistor TR2, and node N2.

[0055] Transistor TR3 may include a gate terminal for receiving a reference voltage Vref. A first end of transistor TR3 may be electrically connected to node N1. A second end of transistor TR3 may be electrically connected to current source CS1. Transistor TR4 may include a gate terminal for receiving a feedback voltage Vfb. A first end of transistor TR4 may be electrically connected to node N2. A second end of transistor TR4 may be electrically connected to current source CS1. Current source CS1 may be electrically connected to an equipotential terminal for providing voltage Vss.

[0056] Transistor TR5 may include a gate terminal receiving voltage Vntc. A first end of transistor TR5 may be electrically connected to node N1. A second end of transistor TR5 may be electrically connected to current source CS2. Transistor TR6 may include a gate terminal receiving voltage Vztc. A first end of transistor TR6 may be electrically connected to node N2. A second end of transistor TR6 may be electrically connected to current source CS2. Current source CS2 may be electrically connected to an equipotential terminal providing voltage Vss.

[0057] The current source CS1 may output a reference current Iref1 having a variable amount. The current source CS1 may control the amplitude of the reference current Iref1 based on the code TC1. For example, the current source CS1 may control the amplitude of the reference current Iref1 to be negatively proportional to the value of the code TC1. The sum of the amplitude of the current I11 flowing through the transistor TR3 and the amplitude of the current I12 flowing through the transistor TR4 may correspond to the amplitude of the reference current Iref1.

[0058] The current source CS2 may output a compensation current ITC1 having a variable amount. For example, the current source CS2 may control the amplitude of the compensation current ITC1 based on the code TC2. For example, the current source CS2 may control the amplitude of the compensation current ITC1 to be proportional to the value of the code TC2. The sum of the amplitude of the current I21 flowing through the transistor TR5 and the amplitude of the current I22 flowing through the transistor TR6 may correspond to the amplitude of the compensation current ITC1.

[0059] The amplitude of the current I11 flowing through the transistor TR3 and the amplitude of the current I12 flowing through the transistor TR4 may vary with the amplitude of the reference current Iref1. The amplitude of the current I21 flowing through the transistor TR5 and the amplitude of the current I22 flowing through the transistor TR6 may vary with the amplitude of the compensation current ITC1. When the amplitude of the current I11 flowing through the transistor TR3 and the amplitude of the current I21 flowing through the transistor TR5 vary, the amplitude of the current ID1 flowing through the transistor TR1 may vary. When the amplitude of the current I12 flowing through the transistor TR4 and the amplitude of the current I22 flowing through the transistor TR6 vary, the amplitude of the current ID2 flowing through the transistor TR2 may vary.

[0060] Refer to Figure 2 and Figure 3 , Figure 2 The amplitude of the current I1 may correspond to the sum of the amplitude of the current I11 and the amplitude of the current I12 . Figure 2 The magnitude of the current I2 may correspond to the sum of the magnitude of the current I21 and the magnitude of the current I22. When the current I1 and the current I2 flow, the voltage Vout1 may be formed at the node N1. Figure 1 As described above, the feedback voltage Vfb may be formed at a node between the resistor R1 and the resistor R2, and the read voltage Vread1 may be output from the read voltage generating circuit 1000. The magnitude of the feedback voltage Vfb may be represented by Equation 1.

[0061] [Equation 1]

[0062] Vfb=Vref+α*(Vntc-Vztc)

[0063] In Equation 1, "Vfb" may represent the magnitude of the feedback voltage Vfb, "Vref" may represent the magnitude of the reference voltage Vref, "Vntc" may represent the magnitude of the voltage Vntc, and "Vztc" may represent the magnitude of the voltage Vztc. "α" in Equation 1 may be represented by Equation 2.

[0064] [Equation 2]

[0065]

[0066] In Equation 2, "W_4" may represent the width of transistor TR4, "I12" may represent the magnitude of current I12, "W_5" may represent the width of transistor TR5, "I21" may represent the magnitude of current I21, and "k" may be a proportionality constant that is independent of temperature, the value of code TC1, and the value of code TC2.

[0067] The current source CS1 may be configured to output a reference current Iref1 having an amplitude that is negatively proportional to the value of the code TC1. The current source CS2 may be configured to output a compensation current ITC1 having an amplitude that is directly proportional to the value of the code TC2. The amplitude of the current I12 and the amplitude of the current I21 may vary with the amplitudes of the reference current Iref1 and the compensation current ITC1. Thus, "α" may vary according to Equation 2, and the amplitude of the feedback voltage Vfb may vary according to Equation 1.

[0068] As reference Figure 1 As described above, the magnitude of the read voltage Vread1 may correspond to the magnitude of the feedback voltage Vfb. Therefore, the magnitude of the read voltage Vread1 may vary based on Equation 1. Hereinafter, the read voltage Vread1 may be described with reference to Equations 1 and 2.

[0069] The read voltage generating circuit 1000 may be configured to output a read voltage Vread1 having a magnitude varying with the values ​​of the code TC1 and the code TC2. For example, the read voltage generating circuit 1000 may be configured to output a read voltage Vread1 having a magnitude increasing with the values ​​of the code TC1 and the code TC2.

[0070] As reference Figure 1 As described above, the amplitude of the voltage Vntc and / or the amplitude of the voltage Vztc may be associated with temperature. For example, the amplitude of the voltage Vntc may be negatively proportional to the temperature, and the amplitude of the voltage Vztc may be uniform regardless of temperature changes. Therefore, the read voltage generation circuit 1000 may be configured to output a read voltage Vread1 having an amplitude associated with temperature. For example, the read voltage generation circuit 1000 may be configured to output a read voltage Vread1 having an amplitude that decreases as the temperature increases.

[0071] When the magnitude of the read voltage Vread1 varies with temperature and the codes TC1 and TC2 , the magnitude of the read voltage Vread1 may vary with a threshold voltage of a memory cell, which varies with various conditions.

[0072] Figure 4 is a circuit diagram showing a read voltage generating circuit according to some embodiments of the inventive concept. Figure 1 compared to, Figure 4 The read voltage generating circuit 2000 may include the compensation circuit 2100 instead of the compensation circuit 1100 . Figure 4 Some components of the read voltage generating circuit 2000 may be related to Figures 1 to 3 Corresponding elements of the described read voltage generating circuit 1000 are the same or similar, and redundant descriptions may be omitted for the sake of brevity.

[0073] The compensation circuit 2100 may receive a code TC from the logic circuit. The code TC may be represented as being composed of "n" bits (n is a natural number). The code TC may include the least significant bit TC <0> To the most significant bit TC <n-1>For example, in an embodiment where the code TC is a 6-bit code, the code TC may have one of the values ​​from “000000” to “111111”.

[0074] For example, the logic circuit may generate the code TC based on various conditions associated with the memory system. The configuration and operation of the read voltage generating circuit 2000 may be similar to the configuration and operation of the read voltage generating circuit 1000. Therefore, additional description may be omitted to avoid redundancy.

[0075] Figure 5 is a diagram showing some embodiments of the present invention. Figure 4 A block diagram of an example configuration of a compensation circuit.

[0076] Reference Figure 5 The compensation circuit 2100 may include a current mirror circuit 2110, a reference current generating circuit 2120, and a compensation current generating circuit 2130. The current mirror circuit 2110 may receive a voltage Vpwr. The current mirror circuit 2110 may provide a reference current generating circuit 2120 to the compensation current generating circuit 2130. Figure 4 The gate terminal of the transistor TR0 outputs the voltage Vout2. The current mirror circuit 2110 may be electrically connected to the reference current generating circuit 2120 and the compensation current generating circuit 2130.

[0077] The reference current generating circuit 2120 may receive a reference voltage Vref and a feedback voltage Vfb. The compensation current generating circuit 2130 may receive a voltage Vztc, a voltage Vntc, and a code TC. The reference current generating circuit 2120 and the compensation current generating circuit 2130 may be electrically connected to an equipotential terminal providing a voltage Vss.

[0078] The reference current generating circuit 2120 may generate a reference current Iref2 based on the received reference voltage Vref and the received feedback voltage Vfb. The reference current generating circuit 2120 may output the reference current Iref2 to the equipotential terminal. The compensation current generating circuit 2130 may generate a compensation current ITC2 based on the received voltage Vztc, the received voltage Vntc, and the received code TC. The compensation current generating circuit 2130 may output the compensation current ITC2 to the equipotential terminal.

[0079] When the reference current generating circuit 2120 generates the reference current Iref2, the reference current generating circuit 2120 may receive the current I3 from the current mirror circuit 2110. When the compensation current generating circuit 2130 generates the compensation current ITC2, the compensation current generating circuit 2130 may receive the current I4 from the current mirror circuit 2110. When the currents I3 and I4 are output from the current mirror circuit 2110, the current mirror circuit 2110 may output the voltage Vout2 to Figure 4 of transistor TR0.

[0080] Will refer to Figure 6 Some operations of the current mirror circuit 2110 , the reference current generating circuit 2120 , and the compensation current generating circuit 2130 are described.

[0081] Figure 6 is a diagram showing some embodiments of the present invention. Figure 4 A circuit diagram of an example configuration of a compensation circuit.

[0082] Figure 4 The compensation circuit 2100 may include Figure 6 Compensation circuit 2100a. Figure 5 The compensation current generating circuit 2130 may include Figure 6 Compensation current generating circuit 2131. Figure 6 , the current mirror circuit 2110 may include a transistor TR1 and a transistor TR2. The reference current generating circuit 2120 may include a transistor TR7, a transistor TR8, and a current source CS3. The compensation current generating circuit 2131 may include a transistor TR9, a transistor TR10, and a current source CS4.

[0083] Transistor TR1 may include a first terminal receiving voltage Vpwr. A second terminal of transistor TR1 may be electrically connected to node N3. Transistor TR2 may include a first terminal receiving voltage Vpwr. A gate terminal of transistor TR1 may be electrically connected to a gate terminal of transistor TR2, a second terminal of transistor TR2, and node N4. Transistor TR1 may transmit current ID3. Transistor TR2 may transmit current ID4.

[0084] Transistor TR7 may include a gate terminal for receiving a reference voltage Vref. A first end of transistor TR7 may be electrically connected to node N3. A second end of transistor TR7 may be electrically connected to a first end of current source CS3. Transistor TR7 may transmit current I31. Transistor TR8 may include a gate terminal for receiving a feedback voltage Vfb. A first end of transistor TR8 may be electrically connected to node N4. A second end of transistor TR8 may be electrically connected to a first end of current source CS3. Transistor TR8 may transmit current I32. A second end of current source CS3 may be electrically connected to an equipotential terminal for providing voltage Vss.

[0085] Transistor TR9 may include a gate terminal receiving voltage Vntc. A first end of transistor TR9 may be electrically connected to node N3. A second end of transistor TR9 may be electrically connected to a first end of current source CS4. Transistor TR9 may transmit current I41. Transistor TR10 may include a gate terminal receiving voltage Vztc. A first end of transistor TR10 may be electrically connected to node N4. A second end of transistor TR10 may be electrically connected to a first end of current source CS4. Transistor TR10 may transmit current I42. A second end of current source CS4 may be electrically connected to an equipotential terminal providing voltage Vss.

[0086] exist Figure 6 , each of transistor TR9 and transistor TR10 is shown as being implemented with one transistor. Figure 8 As shown, each of transistor TR9 and transistor TR10 can be one or more transistors selected from a plurality of transistors based on code TC. The transistors that can be selected as transistor TR9 and transistor TR10 can have different widths. Therefore, the width of transistor TR9 and the width of transistor TR10 can be selected according to code TC.

[0087] The current source CS3 may output a reference current Iref2. The sum of the magnitude of the current I31 flowing through the transistor TR7 and the magnitude of the current I32 flowing through the transistor TR8 may correspond to the magnitude of the reference current Iref2. In an embodiment where the characteristics of the transistors TR7 and TR8 are substantially the same as each other, the magnitude of the current I31 may be substantially equal to the magnitude of the current I32.

[0088] For better understanding, in the specification, an embodiment in which the amplitude of the current I31 is substantially equal to the amplitude of the current I32 may be described. However, it is understood that the concept of the present invention may include some embodiments in which the currents I31 and I32 have different amplitudes according to the amplitude of the reference voltage Vref, the amplitude of the feedback voltage Vfb, and the characteristics of the transistors TR7 and TR8.

[0089] The current source CS4 may output a compensation current ITC2 having an amplitude selected by the code TC2. The sum of the amplitude of the current I41 flowing through the transistor TR9 and the amplitude of the current I42 flowing through the transistor TR10 may correspond to the amplitude of the compensation current ITC2. In an embodiment in which the characteristics of the transistor TR9 and the transistor TR10 are substantially the same as each other, the amplitude of the current I41 may be substantially equal to the amplitude of the current I42. The amplitude of the compensation current ITC2 may be selected based on the code TC. Therefore, the amplitude of the compensation current I41 may be selected based on the code TC.

[0090] For better understanding, in the specification, an embodiment in which the amplitude of the current I41 is substantially equal to the amplitude of the current I42 may be described. However, it is understood that the concept of the present invention may include some embodiments in which the currents I41 and I42 have different amplitudes according to the amplitude of the voltage Vntc, the amplitude of the voltage Vztc, and the characteristics of the transistors (TR9 and TR10) selected by the code TC.

[0091] Figure 3 The reference current generating circuit 1120 can output a reference current Iref1 having an amplitude that varies with the code TC1 and the temperature, but Figure 6 The reference current generating circuit 2120 can output a reference current Iref2 of a fixed value. The compensation circuit 2100a can adjust the amplitude of the voltage Vout2, which varies due to the code TC and the temperature, mainly according to the operation of the compensation current generating circuit 2131.

[0092] Refer to Figure 5 and Figure 6 , Figure 5 The amplitude of the current I3 may correspond to the sum of the amplitude of the current I31 and the amplitude of the current I32 . Figure 5 The magnitude of the current I4 may correspond to the sum of the magnitude of the current I41 and the magnitude of the current I42. When the current I3 and the current I4 flow, the voltage Vout2 may be formed at the node N3. Figure 4 As described above, the feedback voltage Vfb may be formed at a node between the resistor R1 and the resistor R2, and the read voltage Vread2 may be output from the read voltage generating circuit 2000. The magnitude of the feedback voltage Vfb may be represented by Equation 3.

[0093] [Equation 3]

[0094] Vfb=Vref+α*(Vntc-Vztc)

[0095] In Equation 3, "Vfb" may represent the magnitude of the feedback voltage Vfb, "Vref" may represent the magnitude of the reference voltage Vref, "Vntc" may represent the magnitude of the voltage Vntc, and "Vztc" may represent the magnitude of the voltage Vztc. Figure 1 As described above, the amplitude of the voltage Vntc and / or the amplitude of the voltage Vztc may be associated with temperature. For example, the amplitude of the voltage Vntc may be configured to have a value proportional to the temperature, and the amplitude of the voltage Vztc may be configured to have a uniform value regardless of temperature variations. The amplitude "Vfb" of the feedback voltage Vfb may be determined based on the difference between the amplitude of the voltage Vntc and the amplitude of the voltage Vztc. "α" in Equation 3 may be represented by Equation 4.

[0096] [Equation 4]

[0097]

[0098] In Equation 4, "W_8" may represent the width of transistor TR8, "I32" may represent the magnitude of current I32, "W_9" may represent the width of transistor TR9, "I41" may represent the magnitude of current I41, and "k" may be a proportionality constant independent of temperature and the value of code TC.

[0099] Referring to Equation 3 and Equation 4, the magnitude of the feedback voltage Vfb may include nonlinear terms with respect to both the code TC and the temperature caused by "α". That is, due to the term included in "α" Therefore, the magnitude of the feedback voltage Vfb may include a value that varies nonlinearly with the temperature and the value of the code TC.

[0100] In detail, since the currents I41 and I32 are drain currents of the transistors TR9 and TR8, respectively, the magnitude of the current I41 and the magnitude of the current I32 may vary with temperature. According to the relationship described in reference equations 3 and 4, the rate of change of the feedback voltage Vfb with respect to temperature is It can be calculated as "Vntc-Vztc" may be linear with temperature, but "Vntc-Vztc" may be nonlinear with temperature.

[0101] because corresponds to the square root of the value that varies with temperature, so Therefore, the magnitude of the feedback voltage Vfb calculated according to Equation 3 and Equation 4 may include a nonlinear term of temperature variation.

[0102] And, as described with reference to transistors TR9 and TR10, "W_9" and "I41" can vary with the value of code TC. The term is the square root of a value that can vary with the value of code TC, May be a nonlinear term with respect to the value of the code TC. Therefore, the magnitude of the feedback voltage Vfb calculated according to Equation 3 and Equation 4 may include a nonlinear term with respect to the value of the code TC.

[0103] As reference Figure 4 As described above, the magnitude of the read voltage Vread2 may correspond to the magnitude of the feedback voltage Vfb. Therefore, the magnitude of the read voltage Vread2 may vary based on Equation 3. Hereinafter, the read voltage Vread2 may be described with reference to Equations 3 and 4.

[0104] In an embodiment where the magnitude of the feedback voltage Vfb is nonlinear with the temperature and the value of the code TC, the computational burden of the logic circuit may be increased to calculate the read voltage Vread2 having a magnitude for accurately reading the data of the memory cell. The logic circuit configured to process a large number of operations may consume a large amount of power. Also, the logic circuit configured to process a large number of operations may be implemented with a chip placed in a large area.

[0105] According to the concept of the present invention, in the operation of the compensation circuit 2100a, "W_9" and "I41" can vary with the code TC, so that the magnitude of the feedback voltage Vfb calculated according to Equation 3 and Equation 4 does not include nonlinear terms (e.g., (It may have a value that is independent of the temperature and the value of the code TC). For example, "W_9" and "I41" may be set to multiples of "W_8" and "I32", respectively, thereby improving the linearity of temperature compensation.

[0106] Will refer to Figures 8 to 11 Describes examples of "W_9" and "I41" selected differently according to code TC.

[0107] Figure 7 is a diagram showing some embodiments of the present invention. Figure 4 A circuit diagram of an example configuration of a compensation circuit.

[0108] Figure 4 The compensation circuit 2100 may include Figure 7 The compensation circuit 2100b. Figure 6 Compared with the compensation circuit 2100a, Figure 7 The compensation circuit 2100 b may further include a direction selection circuit 2132 . Figure 7 Some components of the read compensation circuit 2100b can be compared with reference Figure 6 Description Figure 6 The corresponding elements of the compensation circuit 2100a are the same or similar, and redundant descriptions may be omitted for the sake of brevity.

[0109] The direction selection circuit 2132 may receive the voltage Vztc and the voltage Vntc. The direction selection circuit 2132 may receive the selection signal SEL from the logic circuit. The direction selection circuit 2132 may output the voltage Va and the voltage Vb in response to the selection signal SEL. The direction selection circuit 2132 may output the voltage Va to the gate terminal of the transistor TR9. The direction selection circuit 2132 may output the voltage Vb to the gate terminal of the transistor TR10.

[0110] The direction selection circuit 2132 may output a voltage Va and a voltage Vb, each of which selectively has one of the values ​​corresponding to the voltage Vztc and the voltage Vntc based on the logic value of the selection signal SEL. For example, in some embodiments, when the selection signal SEL indicates a logic value of "1", the voltage Va may correspond to the voltage Vztc, and the voltage Vb may correspond to the voltage Vntc, and when the selection signal SEL indicates a logic value of "0", the voltage Va may correspond to the voltage Vntc, and the voltage Vb may correspond to the voltage Vztc. However, embodiments of the inventive concept are not limited thereto.

[0111] Below, for the convenience of description, an embodiment in which, in response to a selection signal SEL having a logic value of "1", the voltage Vztc is applied to the gate terminal of the transistor TR9 (i.e., the voltage Vztc is selected as the voltage Va), and the voltage Vntc is applied to the gate terminal of the transistor TR10 (i.e., the voltage Vntc is selected as the voltage Vb), and an embodiment in which, in response to a selection signal SEL having a logic value of "0", the voltage Vntc is applied to the gate terminal of the transistor TR9 (i.e., the voltage Vntc is selected as the voltage Va), and the voltage Vztc is applied to the gate terminal of the transistor TR10 (i.e., the voltage Vztc is selected as the voltage Vb) will be described.

[0112] However, it can be understood that the concept of the present invention may include other embodiments in which, in response to any logic value of the selection signal SEL, one of a voltage having an amplitude corresponding to the amplitude of the voltage Vntc and a voltage having an amplitude corresponding to the amplitude of the voltage Vztc is applied to the gate terminal of the transistor TR9, and the other is applied to the gate terminal of the transistor TR10.

[0113] Just as the magnitude of the voltage Vout2 can vary with the voltage Va and the voltage Vb selected by the selection signal SEL, the magnitudes of the feedback voltage Vfb and the read voltage Vread2 can vary with the voltage Va and the voltage Vb selected by the selection signal SEL. Fig.13 The relationship between the selection signal SEL and the read voltage Vread2 is described.

[0114] Figure 8 is a diagram showing some embodiments of the present invention. Figure 6 and / or Figure 7 A circuit diagram of an example configuration of a compensation current generating circuit. Figure 8 The transistor TR9 receiving the voltage Va and the transistor TR10 receiving the voltage Vb (corresponding to Figure 7 For example, in response to the selection signal SEL “0”, the transistor TR9 may receive the voltage Vntc and the transistor TR10 may receive the voltage Vztc.

[0115] Reference Figure 8 , Figure 6 The transistor TR9 of and / or 7 may be at least one enabling transistor selected from a plurality of transistors (transistors of a group corresponding to reference numeral 'TR9'). Figure 6 The transistor TR10 of and / or 7 may be at least one enabling transistor selected from a plurality of transistors (transistors of a group corresponding to reference numeral "TR10"). For example, the transistor TR9 may be one or more enabled transistors among the transistors TR9_1 to TR9_4, the transistors of the group G1, and the transistors of the group G2. The transistor TR10 may be one or more enabled transistors among the transistors TR10_1 to TR10_4, the transistors of the group G3, and the transistors of the group G4.

[0116] The width of the transistors that can be selected as transistor TR9 can be different. For example, the width of transistor TR9_1 can be "8W", the width of transistor TR9_2 can be "4W", the width of transistor TR9_3 can be "2W", and the width of transistor TR9_4 can be "W". The width of each transistor in groups G1 and G2 can be "W". In other words, the width of transistor TR9_1 can be about eight times the width of "W", the width of transistor TR9_2 can be about four times the width of "W", and the width of transistor TR9_3 can be about twice the width of "W". In an embodiment where the series-connected transistors of group G1 are selected together, the transistors of group G1 can work together. In an embodiment where the series-connected transistors of group G2 are selected together, the transistors of group G2 can work together.

[0117] In an embodiment where transistors are connected in series, the length of the channel through which current flows can be increased, and therefore the ratio of the channel width to the channel length can be reduced. Therefore, the transistors in series can operate like transistors whose width is narrower than the width of each transistor. For example, the transistors in series can operate like transistors whose width is inversely proportional to the number of transistors in series. Therefore, in an embodiment where the transistors in series of group G1 work together, the operation of the two transistors in group G1 can be similar to the operation of a transistor having a width of "(1 / 2)*W" or a width of approximately half the width of "W". As described above, the operation of the four transistors in group G2 can be similar to the operation of a transistor having a width of "(1 / 4)*W" or a width of approximately one-quarter the width of "W".

[0118] exist Figure 8 In the embodiment of the present invention, the transistor that can be selected for the transistor TR9 can be operated as a transistor having a width of "(1 / 4)*W", "(1 / 2)*W", "W", "2W", "4W", and "8W". That is, the transistor that can be selected for the transistor TR9 can be operated as a transistor having a width of "(2i)*W" (i is an integer, -2≤i≤3). In the embodiment in which each of the transistors TR7 and TR8 of the current source CS3 has a width of "W", the width of the transistor that can be selected as the transistor TR9 can be proportional to the widths of the transistors TR7 and TR8, respectively. Although it can be referred to Figure 8 Some embodiments are described with values ​​of i within the range of “−2≤i≤3”, however, it should be understood that the inventive concept may include embodiments with other ranges of integer “i”.

[0119] Therefore, one of various values ​​may be selected as the width "W_9" of transistor TR9 in Equation 4. In an embodiment where the width "W_8" of transistor TR8 is "W", the value that may be selected as "W_9" may be proportional to "W_8". Transistor TR9 may be configured such that a value proportional to "W_8" may be selected as "W_9". Transistor TR10 may have a configuration similar to that of transistor TR9. Therefore, additional description will be omitted to avoid redundancy.

[0120] exist Figure 8 In the example embodiment of FIG. 1 , the code TC can be represented by 6 bits of data (ie, TC <0> To TC <5> Each of them can be represented by 1 bit of data). TC <0> To TC <5> Can indicate 6 bits of data respectively 0 ” to ”2 5 "The value of the position. For example, in some embodiments, when the code TC is represented by "100010", "TC <1> ” and "TC <5> " can be "1", "TC <0> ”、"TC <2> ”、"TC <3> ” and "TC <4> " can be "0".

[0121] Reference Figure 8 , the current source CS4 may include a switch unit SW. The switch unit SW may include switches SW1 to SW6. The switches SW1 to SW6 may receive a TC <5> To TC <0> The corresponding bit of the code TC. <0> To TC <5> Each of the switches SW1 to SW6 may be a logic value "0" or a logic value "1". Each of the switches SW1 to SW6 may be turned on in response to a logic value "1", and may be turned off in response to a logic value "0" of a corresponding bit of the code TC. For example, TC <0> To TC <5> The logic value "1" and logic value "0" can correspond to specific voltage amplitudes respectively.

[0122] For example, in some embodiments, when the code TC is represented by "100010" (ie, when TC <1> and TC <5> is "1" and TC <0> TC <2> ,TC <3> and TC <4> is "0"), the switch SW1 and the switch SW5 may be turned on, and the switch SW2, the switch SW3, the switch SW4, and the switch SW6 may be turned off.

[0123] When a particular switch among switches SW1 to SW6 is turned on, current may flow through the particular switch, and the bias transistor in current source CS4 connected to the particular switch and the differential pair of transistors TR9 and TR10. For example, in some embodiments, when switch SW1 is turned on, current may flow through transistor TR11_1 connected to switch SW1. For example, in some embodiments, when switch SW5 is turned on, current may flow through the transistor of group G5 connected to switch SW5 and the differential pair of transistors TR9 and TR10.

[0124] The current source CS4 may be a current mirror circuit corresponding to a replica of the current source CS3. The voltage Vbias may be a bias voltage commonly provided to the current source CS3 and the current source CS4. Therefore, in some embodiments, when the switches SW1 to SW6 are turned on, the mirror current obtained by mirroring the reference current Iref2 may flow through the bias transistors TR11_1 to TR11_4, the transistors of the group G5, and the transistors of the group G6, which are connected to the switches SW1 to SW6. In detail, the amplitude of the current flowing through the current source CS4 may be proportional to the amplitude of the reference current Iref2.

[0125] Furthermore, as the width of the transistor increases, the amplitude of the current flowing through the transistor may increase. For example, the amplitude of the current flowing through the transistor may be proportional to the width of the transistor. The widths of the bias transistors TR11_1 to TR11_4 may be "16W", "8W", "4W", and "2W", respectively. The width of each transistor in group G5 and group G6 may be "2W". As described with reference to the transistors of groups G1 to G4, the series-connected transistors of group G5 may operate as transistors having a width of "W". The series-connected transistors of group G6 may operate as a single transistor having a width of "(1 / 2)*W".

[0126] For example, in some embodiments, when only switch SW1 is turned on (in some embodiments, when only TC <5> is "1" and TC <0> To TC <4> When the current is "0", the current with the amplitude of "(Iref2) / 2" can flow through the transistor TR11_1 with the width of "16W". As described above, the current with the amplitude of "(Iref2) / 4" can flow through the transistor TR11_2, the current with the amplitude of "(Iref2) / 8" can flow through the transistor TR11_3, the current with the amplitude of "(Iref2) / 16" can flow through the transistor TR11_4, the current with the amplitude of "(Iref2) / 32" can flow through the transistors of group G5, and the current with the amplitude of "(Iref2) / 64" can flow through the transistors of group G6. That is, the current with the amplitude of "(2 j )*(Iref2)" can flow through the transistors TR11_1 to TR11_4, the transistors of the group G5, and the transistors of the group G6 (j is an integer, -6≤j≤-1). Figure 8 An example range of "-6≤j≤-1" is described, however, it should be understood that the inventive concept may include embodiments of other ranges of the integer "j".

[0127] In some embodiments, when only one of the switches SW1 to SW6 is turned on, the amplitude of the current flowing through the current source CS may be one of "(Iref2) / 2", "(Iref2) / 4", "(Iref2) / 8", "(Iref2) / 16", "(Iref2) / 32", and "(Iref2) / 64". In some embodiments, when two or more of the switches SW1 to SW6 are turned on, the amplitude of the current flowing through the current source CS may correspond to the sum of the amplitudes of the currents flowing through the turned-on switches among "(Iref2) / 2", "(Iref2) / 4", "(Iref2) / 8", "(Iref2) / 16", "(Iref2) / 32", and "(Iref2) / 64". Therefore, the amplitude of the current flowing through the current source CS4 may correspond to the amplitude of the current flowing through the current source CS4 indicated by "(Iref2) / 2". j That is, the magnitude of the current flowing through the current source CS4 can be selected according to the code TC to be proportional to the magnitude of the reference current Iref2.

[0128] The compensation current ITC2 may be output as a current flowing through the switch unit SW. Therefore, the magnitude of the compensation current ITC2 may correspond to the magnitude of the current flowing through the current source CS4 (e.g., these magnitudes may be substantially equal to each other). This may mean that the magnitude of the compensation current ITC2 is selected to be proportional to the magnitude of the reference current Iref2.

[0129] For example, in some embodiments, when the code TC has a reference value, a current having the minimum amplitude among the selectable amplitudes (eg, a reference current amplitude: for example, 2 -6 Therefore, in some embodiments, when the value of the code TC increases by the reference value, the magnitude of the compensation current ITC2 may increase by the reference current magnitude.

[0130] For example, in some embodiments, when the reference value of the code TC is "000001", the amplitude of the compensation current ITC2 may increase by "(Iref2) / 64" each time the value of the code TC increases by "000001", where "(Iref2) / 64" may be the amplitude of the current flowing through the switch SW6 and the transistor of the group G6. For example, the amplitude of the compensation current ITC2 selected by the code TC having a value of "000100" is "(Iref2) / 16", while the amplitude of the compensation current ITC2 selected by the code TC having a value of "000101" is "(Iref2) / 64+(Iref2) / 16".

[0131] As reference Figure 6 As described above, in an embodiment where the characteristics of the transistor TR9 and the transistor TR10 selected by the code TC are substantially the same as each other, the amplitude of the current I41 may be substantially equal to the amplitude of the current I42. Therefore, the amplitude of the current flowing through the current source CS4 may be proportional to the amplitude of the reference current I41. Also, in an embodiment where the characteristics of the transistor TR7 and the transistor TR8 are substantially the same as each other, the amplitude of the current I31 may be substantially equal to the amplitude of the current I32. Therefore, Figure 6 The magnitude of the current I32 may be proportional to the magnitude of the reference current Iref2.

[0132] The magnitude of the current I32 may be proportional to the magnitude of the reference current Iref2, and the magnitude of the current I41 may also be proportional to the magnitude of the reference current Iref2. According to the above description, in Equation 3 and Equation 4, "I41" may have a value proportional to "I32". The compensation current generating circuit 2131 may be configured to output a current I41 having a magnitude proportional to the magnitude of the current I32 based on the process described with reference to the operation of the current source CS4.

[0133] In Equation 3 and Equation 4, in an embodiment where "W_9" has a value proportional to "W_8" and "I41" has a value proportional to "I32", It can have a value that is independent of the value of the temperature and the code TC. Therefore, the amplitude of the feedback voltage Vfb calculated according to Equation 3 and Equation 4 can be linear with the value of the temperature and the code TC. Since the amplitude of the read voltage Vread2 corresponds to the amplitude of the feedback voltage Vfb, the amplitude of the read voltage Vread2 can be linear with the value of the temperature and the code TC. For example, in response to the code TC of the reference value, the amplitude of the read voltage Vread2 can have a reference voltage value. And, whenever the value of the code TC increases by the reference amplitude, the amplitude of the read voltage Vread2 can increase by the reference voltage amplitude.

[0134] The read voltage generating circuit 2000 may be configured to output a read voltage Vread2 having an amplitude that is linear with the value of the temperature and code TC. Since the amplitude of the read voltage Vread2 may correspond to the amplitude of the feedback voltage Vfb, the read voltage generating circuit 2000 may be configured to output a read voltage Vread2 having an amplitude that is linear with the value of the temperature and code TC. Figures 9 to 11 Some embodiments in which the transistor TR9 and the transistor TR10 are selected by the code TC are described.

[0135] Fig. 9 It is used to describe some embodiments of the present invention. Figure 8 A circuit diagram of an example operation of a compensation current generating circuit. Fig. 9 In the illustrated operation, one transistor TR9_1 may be selected as the transistor TR9 , and one transistor TR10_1 may be selected as the transistor TR10 .

[0136] For example, the switch unit SW of the current source CS4 may receive a code TC having “100000” (ie, only the code value TC <5> is "1", and the rest are "0"). When the switch SW1 is turned on in response to the logic value "1", a current of (Iref2) / 2" may flow through the transistor TR11_1.

[0137] When the current of "I41+I42" flows through the transistor TR11_1, the current I41 may flow through the transistor TR9_1, and the current I42 may flow through the transistor TR10_1 electrically connected to the transistor TR11_1. When the current I41 and the current I42 flow through the transistors TR9_1 and TR10_1, respectively, the current I41 and the current I42 may be input to the transistor TR9 and the transistor TR10, respectively. In an embodiment in which the transistors TR7 and TR8 of the reference current generating circuit 2120 are symmetrical to each other, the magnitude of the current I32 may be "I41+I42".

[0138] Therefore, based on the code TC of “100000”, the magnitudes of the current I41 and the current I42 may be selected as specific values, the transistor TR9_1 may be selected as the transistor TR9, and the transistor TR10_1 may be selected as the transistor TR10.

[0139] Fig.10 It is used to describe some embodiments of the present invention. Figure 8 A circuit diagram of an example operation of a compensation current generating circuit. Fig.10 In the illustrated operation, two or more transistors TR9_5 and TR9_6 may be selected as the transistor TR9 , and two or more transistors TR10_5 and TR10_6 may be selected as the transistor TR10 .

[0140] For example, the switch unit SW of the current source CS4 may receive a code TC having “000010” (ie, only the code value TC <1> is "1", and the remaining values ​​are "0"). When the switch SW_5 is turned on in response to the logic value "1", a current of "I41+I42" may flow through the transistors TR11_5 and TR11_6 of the group G5.

[0141] When the current of "I41+I42" flows through transistors TR11_5 and TR11_6, current I41 may flow through transistors TR9_5 and TR9_6 of the G1 group electrically connected to transistor TR11_5, and current I42 may flow through transistors TR10_5 and TR10_6 of the group G3 electrically connected to transistor TR11_5. When current I41 flows through transistors TR9_5 and TR9_6 and through transistors TR10_5 and TR10_6, current I41 and current I42 may be input to transistor TR9 and transistor TR10, respectively. In an embodiment in which transistors TR7 and transistor TR8 of the reference current generating circuit 2120 are symmetrical to each other, the magnitude of current I32 may be "I41+I42".

[0142] Therefore, based on the code TC of “000010”, the magnitudes of the currents I41 and I42 may be selected as specific values, the transistors TR9_5 and TR9_6 of the group G1 may be selected as the transistor TR9, and the transistors TR10_5 and TR10_6 of the group G3 may be selected as the transistor TR10.

[0143] Fig.11 It is used to describe some embodiments of the present invention. Figure 8 A circuit diagram of an example operation of a compensation current generating circuit. Fig.11 In the illustrated operation, transistor TR9_1 and transistors TR9_5 and TR9_6 of group G1 may be selected together as transistor TR9. Transistor TR10_1 and transistors TR10_5 and TR10_6 of group G3 may be selected together as transistor TR10.

[0144] In the embodiment where the transistors are connected in parallel, the current can flow through the channel with a wider width. Therefore, the operation of the transistors connected in parallel can be similar to the operation of a transistor whose width corresponds to the sum of the widths of the transistors. In the operation where the transistors connected in parallel are selected as transistor TR9, "W_9" of equation 4 can correspond to the sum of the widths of the selected transistors. For example, in the operation where transistor TR9_1 and transistors TR9_5 and TR9_6 are operated together as transistor TR9, "W_9" can be "(8+1 / 2)*W", which corresponds to the sum of "8W" and "(1 / 2)*W".

[0145] exist Fig.11 In the operation shown, the switch unit SW of the current source CS4 can receive a code TC (ie, a code value TC) represented by "100010" from the logic circuit. <1> and TC <5> is "1", and the remaining value is "0"). When the switch SW_5 is turned on in response to the logic value "1", a current of "I41_2+I42_2" may flow through the transistors TR11_5 and TR11_6 of the group G5. When the switch SW_1 is turned on in response to the logic value "1", a current of "I41_1+I42_1" may flow through the transistor TR11_1.

[0146] For example, when the current of "I41_2+I42_2" flows through transistors TR11_5 and TR11_6, the current I41_2 may flow through transistors TR9_5 and TR9_6 of the G1 group electrically connected to transistor TR11_5, and the current I42_2 may flow through transistors TR10_5 and TR10_6 of the G3 group electrically connected to transistor TR11_5. When the current of "I41_1+I42_1" flows through transistor TR11_1, the current I41_1 may flow through transistor TR9_1, and the current I42_1 may flow through transistor TR10_1.

[0147] When current flows through transistors TR9_5 and TR9_6, transistors TR10_5 and TR10_6, transistor TR9_1, and transistor TR10_1, current I41 and current I42 may be input to transistor TR9 and transistor TR10, respectively. Also, in an embodiment where transistors TR7 and TR8 of the reference current generating circuit 2120 are symmetrical to each other, the magnitude of current I32 may be "I41+I42".

[0148] That is, based on the code TC of "100010", the magnitudes of currents I41 and I42 may be selected as specific values, transistors TR9_5 and TR9_6 and transistor TR9_1 of group G1 may be selected as transistor TR9, and transistors TR10_5 and TR10_6 and transistor TR10_1 of group G3 may be selected as transistor TR10.

[0149] As reference Figures 9 to 11 As stated in Figure 8 In the embodiment of the present invention, "W_9" of Equation 4 may selectively have one of "(1 / 4)*W", "(1 / 2)*W", "W", "2W", "4W", and "8W", or the sum of two or more of "(1 / 4)*W", "(1 / 2)*W", "W", "2W", "4W", and "8W", depending on the value of the code TC. That is, the width "W_9" of the transistor TR9 in Equation 4 may be variously selected to have a value proportional to the width "W" of the transistor TR8.

[0150] And, as referenced Figure 8 As described, depending on the value of the code TC, the amplitude of the compensation current ITC2 can selectively have one of "(Iref2) / 2", "(Iref2) / 4", "(Iref2) / 8", "(Iref2) / 16", "(Iref2) / 32" and "(Iref2) / 64", or the sum of two or more of "(Iref2) / 2", "(Iref2) / 4", "(Iref2) / 8", "(Iref2) / 16", "(Iref2) / 32" and "(Iref2) / 64".

[0151] Since the magnitude of the current I41 may be proportional to the magnitude of the compensation current ITC2 (e.g., the magnitude of the current I41 may be 1 / 2 times the magnitude of the compensation current ITC2), "I41" may be variously selected to have a value proportional to the magnitude of the reference current Iref2. Since the magnitude of the current I32 may be proportional to the magnitude of the reference current Iref2 (e.g., the magnitude of the current I32 may be 1 / 2 times the magnitude of the reference current Iref2), "I32" may be variously selected to have a value proportional to the magnitude of the reference current Iref2. Therefore, "I41" in Equation 4 may be variously selected to have a value proportional to "I32".

[0152] Fig.12 is a diagram showing some embodiments of the present invention. Figure 4 A graph of the voltage received by the compensation circuit. Fig.12 In the example of a graph of , the x-axis may represent the temperature in units of ° C, and the y-axis may represent the magnitude of the voltage in units of V. Fig.12 The graph of shows the magnitude of the voltages Vztc and Vntc as a function of temperature at a particular value of the code TC.

[0153] Reference Fig.12 , the amplitude of the voltage Vntc may be negatively proportional to the temperature. The amplitude of the voltage Vztc may be uniform regardless of temperature changes. Figure 1 As described, the voltage Vztc and the voltage Vntc may be received from a voltage generator included in the memory system. For example, the voltage generator may detect a temperature change of the memory system. The voltage generator may output voltages Vztc and Vntc of amplitudes corresponding to the detected temperature. For example, in an operation at a temperature of "T1", the voltage generator may output a voltage Vztc of "V1" and a voltage Vntc of "V2". For example, in an operation at a temperature of "T2", the voltage generator may output a voltage Vztc of "V1" and a voltage Vntc of "V1" equal in amplitude to the voltage Vztc.

[0154] Fig.13 FIG. 1 is a diagram showing a method of performing a selection operation according to some embodiments of the present invention. Figure 4 The graph of the read voltage. Fig.13 In the graph of , the x-axis may represent the value of the code TC, and the y-axis may represent the magnitude of the read voltage Vread2.

[0155] The successive values ​​of the code TC show Fig.13 However, in some embodiments, the actual value of the code TC may be discontinuous. However, in order to easily describe how the amplitude of the read voltage Vread2 varies with the value of the code TC, the graph may be shown as being continuous with respect to the value of the code TC.

[0156] As reference Figure 7 As described above, in some embodiments, when the selection signal SEL has a logic value of "1", the voltage Vztc may be selected as the voltage Va, and the voltage Vntc may be selected as the voltage Vb. Also, when the selection signal SEL has a logic value of "0", the voltage Vntc may be selected as the voltage Va, and the voltage Vztc may be selected as the voltage Vb.

[0157] Referring to Equation 3, Figure 7 The magnitude of the voltage Vout2 in can be expressed by Equation 5.

[0158] [Equation 5]

[0159] Vfb=Vref+α*(Va-Vb)

[0160] The value of "Vntc" may be negatively proportional to the temperature. And, "Vztc" may have a uniform value regardless of the temperature. In Equation 5, in an operation where "Va" is "Vntc" and "Vb" is "Vztc" (for example, the logic value of the selection signal SEL is "0"), "Vfb" may be calculated as a value negatively proportional to the temperature. In Equation 5, in an operation where "Va" is "Vztc" and "Vb" is "Vntc" (for example, the logic value of the selection signal SEL is "1"), "Vfb" may be calculated as a value directly proportional to the temperature.

[0161] As reference Figure 4 As described above, the magnitude of the read voltage Vread2 may correspond to the magnitude of the feedback voltage Vfb, and the magnitude of the feedback voltage Vfb may correspond to the magnitude of the voltage Vout2 .

[0162] Since the threshold voltage of the memory cell varies with various conditions, a read voltage Vread2 having an amplitude that varies with the threshold voltage of the memory cell may be provided to accurately read the data stored in the memory cell. In an embodiment where the read voltage Vread2 is expected to have an amplitude that increases according to an increase in the value of the code TC, the logic circuit may output a selection signal SEL having a logic value of "1". In an embodiment where the read voltage Vread2 is expected to have an amplitude that decreases according to an increase in the value of the code TC, the logic circuit may output a selection signal SEL having a logic value of "0".

[0163] Fig.14 is a diagram showing some embodiments of the present invention. Figure 1 and / or Figure 4 A graph showing the voltage output by the read voltage generating circuit. Fig.14 In the example of a graph of , the x-axis may represent the temperature in units of ° C, and the y-axis may represent the voltage amplitude in units of V.

[0164] Reference Fig.14 , the amplitude of the read voltage Vread1 and the amplitude of the read voltage Vread2 may decrease as the temperature increases. Fig.14 In the temperature domain, the change of the differential non-linearity (DNL) value of the read voltage Vread1 may be greater than the change of the DNL value of the read voltage Vread2.

[0165] The DNL value may be associated with the difference between the amplitude of an ideal linear voltage and the amplitude of an actual voltage on a specific domain. That is, the DNL value may be associated with the linearity of the voltage amplitude on a specific domain. In the specification, high voltage linearity may refer to a small change in the DNL value of the voltage amplitude on a specific domain.

[0166] As reference Figures 4 to 11 As described above, since the voltage generating circuit 2000 is configured to output the read voltage Vread2 whose amplitude is proportional to the temperature, the amplitude of the read voltage Vread2 output from the voltage generating circuit 2000 can have high linearity over the temperature domain. Figure 1 and Figure 4 , in the temperature domain, the linearity of the read voltage Vread2 output from the voltage generating circuit 2000 may be higher than the linearity of the read voltage Vread1 output from the voltage generating circuit 1000 .

[0167] As reference Figure 8 As described above, "W_9" and "I41" of equation 4 may be selected to have values ​​proportional to "W_8" and "I32". Therefore, "α" of equation 4 may be calculated as a constant independent of temperature. However, "α" of equation 2 may include a square root term (a term that is nonlinear with temperature). Therefore, over the temperature domain, the linearity of the read voltage Vread2 may be higher than the linearity of the read voltage Vread1.

[0168] Fig.15 is a diagram showing some embodiments of the present invention. Figure 1 and / or Figure 4 A graph showing the voltage output by the read voltage generating circuit. Fig.15 In the example of a graph of , the x-axis may represent the value of code TC, TC1, or TC2, and the y-axis may represent the magnitude of the voltage expressed in unit V.

[0169] Reference Fig.15 , the amplitude of the read voltage Vread1 and the amplitude of the read voltage Vread2 may increase as the value of the code TC increases. In the code domain, the change of the DNL value of the read voltage Vread1 may be greater than the change of the DNL value of the read voltage Vread2.

[0170] As reference Figures 4 to 11 As described above, since the read voltage generating circuit 2000 is configured to output the read voltage Vread2 whose amplitude is proportional to the value of the code TC, the amplitude of the read voltage Vread2 output from the compensation circuit 2100 can have high linearity in the code domain. Figure 1 and Figure 4 , in the code domain, the linearity of the read voltage Vread2 output from the voltage generating circuit 2000 may be higher than the linearity of the read voltage Vread1 output from the read voltage generating circuit 1000 .

[0171] As reference Figure 8 As described above, "W_9" and "I41" of equation 4 may be selected to have values ​​proportional to "W_8" and "I32". Therefore, "α" of equation 4 may be calculated as a constant that is independent of the value of code TC. However, "α" of equation 2 may include a square root term (a term that is nonlinear with codes TC1 and TC2). Therefore, in the code domain, the linearity of the read voltage Vread2 may be higher than the linearity of the read voltage Vread1.

[0172] Fig.16 Some embodiments of the present invention include Figure 1 and / or Figure 4 Block diagram of an example memory system with a read voltage generation circuit.

[0173] The memory system 3000 may include a host 3100, a memory controller 3200, and a memory device 3300. The memory device 3300 may include memory devices 3300_1 to 3300_n. Each of the memory devices 3300_1 to 3300_n may include a logic circuit and a voltage generator. For example, the memory device 3300_1 may include a logic circuit 3210_1 and a voltage generator 3220_1.

[0174] The memory controller 3200 may exchange a command signal CMD, a data signal DAT, and an address signal ADDR with the host 3100. The command signal CMD may be associated with the operation of the memory device 3300. The data signal DAT may indicate data stored or to be stored in the memory device 3300. The address signal ADDR may indicate an address of a specific memory cell in the memory device 3300 corresponding to a location where the data is stored or to be stored.

[0175] The voltage generator 3220_1 can generate Figure 1 and 4 The voltages Vztc and Vntc and the reference voltage Vref are generated by the voltage generator 3220_1. For example, the voltage generator 3220_1 may generate the voltages Vztc and Vntc based on the temperature of the memory system 3000. The logic circuit 3210_1 may generate Figure 1 The codes TC1 and TC2 and Figure 4 The code is TC.

[0176] Each of the memory devices 3300_1 to 3300_n may include Figure 1 and Figure 4 At least one of the read voltage generating circuits 1000 and 2000 of the memory device 3300_1 to 3300_n. Each of the memory devices 3300_1 to 3300_n can generate a read voltage Vread1 or Vread2 based on the voltages Vztc and Vntc, the reference voltage Vref, the codes TC1 and TC2, and the code TC. For example, the logic circuit 3220 can track the change in the threshold voltage of the memory cell in the memory device 3300 to determine the values ​​of the codes TC1 and TC2 and the value of the code TC. The logic circuit 3220 can output the determined values ​​of the codes TC1, TC2, and TC to the memory device 3300.

[0177] The memory devices 3300_1 to 3300_n of the memory device 3300 may store or output data under the control of the memory controller 3200. The memory devices 3300_1 to 3300_n may read data by using a read voltage Vread 1 or Vread 2. The memory devices 3300_1 to 3300_n may have the same configuration or may have a similar configuration. Alternatively, the memory devices 3300_1 to 3300_n may have different configurations.

[0178] For example, each of the memory devices 3300_1 to 3300_n may include a volatile memory, such as SRAM, DRAM, SDRAM, etc., or a non-volatile memory, such as flash memory, PRAM, MRAM, ReRAM, FRAM, etc. Alternatively, the memory devices 3300_1 to 3300_n may include heterogeneous memories.

[0179] According to some embodiments of the inventive concept, an electronic circuit may be provided that generates a read voltage whose magnitude varies with changes in temperature and code value.

[0180] While the inventive concepts have been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concepts as set forth in the appended claims.

Claims

1. A compensation circuit, comprising: A reference current generating circuit, comprising: a first transistor of a first width, configured to transmit a first current, the reference current generating circuit being configured to output a reference current based on the first current; A compensation current generating circuit, comprising: a second transistor of a second width configured to transmit a second current, the second transistor being selected from a first group of transistors based on a code, the first group of transistors respectively having a width proportional to the first width, the compensation current generating circuit being configured to output a compensation current having an amplitude selected to be proportional to the amplitude of the reference current based on the second current; a current mirror circuit configured to output a compensation voltage having a magnitude based on a magnitude of the second current; and an output transistor configured to output a sense voltage based on the compensation voltage, Wherein, with respect to the first value, the second value and the third value of the code, when the difference between the first value and the second value is equal to the difference between the second value and the third value, the difference between the first amplitude of the sensing voltage output based on the first value and the second amplitude of the sensing voltage output based on the second value corresponds to the difference between the third amplitude of the sensing voltage output based on the third value and the second amplitude.

2. The compensation circuit according to claim 1, wherein: The reference current generating circuit further includes: A first current source configured to output the reference current; and A third transistor has the first width and is configured to transmit a third current for outputting the reference current to the first current source.

3. The compensation circuit according to claim 2, wherein: The magnitude of the reference current corresponds to the sum of the magnitude of the first current and the magnitude of the third current.

4. The compensation circuit according to claim 2, wherein: The compensation current generating circuit further includes: A second current source configured to output the compensation current; and A fourth transistor has the second width and is configured to transmit a fourth current for outputting the compensation current to the second current source.

5. The compensation circuit according to claim 4, further comprising a direction selection circuit, wherein the direction selection circuit is configured to: receiving a first gate voltage and a second gate voltage, wherein the magnitude of the first gate voltage varies with temperature and the magnitude of the second gate voltage is uniform regardless of temperature variation; outputting the first gate voltage to a gate terminal of the second transistor and outputting the second gate voltage to a gate terminal of the fourth transistor in response to a first logic value of a selection signal; and In response to a second logic value of the selection signal, the first gate voltage is output to a gate terminal of the fourth transistor, and the second gate voltage is output to a gate terminal of the second transistor.

6. The compensation circuit according to claim 4, in, The second current source includes a fifth transistor configured to transmit a fifth current in response to a reference value of the code for outputting the compensation current, and Wherein, a reference value is increased based on the value of the code, and the magnitude of the compensation current is increased by the magnitude of the fifth current.

7. The compensation circuit according to claim 4, wherein: The magnitude of the compensation current corresponds to the sum of the magnitude of the second current and the magnitude of the fourth current.

8. The compensation circuit according to claim 4, in, The second transistor includes a gate terminal receiving a first temperature-dependent voltage, and The amplitude of the first temperature-dependent voltage varies with temperature.

9. The compensation circuit according to claim 8, wherein: The fourth transistor includes a gate terminal receiving a second temperature-dependent voltage, and Wherein, the magnitude of the sensing voltage is further determined based on a difference between the first temperature-dependent voltage and the second temperature-dependent voltage.

10. The compensation circuit according to claim 4, wherein: The fourth transistor is selected from a second group of transistors based on the code, wherein transistors in the second group of transistors are configured to respectively have widths proportional to the first width.

11. The compensation circuit according to claim 4, wherein: The current mirror circuit comprises: a sixth transistor including a first terminal configured to output the compensation voltage, and the sixth transistor being configured to transmit the second current to the second transistor and transmit the third current to the third transistor; and A seventh transistor includes a gate terminal electrically connected to the gate terminal of the sixth transistor, the seventh transistor being configured to transmit the first current to the first transistor and to transmit the fourth current to the fourth transistor.

12. The compensation circuit according to claim 1, wherein: The reference current generating circuit is configured to output the reference current of a fixed amplitude.

13. A compensation circuit, comprising: A reference current generating circuit is configured to output a reference current of a fixed amplitude; a compensation current generating circuit configured to output a compensation current having an amplitude selected to be proportional to the amplitude of the reference current based on a code; a current mirror circuit configured to output a first current to the reference current generating circuit based on the reference current, output a second current based on the compensation current, and output a compensation voltage based on the first current and the second current; as well as an output transistor configured to output a sense voltage based on the compensation voltage, The amplitude of the sensing voltage is associated with the amplitude of the second current, so that when the code is a reference value, the amplitude of the sensing voltage is a reference amplitude, and when the value of the code increases by the reference value, the amplitude of the second current increases by the reference amplitude.

14. The compensation circuit according to claim 13, in, The reference current generating circuit includes a first transistor having a first width, the first transistor being configured to transmit the first current for outputting the reference current, The compensation current generating circuit includes a second transistor having a second width proportional to a first width of the first transistor, and the second transistor is configured to transmit the second current for outputting the compensation current.

15. The compensation circuit according to claim 14, in, The second transistor is selected from a group of transistors based on the code, the transistors in the group of transistors having a width proportional to the first width.

16. The compensation circuit according to claim 14, in, The compensation current generating circuit further includes a third transistor configured to transmit a third current based on the second current transmitted from the second transistor, and Wherein, whenever the value of the code increases by the reference value, the magnitude of the compensation current increases by the magnitude of the third current.

17. A voltage generating circuit, comprising: a compensation circuit configured to receive a reference voltage, a feedback voltage, a first temperature-dependent voltage, a second temperature-independent voltage, and a code having a variable value, respectively, and output a compensation voltage whose amplitude is based on the code based on the first temperature-dependent voltage and the second temperature-independent voltage, the amplitude of the first temperature-dependent voltage varying with a change in temperature, and the amplitude of the second temperature-independent voltage being uniform regardless of a change in temperature; as well as an output transistor configured to output a sense voltage having a magnitude based on a magnitude of the compensation voltage, The voltage generating circuit is configured to generate a sensing voltage whose amplitude is proportional to the value of the code, and the amplitude of the sensing voltage is associated with a difference between an amplitude of the first temperature-dependent voltage and an amplitude of the second temperature-independent voltage.

18. The voltage generating circuit according to claim 17, wherein: The compensation circuit is configured to receive the feedback voltage whose magnitude is based on the magnitude of the sense voltage, and output the compensation voltage further based on the feedback voltage.

19. The voltage generating circuit according to claim 17, in, The compensation circuit includes a plurality of transistors, wherein the compensation circuit is configured to select one or more transistors from among the plurality of transistors based on the code so that the selected one or more transistors transmit current in response to the first temperature-dependent voltage, and Wherein, the compensation voltage is output based on the current.

20. The voltage generating circuit according to claim 17, in, The magnitude of the first temperature-dependent voltage is negatively proportional to the temperature, and The magnitude of the sensed voltage is proportional to a value obtained by subtracting the magnitude of the first temperature-dependent voltage from the magnitude of the second temperature-independent voltage.

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