semiconductor structure

Abstract

One embodiment provides a semiconductor structure. The semiconductor structure includes a substrate. A fin is located on the substrate. The fin comprises silicon germanium. An interface layer is located on the fin. The interface layer has a thickness greater than 0 nm and less than or equal to approximately 4 nm. Source / drain regions are located on the interface layer. The source / drain regions comprise silicon germanium.

Description

Technical Field

[0001] Embodiments of the present invention relate to forming an interfacial layer between a fin and epitaxial source / drain regions of a FinFET. Background Art

[0002] As the semiconductor industry progresses to nanometer technology nodes, seeking higher device density, higher performance, and lower costs, challenges in manufacturing and design have led to the development of three-dimensional designs (such as fin field-effect transistors). Fin field-effect transistors typically include a high-aspect-ratio semiconductor fin in which the channel region and source / drain regions are formed. The gate is formed along the sidewalls and topside of the fin structure (e.g., wrapping the fin structure), which has the advantage of increasing the channel surface area, resulting in faster, more reliable, and better controlled semiconductor transistor devices. However, as dimensions decrease, this approach presents new challenges. Summary of the Invention

[0003] A semiconductor structure provided by one embodiment of the present invention includes: a substrate; a fin located on the substrate, the fin including silicon germanium and having a plurality of recessed portions; an interface layer located on the recessed portions of the fin, the thickness of the interface layer being between approximately 1 nm and approximately 4 nm; and a source / drain region located on the interface layer, the source / drain region including silicon germanium.

[0004] One embodiment of the present invention provides a method for forming a semiconductor device, including forming a fin on a substrate; forming a gate structure on the fin; forming a recess in the fin adjacent to the gate structure; forming an interface layer in the recess, wherein the interface layer includes silicon germanium; and epitaxially growing an epitaxial source / drain region on the interface layer.

[0005] One embodiment of the present invention provides a semiconductor structure, including a substrate; a fin located on the substrate; a first interface layer located on a first portion of the fin; a second interface layer located on a second portion of the fin, and the height variation between the first interface layer and the second interface layer is within 5 nm; a first source / drain region located on the first interface layer; and a second source / drain region located on the second interface layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a flow chart of a method for forming a semiconductor device such as a fin field effect transistor structure in some embodiments.

[0007] Figures 2A to 2B 、 Figures 3A to 3C 、 Figure 4A and Figure 4B 、 Figure 5A and Figure 5B 、 Figure 6A and Figure 6B 、 Figure 7A and Figure 7B,and Figure 8A and Figure 8B Various figures illustrate respective intermediate structures of a semiconductor device at intermediate stages of forming the semiconductor device in some embodiments.

[0008] Figure 6C and Figure 6D FIG. 1 is a diagram illustrating the atomic % content of the fin, the interface layer, and the source / drain regions in some embodiments.

[0009] Description of reference numerals:

[0010] AA, BB sections

[0011] L1 layer

[0012] L2 second layer

[0013] L3 layer

[0014] 10 methods

[0015] 12, 14, 16, 18, 20 steps 30 semiconductor structure

[0016] 54a, 54b, 54c, 54d, 54e, 54f, 94, 94A, 94B source / drain regions

[0017] 60 semiconductor substrates

[0018] 62n type well

[0019] 64 epitaxial layers

[0020] 74 fins

[0021] 78 Isolation Zone

[0022] 80 dielectric layer

[0023] 82 dummy gate layer

[0024] 84 Mask

[0025] 85 dummy gate structure

[0026] 86 gate spacer

[0027] 90 Depression

[0028] 90A first depression

[0029] 90B second depression

[0030] 92 interface layer

[0031] 92A first interface layer

[0032] 92B second interface layer

[0033] 92H, 94H height

[0034] 92T deposition thickness

[0035] 96 contact etch stop layer

[0036] 98, 99 directions

[0037] 100 first interlayer dielectric layer

[0038] 112 gate dielectric layer

[0039] 114 metal liner layer

[0040] 116 conductive gate filling layer

[0041] 130 second interlayer dielectric layer

[0042] 146, 146A, 146B, 146C contacts

[0043] Attached Figures 200 and 300 DETAILED DESCRIPTION

[0044] The following content provides different embodiments or examples that can implement different structures of the present invention. The embodiments of specific components and arrangements are used to simplify the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes the two being in direct contact, or the two being separated by other additional components rather than in direct contact. In addition, the numbering may be repeated in various examples of the present disclosure, but such repetition is only for simplification and clarity of description and does not mean that the units with the same numbering between different embodiments and / or settings have the same corresponding relationship.

[0045] Additionally, spatially relative terms such as "below," "beneath," "below," "above," "above," or similar terms may be used to simplify descriptions of an element's relative relationship to another element in a diagram. Spatially relative terms extend to elements used in other orientations and are not limited to the orientation shown. Elements may also be rotated 90° or other angles, so directional terms are used only to describe the orientation shown in the diagram.

[0046] Embodiments of the present invention generally relate to forming an interfacial layer between a fin and epitaxial source / drain regions of a FinFET device. For example, the fin may have a recess formed therein, and the interfacial layer may be formed along the surface of the recess, and the epitaxial source / drain regions may be formed on the interfacial layer. In these embodiments, the interfacial layer may suppress the effects of surface impurities formed during the formation of the FinFET device. In these embodiments, the interfacial layer may improve the growth uniformity of the epitaxial source / drain regions within the recess of the fin of the FinFET device.

[0047] The patterning method of the fins may be any suitable method. For example, one or more photolithographic processes (such as double patterning or multiple patterning processes) may be used to pattern the fins. Generally speaking, double patterning or multiple patterning processes combine photolithography with self-alignment processes, and the pattern spacing produced may be smaller than the pattern spacing obtained using a single direct photolithographic process. For example, one embodiment forms a sacrificial layer on a substrate and uses a photolithographic process to pattern the sacrificial layer. Using a self-alignment process, spacers are formed along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the retained spacers can then be used to pattern the fins.

[0048] The foregoing broadly summarizes some embodiments of the present invention. Some embodiments described herein are in the context of fin field effect transistors. Some embodiments described herein are in the context of replacement gate processes. Some embodiments may be implemented in other processes and / or other devices. For example, examples of other processes may include gate-first processes, while examples of other devices may include horizontal all-around gate field effect transistors, vertical all-around gate field effect transistors, nanowire channel field effect transistors, or other devices. Some variations of the method and structure examples are described below. It will be understood by those skilled in the art that other adjustments may be considered within the scope of other embodiments. Although the method of the embodiments is described in a particular order, other embodiments may perform the method in any logical order and may include more or fewer steps than the method described herein.

[0049] Figure 1 is a flow chart of a method 10 for forming a semiconductor device such as a fin field effect transistor structure in some embodiments. Figure 2A and Figures 2B to 8A and Figure 8B illustrate. Figure 2A and Figures 2B to 8A and Figure 8B 1 and 2 are cross-sectional and perspective views of respective intermediate semiconductor structures 30 at intermediate stages of a process for forming a semiconductor device in some embodiments.

[0050] Figure 2A and Figure 2B In some embodiments, the semiconductor substrate 60 is a semiconductor substrate. The semiconductor substrate 60 may be or include a semiconductor base substrate, a semiconductor-on-insulator substrate, or the like, and may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 60 may include a semiconductor element such as silicon or germanium, a semiconductor compound, a semiconductor alloy, or combinations thereof.

[0051] exist Figure 2A and Figure 2BIn the illustrated embodiment, the semiconductor substrate 60 may be a silicon wafer having regions implanted or doped with n-type dopants to form an n-well 62. Other regions of the semiconductor substrate 60 may be implanted or doped with p-type dopants to form a p-well (not shown). In these embodiments, a p-type FinFET device or a p-type metal oxide semiconductor device is formed on the n-well 62. The n-type dopant concentration in the n-well 62 may be between approximately 5×10 16 cm -3 to about 1×10 19 cm -3 In these embodiments, the epitaxial layer 64 can be deposited on the n-type well 62 by epitaxial growth. In these embodiments, the epitaxial layer 64 is a silicon germanium layer having a germanium atomic % content between about 5% and about 40%. In other embodiments, the epitaxial layer 64 is a silicon germanium layer having a germanium atomic % content between about 40% and about 80%. The epitaxial layer 64 can also include a compositionally graded layer, wherein the content of an element (e.g., germanium) varies along the depth of the epitaxial layer 64. The deposition method used to deposit the epitaxial layer 64 includes chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-vacuum chemical vapor deposition, remote plasma chemical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, any other suitable deposition process, or any combination of the foregoing.

[0052] like Figures 3A to 3C As shown, step 12 of method 10 forms fins 74 in the epitaxial layer 64 and the semiconductor substrate 60 (such as the n-type well 62). The fins 74 may be formed by etching trenches through the epitaxial layer 64 into the semiconductor substrate 60, such as into the n-type well 62. For example, the trenches may be formed using a suitable photolithography and etching process. Isolation regions 78 are then formed, each located in a corresponding trench. The isolation regions 78 may include or may be an insulating material such as an oxide (e.g., silicon oxide), a nitride, the like, or a combination thereof. The insulating material may be deposited by any acceptable deposition process, and the insulating material may be recessed by an acceptable etching process to form the isolation regions 78. The fins 74 protrude from between adjacent isolation regions 78, thereby at least partially defining the fins 74 as active regions on the semiconductor substrate 60.

[0053] In some embodiments, in addition to forming fins 74 from epitaxial layer 64, trenches may be etched into semiconductor substrate 60 to form fins 74, as previously described. Fins 74 can thus be made of the same material as the semiconductor substrate. In these embodiments, semiconductor substrate 60 is a silicon wafer, and fins 74 are also made of silicon. While fins 74 are generally shown in some subsequent figures, the epitaxial layer 64 may be included or omitted.

[0054] Those skilled in the art will appreciate that the above process is only one example of how to form fin 74. In other embodiments, a dielectric layer may be formed on the upper surface of semiconductor substrate 60, trenches may be etched through the dielectric layer, epitaxial structures (such as homoepitaxial structures or heteroepitaxial structures) may be epitaxially grown in the trenches, and the dielectric layer may be recessed so that the epitaxial structures protrude from the dielectric layer to form the fin. The fins formed by these processes generally have a structure similar to that shown.

[0055] like Figures 3A to 3C As shown, step 14 of method 10 forms a dummy gate structure 85 on the fin 74. The dummy gate structure 85 is located on the fin 74, and its lateral extension direction is perpendicular to the fin 74. Each dummy gate structure 85 includes a dielectric layer 80, a dummy gate layer 82, and a mask 84. The method for forming the dielectric layer, dummy gate layer 82, and mask 84 used for the dummy gate structure 85 can be to form individual layers in sequence (for example, using a suitable deposition process), and then pattern these layers into the dummy gate structure 85 (for example, using a suitable photolithography and etching process). For example, the dielectric layer 80 may include or be silicon oxide, silicon nitride, the like, or a multilayer thereof. The dummy gate layer 82 may include or be silicon (such as polysilicon) or another material. The mask 84 may include or be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof.

[0056] Figure 3C FIG3 is a three-dimensional diagram of an intermediate structure after forming dummy gate structures 85. Fins 74 are formed on semiconductor substrate 60, and each fin 74 protrudes upward between adjacent isolation regions 78. In each dummy gate structure 85, a dielectric layer 80 is formed along the sidewalls of fin 74 and on the upper surface of fin 74. A dummy gate layer 82 is located on dielectric layer 80, and a mask 84 is located on dummy gate layer 82. Source / drain regions 54a, 54b, 54c, 54d, 54e, and 54f are located in respective regions of fin 74 on both sides of dummy gate structure 85.

[0057] Figure 3C Reference cross sections used in the accompanying drawings are also shown. Cross section AA follows the channel region in the fin 74, between the source / drain regions 54a, 54b, and 54c on either side. Cross section BB is perpendicular to cross section AA and passes over the source / drain region 54a and the source / drain region 54d of the adjacent fin 74. The figures ending with "A" refer to cross-sectional views of various process examples corresponding to cross section AA, while the figures ending with "B" refer to cross-sectional views of various process examples corresponding to cross section BB. To facilitate depiction of the drawings, some of the drawings may omit the reference numbers of some components or structures to avoid obscuring other components or structures.

[0058] In some embodiments, after forming the dummy gate structure 85, a lightly doped drain region (not shown) may be formed in the fin 74. For example, the dummy gate structure 85 may be used as a mask to implant dopants into the fin 74. For example, examples of dopants used in the lightly doped drain region may include or may be boron (for p-type devices) or phosphorus or arsenic (for n-type devices), although other dopants may be used. The dopant concentration of the lightly doped drain region may be between about 10 15 cm -3 to about 10 17 cm -3 between.

[0059] like Figure 4A and Figure 4B As shown, gate spacers 86 are formed along the sidewalls of dummy gate structure 85 (e.g., the sidewalls of dielectric layer 80, dummy gate layer 82, and mask 84) and on fin 74. Gate spacers 86 may be formed by conformally depositing one or more layers for gate spacers 86 (e.g., using a suitable deposition process) and anisotropically etching one or more layers to form gate spacers 86 (e.g., using a suitable etching process). Gate spacers 86 may include or be silicon nitride, silicon oxynitride, silicon carbonitride, the like, multiple layers thereof, or combinations thereof.

[0060] like Figure 4A and Figure 4B As shown, step 16 of method 10 forms a recess 90 in the fin 74. As shown, the recess 90 is formed in the fin 74 on both sides of the dummy gate structure 85. The method for forming the recess 90 can be an etching process. The etching process can be isotropic or anisotropic, or selective to one or more crystal planes of the semiconductor substrate 60 and / or the epitaxial layer 64. Therefore, the recess can have a variety of cross-sectional profiles, depending on the etching process implemented. The etching process can be dry etching, such as plasma etching using a process gas, and the process gas includes but is not limited to carbon tetrafluoride, chlorine, nitrogen trifluoride, or sulfur hexafluoride.

[0061] like Figure 5A and Figure 5B As shown, step 18 of method 10 forms an interface layer 92 on the surface of each recess 90 in the fin 74. The interface layer 92 may include or may be silicon germanium (Si x Ge 1-x, and x may be between approximately 0 and 1). In these embodiments, the interface layer 92 comprises silicon germanium having a silicon atomic % content greater than or equal to approximately 90% (e.g., between approximately 90% and approximately 99.9%) and a germanium atomic % content less than or equal to approximately 10% (e.g., between approximately 0.1% and approximately 10%). In these embodiments, the interface layer 92 is deposited to a thickness 92T between approximately 1 nm and approximately 10 nm. In these embodiments, the interface layer 92 is deposited to a thickness 92T between approximately 1 nm and approximately 4 nm. In these embodiments, a first interface layer 92A is formed on a first portion of the fin 74 (e.g., in the first recess 90A), and a second interface layer 92B is formed on a second portion of the fin 74 (e.g., in the second recess 90B). The first interface layer 92A and the second interface layer 92B have a height 92H. The height 92H of the interface dielectric layer 92 is defined by the lowest point of the upper surface of the interface layer 92 in the recess 90 of the fin 74. In these embodiments, the difference between the height 92H of the first interface layer 92A and the height 92H of the second interface layer 92B is less than or equal to approximately 5 nm, such as greater than 0 nm and less than or equal to approximately 5 nm.

[0062] The interface layer 92 may be formed by epitaxially growing a material in the recess 90 , and the epitaxial growth method may be low pressure chemical vapor deposition, remote plasma chemical vapor deposition, metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, similar methods, or combinations thereof.

[0063] In one example, the growth process for the silicon-germanium interfacial layer includes an epitaxial growth process at a temperature between about 500° C. and about 800° C. The epitaxial growth process may be performed at a pressure between about 1 Torr and about 100 Torr. The process gas may include hydrogen chloride, silane, dichlorosilane, germanium, hydrogen, nitrogen, a carrier gas, other silicon precursors, other germanium precursors, other etching gases, other carrier gases, or combinations thereof.

[0064] In these embodiments, the interface layer 92 helps to suppress the effects of surface impurities formed on or in the fin 74 during the various stages of forming the semiconductor structure 30. The interface layer 92 helps to cover the impurities and helps to prevent the impurities from entering the underlying layers or preventing the underlying layers from diffusing outward. For example, the impurities can be chlorine, oxygen, carbon, fluorine, and / or silicon species created and retained by the etching process of step 16 of the recess 90 to form the fin 74. For example, the halogen impurities can come from etching gases used in the dry etching process, such as carbon tetrafluoride, chlorine, nitrogen trifluoride, or sulfur hexafluoride. Silicon impurities can come from silicon in the epitaxial layer 64 comprising silicon germanium or silicon. Oxygen impurities can come from partially etching the isolation region 78 containing silicon oxide. Carbon impurities can come from residual carbon material from the photoresist or other layers of the semiconductor structure 30.

[0065] The composition of the interface layer 92 is not limited by any theory unless specifically stated in the claims. The interface layer 92 includes a high content of silicon, with a silicon atomic % content greater than or equal to about 90% (e.g., between about 90% and about 99.9%), which helps suppress the effects of surface impurities and reduce roughness. In these embodiments, a high proportion of a silicon precursor, such as silane, is used when forming the interface layer 92 to help volatilize or remove impurities. In these embodiments, a large amount of silicon precursor (such as silane) when forming the interface layer 92 helps to cover or encapsulate impurities in the interface layer 92. The interface layer 92 helps to collect impurities, so that the impurities remain in the interface layer 92 rather than in the source / drain regions. Impurities in the source / drain regions may disrupt epitaxial growth and cause inconsistent growth of the source / drain regions. If the thickness of the interface layer 92 is less than 1 nm, surface impurities may still remain on the fin 74, or the interface layer 92 may not completely cover the surface impurities. If the thickness of the interface layer 92 is greater than 5 nm, undesirable lattice misalignment may occur in the epitaxial source / drain regions formed by epitaxial growth on the interface layer 92. The lattice misalignment in the epitaxial source / drain regions may lead to undesirable consequences, such as lower stress transferred to the channel of the strained channel device, which may reduce device performance.

[0066] In these embodiments, the interfacial layer 92 helps reduce the surface roughness of the recess 90 of the fin 74. The surface roughness of the recess 90 of the fin 74 may be greater than about 2.5 nm RMS. In these embodiments, the surface roughness of the interfacial layer 92 is less than or equal to about 2 nm RMS, such as between about 0.1 nm RMS and about 2 nm RMS. In these embodiments, the smooth interfacial layer 92 helps to form a uniform epitaxial growth of the epitaxial source / drain regions thereon. In these embodiments, the smooth interfacial layer 92 helps to reduce crystallographic dislocations in the epitaxial source / drain regions, resulting in increased conductivity of the epitaxial source / drain regions and / or increased adhesion of the epitaxial source / drain regions. In these embodiments, the smooth interfacial layer 92 helps to reduce crystallographic dislocations in the epitaxial source / drain regions, resulting in increased strain properties of the channel formed by the fin 74 under the dummy gate structure 85. For example, epitaxial source / drain regions (e.g., silicon germanium source / drain regions) can induce strain in the channel to increase semiconductor device performance. In these embodiments, the smooth interfacial layer 92 helps to uniformly grow the epitaxial source / drain regions with respect to both lateral and vertical growth, thereby controlling the shape of the epitaxial source / drain regions. In these embodiments, the smooth interfacial layer 92 helps to uniformly grow the epitaxial source / drain regions, achieving consistent size and shape. The consistent size and shape of the epitaxial source / drain regions facilitates the formation of consistent multiple contacts to the respective epitaxial source / drain regions.

[0067] like Figure 6A and Figure 6B As shown, step 20 of method 10 forms epitaxial source / drain regions 94 on the interface layer 92. The epitaxial source / drain regions 94 may include or may be silicon germanium (Si x Ge 1-x , and x may be between 0 and 1), silicon carbide, silicon phosphide, silicon carbon phosphide, germanium, a III-V semiconductor compound, a II-VI semiconductor compound, or the like.

[0068] In these embodiments, the epitaxial source / drain regions 94 comprise silicon germanium, the interfacial layer 92 comprises silicon germanium, and the fin 74 (e.g., epitaxial layer 64) comprises silicon germanium. In these embodiments, the epitaxial source / drain regions 94 comprise silicon germanium with a germanium atomic percentage greater than or equal to approximately 25% (e.g., between approximately 25% and approximately 70%); the interfacial layer 92 comprises silicon germanium with a silicon atomic percentage greater than or equal to approximately 90% (e.g., between approximately 90% and approximately 99.9%); and the fin 74 (e.g., epitaxial layer 64) comprises silicon germanium with a germanium atomic percentage greater than or equal to approximately 5% (e.g., between approximately 5% and approximately 40%). In these embodiments, the silicon germanium source / drain regions 94 have a germanium atomic percentage of approximately 20%, or greater than the silicon germanium atomic percentage of the fin 74.

[0069] In some cases, the epitaxial source / drain regions 94 may also be doped, such as by in-situ doping during epitaxial growth of the source / drain regions 94 and / or by implanting dopants into the epitaxial source / drain regions 94 after epitaxial growth. For example, examples of dopants for the epitaxial source / drain regions 94 may include or may be boron (for p-type devices) or phosphorus or arsenic (for n-type devices), although other dopants may be used. The dopant concentration of the epitaxial source / drain regions 94 (or other source / drain regions) may be between about 10 19 cm -3 to about 10 21 cm -3 The source / drain regions may be defined by doping (such as in-situ doping during fabrication and / or epitaxial growth, if appropriate) and / or epitaxial growth (if appropriate), which may further define the active region, i.e., where the source / drain regions are defined.

[0070] In these embodiments, the epitaxial source / drain region 94 may comprise multiple layers. In these examples, the epitaxial source / drain region 94 comprises a first layer L1, a second layer L2, and a third layer L3. In these embodiments, the epitaxial source / drain region comprises a first layer of silicon germanium, a second layer of silicon germanium, and a third layer of silicon germanium, wherein each layer has a different atomic percent germanium content and / or dopant concentration. In these embodiments, the epitaxial source / drain region 94 comprises a first layer of silicon germanium, a second layer of silicon germanium, and a third layer of capping material. The capping material may be or include silicon or another suitable material. In these embodiments, the capping material helps protect the underlying silicon germanium from environmental influences (such as oxidation and moisture). The capping layer may also form a better ohmic contact with the metal to establish electrical contact with the epitaxial source / drain region 94. In these embodiments, the capping material helps protect the underlying silicon germanium from germanium outgassing.

[0071] Although the epitaxial source / drain regions 94 are shown as three layers in the figures, the epitaxial source / drain regions 94 are not limited to these layers. In other embodiments, the epitaxial source / drain regions 94 may include one, two, or more layers. In other embodiments, the epitaxial source / drain regions 94 may include additional layers (e.g., additional middle layers or additional outer layers).

[0072] like Figure 6B As shown, two epitaxial source / drain regions 94 are formed into a merged source / drain region. In other embodiments, epitaxial source / drain regions 94 may form unmerged doped source / drain regions. Epitaxial source / drain regions 94 may be grown in other shapes depending on the lower surface of recess 90 and / or the lateral and vertical growth of epitaxial source / drain regions 94 on interface layer 92.

[0073] Epitaxial source / drain regions 94 may be formed on the interface layer 92 by epitaxially growing material in the recess 90, such as by low pressure chemical vapor deposition, remote plasma chemical vapor deposition, metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, similar methods, or combinations thereof. Figure 6A and Figure 6B As shown, due to the obstruction of isolation region 78, epitaxial source / drain regions 94 are initially grown vertically within recess 90, without horizontal growth of epitaxial source / drain regions 94. After recess 90 is completely filled, epitaxial source / drain regions 94 can be grown vertically and horizontally to form crystal planes corresponding to the crystallographic planes of semiconductor substrate 60. In some cases, different materials are used for the epitaxial source / drain regions of p-type and n-type devices. Using appropriate masks during recess or epitaxial growth allows for the use of different materials in different devices.

[0074] In these embodiments, the first interface layer 92A and the second interface layer 92B may have a height 92H that varies by less than or equal to approximately 5 nm. The variation in height 92H of less than or equal to approximately 5 nm facilitates the epitaxial growth of source / drain regions 94A and 94B on the interface layer 92, with the variation in height 94H ranging from approximately 0 nm to approximately 10 nm. For example, the height 94H of the first source / drain region 94A formed on the first interface layer 92A is substantially the same as the height 94H of the second source / drain region 94B formed on the second interface layer 92B. The height 94H of the source / drain region 94 is defined by the highest point of the top surface of the source / drain region 94.

[0075] Figure 6C In some embodiments, the direction 98 (e.g., through the fin 74, the interface layer 92, the source / drain region 94, and back through the interface layer 92 and the fin 74) is Figure 6A 200 ). The germanium atomic % content of the interface layer 92 is lower than the germanium atomic % content of the source / drain regions 94 and the fin 74 adjacent to the interface layer 92. The germanium atomic % content of the source / drain regions 94 is higher than the germanium atomic % content of the fin 74 adjacent to the interface layer 92.

[0076] Figure 6D In some embodiments, the direction 99 (eg, through the third layer L3, the second layer L2, the first layer L1, and the interface layer 92 of the source / drain region 94 to the fin 74) is Figure 6A 300 ). The germanium atomic % content of the interface layer 92 is lower than the germanium atomic % content of the first layer L1 of the source / drain region 94 and the fin 74 adjacent to the interface layer 92. The germanium atomic % content of the first layer L1 of the source / drain region 94 is higher than the germanium atomic % content of the fin 74 adjacent to the interface layer 92. The germanium atomic % content of the third layer L3 of the source / drain region 94 is lower than the germanium atomic % content of the second layer L2 of the source / drain region 94, but higher than the germanium atomic % content of the first layer L1 of the source / drain region 94.

[0077] like Figure 7A and Figure 7BAs shown, a contact etch stop layer 96 is formed, and a first interlayer dielectric layer 100 is formed on the contact etch stop layer 96. Generally speaking, the contact etch stop layer provides a mechanism for stopping the etching process when forming contacts or vias. The contact etch stop layer can be composed of a dielectric material that has a different etch selectivity than adjacent layers or components. The contact etch stop layer 96 can be deposited by a suitable deposition process on the surface of the epitaxial source / drain region 94, the sidewalls and upper surface of the gate spacer 86, the upper surface of the mask 84, and the upper surface of the isolation region 78. The contact etch stop layer 96 can include or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or a combination thereof. The first interlayer dielectric layer 100 may include or be silicon oxide, a low-k dielectric material (e.g., a material having a lower k than silicon oxide), silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, organosilicate glass, silicon oxycarbide, spin-on glass, spin-on polymer, carbon silicon material, compounds thereof, composites thereof, the like, or combinations thereof. After depositing the first interlayer dielectric layer 100, the first interlayer dielectric layer 100 may be planarized by chemical mechanical polishing (CMP), which may remove the mask 84 from the dummy gate structure 85 and expose the dummy gate layer 82.

[0078] like Figure 8A and Figure 8B The intermediate structure shown can replace the dummy gate structure 85 with individual replacement gate structures to form a second interlayer dielectric layer 130 and contacts 146A, 146B, and 146C. A suitable etching process can be used to remove the dummy gate structure 85 to form trenches. The trenches can be filled with individual replacement gate structures. Each replacement gate structure includes a compliant gate dielectric layer 112, an optional metal liner layer 114, and a conductive gate fill layer 116. The compliant gate dielectric layer 112, the optional metal liner layer 114, and the conductive gate fill layer 116 can be deposited using any suitable deposition technique.

[0079] A gate dielectric layer 112 is conformally formed in the trench, such as along the sidewalls and top surface of the fin 74 and along the sidewalls of the gate spacer 86. The gate dielectric layer 112 may be silicon oxide, silicon nitride, a high-k dielectric material, or multiple layers thereof. The high-k dielectric material, such as a dielectric having a dielectric constant greater than approximately 7.0, may include or be a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, titanium, yttrium, scandium, lutetium, gadolinium, strontium, dysprosium, calcium, samarium, or combinations thereof.

[0080] One or more metal liner layers 114 may be conformally formed on the gate dielectric layer 112. The metal liner layer 114 may include a capping layer, a barrier layer, and / or a work function adjustment layer. The capping layer and the barrier layer may be used to prevent impurities from diffusing into or out of underlying layers. The capping layer and / or the barrier layer may include tantalum nitride, titanium nitride, the like, or a combination thereof. The work function adjustment layer may be selected to adjust the work function value to achieve the desired threshold voltage of the transistor to be formed. Examples of work function adjustment layers include tantalum aluminum, tantalum nitride, tantalum aluminum carbide, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, titanium, titanium nitride, titanium aluminum nitride, silver, manganese, zirconium, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other suitable work function materials, or a combination thereof.

[0081] A conductive gate fill layer 116 is formed on the optional metal liner layer 114 (if implemented) and / or the gate dielectric layer 112 and fills the trench. The conductive gate fill layer 116 may include a metal-containing material such as tungsten, cobalt, ruthenium, aluminum, titanium nitride, tantalum nitride, tantalum carbide, titanium aluminum nitride, titanium aluminum carbide, titanium aluminum oxide, combinations thereof, multilayers thereof, or other suitable conductive materials.

[0082] Portions of the conductive gate fill layer 116 above the first interlayer dielectric layer 100, the contact etch stop layer 96, and the upper surface of the gate spacer 86, the metal liner layer 114 formed as needed, and the layers used for the gate dielectric layer 112 can be removed, and the removal method can be a planarization process such as a chemical mechanical polishing process.

[0083] A second interlayer dielectric layer 130 is formed over the first interlayer dielectric layer 100, the replacement gate structure, the gate spacer 86, and the contact etch stop layer 96. Although not shown, in some embodiments, an etch stop layer may be deposited over the first interlayer dielectric layer 100, and the second interlayer dielectric layer 130 may be deposited over the etch stop layer. The second interlayer dielectric layer 130 may include or be silicon oxide, a low-k dielectric material, silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, organosilicate glass, silicon oxycarbide, spin-on glass, spin-on polymer, carbon silicon material, compounds thereof, composites thereof, the like, or combinations thereof. The second interlayer dielectric layer 130 may be deposited using any acceptable deposition technique.

[0084] Openings are formed through the second interlayer dielectric layer 130, the first interlayer dielectric layer 100, and the contact etch stop layer 96 to the epitaxial source / drain regions 94 to expose at least a portion of the epitaxial source / drain regions 94. The openings may be formed using suitable photolithography and one or more etching processes. Contacts 146 are formed in the openings to the epitaxial source / drain regions 94. The contacts 146 may include a fill metal such as tungsten, aluminum, cobalt, ruthenium, copper, or other suitable metal. The contacts 146 may also include silicide on the respective epitaxial source / drain regions 94, and a barrier and / or adhesion layer between the fill metal and the sidewalls of the openings.

[0085] It is understood that the semiconductor devices and formation methods may also include additional layers such as photoresist layers, mask layers, diffusion barriers, capping layers, silicide regions, etch stop layers, dielectric layers, adhesion layers, and other suitable layers. It is understood that the substrate may include multiple structures (such as doped regions or wells, fins, source / drain regions, isolation regions, shallow trench isolation structures, gate structures, interconnect pads, through-holes, and other suitable structures) in and / or on the substrate. Multiple layers and / or structures may be used when manufacturing semiconductor devices and integrated circuits. In the steps of the methods and figures described herein, the substrate may also include additional materials formed in and / or on the substrate. The semiconductor devices and formation methods may also include additional processes, such as applying photoresist (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, drying, hard baking, inspection, etching, planarization, chemical mechanical polishing, wet cleaning, ashing, and / or other feasible processes. Although the source / drain regions are fabricated using recessed fins as described herein, source / drain regions may also be formed on non-recessed fins.

[0086] In these embodiments, the p-type FinFET in the FinFET device is formed on an n-type well and / or has p-type / p-type doped epitaxial source / drain regions. It is understood that the p-type FinFET device can also be integrated with the formation method of the n-type FinFET device.

[0087] The embodiments described herein generally relate to forming an interfacial layer, such as a silicon-germanium-containing interfacial layer, along the surface of a recess in a fin between the fin and epitaxial source / drain regions of a FinFET device. In these embodiments, the interfacial layer can suppress the effects of surface impurities during the formation of the FinFET device. In these embodiments, the interfacial layer can increase the uniformity of the growth of epitaxial source / drain regions in the respective recesses of the fin of the FinFET device. In these embodiments, the epitaxial source / drain regions include p-type doped silicon-germanium to induce stress in the channel region defined by the gate structure on the fin.

[0088] One embodiment provides a semiconductor structure. The semiconductor structure includes a substrate. A fin is located on the substrate. The fin comprises silicon germanium and has a plurality of recessed portions. An interface layer is located on the recessed portions of the fin. The thickness of the interface layer is between approximately 1 nm and approximately 4 nm. Source / drain regions are located on the interface layer. The source / drain regions comprise silicon germanium.

[0089] In some embodiments, the germanium atomic % content of the fin is between about 5% and about 40%.

[0090] In some embodiments, the source / drain regions have a germanium atomic % content between about 25% and about 70%.

[0091] In some embodiments, the source / drain regions include p-type dopants.

[0092] In some embodiments, the surface roughness of the interfacial layer is less than or equal to about 2 nm RMS.

[0093] In some embodiments, the interface layer encapsulates impurities on the surface of the fin.

[0094] In some embodiments, the interfacial layer includes silicon germanium.

[0095] In some embodiments, the interfacial layer has a silicon atomic % content of between about 90% and about 99.9%.

[0096] One embodiment provides a method for forming a semiconductor device. The method includes forming a fin on a substrate, forming a gate structure on the fin, forming a recess in the fin adjacent to the gate structure, forming an interface layer in the recess, the interface layer comprising silicon germanium, and epitaxially growing epitaxial source / drain regions on the interface layer.

[0097] In some embodiments, the interfacial layer has a silicon atomic % content greater than or equal to about 90%.

[0098] In some embodiments, the method of forming the interfacial layer includes providing a silicon precursor.

[0099] In some embodiments, the silicon precursor includes silane.

[0100] In some embodiments, the silane volatilizes impurities from the fin surface.

[0101] In some embodiments, the surface roughness of the interfacial layer is less than about 2 nm RMS for epitaxial growth of source / drain regions.

[0102] In some embodiments, the interface layer encapsulates impurities on the surface of the fin.

[0103] One embodiment provides another semiconductor structure. The semiconductor structure includes a substrate. A fin is located on the substrate. A first interface layer is located on a first portion of the fin. A second interface layer is located on a second portion of the fin. A height variation between the first interface layer and the second interface layer is within 5 nm. A first source / drain region is located on the first interface layer. A second source / drain region is located on the second interface layer.

[0104] In some embodiments, the first interface layer and the second interface layer each have a thickness between about 1 nm and about 4 nm.

[0105] In some embodiments, the first interface layer and the second interface layer each have a silicon atomic % content between about 90% and about 99.9%.

[0106] In some embodiments, the germanium atomic % content of the fin is between about 5% and about 40%.

[0107] In some embodiments, a height variation between the first source / drain region and the second source / drain region is less than about 10 nm.

[0108] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention may be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: a substrate; a fin located on the substrate, the fin comprising silicon germanium and having a plurality of recessed portions; an interface layer located on the recessed portions of the fin, wherein the thickness of the interface layer is between 1 nm and 4 nm, wherein the interface layer covers impurities on the surface of the fin; as well as a source / drain region located on the interface layer, wherein the source / drain region comprises silicon germanium, The surface roughness of the interface layer is smaller than the surface roughness of the recessed portions. 2 . The semiconductor structure of claim 1 , wherein the germanium atomic % content of the fin is between 5% and 40%. 3 . The semiconductor structure of claim 1 , wherein the germanium atomic % content of the source / drain region is between 25% and 70%. The semiconductor structure of claim 1 , wherein the source / drain regions comprise p-type dopants. The semiconductor structure according to claim 1 , wherein the surface roughness of the interface layer is less than or equal to 2 nm RMS. The semiconductor structure of claim 1 , wherein the interfacial layer comprises silicon germanium. 7 . The semiconductor structure of claim 6 , wherein the silicon atomic % content of the interface layer is between 90% and 99.9%. 8 . The semiconductor structure of claim 1 , wherein the interfacial layer comprises silicon germanium, and a germanium atomic % content of the interfacial layer is lower than a germanium atomic % content of the source / drain regions and the fin.

9. A method for forming a semiconductor structure, comprising: forming a fin on a substrate; forming a gate structure on the fin; forming a recess in the fin adjacent to the gate structure; forming an interface layer in the recess, the interface layer comprising silicon germanium, wherein the silicon atomic % content of the interface layer is greater than or equal to 90%; as well as Epitaxially growing an epitaxial source / drain region on the interface layer, The surface roughness of the interface layer is smaller than the surface roughness of the recess. 10 . The method for forming a semiconductor structure as claimed in claim 9 , wherein the method for forming the interface layer comprises providing a silicon precursor. The method for forming a semiconductor structure as claimed in claim 10 , wherein the silicon precursor comprises silane. 12 . The method for forming a semiconductor structure according to claim 11 , wherein the silane volatilizes impurities from the surface of the fin. 13 . The method for forming a semiconductor structure according to claim 9 , wherein the surface roughness of the interface layer is less than 2 nm RMS for growing the epitaxial source / drain regions. The method for forming a semiconductor structure as claimed in claim 9 , wherein the interface layer covers impurities on the surface of the fin. 15 . The method for forming a semiconductor structure according to claim 9 , wherein the interfacial layer comprises silicon germanium, and a germanium atomic % content of the interfacial layer is lower than a germanium atomic % content of the epitaxial source / drain regions and the fin.

16. A semiconductor structure comprising: a substrate; a fin located on the substrate, wherein the fin comprises silicon germanium; a first interface layer located on the first portion of the fin, wherein the first interface layer comprises silicon germanium; a second interface layer located on the second portion of the fin, wherein the second interface layer comprises silicon germanium, and wherein the height variation between the first interface layer and the second interface layer is within 5 nm; a first source / drain region located on the first interface layer, wherein the first source / drain region comprises silicon germanium, and the germanium atomic percentage content of the silicon germanium in the first interface layer is lower than the germanium atomic percentage content of the silicon germanium in the fin and the silicon germanium in the first source / drain region; and a second source / drain region located on the second interface layer, wherein the second source / drain region comprises silicon germanium, and the germanium atomic percentage content of the silicon germanium in the second interface layer is lower than the germanium atomic percentage content of the silicon germanium in the fin and the silicon germanium in the second source / drain region; The surface roughness of the first interface layer and the second interface layer is smaller than the surface roughness of the first portion and the second portion of the fin. 17 . The semiconductor structure of claim 16 , wherein the first interface layer and the second interface layer each have a thickness ranging from 1 nm to 4 nm. 18 . The semiconductor structure of claim 16 , wherein the first interface layer and the second interface layer each have a silicon atomic % content between 90% and 99.9%. The semiconductor structure of claim 16 , wherein the germanium atomic % content of the fin is between 5% and 40%. 20 . The semiconductor structure of claim 16 , wherein a height variation between the first source / drain region and the second source / drain region is less than 10 nm.

21. A method for forming a semiconductor structure, comprising: forming a fin and an isolation region on both sides of the fin, wherein the fin protrudes from a substrate; forming a dummy gate structure on the fin; forming a recess in the fin adjacent to the dummy gate structure; forming an interface layer in the recess, wherein the interface layer comprises silicon germanium, wherein the silicon atomic % content of the interface layer is greater than or equal to 90%; as well as epitaxially growing an epitaxial source / drain region on the interface layer, wherein the epitaxial source / drain region comprises silicon germanium, wherein the interface layer completely separates the epitaxial source / drain region from the fin, wherein the interface layer has a lower germanium atomic % content than the epitaxial source / drain region and the fin, The surface roughness of the interface layer is smaller than the surface roughness of the recess. 22 . The method for forming a semiconductor structure as claimed in claim 21 , wherein a thickness of the interface layer is between 1 nm and 4 nm. 23 . The method for forming a semiconductor structure according to claim 21 , wherein the interface layer covers impurities on the surface of the fin. 24 . The method for forming a semiconductor structure as claimed in claim 23 , wherein the impurity comprises chlorine, oxygen, carbon, or fluorine.

25. A method for forming a semiconductor structure, comprising: forming a first fin and a second fin, and forming an isolation region sandwiched between the first fin and the second fin; forming a dummy gate structure on the first fin and the second fin; forming a first recess in the first fin adjacent to the dummy gate structure, and forming a second recess in the second fin adjacent to the dummy gate structure; forming a first interface layer in the first recess and forming a second interface layer in the second recess, wherein the first interface layer is separated from the second interface layer; as well as Growing an epitaxial source / drain region on the first interface layer and the second interface layer, wherein the first interface layer and the second interface layer have a germanium atomic percentage less than the germanium atomic percentage of the first fin, the second fin, and the epitaxial source / drain region, wherein the epitaxial source / drain region comprises silicon germanium and has a germanium atomic percentage between 25% and 70%. The surface roughness of the first interface layer and the second interface layer is smaller than the surface roughness of the first recess and the second recess. 26 . The method for forming a semiconductor structure according to claim 25 , wherein the first interface layer and the second interface layer comprise silicon germanium, and a silicon atomic % content ranges from 90% to 99.9%. 27 . The method for forming a semiconductor structure according to claim 26 , wherein the first fin and the second fin comprise silicon germanium, and a germanium atomic % content is between 5% and 40%. 28 . The method of forming a semiconductor structure according to claim 27 , wherein the epitaxial source / drain region comprises silicon germanium and has a germanium atomic % content greater than that of the first fin and the second fin.

29. A method for forming a semiconductor structure as described in claim 25, wherein the difference between the first height of the first interface layer and the second height of the second interface layer is less than 5 nm, wherein the first height is the height of the lowest point of the upper surface of the first interface layer, and the second height is the height of the lowest point of the upper surface of the second interface layer.

30. A method for forming a semiconductor structure, comprising: forming a first fin and a second fin, and forming an isolation region sandwiched between the first fin and the second fin; forming a dummy gate structure on the first fin and the second fin; forming a first recess in the first fin adjacent to the dummy gate structure, and forming a second recess in the second fin adjacent to the dummy gate structure; forming a first interface layer in the first recess and forming a second interface layer in the second recess, wherein the first interface layer is separated from the second interface layer; as well as growing an epitaxial source / drain region on the first interface layer and the second interface layer, wherein the first interface layer and the second interface layer have a germanium atomic % content less than the germanium atomic % content of the first fin, the second fin, and the epitaxial source / drain region, wherein the epitaxial source / drain region includes a first silicon germanium layer on the first interface layer and the second interface layer, a second silicon germanium layer on the first silicon germanium layer, and a third silicon germanium layer on the second silicon germanium layer, wherein the first silicon germanium layer, the second silicon germanium layer, and the third silicon germanium layer each have a different germanium atomic % content, The surface roughness of the first interface layer and the second interface layer is smaller than the surface roughness of the first recess and the second recess. 31 . The method for forming a semiconductor structure according to claim 30 , wherein the first silicon germanium layer continuously extends from the first interface layer to the second interface layer.

32. A method for forming a semiconductor structure, comprising: forming a first fin and a second fin, and forming an isolation region sandwiched between the first fin and the second fin; forming a dummy gate structure on the first fin and the second fin; forming a first recess in the first fin adjacent to the dummy gate structure, and forming a second recess in the second fin adjacent to the dummy gate structure; forming a first interface layer in the first recess and forming a second interface layer in the second recess, wherein the first interface layer is separated from the second interface layer; as well as Growing an epitaxial source / drain region on the first interface layer and the second interface layer, wherein the first interface layer and the second interface layer have a germanium atomic % content less than the germanium atomic % content of the first fin, the second fin, and the epitaxial source / drain region, wherein the epitaxial source / drain region includes a first silicon germanium layer, a second silicon germanium layer, and a cap layer, wherein the cap layer includes a silicon-containing material, The surface roughness of the first interface layer and the second interface layer is smaller than the surface roughness of the first recess and the second recess.

33. A method for forming a semiconductor structure as described in claim 32, wherein the difference between the first height of the first interface layer and the second height of the second interface layer is less than 5 nm, wherein the first height is the height of the lowest point of the upper surface of the first interface layer, and the second height is the height of the lowest point of the upper surface of the second interface layer.

34. A semiconductor structure comprising: a substrate; A first fin and a second fin are located on the substrate, wherein the first fin and the second fin comprise silicon germanium with a first germanium atomic % content; a first interface layer on the first fin, wherein the first interface layer comprises silicon germanium with a second germanium atomic % content, wherein a surface roughness of the first interface layer is less than a surface roughness of the first fin below the first interface layer; a second interface layer on the second fin, wherein the second interface layer comprises silicon germanium with the second germanium atomic % content, and wherein a surface roughness of the second interface layer is less than a surface roughness of the second fin below the second interface layer; as well as A source / drain region is located on the first interface layer and the second interface layer, wherein the source / drain region comprises silicon germanium with a third germanium atomic % content, wherein the second germanium atomic % content is lower than the third germanium atomic % content and the first germanium atomic % content.

35. The semiconductor structure of claim 34, wherein the silicon germanium of the first and second interface layers has a silicon atomic % content between 90% and 99.9%.

36. A semiconductor structure as described in claim 34, wherein the source / drain region includes a first silicon germanium layer located on the first interface layer and the second interface layer, a second silicon germanium layer located on the first silicon germanium layer, and a third silicon germanium layer located on the second silicon germanium layer, wherein the first silicon germanium layer, the second silicon germanium layer, and the third silicon germanium layer each contain a different germanium atomic % content.

37. The semiconductor structure of claim 36, wherein the germanium atomic % content of the second silicon germanium layer is greater than the germanium atomic % content of the first silicon germanium layer.

38. The semiconductor structure of claim 37, wherein the germanium atomic % content of the second silicon germanium layer is greater than the germanium atomic % content of the third silicon germanium layer, and the germanium atomic % content of the third silicon germanium layer is greater than the germanium atomic % content of the first silicon germanium layer.

39. A semiconductor structure comprising: a first fin and a second fin, and an isolation region sandwiched between the first fin and the second fin; a first recess in the first fin, and a second recess in the second fin; A first interface layer is located in the first recess, and a second interface layer is located in the second recess, and the first interface layer is separated from the second interface layer; as well as an epitaxial source / drain region located on the first interface layer and the second interface layer, wherein the first interface layer and the second interface layer have a germanium atomic percentage less than the germanium atomic percentage of the first fin, the second fin, and the epitaxial source / drain region, wherein the epitaxial source / drain region comprises silicon germanium and has a germanium atomic percentage between 25% and 70%, The surface roughness of the first interface layer and the second interface layer is smaller than the surface roughness of the first recess and the second recess.

40. The semiconductor structure of claim 39, wherein the silicon atomic % content of the first interface layer is between 90% and 99.9%. The semiconductor structure of claim 39 , wherein the first fin and the second fin comprise silicon germanium and a germanium atomic % content is between 5% and 40%.

42. A semiconductor structure as described in claim 39, wherein the epitaxial source / drain region includes a first silicon germanium layer located on the first interface layer and a second silicon germanium layer located on the first silicon germanium layer, wherein the first silicon germanium layer and the second silicon germanium layer have different germanium atomic % contents. The semiconductor structure of claim 42 , wherein the first silicon germanium layer fills the first recess. The semiconductor structure of claim 42 , wherein the second silicon germanium layer extends over an upper surface of the first interface layer.

45. A semiconductor structure as described in claim 39, wherein the difference between a first height of the first interface layer and a second height of the second interface layer is less than 5 nm, wherein the first height is the height of the lowest point of the upper surface of the first interface layer, and the second height is the height of the lowest point of the upper surface of the second interface layer.

46. ​​A semiconductor structure comprising: A first fin and a second fin, and an isolation region are sandwiched between the first fin and the second fin, the first fin having a first recess, and the second fin having a second recess; a gate structure located on the first fin and the second fin; A first interface layer is located in the first recess, and a second interface layer is located in the second recess; and an epitaxial source / drain region located on the first interface layer and the second interface layer, wherein the first interface layer and the second interface layer have a germanium atomic % content that is less than the germanium atomic % content of the first fin, the second fin, and the epitaxial source / drain region, wherein the epitaxial source / drain region includes a first silicon germanium layer located on the first interface layer and the second interface layer, a second silicon germanium layer located on the first silicon germanium layer, and a third silicon germanium layer located on the second silicon germanium layer, wherein the first silicon germanium layer, the second silicon germanium layer, and the third silicon germanium layer each have a different germanium atomic % content, The surface roughness of the first interface layer and the second interface layer is smaller than the surface roughness of the first recess and the second recess. The semiconductor structure of claim 46 , wherein the silicon atomic % content of the first interface layer is greater than 90%. The semiconductor structure of claim 47 , wherein the thickness of the first interface layer is between 1 nm and 4 nm. The semiconductor structure of claim 47 , wherein the surface roughness of the first interface layer is between 0.1 nm RMS and 2 nm RMS.

50. The semiconductor structure of claim 46, wherein: The epitaxial source / drain regions include silicon germanium with a germanium atomic % content ranging from 25% to 70%; The first interface layer comprises silicon germanium and has a silicon atomic % content between 90% and 99.9%; and The first fin includes silicon germanium and a germanium atomic % content ranges from 5% to 40%.

51. The semiconductor structure of claim 46, wherein the epitaxial source / drain regions have a greater germanium atomic % content than the first fin. 52 . The semiconductor structure of claim 46 , wherein a height variation between the first interface layer and the second interface layer is less than or equal to 5 nm. 53 . The semiconductor structure of claim 52 , wherein a height variation between the epitaxial source / drain region on the first recess and the epitaxial source / drain region on the second recess is between 0 nm and 10 nm.

54. A semiconductor structure comprising: a first fin, and an isolation region adjacent to the first fin; a gate structure located on the first fin; a first recess located in the first fin adjacent to the gate structure; a first interface layer located in the first recess; as well as an epitaxial source / drain region located on the first interface layer, wherein the first interface layer has a germanium atomic % content less than the germanium atomic % content of the first fin and the epitaxial source / drain region, wherein the epitaxial source / drain region includes a first silicon germanium layer, a second silicon germanium layer, and a cap layer, wherein the cap layer includes a silicon-containing material, The surface roughness of the first interface layer is smaller than the surface roughness of the first recess.

55. The semiconductor structure of claim 54, wherein the germanium atomic % content of the second silicon germanium layer is greater than the germanium atomic % content of the first silicon germanium layer.

56. A semiconductor structure as described in claim 55, wherein the epitaxial source / drain region includes a third silicon germanium layer sandwiched between the second silicon germanium layer and the cap layer, wherein the germanium atomic % content of the second silicon germanium layer is greater than the germanium atomic % content of the third silicon germanium layer, and the germanium atomic % content of the third silicon germanium layer is greater than the germanium atomic % content of the first silicon germanium layer. The semiconductor structure of claim 54 , wherein the thickness of the first interface layer is between 1 nm and 4 nm.

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