Semiconductor Devices

Abstract

A semiconductor device is provided, comprising: a multi-channel active pattern on a substrate; a high dielectric constant insulating layer formed on and along the multi-channel active pattern, wherein the high dielectric constant insulating layer contains metal; a silicon nitride layer formed on and along the high dielectric constant insulating layer; and a gate electrode on the silicon nitride layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0067146 filed in the Korean Intellectual Property Office on June 12, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device using a multi-channel active pattern as a channel region. Background Art

[0004] As one of scaling-down technologies for increasing the density of semiconductor devices, a gate-all-around structure has been proposed in which a nanowire-shaped silicon body is formed on a substrate and a gate is formed to surround the silicon body.

[0005] Since this all-around gate structure uses a three-dimensional channel, it is easy to achieve shrinkage. In addition, the current control capability can be improved without increasing the gate length. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed. Summary of the invention

[0006] Aspects of the inventive concept provide a semiconductor device having improved performance and reliability by improving interface characteristics of a gate insulating layer.

[0007] Aspects of the inventive concept are not limited to the above contents, and other aspects not mentioned can be clearly understood by those skilled in the art from the following description.

[0008] According to some example embodiments conceived in the present invention, there is provided a semiconductor device, comprising: a multi-channel active pattern on a substrate; a high dielectric constant insulating layer formed on the multi-channel active pattern along the multi-channel active pattern, wherein the high dielectric constant insulating layer contains metal; a silicon nitride layer formed on the high dielectric constant insulating layer along the high dielectric constant insulating layer; and a gate electrode on the silicon nitride layer.

[0009] According to some example embodiments of the present invention, there is provided a semiconductor device, comprising: a multi-channel active pattern on a substrate; a gate insulating layer formed on the multi-channel active pattern along the multi-channel active pattern, wherein the gate insulating layer comprises an interface layer and a high dielectric constant insulating layer; and a gate electrode structure on the gate insulating layer, wherein the gate electrode structure comprises a work function adjustment liner contacting the gate insulating layer, the dielectric constant of the work function adjustment liner is smaller than the dielectric constant of the high dielectric constant insulating layer, and the thickness of the work function adjustment liner is smaller than the thickness of the high dielectric constant insulating layer.

[0010] According to some example embodiments conceived in the present invention, there is provided a semiconductor device, comprising: a first nanowire on a substrate; a second nanowire spaced apart from the first nanowire; a gate insulating layer formed on the first nanowire and the second nanowire along a periphery of the first nanowire and a periphery of the second nanowire, wherein the gate insulating layer comprises a metal; a silicon nitride layer formed on the gate insulating layer along a periphery of the first nanowire and a periphery of the second nanowire, the silicon nitride layer being in contact with the gate insulating layer; and a gate electrode on the silicon nitride layer, comprising a conductive liner containing titanium, the conductive liner being formed along a periphery of the first nanowire and a periphery of the second nanowire.

[0011] According to some example embodiments conceived in the present invention, there is provided a semiconductor device, comprising: a substrate, comprising a first region and a second region; a first multi-channel active pattern on the substrate in the first region; a first high dielectric constant insulating layer formed on the first multi-channel active pattern along the first multi-channel active pattern, wherein the first high dielectric constant insulating layer contains metal; a first gate electrode structure, comprising a first silicon nitride layer and a first conductive liner, the first silicon nitride layer and the first conductive liner are formed on the first high dielectric constant insulating layer along the first high dielectric constant insulating layer, and the first conductive liner is disposed on the first silicon nitride layer; a second multi-channel active pattern on the substrate in the second region; a second high dielectric constant insulating layer formed on the second multi-channel active pattern along the second multi-channel active pattern, wherein the second high dielectric constant insulating layer contains metal; and a second gate electrode structure, comprising a second conductive liner formed on the second high dielectric constant insulating layer along the second high dielectric constant insulating layer.

[0012] According to some example embodiments of the present invention, there is provided a semiconductor device, comprising: a substrate, comprising a first region and a second region; a first multi-channel active pattern on the substrate in the first region; a first high dielectric constant insulating layer formed on the first multi-channel active pattern along the first multi-channel active pattern, wherein the first high dielectric constant insulating layer contains metal; a first gate electrode structure, comprising a first silicon nitride layer and a first conductive liner, the first silicon nitride layer and the first conductive liner are formed on the first high dielectric constant insulating layer along the first high dielectric constant insulating layer, the first conductive liner is disposed on the first silicon nitride layer; a second multi-channel active pattern on the substrate in the second region; a second high dielectric constant insulating layer formed on the second multi-channel active pattern along the second multi-channel active pattern, wherein the second high dielectric constant insulating layer contains metal; and a second gate electrode structure, comprising a second silicon nitride layer and a second conductive liner, the second silicon nitride layer and the second conductive liner are formed on the second high dielectric constant insulating layer along the second high dielectric constant insulating layer, the second conductive liner is disposed on the second silicon nitride layer, and the structure of the second conductive liner is different from that of the first conductive liner.

[0013] According to some example embodiments of the present invention, there is provided a semiconductor device, comprising: a first p-type transistor formed in a first region of a substrate and having a first threshold voltage; and a second p-type transistor formed in a second region of the substrate and having a second threshold voltage lower than the first threshold voltage, wherein the first p-type transistor comprises: a first nanowire and a second nanowire sequentially disposed on the substrate; a first gate insulating layer formed along a periphery of the first nanowire and a periphery of the second nanowire; and a first gate electrode surrounding the first nanowire and the second nanowire on the first gate insulating layer, wherein the first gate electrode comprises a first nanowire and a second nanowire sequentially disposed along a periphery of the first nanowire and a periphery of the second nanowire. A first titanium nitride layer and a first titanium silicon nitride layer are formed, and a first upper electrode is formed on the first titanium silicon nitride layer, the second p-type transistor includes: a third nanowire and a fourth nanowire are sequentially arranged on the substrate; a second gate insulating layer is formed along the periphery of the third nanowire and the periphery of the fourth nanowire; and a second gate electrode surrounding the third nanowire and the fourth nanowire on the second gate insulating layer, wherein the second gate electrode includes a second titanium nitride layer and a second titanium silicon nitride layer, wherein the second titanium nitride layer and the second titanium silicon nitride layer are formed along the periphery of the third nanowire and the periphery of the fourth nanowire, and the ratio of the thickness of the first titanium silicon nitride layer to the thickness of the first titanium nitride layer is in the range of about 5 / 3 to about 7. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects and features of the inventive concept will become more apparent by describing in detail example embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0015] Figures 1 to 3 is a diagram for explaining a semiconductor device according to some embodiments of the inventive concept;

[0016] FIG. 4A to FIG. 4D It is taken along BB Figure 1 Various cross-sectional views of the first line pattern;

[0017] FIG. 5A to FIG. 5C and Figure 6 It is taken along AA Figure 1 Various cross-sectional views of the first line pattern;

[0018] Figure 7 and Figure 8 is a diagram for explaining a semiconductor device according to some embodiments of the inventive concept;

[0019] Fig. 9 and Fig.10 is a diagram for explaining a semiconductor device according to some embodiments of the inventive concept;

[0020] Figures 11 to 13 are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept;

[0021] Fig.14 and Fig.15 is a diagram for explaining a semiconductor device according to some embodiments of the inventive concept;

[0022] Figures 16 to 18 is a diagram for explaining a semiconductor device according to some embodiments of the inventive concept;

[0023] Fig.19 and Fig. 20 are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept;

[0024] Fig.21 and Fig. 22 are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept;

[0025] Figures 23 to 24D is a diagram for explaining a semiconductor device according to some embodiments of the inventive concept;

[0026] FIG. 25A to FIG. 25D is a diagram for explaining a semiconductor device according to some embodiments of the inventive concept;

[0027] Figure 26 to Figure 28 are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept; and

[0028] Figures 29 to 34 are diagrams for explaining intermediate steps of a method for fabricating a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0029] In the illustration of the semiconductor device of some embodiments of the present invention, a gate-all-around transistor (GAA FET) including a nanowire-shaped or nanosheet-shaped channel region is exemplarily shown, but is not limited thereto. The semiconductor device of some embodiments of the present invention may include a tunneling transistor (FET), a bipolar junction transistor, a lateral double diffused transistor (LDMOS), etc.

[0030] Figures 1 to 3 are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept. Figure 1 is a plan view for explaining a semiconductor device according to some embodiments of the inventive concept, and Figure 2 and Figure 3 Along Figure 1 A cross-sectional view taken along lines AA and BB. FIG. 4A to FIG. 4D It is taken along BB Figure 1 Various cross-sectional views of the first line patterns. FIG. 5A to FIG. 5C and Figure 6 It is taken along AA Figure 1 Various cross-sectional views of the first line pattern. For ease of illustration, Figure 1 The interlayer insulating layer 190 is not shown.

[0031] Reference Figures 1 to 3 , a semiconductor device according to some embodiments of the inventive concept may include a first multi-channel active pattern 110, a second multi-channel active pattern 210, a first gate electrode structure 115, and a first gate insulating layer 135. The first gate electrode structure 115 may include a first work function adjustment liner 130 and a first gate electrode 120.

[0032] The substrate 100 may be bulk silicon or silicon on insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate, or may include, but is not limited to, other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0033] The first fin-type protrusion 100P may protrude from the substrate 100 . The first fin-type protrusion 100P may extend longitudinally in the first direction X1 . The first fin-type protrusion 100P may be formed by etching a portion of the substrate 100 , or may include an epitaxial layer grown from the substrate 100 .

[0034] The first fin-type protrusion 100P may include silicon or germanium as an elemental semiconductor material. In addition, the first fin-type protrusion 100P may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge) and tin (Sn), or a compound obtained by doping these elements with group IV elements. For example, the group III-V compound semiconductor may be, for example, a binary compound, a ternary compound or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga) and indium (In) as group III elements with at least one of phosphorus (P), arsenic (As) and antimony (Sb) as group V elements.

[0035] A field insulating layer 105 may be formed on the substrate 100. The field insulating layer 105 may surround at least a portion of a sidewall of the first fin-type protrusion 100P. The first fin-type protrusion 100P may be defined by the field insulating layer 105. Figure 3 , the sidewall of the first fin type protrusion 100P is illustrated as being completely surrounded by the field insulation layer 105 , but this is for convenience of explanation and the inventive concept is not limited thereto.

[0036] The field insulating layer 105 may include, for example, one of an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof. In addition, the field insulating layer 105 may further include at least one field liner (not shown) formed between the first fin-type protrusion 100P and the field insulating layer 105. When the field insulating film 105 further includes a field liner, the field liner may include at least one of polycrystalline silicon, amorphous silicon, silicon oxynitride, silicon nitride, and / or silicon oxide.

[0037] The first multi-channel active pattern 110 and the second multi-channel active pattern 210 may be sequentially formed on the substrate 100. For example, the first multi-channel active pattern 110 and the second multi-channel active pattern 210 may be sequentially disposed on the first fin-type protrusion 100P. In the semiconductor device according to some embodiments of the inventive concept, the distance at which the first fin-type protrusion 100P and the first multi-channel active pattern 110 are spaced apart from each other in the height direction may be substantially equal to the distance at which the first multi-channel active pattern 110 and the second multi-channel active pattern 210 are spaced apart from each other in the height direction.

[0038] The first multi-channel active pattern 110 and the second multi-channel active pattern 210 may extend in the first direction X1 like the first fin type protrusion 100P, respectively. The first multi-channel active pattern 110 and the second multi-channel active pattern 210 may be sequentially arranged in the thickness direction of the substrate 100 .

[0039] The first multi-channel active pattern 110 may be formed to be spaced apart from the substrate 100. For example, the first multi-channel active pattern 110 may be formed to be spaced apart from the first fin-type protrusion 100P. The first multi-channel active pattern 110 may overlap with the first fin-type protrusion 100P in the vertical direction. The first multi-channel active pattern 110 is not formed on the field insulating layer 105 along the upper surface of the field insulating layer 105, but may be formed on the first fin-type protrusion 100P along the upper surface of the first fin-type protrusion 100P. The second multi-channel active pattern 210 may be formed to be spaced apart from the first multi-channel active pattern 110. Since the first multi-channel active pattern 110 is formed to be spaced apart from the substrate 100 and the first fin-type protrusion 100P, the second multi-channel active pattern 210 may also be formed to be spaced apart from the substrate 100 and the first fin-type protrusion 100P.

[0040] The first multi-channel active pattern 110 and the second multi-channel active pattern 210 may include silicon or germanium as an elemental semiconductor material, respectively.

[0041] The second multi-channel active pattern 210 may include a compound semiconductor, respectively, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The first multi-channel active pattern 110 and the second multi-channel active pattern 210 may be used as a channel region of a transistor, respectively. Each of the first multi-channel active pattern 110 and the second multi-channel active pattern 210 may include the same material, or may include other materials. Each of the first multi-channel active pattern 110 and the second multi-channel active pattern 210 may include the same material as the first fin-type protrusion 100P, or may include a material different from the first fin-type protrusion 100P.

[0042] In the semiconductor device according to some embodiments of the present inventive concept, the first multi-channel active pattern 110 and the second multi-channel active pattern 210 may include nanowires. For example, the first multi-channel active pattern 110 may be a first nanowire, and the second multi-channel active pattern 210 may be a second nanowire. In the following description, each of the first multi-channel active pattern 110 and the second multi-channel active pattern 210 will be described as a silicon-containing nanowire.

[0043] exist Figures 1 to 3 , two multi-channel active patterns 110 and 210 are shown to be formed on the substrate 100 spaced apart from each other, but this is only for convenience of explanation, and the inventive concept is not limited thereto. In other words, one multi-channel active pattern may be formed on the substrate 100, and three or more multi-channel active patterns spaced apart from each other may be formed on the substrate 100.

[0044] The first gate spacer 140 may extend in the second direction Y1. The first gate spacer 140 may intersect the first multi-channel active pattern 110 and the second multi-channel active pattern 210. The first gate spacer 140 may define a first gate trench 140t intersecting the first multi-channel active pattern 110 and the second multi-channel active pattern 210.

[0045] The first gate spacer 140 may be located at both ends of each of the first multi-channel active pattern 110 and the second multi-channel active pattern 210 extending in the first direction X1. The first gate spacer 140 may be formed at both sides of the first multi-channel active pattern 110 and the second multi-channel active pattern 210 to face each other. The first gate spacer 140 may include a penetration portion through which the first multi-channel active pattern 110 and the second multi-channel active pattern 210 pass, respectively. Each of the first multi-channel active pattern 110 and the second multi-channel active pattern 210 may pass through the first gate spacer 140. The first gate spacer 140 may be in full contact with the outer periphery of each end of the first multi-channel active pattern 110 and the second multi-channel active pattern 210.

[0046] The first gate spacer 140 includes a first inner spacer 141 and a first outer spacer 142. The first inner spacer 141 may be disposed between the first fin type protrusion 100P and the first multi-channel active pattern 110 and between the first multi-channel active pattern 110 and the second multi-channel active pattern 210.

[0047] The first inner spacer 141 may be formed at a position vertically overlapping the first multi-channel active pattern 110 and the second multi-channel active pattern 210. The first inner spacer 141 may not be formed on the field insulating layer 105 that does not overlap the first multi-channel active pattern 110 and the second multi-channel active pattern 210. That is, the first outer spacer 142 may be formed on the upper surface of the field insulating layer 105. The first outer spacer 142 may be located on the second multi-channel active pattern 210.

[0048] The first inner spacer 141 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxynitride (SiOCN), and combinations thereof. The first outer spacer 142 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), and at least one of a combination thereof. Figure 2 In the embodiment, the first inner spacer 141 and the first outer spacer 142 may be the same material or different materials.

[0049] The first gate insulating layer 135 may be formed along the first multi-channel active pattern 110 and the second multi-channel active pattern 210. The first gate insulating layer 135 may be formed along the outer periphery of each of the first multi-channel active pattern 110 and the second multi-channel active pattern 210. The first gate insulating layer 135 may surround each of the first multi-channel active pattern 110 and the second multi-channel active pattern 210.

[0050] The first gate insulating layer 135 may include a first interface layer 136 and a first high dielectric constant insulating layer 137. The first interface layer 136 may be formed between the first and second multi-channel active patterns 110 and 210, respectively, and the first high dielectric constant insulating layer 137. The first interface layer 136 may be formed along an upper surface of the first fin type protrusion 100P and the first and second multi-channel active patterns 110 and 210.

[0051] Although the first interface layer 136 is not formed along the inner wall of the first gate spacer 140 and the upper surface of the field insulation layer 105, the inventive concept is not limited thereto. Depending on the method of forming the interface layer, the first interface layer 136 may be formed along the sidewall of the first gate spacer 140 and the upper surface of the field insulation layer 105.

[0052] The first high dielectric constant insulating layer 137 may be formed on the first interface layer 136. The first gate insulating layer 135 may also be formed on the upper surface of the field insulating layer 105 and on the first fin-type protrusion 100P. The first gate insulating layer 135 may extend along the inner wall of the gate spacer 140. The first gate insulating layer 135 may extend along the sidewall and bottom surface of the first gate trench 140t and the periphery of the first multi-channel active pattern 110 and the second multi-channel active pattern 210. When the first multi-channel active pattern 110 and the second multi-channel active pattern 210 include silicon, the first interface layer 136 may include silicon oxide (SiO 2 On the other hand, depending on the materials contained in the first multi-channel active pattern 110 and the second multi-channel active pattern 210, the material contained in the first interface layer 136 may of course vary.

[0053] It should be understood that in some embodiments, the high dielectric constant or high κ material may include a material with a dielectric constant greater than that of silicon dioxide. In some embodiments, the first high dielectric constant insulating layer 137 may include a high dielectric constant material with a dielectric constant greater than that of silicon nitride. The first high dielectric constant insulating layer 137 may include a metal-containing insulating material. The high dielectric constant material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0054] The first gate electrode structure 115 may be formed on the first gate insulating layer 135. The first gate electrode structure 115 may contact the first high dielectric constant insulating layer 137. The first gate electrode structure 115 may intersect the first multi-channel active pattern 110 and the second multi-channel active pattern 210. The first gate electrode structure 115 may surround the periphery of the first multi-channel active pattern 110 and the second multi-channel active pattern 210. The first gate electrode structure 115 may be disposed between the first gate spacers 140. The first gate electrode structure 115 fills the first gate trench 140t and may extend in the second direction Y1.

[0055] The first work function adjustment liner 130 may be formed along the first high dielectric constant insulating layer 137. The first work function adjustment liner 130 may be formed along the periphery of the first multi-channel active pattern 110 and the second multi-channel active pattern 210. The first work function adjustment liner 130 may be in contact with the first high dielectric constant insulating layer 137. Here, the term "contact" may mean that there is no intervening layer between the first work function adjustment liner 130 and the first high dielectric constant insulating layer 137.

[0056] The first work function adjustment liner 130 may include an insulating material. The first work function adjustment liner 130 may include an insulating material with a dielectric constant smaller than that of the first high dielectric constant insulating layer 137. The first work function adjustment liner 130 may include, for example, silicon nitride (SiN). In semiconductor devices according to some embodiments of the present inventive concept, the first work function adjustment liner 130 may be a silicon nitride layer.

[0057] For example, the thickness t12 of the first work function adjustment liner 130 is smaller than the thickness t11 of the first high dielectric constant insulating layer 137. The thickness t12 of the first work function adjustment liner 130 may be, for example or smaller.

[0058] Since the first work function adjustment liner 130 is formed to contact the first high dielectric constant insulating layer 137, the effective work function of the semiconductor device can be adjusted. As a result, the threshold voltage of the semiconductor device can be controlled.

[0059] The first gate electrode 120 may be formed on the first work function adjustment liner 130. The first gate electrode 120 may be in contact with the first work function adjustment liner 130. The first gate electrode 120 may include a first conductive liner 121 and a first upper electrode 122.

[0060] The first conductive liner 121 may be formed on the first work function adjustment liner 130. The first conductive liner 121 may be in contact with the first work function adjustment liner 130. The first conductive liner 121 may be formed along the first work function adjustment liner 130. The first conductive liner 121 may be formed along the periphery of the first multi-channel active pattern 110 and the second multi-channel active pattern 210. The first conductive liner 121 may be formed between an upper surface of the first fin type protrusion 100P and a lower surface of the first multi-channel active pattern 110 and between an upper surface of the first multi-channel active pattern 110 and a lower surface of the second multi-channel active pattern 210. The first conductive liner 121 may be formed on an upper surface of the second multi-channel active pattern 210.

[0061] The first conductive liner 121 may include a conductive material. The first conductive liner 121 may include titanium (Ti) as a metal element. The first conductive liner 121 may include, for example, at least one of titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), and titanium aluminum carbide nitride (TiAlC-N).

[0062] As an example, the first conductive liner 121 may include a conductive nitride layer. The first conductive liner 121 may be a conductive layer made of, for example, a material selected from titanium nitride (TiN) and titanium silicon nitride (TiSiN). As another example, the first conductive liner 121 may include an aluminum-containing conductive layer. The aluminum-containing conductive layer may also include a conductive nitride layer. The first conductive liner 121 may be a conductive layer made of, for example, at least one material selected from the group consisting of titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), and titanium aluminum carbide nitride (TiAlC-N).

[0063] The first upper electrode 122 may be formed on the first conductive liner 121. Figure 2 and Figure 3 , the first upper electrode 122 is shown as not being formed between the upper surface of the first fin type protrusion 100P and the lower surface of the first multi-channel active pattern 110 and between the upper surface of the first multi-channel active pattern 110 and the lower surface of the second multi-channel active pattern 210, but is not limited thereto.

[0064] The first upper electrode 122 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide nitride (TaCN), etc. , tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and at least one of their combinations.

[0065] The first semiconductor pattern 150 may be disposed on at least one side of the first gate electrode structure 115. The first semiconductor pattern 150 may be an epitaxial pattern formed by an epitaxial growth process. The first semiconductor pattern 150 may be connected to each of the first multi-channel active pattern 110 and the second multi-channel active pattern 210. For example, the first semiconductor pattern 150 may be formed on the first fin-type protrusion 100P. The first semiconductor pattern 150 may be included in a source / drain of a transistor using the first multi-channel active pattern 110 and the second multi-channel active pattern 210 as a channel region.

[0066] An interlayer insulating layer 190 may be formed on the first semiconductor pattern 150. The interlayer insulating layer 190 may surround the sidewall of the first gate spacer 140. The interlayer insulating layer 190 may include a lower interlayer insulating layer 191 and an upper interlayer insulating layer 192. The upper interlayer insulating layer 192 may be formed on the upper surface of the first gate spacer 140 and the upper surface of the first gate electrode structure 115. The lower interlayer insulating layer 191 and the upper interlayer insulating layer 192 may each include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. Although not shown, an etch stop layer for protecting the first semiconductor pattern 150 when making a contact may be further formed between the first semiconductor pattern 150 and the lower interlayer insulating layer 191. The etch stop layer may include a material having an etching selectivity ratio to the lower interlayer insulating layer 191.

[0067] Reference FIG. 4A to FIG. 4D A cross section of the first multi-channel active pattern 110 is described. Of course, the description of the first multi-channel active pattern 110 may be applied to the second multi-channel active pattern 210.

[0068] exist Figure 4A , a cross section 110S of the first multi-channel active pattern 110 may be a figure composed of a combination of a straight line 110m and a curved line 100n. The cross section 110S of the first multi-channel active pattern 110 may be, for example, a rounded rectangle. In the cross section 110S of the first multi-channel active pattern 110, a width L1 of the first multi-channel active pattern 110 and a height L2 of the first multi-channel active pattern 110 may be different from each other. For example, the cross section 110S of the first multi-channel active pattern 110 may be a rounded rectangle, but is not limited thereto.

[0069] and Figure 4A Different, in Figure 4B In the embodiment, the width L1 of the first multi-channel active pattern 110 and the height L2 of the first multi-channel active pattern 110 in the cross section 110S of the first multi-channel active pattern 110 may be the same as each other. For example, the cross section 110S of the first multi-channel active pattern 110 may be a rounded square, but is not limited thereto. Figure 4A Different in Figure 4C In the embodiment, a width L11 of one side of the first multi-channel active pattern 110 and a width L12 of the other side of the first multi-channel active pattern 110 that are opposite to each other in a cross section 110S of the first multi-channel active pattern 110 may be different from each other. For example, the cross section 110S of the first multi-channel active pattern 110 may be a rounded trapezoid, but is not limited thereto. Figure 4A Different, in Figure 4D , a cross section 110S of the first multi-channel active pattern 110 may be a graph consisting of a combination of curved lines 110n.

[0070] and FIG. 4A to FIG. 4C Unlike the configuration shown in , the cross section 110S of the first multi-channel active pattern 110 may be one of the figures composed of a combination of straight lines. The cross section 110S of the first multi-channel active pattern 110 may also be a rectangle without rounded corners.

[0071] Reference FIG. 5A to FIG. 5C A longitudinal cross section of the first multi-channel active pattern 110 is described. Of course, the description of the first multi-channel active pattern 110 may be applied to the second multi-channel active pattern 210.

[0072] exist Figure 5A , the thickness of the first multi-channel active pattern 110 may be substantially the same in a direction away from the first semiconductor pattern 150 and the first gate spacer 140. For example, a thickness t1_a of a longitudinal end portion of the first multi-channel active pattern 110 adjacent to the first semiconductor pattern 150 may be substantially the same as a thickness t1_b of a central portion of the first multi-channel active pattern 110.

[0073] exist Figure 5B , the thickness of the first multi-channel active pattern 110 may decrease in a direction away from the first semiconductor pattern 150 and the first gate spacer 140. For example, a thickness t1_a of a longitudinal end portion of the first multi-channel active pattern 110 adjacent to the first semiconductor pattern 150 may be thicker than a thickness t1_b of a central portion of the first multi-channel active pattern 110. Figure 5C , the thickness of the first multi-channel active pattern 110 may increase in a direction away from the first semiconductor pattern 150 and the first gate spacer 140. For example, a thickness t1_a of a longitudinal end portion of the first multi-channel active pattern 110 adjacent to the first semiconductor pattern 150 may be thinner than a thickness t1_b of a central portion of the first multi-channel active pattern 110. Figure 5B and Figure 5C In the embodiment, the thickness of the first multi-channel active pattern 110 may continuously change in a direction away from the first semiconductor pattern 150 and the first gate spacer 140 .

[0074] Reference Figure 6 A longitudinal cross section of the first multi-channel active pattern 110 is described. Of course, the description of the first multi-channel active pattern 110 may be applied to the second multi-channel active pattern 210.

[0075] The first multi-channel active pattern 110 may be a trimmed line pattern. The first multi-channel active pattern 110 may include a first portion 110a and a second portion 110b. The second portion 110b of the first multi-channel active pattern may be disposed on both sides of the first portion 110a of the first multi-channel active pattern. The second portion 110b of the first multi-channel active pattern may be a portion overlapping the first gate spacer 140, and the first portion 110a of the first multi-channel active pattern 110 may be a portion overlapping the first gate insulating layer 135 and the first gate electrode structure 115.

[0076] The thickness t1_c of the second portion 110b of the first multi-channel active pattern is greater than the thickness t1_d of the first portion 110a of the first multi-channel active pattern.

[0077] and Figure 6 Unlike the configuration shown, the connection portion between the second portion 110b of the first multi-channel active pattern and the first portion 110a of the first multi-channel active pattern can of course be rounded. Figure 6 In the embodiment, although the width of the first portion 110a of the first multi-channel active pattern is shown as being constant regardless of the position, this is only for ease of description, and the inventive concept is not limited thereto. That is, the width of the first portion 110a of the first multi-channel active pattern may of course be changed, such as Figure 5B or Figure 5C shown.

[0078] Figure 7 and Figure 8 are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept. Fig. 9 and Fig.10 are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept. Figures 11 to 13 Each of the diagrams is for explaining a semiconductor device according to some embodiments of the inventive concept. Fig.14 and Fig.15 1 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. Figures 1 to 3 The differences in the descriptions given.

[0079] Reference Figure 7 and Figure 8 In the semiconductor device according to some embodiments of the present inventive concept, the first conductive liner 121 may include a first lower conductive liner 121 a and a first upper conductive liner 121 b .

[0080] The first lower conductive liner 121a may be in contact with the first work function adjustment liner 130. The first upper conductive liner 121b may be formed on the first lower conductive liner 121a.

[0081] As an example, the first lower conductive liner 121a and the first upper conductive liner 121b may each include a conductive nitride layer. The first lower conductive liner 121a may include a titanium nitride layer, and the first upper conductive liner 121b may include a titanium silicon nitride layer. Alternatively, the first lower conductive liner 121a may include a titanium silicon nitride layer, and the first upper conductive liner 121b may include a titanium nitride layer.

[0082] As another example, the first lower conductive liner 121a may include a conductive nitride layer, and the first upper conductive liner 121b may include an aluminum-containing conductive layer. The first lower conductive liner 121a may include a titanium nitride layer. The first upper conductive liner 121b may include a conductive layer including at least one material selected from the group consisting of titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), and titanium aluminum carbide nitride (TiAlC-N).

[0083] Reference Fig. 9 and Fig.10 In the semiconductor device according to some embodiments of the present inventive concept, the first work function adjustment liner 130 may include a first lower adjustment liner 131 and a first upper adjustment liner 132 .

[0084] The first lower adjustment liner 131 may be in contact with the first high dielectric constant insulating layer 137. The first upper adjustment liner 132 may be formed on the first lower adjustment liner 131.

[0085] The first lower adjustment liner 131 may include an insulating material. The first lower adjustment liner 131 may include an insulating material with a dielectric constant smaller than that of the first high dielectric constant insulating layer 137. The first lower adjustment liner 131 may include, for example, silicon nitride (SiN). In semiconductor devices according to some embodiments of the inventive concept, the first lower adjustment liner 131 may be a silicon nitride layer.

[0086] As an example, the first upper adjustment liner 132 may include a layer obtained by oxidizing a material included in the first lower adjustment liner 131. For example, the first upper adjustment liner 132 may include a silicon oxynitride layer obtained by oxidizing silicon nitride.

[0087] As another example, the first upper adjustment liner 132 may include a layer obtained by oxidizing a material included in the first conductive liner 121. As an example, in the case where the first conductive liner 121 includes titanium nitride, the first upper adjustment liner 132 may include one of titanium oxide or titanium oxynitride.

[0088] Reference Fig.11In the semiconductor device according to some embodiments of the inventive concept, the first gate electrode structure 115 may further include a capping pattern 145 .

[0089] The first gate electrode 120 may fill a portion of the first gate trench 140t. A capping pattern 145 may be formed on the first gate electrode 120. The capping pattern 145 may fill the remaining portion of the first gate trench 140t left after the first gate electrode 120 is formed.

[0090] exist Fig.11 , it is shown that the first high dielectric constant insulating layer 137 and the first work function adjustment liner 130 are not formed between the first gate spacer 140 and the capping pattern 145. However, this is only for convenience of explanation, and the present inventive concept is not limited thereto. Fig.11 , the capping pattern 145 is shown to be formed between the inner walls of the first gate spacer 140, but the inventive concept is not limited thereto. Similar to the first gate electrode 120, the upper surface of the first gate spacer 140 may also be recessed below the upper surface of the lower interlayer insulating layer 191. In this case, the capping pattern 145 may be formed on the upper surface of the first gate spacer 140 and the upper surface of the first gate electrode 120.

[0091] The upper surface of the capping pattern 145 may be on the same plane as the upper surface of the lower interlayer insulating layer 191. The capping pattern 145 may include, for example, a material having an etching selectivity ratio to the lower interlayer insulating layer 191. The capping pattern 145 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbide nitride (SiCN), silicon oxycarbon nitride (SiOCN) and at least one of their combinations.

[0092] Reference Fig.12 The semiconductor device according to some embodiments of the inventive concept may further include a contact 195 connected to the first semiconductor pattern 150 .

[0093] The contact 195 may be formed on the first semiconductor pattern 150 through the interlayer insulating layer 190. Although it is shown that the contact 195 does not enter the first semiconductor pattern 150, the inventive concept is not limited thereto. The contact 195 may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten carbide nitride (WCN), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), and doped polysilicon. Different from the illustrated configuration, a silicide layer may be formed between the contact 195 and the first semiconductor pattern 150.

[0094] Reference Fig.13In the semiconductor device according to some embodiments of the present inventive concept, the distance between the first fin type protrusion 100P and the first multi-channel active pattern 110 spaced apart in the height direction may be different from the distance between the first multi-channel active pattern 110 and the second multi-channel active pattern 210 spaced apart in the height direction.

[0095] A distance between the first fin type protrusion 100P and the first multi-channel active pattern 110 spaced apart in the height direction may be greater than a distance between the first multi-channel active pattern 110 and the second multi-channel active pattern 210 spaced apart in the height direction, but is not limited thereto.

[0096] Reference Fig.14 and Fig.15 , in the semiconductor device according to some embodiments of the inventive concept, the multi-channel active pattern may be a first fin type pattern 110F.

[0097] A portion of the first fin pattern 110F may protrude above the upper surface of the field insulating layer 105. The first fin pattern 110F may include silicon or germanium as an elemental semiconductor material.

[0098] The first fin pattern 110F may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0099] The first interface layer 136 may be formed along the contour of the first fin pattern 110F protruding above the upper surface of the field insulation layer 105. The first high dielectric constant insulation layer 137, the first work function adjustment liner 130, and the first conductive liner 121 may be formed along the contour of the first fin pattern 110F and the upper surface of the field insulation layer 105.

[0100] Figures 16 to 18 are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept. Fig.16 is a plan view for explaining a semiconductor device according to some embodiments of the inventive concept, and Fig.17 and Fig.18 Along Fig.16 For reference, the cross-sectional view taken along the lines CC and DD of FIG. Figures 1 to 3 Describes the content of the duplicate content.

[0101] Reference Figures 16 to 18, the semiconductor device according to some embodiments of the inventive concept may include third to sixth multi-channel active patterns 310, 410, 510, and 610, a second gate electrode structure 315, a third gate electrode structure 515, a second gate insulating layer 335, and a third gate insulating layer 535. The second gate electrode structure 315 may include a second work function adjustment liner 330 and a second gate electrode 320, and the third gate electrode structure 515 may include a third work function adjustment liner 530 and a third gate electrode 520.

[0102] The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be regions spaced apart from each other, or may be regions connected to each other.

[0103] The second fin-type protrusion 300P, the third multi-channel active pattern 310 and the fourth multi-channel active pattern 410, the second gate electrode structure 315 and the second gate insulation layer 335 may be formed in the first region I of the substrate 100. The third fin-type protrusion 500P, the fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610, the third gate electrode structure 515 and the third gate insulation layer 535 may be formed in the second region II of the substrate 100. The second fin-type protrusion 300P and the third fin-type protrusion 500P may protrude from the substrate 100. The second fin-type protrusion 300P may extend longitudinally in the third direction X2. The third fin-type protrusion 500P may extend longitudinally in the fifth direction X3. The field insulation layer 105 may surround at least a portion of the sidewalls of the second fin-type protrusion 300P and the sidewalls of the third fin-type protrusion 500P.

[0104] The third multi-channel active pattern 310 and the fourth multi-channel active pattern 410 may be sequentially formed on the substrate 100. The third multi-channel active pattern 310 and the fourth multi-channel active pattern 410 may be sequentially disposed on the second fin-type protrusion 300P. The third multi-channel active pattern 310 and the fourth multi-channel active pattern 410 may extend in the third direction X2. The fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610 may be sequentially formed on the substrate 100. The fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610 may be sequentially disposed on the third fin-type protrusion 500P. The fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610 may extend in the fifth direction X3. For example, the third to sixth multi-channel active patterns 310, 410, 510, and 610 may be third to sixth nanowires, respectively.

[0105] The second gate spacer 340 may extend in the fourth direction Y2. The second gate spacer 340 may intersect the third multi-channel active pattern 310 and the fourth multi-channel active pattern 410. The second gate spacer 340 may define a second gate trench 340t, which intersects the third multi-channel active pattern 310 and the fourth multi-channel active pattern 410. The second gate spacer 340 may include a second inner spacer 341 and a second outer spacer 342. The third gate spacer 540 may extend in the sixth direction Y3. The third gate spacer 540 may intersect the fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610. The third gate spacer 540 may define a third gate trench 540t, which intersects the fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610. The third gate spacer 540 may include a third inner spacer 541 and a third outer spacer 542.

[0106] A second gate insulating layer 335 may be formed along the third multi-channel active pattern 310 and the fourth multi-channel active pattern 410, respectively. The second gate insulating layer 335 may be formed along the outer periphery of each of the third multi-channel active pattern 310 and the fourth multi-channel active pattern 410. A third gate insulating layer 535 may be formed along each of the fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610. The third gate insulating layer 535 may be formed along the outer periphery of each of the fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610.

[0107] The second gate insulating layer 335 may include a second interface layer 336 and a second high dielectric constant insulating layer 337. The third gate insulating layer 535 may include a third interface layer 536 and a third high dielectric constant insulating layer 537. Each of the second high dielectric constant insulating layer 337 and the third high dielectric constant insulating layer 537 may include a high dielectric constant material having a dielectric constant greater than that of silicon nitride. The second high dielectric constant insulating layer 337 and the third high dielectric constant insulating layer 537 may each include an insulating material containing a metal.

[0108] The second gate electrode structure 315 may be formed on the second gate insulating layer 335. The second gate electrode structure 315 may be in contact with the second high dielectric constant insulating layer 337. The second gate electrode structure 315 fills the second gate trench 340t and may extend in the fourth direction Y2. The third gate electrode structure 515 may be formed on the third gate insulating layer 535. The third gate electrode structure 515 may be in contact with the third high dielectric constant insulating layer 537. The third gate electrode structure 515 fills the third gate trench 540t and may extend in the sixth direction Y3.

[0109] The second work function adjustment liner 330 may be formed along the second high dielectric constant insulating layer 337. The second work function adjustment liner 330 may be formed along the periphery of the third multi-channel active pattern 310 and the fourth multi-channel active pattern 410. The second work function adjustment liner 330 may contact the second high dielectric constant insulating layer 337. The thickness of the second work function adjustment liner 330 is less than the thickness of the second high dielectric constant insulating layer 337.

[0110] The second gate electrode 320 may be formed on the second work function adjustment liner 330. The second gate electrode 320 may be in contact with the second work function adjustment liner 330. The second gate electrode 320 may include a second conductive liner 321 and a second upper electrode 322. The second conductive liner 321 may be formed on the second work function adjustment liner 330. The second conductive liner 321 may be in contact with the second work function adjustment liner 330. The second conductive liner 321 may be formed along the second work function adjustment liner 330. The second conductive liner 321 may be formed along the periphery of the third multi-channel active pattern 310 and the fourth multi-channel active pattern 410.

[0111] The third work function adjustment liner 530 may be formed along the third high dielectric constant insulating layer 537. The third work function adjustment liner 530 may be formed along the outer periphery of the fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610. The third work function adjustment liner 530 may be in contact with the third high dielectric constant insulating layer 537. The thickness of the third work function adjustment liner 530 is less than the thickness of the third high dielectric constant insulating layer 537.

[0112] The third gate electrode 520 may be formed on the third work function adjustment liner 530. The third gate electrode 520 may be in contact with the third work function adjustment liner 530. The third gate electrode 520 may include a third conductive liner 521 and a third upper electrode 522. The third conductive liner 521 may be formed on the third work function adjustment liner 530. The third conductive liner 521 may be in contact with the third work function adjustment liner 530. The third conductive liner 521 may be formed along the third work function adjustment liner 530. The third conductive liner 521 may be formed along the periphery of the fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610.

[0113] The second work function adjustment liner 330 and the third work function adjustment liner 530 may each include an insulating material. The second work function adjustment liner 330 and the third work function adjustment liner 530 may each include an insulating material having a dielectric constant less than the dielectric constant of the second high dielectric constant insulating layer 337 and the third high dielectric constant insulating layer 537. The second work function adjustment liner 330 and the third work function adjustment liner 530 may include, for example, silicon nitride (SiN). In semiconductor devices according to some embodiments of the present inventive concept, the second work function adjustment liner 330 and the third work function adjustment liner 530 may be silicon nitride layers, respectively.

[0114] The second conductive liner 321 and the third conductive liner 521 may each include, for example, at least one of TiN, TiSiN, TiAl, TiAlC, TiAlN, and TiAlC-N. As an example, the first region I may be a PMOS region, and the second region II may be an NMOS region. The second conductive liner 321 may include at least one of TiN and TiSiN. The third conductive liner 521 may include at least one of TiN, TiAl, TiAlC, TiAlN, and TiAlC-N.

[0115] As another example, when the first region I and the second region II are PMOS regions, the threshold voltage of the p-type transistor of the first region I may be different from the threshold voltage of the p-type transistor of the second region II. The second conductive liner 321 may include TiN, and the third conductive liner 521 may include TiSiN. Since the second conductive liner 321 includes a different material from the third conductive liner 521, the structure of the second conductive liner 321 may be different from the structure of the third conductive liner 521.

[0116] The second semiconductor pattern 350 may be disposed on at least one side of the second gate electrode structure 315. The third semiconductor pattern 550 may be disposed on at least one side of the third gate electrode structure 515.

[0117] Fig.19 and Fig. 20 are respectively used to illustrate semiconductor devices according to some embodiments of the present invention. Figures 16 to 18 The differences in the descriptions given.

[0118] Reference Fig.19 In the semiconductor device according to some embodiments of the present inventive concept, the third conductive liner 521 may contact the third high dielectric constant insulating layer 537. For example, the first region I may be a PMOS region, and the second region II may be an NMOS region.

[0119] Different from the first region I, the work function adjustment liner ( Fig. 20 530) may not be formed between the third conductive liner 521 and the third high dielectric constant insulating layer 537. In other words, the third gate electrode structure ( Fig. 20 515 ) may not include the third work function adjustment liner 530 .

[0120] Reference Fig. 20 In the semiconductor device according to some embodiments of the present inventive concept, the third work function adjustment liner 530 may include a second lower adjustment liner 531 and a second upper adjustment liner 532. For example, the first region I may be a PMOS region, and the second region II may be an NMOS region.

[0121] The second lower adjustment liner 531 may contact the third high dielectric constant insulating layer 537. The second upper adjustment liner 532 may be formed on the second lower adjustment liner 531. The second lower adjustment liner 531 may include an insulating material. The second lower adjustment liner 531 may include, for example, silicon nitride (SiN). In semiconductor devices according to some embodiments of the present inventive concept, the second lower adjustment liner 531 may be a silicon nitride layer.

[0122] As an example, the second upper adjustment liner 532 may include a layer obtained by oxidizing a material included in the second lower adjustment liner 531. For example, the second upper adjustment liner 532 may include a silicon oxynitride layer obtained by oxidizing silicon nitride. As another example, the second upper adjustment liner 532 may include a layer obtained by oxidizing a material included in the third conductive liner 521.

[0123] Fig.21 and Fig. 22 are respectively used to illustrate semiconductor devices according to some embodiments of the present invention. Figures 16 to 18 The differences in the descriptions given.

[0124] Reference Fig.21 In the semiconductor device according to some embodiments of the present inventive concept, the second conductive liner 321 may include a second lower conductive liner 321a and a second upper conductive liner 321b. For example, the first region I may be a PMOS region, and the second region II may be an NMOS region.

[0125] The second lower conductive liner 321a may be in contact with the second work function adjustment liner 330. The second upper conductive liner 321b may be formed on the second lower conductive liner 321a. The second lower conductive liner 321a and the second upper conductive liner 321b may each include a conductive nitride layer. The second lower conductive liner 321a may include a TiN layer, and the second upper conductive liner 321b may include a TiSiN layer. Alternatively, the second lower conductive liner 321a may include a TiSiN layer, and the second upper conductive liner 321b may include a TiN layer.

[0126] Reference Fig. 22 In the semiconductor device according to some embodiments of the present inventive concept, the third conductive liner 521 may include a third lower conductive liner 521 a and a third upper conductive liner 521 b .

[0127] The third lower conductive liner 521a may be in contact with the third work function adjustment liner 530. The third upper conductive liner 521b may be formed on the third lower conductive liner 521a.

[0128] As an example, the first region I may be a PMOS region, and the second region II may be an NMOS region. The third lower conductive liner 521a may include a TiN layer. The third upper conductive liner 521b may include at least one of a TiAl layer, a TiAlC layer, a TiAlN layer, and a TiAlC-N layer.

[0129] As another example, when the first region I and the second region II are PMOS regions, the threshold voltage of the p-type transistor of the first region I may be different from the threshold voltage of the p-type transistor of the second region II. The second conductive liner 321 may include one of a TiN layer and a TiSiN layer. The third conductive liner 521 may include a stacked conductive layer having a TiN layer and a TiSiN layer. For example, the third lower conductive liner 521a may include a TiN layer, and the third upper conductive liner 521b may include a TiSiN layer. Alternatively, the third lower conductive liner 521a may include a TiSiN layer, and the third upper conductive liner 521b may include a TiN layer. Since the second conductive liner 321 has a different stacked structure from the third conductive liner 521, the structure of the second conductive liner 321 may be different from the structure of the third conductive liner 521.

[0130] Figures 23 to 24D are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept. Fig.23 is a plan view for explaining a semiconductor device according to some embodiments of the inventive concept, and Fig.24A and Fig. 24B Along Fig.23 A cross-sectional view taken along lines EE and FF. Fig.24CIt is shown Fig.24A The graph shows the variation of the effective work function of the transistor, and Fig.24D It is shown Fig. 24B For ease of explanation, the following description will be mainly based on the reference Figures 16 to 18 The differences in the descriptions given.

[0131] Reference Figures 23 to 24D In the semiconductor device according to some embodiments of the present inventive concept, the second gate electrode 320 may be in contact with the second high dielectric constant insulating layer 337, and the third gate electrode 520 may be in contact with the third high dielectric constant insulating layer 537. In other aspects, the work function adjustment liner ( Fig.16 330 and 530 ) are not formed between the second gate electrode 320 and the second gate insulating layer 335 and between the third gate electrode 520 and the third gate insulating layer 535 .

[0132] The first region I and the second region II may be PMOS regions. The transistor formed in the first region I may be a first p-type transistor, and the transistor formed in the second region II may be a second p-type transistor. In the semiconductor device of some embodiments of the present invention, the threshold voltage of the first p-type transistor is greater than the threshold voltage of the second p-type transistor. For example, the first p-type transistor may be a conventional voltage transistor, and the second p-type transistor may be a low voltage transistor.

[0133] The second conductive liner 321 includes a first metal nitride layer 321c and a first metal silicon nitride layer 321d. The first metal nitride layer 321c and the first metal silicon nitride layer 321d may be sequentially formed along the peripheries of the third multi-channel active pattern 310 and the fourth multi-channel active pattern 410, respectively. The first metal silicon nitride layer 321d may be formed on the first metal nitride layer 321c.

[0134] The third conductive liner 521 includes a second metal nitride layer 521c and a second metal silicon nitride layer 521d. The second metal silicon nitride layer 521d and the second metal nitride layer 521c may be sequentially formed along the peripheries of the fifth multi-channel active pattern 510 and the sixth multi-channel active pattern 610, respectively. The second metal nitride layer 521c may be formed on the second metal silicon nitride layer 521d. The first metal nitride layer 321c and the second metal nitride layer 521c may each be, for example, a titanium nitride layer, and the first metal silicon nitride layer 321d and the second metal silicon nitride layer 521d may each be a titanium silicon nitride layer.

[0135] For example, the second conductive liner 321 is formed between the upper surface of the third multi-channel active pattern 310 and the lower surface of the fourth multi-channel active pattern 410, but the second upper electrode may not be formed. The third conductive liner 521 is formed between the upper surface of the fifth multi-channel active pattern 510 and the lower surface of the sixth multi-channel active pattern 610, but the third upper electrode 522 may not be formed.

[0136] In the semiconductor device according to some embodiments of the present inventive concept, the second upper electrode 322 is formed along the sidewalls of the third multi-channel active pattern 310, the sidewalls of the fourth multi-channel active pattern 410, and the upper surface of the fourth multi-channel active pattern 410, and may not include a conductive insertion liner containing aluminum (Al). In addition, the third upper electrode 522 is formed along the sidewalls of the fifth multi-channel active pattern 510, the sidewalls of the sixth multi-channel active pattern 610, and the upper surface of the sixth multi-channel active pattern 610, and may not include a conductive insertion liner containing aluminum (Al).

[0137] Fig.24C and Fig.24D The effective work function eWF is shown according to the thickness (t21, t31 and t TiN ) and the thickness of the titanium silicon nitride layer (t22, t32 and t TiSiN ) ratio changes.

[0138] exist Fig.24C In the embodiment, the thickness of the first metal silicon nitride layer 321d (t22 or t TiSiN ) and the thickness (t21 or t TiN ) ratio (t22:t21 or t22 / t21) may be in the range of about 5 / 3 to about 7. For example, by adjusting the thickness (t TiSiN ) and the thickness of the titanium nitride layer (t TiN ), various effective work functions (less than the value of line (ii)) lower than the effective work function (line (i)) using only the titanium nitride layer can be obtained. Therefore, a transistor with a higher threshold voltage than the threshold voltage of a transistor including only the titanium nitride layer can be manufactured.

[0139] exist Fig.24D In the embodiment, the ratio of the thickness t32 of the second metal silicon nitride layer 521d to the thickness t31 of the second metal nitride layer 521c (t32:t31 or t32 / t31) may be in the range of about 3 / 37 to about 1 / 3. TiSiN ) and the thickness of the titanium nitride layer (t TiN), various effective work functions higher than the effective work function (line (i)) using only the titanium nitride layer can be obtained. Therefore, a transistor having a threshold voltage lower than the threshold voltage of a transistor including only the titanium nitride layer can be manufactured.

[0140] exist Fig.24C and Fig.24D In each figure, although the thickness of the titanium nitride layer (t TiN ) and the thickness of the titanium silicon nitride layer (t TiSiN ) ratio changes, but the thickness of the titanium nitride layer (t TiN ) and the thickness of the titanium silicon nitride layer (t TiSiN ) is the same in each test sample. Fig.24C and Fig.24D , “0 / 1” on the horizontal axis indicates that the conductive liner layer includes only the titanium nitride layer without the titanium silicon nitride layer, and is irrelevant to the thickness of the titanium nitride layer.

[0141] FIG. 25A to FIG. 25D are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept. Fig.25A and Fig.25B Along Fig.23 A cross-sectional view along lines EE and FF. Fig.25C It is shown Fig.25A The graph shows the variation of the effective work function of the transistor, and Fig.25D It is shown Fig.25B For ease of explanation, the following description will be mainly based on the reference Figures 23 to 24D The differences in the descriptions given.

[0142] Reference FIG. 25A to FIG. 25D In the semiconductor device according to some embodiments of the present inventive concept, the second upper electrode 322 includes a first conductive insertion liner 322a and a first filling layer 322b, and the third upper electrode 522 may include a second conductive insertion liner 522a and a second filling layer 522b.

[0143] In the third conductive liner 521, a second metal nitride layer 521c and a second metal silicon nitride layer 521d may be sequentially formed along the peripheries of the fifth and sixth multi-channel active patterns 510 and 610, respectively. The second metal silicon nitride layer 521d may be formed on the second metal nitride layer 521c.

[0144] The first conductive insertion liner 322a may be formed on the second conductive liner 321. The first conductive insertion liner 322a may be formed along the sidewalls of the third multi-channel active pattern 310, the sidewalls of the fourth multi-channel active pattern 410, and the upper surface of the fourth multi-channel active pattern 410. The first filling layer 322b may be formed on the first conductive insertion liner 322a.

[0145] The second conductive insertion liner 522a may be formed on the third conductive liner 521. The second conductive insertion liner 522a may be formed along the sidewalls of the fifth multi-channel active pattern 510, the sidewalls of the sixth multi-channel active pattern 610, and the upper surface of the sixth multi-channel active pattern 610. The second filling layer 522b may be formed on the second conductive insertion liner 522a.

[0146] The first conductive insert liner 322a and the second conductive insert liner 522a may each include a conductive material including aluminum (Al). The first conductive insert liner 322a and the second conductive insert liner 522a may each include, but are not limited to, at least one of TiAl, TiAlC, TiAlN, and TiAlC-N.

[0147] Fig.25C and Fig.25D The effective work function eWF is shown according to the thickness (t21, t31 and t TiN ) and the thickness of the titanium silicon nitride layer (t22, t32 and t TiSiN ) ratio changes.

[0148] exist Fig.25C In the embodiment, the thickness of the first metal silicon nitride layer 321d (t22 or t TiSiN ) and the thickness (t21 or t TiN ) ratio (t22:t21 or t22 / t21) may be in the range of about 5 / 3 to about 7. For example, by adjusting the thickness (t TiSiN ) and the thickness of the titanium nitride layer (t TiN ) ratio, various effective work functions below line (ii) can be obtained. In addition, by adjusting the thickness of the titanium silicon nitride layer (t TiSiN ) and the thickness of the titanium nitride layer (t TiN ) ratio, an effective work function higher than that of using only the titanium nitride layer can be obtained. As a result, various transistors with a threshold voltage lower than the threshold voltage of a transistor including only the titanium nitride layer can be manufactured.

[0149] exist Fig.25D In the embodiment, the ratio of the thickness t32 of the second metal silicon nitride layer 521d to the thickness t31 of the second metal nitride layer 521c (t32:t31 or t32 / t31) may be in the range of about 2 / 3 to about 4. For example, by adjusting the thickness (t32 of the titanium silicon nitride layer) TiSiN ) and the thickness of the titanium nitride layer (t TiN) ratio, various effective work functions higher than the effective work function (line (i)) of using only the titanium nitride layer can be obtained. In addition, by adjusting the thickness of the titanium silicon nitride layer (t TiSiN ) and the thickness of the titanium nitride layer (t TiN ) ratio, an effective work function higher than that of using only the titanium silicon nitride layer can be obtained. As a result, various transistors with lower threshold voltages than the threshold voltages of transistors including only the titanium nitride layer and transistors including only the titanium silicon nitride layer can be manufactured.

[0150] exist Fig.25C and Fig.25D In the embodiment of the present invention, the titanium silicon nitride layer can prevent the diffusion of aluminum (Al) contained in the first conductive insertion liner 322a and the second conductive insertion liner 522a. As a result, the effective work function can be increased. However, when the thickness ratio of the titanium silicon nitride layer increases, the tendency of the effective work function of the titanium silicon nitride itself may exceed the effect of preventing the diffusion of aluminum (Al).

[0151] exist Fig.25C and Fig.25D In each figure, although the thickness of the titanium nitride layer (t TiN ) and the thickness of the titanium silicon nitride layer (t TisiN ) ratio changes, but the thickness of the titanium nitride layer (t TiN ) and the thickness of the titanium silicon nitride layer (t TiSiN ) is the same in each test sample. Fig.25C and Fig.25D In FIG. 1 , “0 / 1” on the horizontal axis indicates that the conductive liner includes a titanium nitride layer but no titanium silicon nitride layer, and has nothing to do with the thickness of the titanium nitride layer. Fig.25D , “1 / 0” on the horizontal axis indicates that the conductive liner layer includes the titanium silicon nitride layer but not the titanium nitride layer, and is irrelevant to the thickness of the titanium silicon nitride layer.

[0152] Figure 26 to Figure 28 are diagrams for explaining semiconductor devices according to some embodiments of the inventive concept. Fig.26 is a plan view for explaining a semiconductor device according to some embodiments of the inventive concept, and Fig. 27 and Fig.28 Along Fig.26 For reference, the following sections will be briefly described or omitted. Figures 16 to 18 Describes the content of the duplicate content.

[0153] Reference Figure 26 to Figure 28 , in the semiconductor device according to some embodiments of the inventive concept, the multi-channel active pattern may be a second fin type pattern 510F in the second region II.

[0154] A portion of the second fin pattern 510F may protrude upward from the upper surface of the field insulating layer 105. The second fin pattern 510F may include silicon or germanium as an elemental semiconductor material. In addition, the second fin pattern 510F may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The third interface layer 536 may be formed along the contour of the second fin pattern 510F protruding upward from the upper surface of the field insulating layer 105. The third high dielectric constant insulating layer 537, the third work function adjustment liner 530, and the third conductive liner 521 may be formed along the contour of the second fin pattern 510F and the upper surface of the field insulating layer 105.

[0155] Each of the first region I and the second region II may be any one of an SRAM region, a logic region, and an I / O region. For example, the first region I may be a region that performs a different function from the second region II.

[0156] Figures 29 to 34 are diagrams for explaining intermediate steps of a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 30 to Figure 34 Use along Fig.29 The cross-sectional view taken along the line GG shows the manufacturing method performed. Figures 29 to 34 The manufactured semiconductor device can be referenced Figures 1 to 3 A semiconductor device is described.

[0157] Reference Fig.29 , a fin structure F may be formed on the substrate 100. The fin structure F may extend longitudinally in a first direction X1.

[0158] The fin structure F may include a first fin protrusion 100P, a sacrificial pattern 111, an active pattern 112, a sacrificial pattern 111, and an active pattern 112 sequentially stacked on a substrate 100. Since the fin structure F extends in a first direction X1, each of the sacrificial pattern 111 and the active pattern 112 may extend in the first direction X1. The active pattern 112 may include a material having an etching selectivity ratio to the sacrificial pattern 111. A field insulating layer 105 covering at least a portion of a sidewall of the fin structure F may be formed on the substrate 100.

[0159] exist Fig.29 , the active pattern 112 is shown as being located at the uppermost portion of the fin type structure F, but the inventive concept is not limited thereto. In addition, although the fin type structure F is shown as including two active patterns 112 formed on the substrate 100, it is not limited thereto.

[0160] Reference Fig.30 , can be formed to intersect with the fin structure F and in the second direction ( Figure 1 A dummy gate electrode 120p extending on Y1) in FIG.

[0161] A dummy gate insulating layer 130p may be formed between the dummy gate electrode 120p and the fin structure F. A hard mask pattern 2101 may be located on the dummy gate electrode 120p. An outer spacer 142 may be formed on a sidewall of the dummy gate electrode 120p. By using the dummy gate electrode 120p and the outer spacer 142 as a mask, a portion of the fin structure F may be removed.

[0162] After removing a portion of the fin structure F, an inner spacer 141 is formed between the active pattern 112 and the first fin protrusion 100P. The inner spacer 141 is also formed between the active pattern 112 on the first fin protrusion 100P. Thus, the gate spacer 140 is formed. For example, a portion of the sacrificial pattern 111 at least overlapping with the outer spacer 142 may be removed using, for example, an etching selectivity between the active pattern 112 and the sacrificial pattern 111. The inner spacer 141 may be formed at a portion where a portion of the sacrificial pattern 111 is removed.

[0163] Subsequently, a first semiconductor pattern 150 may be formed on the substrate 100 at both sides of the dummy gate electrode 120 p and the gate spacer 140 . The first semiconductor pattern 150 may be formed on the first fin type protrusion 100P. The first semiconductor pattern 150 may be connected to the active pattern 112 .

[0164] refer to Fig.30 and Fig.31 , a lower interlayer insulating layer 191 may be formed on the first semiconductor pattern 150. The dummy gate electrode 120p may be exposed through the lower interlayer insulating layer 191. During the formation of the lower interlayer insulating layer 191, the hard mask pattern 2101 may be removed.

[0165] Subsequently, the first multi-channel active pattern 110 and the second multi-channel active pattern 210 sequentially disposed on the substrate 100 may be formed by removing the dummy gate electrode 120p, the dummy gate insulating layer 130p, and the sacrificial pattern 111. The first multi-channel active pattern 110 may be formed to be spaced apart from the first fin type protrusion 100P. By removing the dummy gate electrode 120p, the dummy gate insulating layer 130p, and the sacrificial pattern 111, a first gate trench 140t defined by the gate spacer 140 may be formed.

[0166] refer to Fig.32 , a first gate insulating layer 135 is formed along the first multi-channel active pattern 110 and the second multi-channel active pattern 210 .

[0167] The first gate insulating layer 135 may be formed on the sidewalls and bottom surfaces of the first gate trench 140t and the peripheries of the first and second multi-channel active patterns 110 and 210. The first gate insulating layer 135 includes a first interface layer 136 and a first high dielectric constant insulating layer 137. The first high dielectric constant insulating layer 137 may also be formed on an upper surface of the lower interlayer insulating layer 191.

[0168] Reference Fig.33 , a first work function adjustment liner 130 is formed on the first gate insulating layer 135 .

[0169] The first work function adjustment liner 130 may be formed along the contour of the first high dielectric constant insulating layer 137. The first work function adjustment liner 130 may also be formed on the upper surface of the lower interlayer insulating layer 191. The first work function adjustment liner 130 may be formed using, for example, atomic layer deposition, but is not limited thereto.

[0170] Reference Fig.34 , a first conductive liner 121 is formed on the first work function adjustment liner 130 .

[0171] The first conductive liner 121 may be formed along the contour of the first work function adjustment liner 130. The first work function adjustment liner 121 may be formed by, for example, atomic layer deposition, but is not limited thereto.

[0172] A first upper electrode 122 for filling the first gate trench 140t may be formed on the first conductive liner 121. Subsequently, the first high dielectric constant insulating layer 137, the first work function adjustment liner 130, the first conductive liner 121, and the first upper electrode 122 on the upper surface of the lower interlayer insulating layer 191 may be removed.

[0173] Although the present invention has been specifically shown and described with reference to the exemplary embodiments of the present invention, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Therefore, it is expected that these embodiments are considered to be illustrative and not restrictive in all aspects, and reference is made to the appended claims rather than the foregoing description to indicate the scope of the present invention.

Claims

1. A semiconductor device, comprising: a fin-type protrusion protruding from the substrate and including a protrusion portion protruding from a top surface of the fin-type protrusion; a multi-channel active pattern on the protrusion, the multi-channel active pattern comprising a first active pattern and a second active pattern spaced apart from the first active pattern on the first active pattern; a high dielectric constant insulating layer formed on the multi-channel active pattern and along the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises metal; a silicon nitride layer formed on the high dielectric constant insulating layer and along the high dielectric constant insulating layer; a gate electrode on the silicon nitride layer; an inner spacer disposed between the first active pattern and the second active pattern at a position overlapping the first active pattern and the second active pattern, and between the protrusion and the first active pattern at a position overlapping the fin-type protrusion and the first active pattern; an outer spacer disposed on the second active pattern; an interface layer formed between the multi-channel active pattern and the high dielectric constant insulating layer along the multi-channel active pattern; a semiconductor pattern disposed on at least one side of the gate electrode; and The interlayer insulating layer on the semiconductor pattern contacts at least one side of the outer spacer, wherein the outer sidewall of the inner spacer is coplanar with the outer sidewall of the outer spacer and the outer sidewall of the multi-channel active pattern, wherein the bottom surface of the interface layer contacts the protrusion, wherein the bottom surface of the inner spacer contacts the protrusion, wherein the width of the top surface of the protrusion in the first direction is the same as the width of the first active pattern in the first direction, The thickness of the silicon nitride layer is smaller than the thickness of the high dielectric constant insulating layer. wherein the gate electrode comprises a conductive nitride layer formed along the silicon nitride layer, The conductive nitride layer includes a titanium nitride TiN layer and a titanium silicon nitride TiSiN layer stacked on each other, and Wherein, the TiN layer is in contact with the silicon nitride layer.

2. The semiconductor device according to claim 1, wherein The high dielectric constant insulating layer is in contact with the silicon nitride layer.

3. The semiconductor device according to claim 1, further comprising: An insertion layer including an oxide layer is provided between the silicon nitride layer and the gate electrode.

4. The semiconductor device according to claim 3, wherein: The insertion layer includes silicon oxynitride.

5. The semiconductor device according to claim 1, wherein The first active pattern and the second active pattern each include a nanowire.

6. A semiconductor device comprising: a fin-shaped protrusion protruding from the substrate and comprising a protrusion portion protruding from a first surface of the fin-shaped protrusion; a multi-channel active pattern on the protrusion, the multi-channel active pattern comprising a first active pattern and a second active pattern spaced apart from the first active pattern on the first active pattern; a gate insulating layer formed on the multi-channel active pattern and along the multi-channel active pattern, wherein the gate insulating layer includes an interface layer and a high dielectric constant insulating layer; A gate electrode structure on the gate insulating layer; an inner spacer disposed between the first active pattern and the second active pattern at a position overlapping the first active pattern and the second active pattern, and between the protrusion and the first active pattern at a position overlapping the fin-type protrusion and the first active pattern; an outer spacer disposed on the second active pattern; A semiconductor pattern disposed on at least one side of the gate electrode structure; and The interlayer insulating layer on the semiconductor pattern contacts at least one side of the outer spacer, The interface layer is formed between the multi-channel active pattern and the high dielectric constant insulating layer along the multi-channel active pattern. wherein the outer sidewall of the inner spacer is coplanar with the outer sidewall of the outer spacer and the outer sidewall of the multi-channel active pattern, wherein the bottom surface of the interface layer contacts the protrusion, wherein the bottom surface of the inner spacer contacts the protrusion, wherein the width of the top surface of the protrusion in the first direction is the same as the width of the first active pattern in the first direction, Wherein, the gate electrode structure comprises a work function adjustment liner in contact with the high dielectric constant insulating layer of the gate insulating layer, The dielectric constant of the work function adjustment liner is smaller than the dielectric constant of the high dielectric constant insulating layer. The thickness of the work function adjustment liner is smaller than the thickness of the high dielectric constant insulating layer. The gate electrode structure further includes a titanium silicon nitride TiSiN layer and a titanium nitride TiN layer stacked on each other, and The TiN layer is formed along the work function adjustment liner and is in contact with the work function adjustment liner.

7. The semiconductor device according to claim 6, wherein: The work function adjustment liner includes a silicon nitride layer.

8. The semiconductor device according to claim 6, wherein: The work function adjustment liner includes a silicon nitride layer and a silicon oxynitride layer on the silicon nitride layer.

9. The semiconductor device according to claim 6, wherein: The high dielectric constant insulating layer is an insulating layer containing metal.

10. The semiconductor device according to claim 6, wherein The multi-channel active pattern includes silicon, and The interface layer includes silicon oxide.

11. The semiconductor device according to claim 6, wherein: The thickness of the work function adjustment liner is equal to or less than 5Å.

12. A semiconductor device comprising: a fin-shaped protrusion protruding from the substrate and comprising a protrusion portion protruding from a first surface of the fin-shaped protrusion; a first nanowire on the protrusion; a second nanowire on the first nanowire spaced apart from the first nanowire; a gate insulating layer formed on the first nanowire and the second nanowire along an outer periphery of the first nanowire and an outer periphery of the second nanowire, wherein the gate insulating layer comprises a high dielectric constant insulating layer; a silicon nitride layer formed on the gate insulating layer along the periphery of the first nanowire and the periphery of the second nanowire, the silicon nitride layer being in contact with the gate insulating layer; The gate electrode on the silicon nitride layer includes a conductive liner containing titanium, and the conductive liner is formed along the periphery of the first nanowire and the periphery of the second nanowire; An inner spacer is disposed at a position between the first nanowire and the second nanowire where the first nanowire and the second nanowire overlap, and at a position between the protrusion and the first nanowire where the fin-shaped protrusion and the first nanowire overlap; an outer spacer disposed on the second nanowire; an interface layer formed between each of the first nanowire and the second nanowire and the high dielectric constant insulating layer along the first nanowire and the second nanowire; a semiconductor pattern disposed on at least one side of the gate electrode; and The interlayer insulating layer on the semiconductor pattern contacts at least one side of the outer spacer, wherein the outer sidewall of the inner spacer is coplanar with the outer sidewall of the outer spacer and the outer sidewalls of the first nanowire and the second nanowire, wherein the bottom surface of the interface layer contacts the protrusion, wherein the bottom surface of the inner spacer contacts the protrusion, The width of the first nanowire in the first direction is the same as the width of the protrusion in the first direction. The thickness of the silicon nitride layer is smaller than the thickness of the high dielectric constant insulating layer. The conductive liner includes a titanium nitride TiN layer and a titanium silicon nitride TiSiN layer stacked on each other, and The TiN layer is formed along the silicon nitride layer and is in contact with the silicon nitride layer.

13. The semiconductor device according to claim 12, wherein: The thickness of the silicon nitride layer is equal to or less than 5Å.

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