Cell architecture based on multiple-gate vertical field effect transistors

Abstract

A cell architecture is provided. A cell architecture can be provided that includes a vertical field effect transistor having at least two fins serving as vertical channels, a gate including a first gate portion surrounding a first fin, a second gate portion surrounding a second fin, and a third gate portion providing a connection therebetween, and a top source / drain including a first top source / drain portion on the first fin and a second top source / drain portion on the second fin. The cell architecture further includes a gate contact structure connected to the third gate portion, a top source / drain contact structure connected to one of the first and second top source / drain portions and serving as a horizontal conductive wiring layer, and a metal pattern on and connected to the gate contact structure and the top source / drain contact structure through vias and serving as a vertical conductive wiring layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 685,340, filed June 15, 2018, and U.S. Non-Provisional Patent Application No. 16 / 257,890, filed January 25, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some example embodiments of the inventive concepts disclosed herein relate to cell architectures based on vertical field-effect transistors (VFETs) comprising two or more fins and / or methods of their fabrication. Background Technology

[0004] In the semiconductor industry, the term "gear ratio" (GR) refers to the ratio between the gate pitch and the vertical metal layer pitch. GR affects pin accessibility, wiring availability, and / or cell density characteristics.

[0005] Traditional planar or horizontal field-effect transistors (FETs), such as planar FETs, horizontal fin FETs (FinFETs), or horizontal nanosheet FETs (HNS FETs), typically offer a 1:1 gear ratio. To improve gear ratios (GR), standard cell architectures based on such planar or horizontal FETs utilize both horizontal and vertical metal wiring layers. This increases the fabrication complexity and production cost of standard cell architectures.

[0006] There is a great need for a cell architecture that has improved GR (meaning GR is m:n, where m and n are natural numbers and n is greater than m) and can be implemented without using additional metal wiring layers. Summary of the Invention

[0007] Some example embodiments of the inventive concepts disclosed herein relate to standard cells implemented based on one or more multi-gate vertical field-effect transistors (VFETs).

[0008] Some example embodiments of the inventive concepts disclosed herein relate to cell architectures based on multi-gate vertical field-effect transistors (VFETs) comprising two or more fins.

[0009] Some example embodiments of the inventive concept disclosed herein relate to a standard unit having a gear ratio of m:n, where m and n are natural numbers, and n is greater than m.

[0010] According to example embodiments of the inventive concepts, a cell architecture includes a VFET including: a first fin and a second fin protruding from a substrate, the first fin and the second fin spaced apart from each other in a first direction and elongated in a second direction that intersects the first direction; a gate including a first gate portion on a sidewall of the first fin, a second gate portion on a sidewall of the second fin, and a third gate portion connecting the first gate portion and the second gate portion; and a top S / D including a first top S / D portion at a top of the first fin and a second top S / D portion at a top of the second fin. The cell architecture further includes: a gate contact structure spaced apart from the first fin and the second fin in the second direction when viewed in a plan view, and the gate contact structure connected to the third gate portion; a top S / D contact structure connected to one of the first top S / D portion and the second top S / D portion, at least one of the top S / D contact structure and the gate contact structure serving as a first conductive wiring layer in the first direction; and a metal pattern on the gate contact structure and the top S / D contact structure, the metal pattern configured to be connected to at least one of the gate contact structure and the top S / D contact structure through a via, respectively, the metal pattern serving as a second conductive wiring layer in the second direction.

[0011] According to example embodiments of the inventive concepts, a cell architecture includes a multi-gate vertical field effect transistor including: a first fin and a second fin protruding from a substrate, the first fin and the second fin spaced apart from each other in a first direction and elongated in a second direction that intersects the first direction; a bottom S / D on the substrate, the bottom S / D surrounding the first fin and the second fin; a gate including a first gate portion on a sidewall of the first fin, a second gate portion on a sidewall of the second fin, and a third gate portion connecting the first gate portion and the second gate portion, the third gate portion overlapping with an end region of the bottom S / D and including an extension region extending away from the first fin and the second fin in the second direction when viewed in a plan view; a top S / D including a first top S / D portion at a top of the first fin and a second top S / D portion at a top of the second fin, the bottom S / D being in the substrate. The cell architecture further includes: a gate contact structure connected to the third gate portion at the extension region of the third gate portion; a top S / D contact structure connected to one of the first top S / D portion and the second top S / D portion, at least one of the gate contact structure and the top S / D contact structure serving as a first conductive wiring layer in the first direction; and a metal pattern on the gate contact structure and the top S / D contact structure, the metal pattern configured to be connected to at least one of the gate contact structure and the top S / D contact structure through a via, the metal pattern serving as a second conductive wiring layer in the second direction.

[0012] According to example embodiments of the inventive concept, a standard inverter cell architecture includes a PMOS vertical field effect transistor (PMOS VFET) and an NMOS vertical field effect transistor (NMOS VFET). The PMOS VFET includes: a first fin and a second fin protruding from a substrate, the first fin and the second fin being spaced apart from each other in a first direction and elongated in a second direction crossing the first direction; a first gate including a first gate portion on a sidewall of the first fin and a second gate portion on a sidewall of the second fin; and a first top S / D including a first top S / D portion at a top of the first fin and a second top S / D portion at a top of the second fin. The NMOS VFET includes: a third fin and a fourth fin protruding from the substrate, the third fin and the fourth fin being spaced apart from each other in the first direction and elongated in the second direction; a second gate including a third gate portion on a sidewall of the third fin and a fourth gate portion on a sidewall of the fourth fin; and a second top S / D including a third top S / D portion at a top of the third fin and a fourth top S / D portion at a top of the fourth fin. The standard inverter cell architecture further includes: a gate connection structure at a region between the PMOS VFET and the NMOS VFET and connecting the first gate portion, the second gate portion, the third gate portion, and the fourth gate portion to each other, the gate connection structure having a shape enclosing four ends of the first fin, the second fin, the third fin, and the fourth fin, the four ends facing each other in at least one of the first direction, the second direction, and a third direction diagonal with respect to the first direction and the second direction; a top S / D contact structure connected to the second top S / D contact portion and the fourth top S / D contact portion, respectively; a gate contact structure connected to the gate connection structure and laterally away from the top S / D contact structure in the second direction, at least one of the top S / D contact structure and the gate contact structure serving as a first conductive wiring layer in the first direction; and a metal pattern configured to be connected to at least one of the gate contact structure, the second top S / D portion, and the fourth top S / D portion through a via, the metal pattern serving as a second conductive wiring layer in the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0013] The above and other objects, features and effects of the inventive concept will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] FIG. 1A and FIG. 1B FIGS. 1A and 1B respectively illustrate gate-metal layouts of standard cell architectures having gear ratios of 2:3 and 3:4 according to some example embodiments of the inventive concept;

[0015] FIG. 2The equivalent circuit of the inverter X1 standard cell according to an example embodiment of the present invention is shown;

[0016] FIG. 3 These are exemplary embodiments of the concept of the present invention. FIG. 2 The X1 inverter standard unit has a 2:3 gear ratio layout;

[0017] FIG. 4 These are exemplary embodiments of the concept of the present invention. FIG. 3 A cross-sectional view of the inverter taken along line IV-IV';

[0018] FIG. 5 These are exemplary embodiments of the concept of the present invention. FIG. 3 A cross-sectional view of the inverter taken along line V-V';

[0019] FIG. 6A to FIG. 6G These are exemplary embodiments of the invention used to illustrate manufacturing. FIG. 3 to FIG. 5 The layout of the standard cell method for the inverter X1;

[0020] FIG. 7A These are exemplary embodiments of the concept of the present invention. FIG. 3 The first modified layout of the X1 standard inverter cell;

[0021] FIG. 7B This is a cross-sectional view taken along line VIIB-VIIB' of a modified layout of FIG7 according to an exemplary embodiment of the present invention.

[0022] FIG. 8 These are exemplary embodiments of the concept of the present invention. FIG. 3 The second modified layout of the inverter X1 standard cell;

[0023] FIG. 9A These are exemplary embodiments of the concept of the present invention. FIG. 3 The third modified layout of the X1 standard inverter cell;

[0024] FIG. 9B These are exemplary embodiments of the concept of the present invention. FIG. 9A The modified layout is shown in the cross-sectional view taken along line IXB-IXB';

[0025] FIG. 10A These are exemplary embodiments of the concept of the present invention. FIG. 3 The fourth modified layout of the X1 standard inverter cell; and

[0026] FIG. 10B These are exemplary embodiments of the concept of the present invention. FIG. 10A The modified layout is a cross-sectional view taken along line XB-XB'. Detailed Implementation

[0027] Various example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. The

[0028] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," or "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms "first," "second," etc. can be used herein to describe various elements or

[0029] As used herein, the term "and / or" includes any or all combinations of one or more of the associated listed items. When the phrase "at least one of' appears herein with respect to a listing of items prefaced by "at least one of', that take effect to mean that one or more of the listed items are present at the minimum, and that one or more of the listed items can be present even if the minimum value is met by, for example, duplicate items. For example, "at least one of A, B, and C" means A or B or C or any combination thereof. (When the phrase "at least one of' appears herein with respect to a listing of items prefaced by "at least one of', that take effect to mean that one or more of the listed items are present at the minimum, and that one or more of the listed items can be present even if the minimum value is met by, for example, duplicate items.)

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0031] Hereinafter, some example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0032] FIG. 1A and FIG. 1B FIGS. 1 and 2 respectively illustrate gate-metal layouts of standard cell architectures with gear ratios of 2:3 and 3:4, according to some example embodiments of the inventive concept.

[0033] Referring to FIG. 1A ​In a unit area, 9 metal layer wiring patterns MP are arranged to correspond to 6 gate portions GP (the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4 can be collectively referred to as gate portions GP). Thus, the gear ratio between GP and MP is 2:3. Referring to FIG. 1B In a unit area, 8 metal layer wiring patterns MP are arranged to correspond to 6 gate portions GP. Thus, the gear ratio between GP and MP is 3:4. Although FIG. 1A and FIG. 1B Examples with 2:3 and 3:4 gear ratios are shown, but example embodiments of the present inventive concept are not limited thereto. According to some example embodiments, a 1:2 or other gear ratio can be implemented.

[0034] FIG. 2 An equivalent circuit of an inverter X1 standard cell according to example embodiments of the present inventive concept is shown.

[0035] Referring to FIG. 2 , the inverter X1 standard cell includes an NMOS field effect transistor (NMOS FET) and a PMOS field effect transistor (PMOS FET). The gates of both the PMOS FET and the NMOS FET are commonly connected to an input node Vin, one source / drain (S / D) region of the PMOS FET is connected to a power supply Vdd, another S / D region of the PMOS FET and one S / D region of the NMOS FET are connected to each other and commonly connected to an output node Vout, and the other S / D region of the NMOS FET is connected to ground. According to some example embodiments of the present inventive concept, as described in detail below, the NMOS FET and the PMOS FET of the inverter X1 standard cell are implemented by a multi-gate vertical field effect transistor (VFET).

[0036] FIG. 3 is a layout of an inverter X1 standard cell according to example embodiments of the present inventive concept FIG. 2 The inverter X1 standard cell of has a layout with a 2:3 gear ratio. In this layout, the upper half corresponds to the PMOS FET of FIG. 2 , and the lower half corresponds to the NMOS FET of FIG. 2 .

[0037] Referring to FIG. 3 , a plurality of fins (e.g., a first fin F1, a second fin F2, a third fin F3, and a fourth fin F4) are provided. The fins F1, F2, F3, and F4 are structures protruding from a substrate SUB. In some example embodiments, the fins F1, F2, F3, and F4 can be provided by growing epitaxial structures at desired locations of a semiconductor substrate SUB.

[0038] The first fin Fl and the second fin F2 protrude from the substrate SUB, are spaced apart from each other in the first direction Dl, and are elongated in a second direction D2 that intersects (or alternatively, is perpendicular to) the first direction Dl. The first fin Fl and the second fin F2 collectively function as a channel for a PMOS FET.

[0039] The third fin F3 and the fourth fin F4 protrude from the substrate SUB, are spaced apart from each other in the first direction Dl, and are elongated in the second direction D2. The third fin F3 and the fourth fin F4 collectively function as a channel for an NMOS FET. As shown, the first fin Fl and the third fin F3 are spaced apart from each other in the second direction D2, and the second fin F2 and the fourth fin F4 are spaced apart from each other in the second direction D2.

[0040] A first bottom S / D region RXl and a second bottom S / D region RX2 (collectively, bottom S / D regions RX) are disposed on the semiconductor substrate SUB. The first bottom S / D region RXl and the second bottom S / D region RX2 can be doped differently. For example, the first bottom S / D region RXl in the PMOS FET region can be doped with a p-type dopant (e.g., boron), and the second bottom S / D region RX2 in the NMOS FET region can be doped with an n-type dopant (e.g., arsenic or phosphorus).

[0041] When viewed in plan view, the first bottom S / D region RXl (e.g., a layout pattern of the first bottom S / D region RXl) encloses a substantial portion or a majority of the first fin Fl, the second fin F2, the first gate portion GP1, the second gate portion GP2. When viewed in plan view, the second bottom S / D region RX2 (e.g., a layout pattern of the second bottom S / D region RX2) encloses a substantial portion or a majority of the third fin F3, the fourth fin F4, the third gate portion GP3, the fourth gate portion GP4.

[0042] The first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4 can be formed on sidewalls of the fins Fl, F2, F3, and F4, respectively. For example, the gate portions GP can be formed to enclose the sidewalls of the fins Fl, F2, F3, and F4, respectively. The first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4 can be collectively referred to as gate portions GP.

[0043] Each gate portion GP includes a gate insulating layer (not shown) and a work function metal layer (not shown) on the gate insulating layer (not shown). In some example embodiments, the gate portion GP can further include a capping metal layer (not shown) on the work function metal layer.

[0044] A gate connection structure PB can be provided to connect the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4 to each other. The gate connection structure PB can form an integral structure with the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4, the integral structure including respective portions corresponding to the gate connection structure PB and the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4.

[0045] Although not shown in this layout, a first top S / D region (not shown), a second top S / D region (not shown), a third top S / D region (not shown), and a fourth top S / D region (not shown) can be provided on the first fin F1, the second fin F2, the third fin F3, and the fourth fin F4, respectively.

[0046] A first top S / D contact structure CA1 can be provided to cover a portion of the first top S / D region on the first fin F1 and a portion of the second top S / D region on the second fin F2, and to connect to the first top S / D region on the first fin F1 and the second top S / D region on the second fin F2. A second top S / D contact structure CA2 can be provided to cover a portion of the third top S / D region on the third fin F3 and a portion of the fourth top S / D region on the fourth fin F4, and to connect to the third top S / D region on the third fin F3 and the fourth top S / D region on the fourth fin F4.

[0047] The first top S / D contact structure CA1 can connect to the first top S / D region and the second top S / D region. The second top S / D contact structure CA2 can connect to the third top S / D region and the fourth top S / D region. The first top S / D contact structure CA1 and the second top S / D contact structure CA2 can be elongated in the first direction D1 (e.g., a direction along which the first fin F1 and the second fin F2 (and the third fin F3 and the fourth fin F4) are arranged). The first top S / D contact structure CA1 and the second top S / D contact structure CA2 can be collectively referred to as a top S / D contact structure CA.

[0048] Accordingly, the first top S / D contact structure CA1 and the second top S / D contact structure CA2 can function as a horizontal conductive wiring layer (or, alternatively, a first conductive wiring layer that runs in the first direction D1) of this layout.

[0049] A gate contact structure CB can be provided on the gate connection structure PB, such that the gate contact structure CB connects to the gate connection structure PB. The gate contact structure CB can function as a horizontal conductive wiring layer of this layout. See FIG. 3In the example embodiment shown, the gate contact structure CB is disposed on the gate connection structure PB at a region between the first fin Fl and the third fin F3 in the second direction D2. The gate contact structure CB can be spaced apart from the first fin Fl, the second fin F2, the third fin F3, and the fourth fin F4 while connected to the gate connection structure PB when viewed in a plan view.

[0050] A first bottom S / D contact structure CR1 can be disposed on the first bottom S / D region RX1 to contact the first bottom S / D region RX1. A second bottom S / D contact structure CR2 can be disposed on the second bottom S / D region RX2 to contact the second bottom S / D region RX2. The first bottom S / D contact structure CR1 and the second bottom S / D contact structure CR2 can be collectively referred to as a bottom S / D contact structure CR.

[0051] All or some of the plurality of metal patterns MP can be connected to the respective gate contact structure CB and the first and second top S / D contact structures CA1 and CA2, respectively, through respective ones of the plurality of vias VO. The plurality of metal patterns MP can be elongated in the second direction D2 (e.g., the direction of elongation of the fins Fl, F2, F3, and F4). Thus, the plurality of metal patterns MP can serve as a vertically conductive wiring layer (or, alternatively, a second conductive wiring layer running in the second direction D2) of the layout.

[0052] Thus, an inverter Xl standard cell including PMOS FETs and NMOS FETs, each having a vertical channel implemented by two fins, can be provided. In other words, an inverter Xl standard cell including multi-gate NMOS VFETs and multi-gate PMOS VFETs can be provided. While FIG. 3 Examples are shown in which each of the respective channels is disposed to include two fins, but example embodiments of the inventive concept are not limited thereto. According to some example embodiments, a vertical channel of a VFET can be implemented by three or more fins.

[0053] FIG. 4 is a cross-sectional view of the inverter of FIG. 3 taken along line IV-IV'. FIG. 5 is a cross-sectional view of the inverter of FIG. 3 taken along line V-V'.

[0054] Reference is made to FIG. 4 and FIG. 5The bottom S / D region RX is surrounded by (or isolated from each other by) a shallow trench isolation region STI on the substrate SUB, for example. The first gate portion GP1 surrounds a sidewall of the first fin Fl. The third gate portion GP3 surrounds a sidewall of the third fin F3. Lower surfaces of the first gate portion GP1, the third gate portion GP3, and the gate connection structure PB are insulated from the substrate SUB by a bottom spacer layer SI. Upper surfaces of the first gate portion GP1 and the third gate portion GP3 are insulated by an upper spacer layer S2. In addition, interlayer dielectric layers ILD1, ILD2, ILD3, and ILD4 (collectively referred to as ILDs) can be formed to provide suitable insulation between the various conductive layers. The interlayer dielectric layers ILD1, ILD2, ILD3, and ILD4 can include nitride material or oxide material, as desired for etching and / or insulating properties.

[0055] FIG. 6A to FIG. 6G A layout of a method for fabricating an inverter Xl standard cell according to example embodiments of inventive concepts. FIG. 3 to FIG. 5

[0056] Referring to FIG. 6A A plurality of fins (e.g., first fin Fl, second fin F2, third fin F3, and fourth fin F4) are formed on a substrate SUB. The fins Fl, F2, F3, and F4 are structures that protrude from the semiconductor substrate SUB. In some example embodiments, the fins Fl, F2, F3, and F4 can be formed on the substrate SUB using an epitaxial growth process.

[0057] The first fin Fl and the second fin F2 (and the third fin F3 and the fourth fin F4) can be formed to be spaced apart in a first direction Dl. In addition, the first fin Fl and the third fin F3 (and the second fin F2 and the fourth fin F4) can be formed to be spaced apart in a second direction D2 that is transverse (or alternatively, perpendicular) to the first direction Dl. In addition, the fins Fl, F2, F3, and F4 can be formed to be elongated in the second direction D2.

[0058] The substrate SUB can be bulk silicon. For example, the substrate SUB can be a silicon substrate, or can include materials other than silicon, including but not limited to Ge, SiGe, SiC, GeP, GeN, InGaAs, GaAs, InSb, InAs, GaSb, and InP. The semiconductor substrate SUB can be part of a bulk silicon wafer. The substrate SUB can be a silicon-on-insulator (SOI). The substrate SUB can be a silicon portion of a silicon-on-insulator (SOI) wafer. In some example embodiments, the substrate SUB can refer to a semiconductor layer that is epitaxially grown on a base substrate.

[0059] Referring to FIG. 6B ​A first bottom S / D region RX1 and a second bottom S / D region RX2 can be provided on the semiconductor substrate SUB. According to some example embodiments, the bottom S / D regions RX1 and RX2 can be formed by etching the substrate SUB to a certain depth using the fins F1, F2, F3, F4 and a hard mask pattern (not shown) on the bottom S / D regions RX1 and RX2 (and an additional mask pattern covering the entire area of the substrate SUB except for the area defining the first bottom S / D region RX1 and the second bottom S / D region RX2) as an etch mask. Then, a semiconductor material layer can be epitaxially grown in the recessed areas defined by the etching and doped with different dopants to form the first bottom S / D region RX1 for a PMOS FET and the second bottom S / D region RX2 for an NMOS FET, respectively.

[0060] The first bottom S / D region RX1 and the second bottom S / D region RX2 can be doped differently by using an additional mask as an implantation mask. For example, the first bottom S / D region RX1 in the PMOS FET region can be doped with a p-type dopant (e.g., boron) and the second bottom S / D region RX2 in the NMOS FET region can be doped with an n-type dopant (e.g., arsenic or phosphorus).

[0061] Referring to FIG. 6C A gate portion GP (e.g., a first gate portion GP1, a second gate portion GP2, a third gate portion GP3, and a fourth gate portion GP4) can be formed on the sidewalls of the fins F1, F2, F3, and F4, respectively. For example, the gate portions GP can be formed to surround the sidewalls of the fins F1, F2, F3, and F4, respectively. Each of the gate portions GP includes a gate insulating layer (not shown) and a work function metal layer (not shown) on the gate insulating layer. In some example embodiments, the gate portions GP can further include a capping metal layer (not shown) on the work function metal layer.

[0062] The gate insulating layer can include a high-k dielectric material.

[0063] The work function metal layer can include TiN. In some example embodiments, the work function metal layer can include titanium nitride (TiN) or titanium carbide (TiC). The work function of the work function metal layer for a VFET can be determined based on material properties and thickness of the work function metal layer. In some example embodiments, the work function metal layer can be implemented to have different thicknesses depending on the location.

[0064] A capping metal layer can be subsequently formed on the work function metal layer. The capping metal layer can include at least one of TiC, TiAlC, and TiAl.

[0065] Referring to FIG. 6DThe gate connection structure PB is formed on and connected to the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4. The gate connection structure PB is a structure that connects the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4 to each other. The gate connection structure PB and the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4 can be an integral structure including respective portions corresponding to the gate connection structure PB and the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4. The gate connection structure PB and the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4 can include the same material.

[0066] Although not specifically shown in the drawings, a first top S / D region (not shown), a second top S / D region (not shown), a third top S / D region (not shown), and a fourth top S / D region (not shown) can be respectively provided on the first fin F1, the second fin F2, the third fin F3, and the fourth fin F4.

[0067] The first top S / D region, the second top S / D region, the third top S / D region, and the fourth top S / D region can be formed by epitaxially growing a p+ doped semiconductor layer or an n+ doped semiconductor layer on the respective fin among the first fin F1, the second fin F2, the third fin F3, and the fourth fin F4, respectively. However, example embodiments of the present inventive concept are not limited thereto. According to some example embodiments of the present inventive concept, the first top S / D region, the second top S / D region, the third top S / D region, and the fourth top S / D region can be formed by implanting a desired dopant on the first fin F1, the second fin F2, the third fin F3, and the fourth fin F4.

[0068] Referring to FIG. 6E The first top S / D contact structure CA1 can be formed to cover and electrically connect to both the first top S / D region on the first fin F1 and the second top S / D region on the second fin F2. The second top S / D contact structure CA2 can be provided to cover and electrically connect to both the third top S / D region on the third fin F3 and the fourth top S / D region on the fourth fin F4. The first top S / D contact structure CA1 and the second top S / D contact structure CA2 can include a conductive material such as a metal.

[0069] The first top S / D contact structure CA1 and the second top S / D contact structure CA2 can be used as horizontal conductive wiring layers of the layout. The first top S / D contact structure CA1 and the second top S / D contact structure CA2 can be elongated in the first direction D1 and used as first conductive wiring layers that run in the first direction D1 (e.g., the direction along which the first fin F1 and the second fin F2 (or the third fin F3 and the fourth fin F4) are arranged).

[0070] A gate contact structure CB can be formed on the gate connection structure PB such that the gate contact structure CB is electrically connected to the gate connection structure PB. According to example embodiments, the gate contact structure CB is formed on the gate connection structure PB at an area between the first fin F1 and the third fin F3 in the second direction D2. When viewed in a plan view, the gate contact structure CB can be formed spaced apart from the first fin F1, the second fin F2, the third fin F3, and the fourth fin F4 while connected to the gate connection structure PB. The gate contact structure CB can include a conductive material such as metal.

[0071] A first bottom S / D contact structure CR1 can be formed on the first bottom S / D region RX1 to be electrically connected to the first bottom S / D region RX1. A second bottom S / D contact structure CR2 can be formed on the second bottom S / D region RX2 to be electrically connected to the second bottom S / D region RX2. The first bottom S / D contact structure CR1 and the second bottom S / D contact structure CR2 can include a conductive material such as metal.

[0072] The first top S / D contact structure CA1, the second top S / D contact structure CA2, the gate contact structure CB, the first bottom S / D contact structure CR1, and the second bottom S / D contact structure CR2 can include the same material. The first top S / D contact structure CA1, the second top S / D contact structure CA2, the gate contact structure CB, the first bottom S / D contact structure CR1, and the second bottom S / D contact structure CR2 can be formed simultaneously in the same process. As FIG. 4 and FIG. 5 As shown in FIGS. 1A and 1B, top surfaces of the first top S / D contact structure CA1, the second top S / D contact structure CA2, the gate contact structure CB, the first bottom S / D contact structure CR1, and the second bottom S / D contact structure CR2 can be formed at substantially the same level relative to (or alternatively, from) a top surface of the substrate SUB.

[0073] Referring to FIG. 6F a plurality of vias V0 are formed on the first top S / D contact structure CA1, the second top S / D contact structure CA2, and the gate contact structure CB, respectively.

[0074] Referring to FIG. 6GA plurality of metal patterns MP is formed corresponding to a plurality of vias V0. Although not shown in FIG. 6G

[0075] According to example embodiments, an inverter standard cell can be provided that includes a PMOS FET and an NMOS FET, both having a vertical channel implemented by two fins. In other words, an inverter standard cell can be provided that includes a multi-gate NMOS VFET and a multi-gate PMOS VFET.

[0076] According to example embodiments, an inverter standard cell can be provided that has a gear ratio of 2:3. In some example embodiments, other gear ratios (e.g., 1:2 or 3:4) can be implemented.

[0077] In a VFET, a fin protruding vertically from a substrate is used as a channel, and a structure surrounding a sidewall of the fin is used as a gate. Thus, a top S / D contact structure connected to a top S / D of a VFET and a bottom S / D contact structure connected to a bottom S / D of the VFET are less affected by the area occupied by the gate (meaning more design freedom or layout tolerance) compared to a conventional planar field effect transistor or horizontal field effect transistor.

[0078] According to example embodiments, a multi-gate VFET, two or more fins are used as a channel of the VFET, and respective gate portions surrounding respective fins are used as a gate and are connected to each other using a gate connection pattern therebetween. Thus, the multi-gate VFET can provide a larger area for each of a gate contact structure, a top S / D contact structure, and / or a bottom S / D contact structure compared to a single-gate VFET or a conventional planar field effect transistor or horizontal field effect transistor.

[0079] ​Thus, according to example embodiments, a standard cell with a gear ratio of m:n (where m and n are natural numbers, and n is larger than m) can be implemented without the need to use two crossing metal wiring layers (e.g., a lower metal wiring layer and an upper metal wiring layer crossing the lower metal wiring layer and connected to the lower metal wiring layer by a via). Thus, a standard cell with a gear ratio of m:n (where m and n are natural numbers, and n is larger than m) can be implemented using a single metal wiring layer.

[0080] FIG. 7A is a cross-sectional view of the modified layout of Fig. 7 taken along line VI IB-VI IB’ according to example embodiments of the inventive concept. FIG. 3 is a first modified layout of an inverter X1 standard cell according to example embodiments of the inventive concept. FIG. 7B is a cross-sectional view of the modified layout of Fig. 7 taken along line VI IB-VI IB’ according to example embodiments of the inventive concept.

[0081] Referring to FIG. 7A At the region between the PMOS VFET and the NMOS VFET, a gate connection structure PB is provided, which connects the first gate portion GP1, the second gate portion GP2, the third gate portion GP3, and the fourth gate portion GP4 to each other. The gate connection structure PB has a shape that encloses an end portion of each of the first fin F1, the second fin F2, the third fin F3, and the fourth fin F4, which face each other in at least one of the first direction D1, the second direction D2, and a diagonal direction between the first direction D1 and the second direction D2.

[0082] As FIG. 7A shown, to ensure sufficient space for the via V0 connecting to the underlying gate contact structure CB (which is desired to achieve uniform metal spacing), the standard cell layout can be modified such that the gate connection structure PB includes an extension portion EP, which extends beyond one side of the bottom S / D in the first direction D1.

[0083] In some example embodiments, at least one side of the gate connection structure PB can include an extension portion in the first direction D1. The extension portion (or extension region) can be located outside an imaginary line IL extending from one side of the first bottom S / D region RX1 (or the second bottom S / D region RX2) in the second direction D2. The extension portion (or extension region) can be located outside an imaginary line IL connecting one side of the first bottom S / D region RX1 to one side of the second bottom S / D region RX2 in the second direction D2.

[0084] Referring to FIG. 7B Due to the extension portion EP of the gate connection structure PB, the landing space for the gate contact structure CB falling on the gate connection structure PB is enlarged. Thus, the via V0 can ensure connection to the gate contact structure CB, and thus, uniform metal spacing can be achieved.

[0085] FIG. 8 is a second modified layout of the inverter X1 standard cell according to example embodiments of inventive concepts FIG. 3 is a second modified layout of the inverter X1 standard cell according to example embodiments of inventive concepts

[0086] Referring to FIG. 8 In the case of a tight margin between the gate contact structure CB and the adjacent gate connection structure PB, to avoid an undesired bridging between the gate contact structure CB and the adjacent gate connection structure PB (not shown), the gate connection structure PB corresponding to the gate contact structure CB can be formed such that, when viewed in plan view, one side of the gate connection structure PB is recessed (e.g., not located outside of) from an imaginary line IL (which is a line connecting one side of the first bottom S / D region RX1 to one side of the second bottom S / D region RX2 in the second direction D2). For example, a first lateral side of the gate connection structure PB can be inward in the first direction D1 with respect to the imaginary line IL, such that, when viewed in plan view, among two opposite sides of the gate connection structure PB facing each other in the first direction, one side of the gate connection structure PB can be laterally located between the two opposite sides in the first direction of the first bottom S / D region RX1 (or the two opposite sides of the second bottom S / D region RX2).

[0087] FIG. 9A is a third modified layout of the inverter X1 standard cell according to example embodiments of inventive concepts FIG. 3 is a third modified layout of the inverter X1 standard cell according to example embodiments of inventive concepts FIG. 9B is a cross-sectional view taken along line IXB-IXB’ of the modified layout of FIG. 9A is a cross-sectional view taken along line IXB-IXB’ of the modified layout of

[0088] Referring to FIG. 9A To ensure sufficient space for the via V0 to connect to the underlying gate contact structure CB, the standard cell layout can be modified such that the gate contact structure CB extends in the first direction D1. Thus, FIG. 7A the gate contact structure CB shown in

[0089] As FIG. 9B shown, FIG. 9A the modified layout shown provides an increased landing area for the via V0, thus facilitating a more uniform metal pitch. Thus, a semiconductor device employing such a layout can exhibit improved reliability.

[0090] FIG. 10A is a fourth modified layout of the inverter X1 standard cell according to example embodiments of inventive concepts FIG. 3 is a fourth modified layout of the inverter X1 standard cell according to example embodiments of inventive concepts FIG. 10B is a fourth modified layout of the inverter X1 standard cell according to example embodiments of inventive conceptsFIG. 10A The modified layout is a cross-sectional view taken along line XB-XB'.

[0091] Reference FIG. 10A To ensure sufficient space for the via V0 to connect to the underlying gate contact structure CB, the standard cell layout can be modified so that the additional top S / D contact structure CA' is set and connected with... FIG. 9A The gate contact structure CB shown is merged. An additional top S / D contact structure CA' is formed simultaneously with the top S / D contact structure for the top S / D region. The additional top S / D contact structure CA' can be formed to overlap with the gate contact structure CB without being connected to any one of the top S / D regions.

[0092] like FIG. 10B As shown, the gate contact structure CB and the additional top S / D contact structure overlap each other and provide extended space for the via V0 to fall on the gate contact structure CB below (which is desired to achieve uniform metal pitch). FIG. 10A and FIG. 10B The modified layout shown provides an increased landing area for the via V0, thus contributing to a more uniform metal spacing. Consequently, semiconductor devices employing this layout can exhibit improved reliability.

[0093] Based on the modified layout described above, sufficient space can be provided for the vias desired to achieve uniform metal spacing. Therefore, a standard unit with a gear ratio of m:n can be implemented (where m and n are natural numbers, and n is greater than m).

[0094] It should be understood that the embodiments described herein are for descriptive purposes only and not for limiting purposes. While some exemplary embodiments have been specifically shown and described, those skilled in the art will understand that various modifications in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A unit architecture, comprising: Vertical field-effect transistors, including: A first fin and a second fin protrude from the substrate, the first fin and the second fin being spaced apart from each other in a first direction and extending in a second direction intersecting the first direction. The gate includes a first gate portion on the sidewall of the first fin, a second gate portion on the sidewall of the second fin, and a third gate portion connecting the first gate portion and the second gate portion, wherein the first gate portion and the second gate portion are spaced apart in the first direction. The top source / drain includes a first top source / drain portion at the top of the first fin and a second top source / drain portion at the top of the second fin; A gate contact structure, which, when viewed in a plan view, is spaced apart from the first fin and the second fin in the second direction, and the gate contact structure is connected to the third gate portion; A top source / drain contact structure is connected to one of the first top source / drain portion and the second top source / drain portion, and at least one of the top source / drain contact structure and the gate contact structure serves as a first conductive wiring layer in the first direction; A metal pattern located on the gate contact structure and the top source / drain contact structure, the metal pattern being configured to be connected to at least one of the gate contact structure and the top source / drain contact structure via vias, the metal pattern serving as a second conductive wiring layer in the second direction; and An additional top source / drain contact structure is provided, which overlaps with the gate contact structure and is not connected to either the first top source / drain portion or the second top source / drain portion.

2. The unit architecture according to claim 1, wherein, The first gate portion and the second gate portion are spaced apart by a first pitch in the first direction, and the metal pattern is arranged in the first direction by a second pitch different from the first pitch.

3. The unit architecture according to claim 2, wherein, The ratio between the first spacing and the second spacing is m:n, where m and n are natural numbers, and n is less than m.

4. The unit architecture according to claim 1 further includes: The bottom source / drain of the vertical field-effect transistor, when viewed in a plan view, surrounds at least a portion of the first fin, the second fin, the first gate portion, and the second gate portion.

5. The unit architecture according to claim 4, wherein, The third gate portion includes an extension region that extends beyond one side of the bottom source / drain in the first direction.

6. The unit architecture according to claim 5, wherein, When viewed in a plan view, the gate contact structure extends in the first direction toward the side of the third gate portion away from the bottom source / drain.

7. The unit architecture according to claim 4, wherein, When viewed in a plan view, at least one side of the third gate portion includes an extension region in a first direction, the extension region being located outside an imaginary line extending from one side of the bottom source / drain in a second direction.

8. The unit architecture according to claim 7, wherein, When viewed in a plan view, the gate contact structure extends away from the imaginary line toward the center of the third gate portion in the first direction.

9. The unit architecture according to claim 4, wherein, When viewed in a plan view, one side of the third gate portion is laterally located between the two ends of the bottom source / drain in the first direction.

10. The unit architecture according to claim 4, wherein, When viewed in a plan view, the gate contact structure extends away from the adjacent side of the bottom source / drain in the first direction.

11. A unit architecture, comprising: A multi-gate vertical field-effect transistor, comprising: A first fin and a second fin protrude from the substrate, the first fin and the second fin being spaced apart from each other in a first direction and extending in a second direction intersecting the first direction. The bottom source / drain on the substrate, the bottom source / drain surrounding the first fin and the second fin. The gate includes a first gate portion on the sidewall of the first fin, a second gate portion on the sidewall of the second fin, and a third gate portion connecting the first gate portion and the second gate portion. The first gate portion and the second gate portion are spaced apart in a first direction. The third gate portion overlaps with the end region of the bottom source / drain and includes an extension region that, when viewed in a plan view, extends away from the first and second fins in a second direction. The top source / drain includes a first top source / drain portion at the top of the first fin and a second top source / drain portion at the top of the second fin; the bottom source / drain is located in the substrate; A gate contact structure that is connected to the third gate portion at an extension region of the third gate portion; A top source / drain contact structure is connected to one of the first top source / drain portion and the second top source / drain portion, and at least one of the gate contact structure and the top source / drain contact structure serves as a first conductive wiring layer in the first direction; A metal pattern located on the gate contact structure and the top source / drain contact structure, the metal pattern being configured to be connected to at least one of the gate contact structure and the top source / drain contact structure via vias, the metal pattern serving as a second conductive wiring layer in the second direction; and An additional top source / drain contact structure is provided, which overlaps with the gate contact structure and is not connected to either the first top source / drain portion or the second top source / drain portion.

12. The unit architecture according to claim 11, wherein, The first gate portion and the second gate portion are spaced apart by a first pitch in the first direction, and the metal pattern is arranged in the first direction by a second pitch different from the first pitch.

13. The unit architecture according to claim 12, wherein, The ratio between the first spacing and the second spacing is m:n, where m and n are natural numbers, and n is less than m.

14. The unit architecture according to claim 11, wherein, When viewed in a plan view, the third gate portion includes an extension region that extends beyond one side of the bottom source / drain in the first direction.

15. The unit architecture according to claim 14, wherein, When viewed in a plan view, the gate contact structure extends in the first direction toward the side of the third gate portion away from the bottom source / drain.

16. The unit architecture according to claim 11, wherein, When viewed in a plan view, at least one side of the third gate portion includes an extension region in a first direction, the extension region being located outside an imaginary line extending from one side of the bottom source / drain in a second direction.

17. The unit architecture according to claim 16, wherein, When viewed in a plan view, the gate contact structure extends in the first direction toward the side of the third gate portion away from the bottom source / drain.

18. The unit architecture according to claim 11, wherein, When viewed in a plan view, the gate contact structure extends away from the adjacent side of the bottom source / drain in the first direction.

19. A standard inverter cell architecture, comprising: PMOS vertical field-effect transistor, which includes: A first fin and a second fin protrude from the substrate, the first fin and the second fin being spaced apart from each other in a first direction and extending in a second direction intersecting the first direction. A first gate includes a first gate portion on the sidewall of the first fin and a second gate portion on the sidewall of the second fin, the first gate portion and the second gate portion being spaced apart in the first direction. The first top source / drain includes a first top source / drain portion at the top of the first fin and a second top source / drain portion at the top of the second fin. NMOS vertical field-effect transistor, which includes: A third and fourth fin protruding from the substrate, the third and fourth fins being spaced apart from each other in the first direction and extending in the second direction. The second gate includes a third gate portion on the sidewall of the third fin and a fourth gate portion on the sidewall of the fourth fin, the third gate portion and the fourth gate portion being spaced apart in the first direction. The second top source / drain includes a third top source / drain portion at the top of the third fin and a fourth top source / drain portion at the top of the fourth fin; A gate connection structure is located in the region between the PMOS vertical field-effect transistor and the NMOS vertical field-effect transistor, and connects the first gate portion, the second gate portion, the third gate portion and the fourth gate portion to each other. The gate connection structure has a shape that surrounds four ends of the first fin, the second fin, the third fin and the fourth fin, and the four ends face each other in at least one of the first direction, the second direction and a third direction that is diagonal to the first direction and the second direction. A top source / drain contact structure, which is respectively connected to the second top source / drain portion and the fourth top source / drain portion; A gate contact structure connected to the gate connection structure and laterally away from the top source / drain contact structure in the second direction, at least one of the top source / drain contact structure and the gate contact structure serving as a first conductive wiring layer in the first direction; A metal pattern configured to be connected via vias to at least one of the gate contact structure, the second top source / drain portion, and the fourth top source / drain portion, the metal pattern serving as a second conductive wiring layer in the second direction; and An additional top source / drain contact structure is provided, which overlaps with the gate contact structure and is not connected to any one of the first top source / drain portion, the second top source / drain portion, the third top source / drain portion, and the fourth top source / drain portion.

20. The standard inverter cell architecture according to claim 19, wherein, The first gate portion and the third gate portion are aligned in the second direction. The second gate portion and the fourth gate portion are aligned in the second direction. The first gate portion and the third gate portion are spaced apart from the second gate portion and the fourth gate portion by a first distance in the first direction, and The metal pattern is arranged in the first direction at a second spacing different from the first spacing.

21. The standard inverter cell architecture according to claim 20, wherein, The ratio between the first spacing and the second spacing is m:n, where m and n are natural numbers, and n is less than m.

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