Semiconductor devices and bus generators

Abstract

Embodiments of the present disclosure relate to semiconductor devices and bus generators. Even under various conditions, the stay of requests on the bus can be eliminated, and memory efficiency can also be improved. Each of master devices A, master device B, and master device X issues an access request to a memory. A memory controller receives the access request through a bus. A central bus control unit controls the output of the access request issued by the master device to the memory controller by granting access rights to the memory to the master device. The central bus control unit manages the number of permissions that can be granted based on the access size of the access request issued by the master device that grants access rights, the number of permissions indicating the number of access rights that can be granted, and performs the granting of access rights within the range of the number of permissions that can be granted.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-118689 filed on June 22, 2018 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, for example, to a semiconductor device that performs access to a memory.

[0004] Furthermore, the present invention relates to a bus generator for generating a bus in a semiconductor device. Background Art

[0005] International Publication No. 2017 / 056132 discloses access control in a bus system in which multiple bus masters are coupled to a common bus. The semiconductor device described in International Publication No. 2017 / 056132 has multiple master devices, a memory controller, a bus coupling the multiple master devices to the memory controller, and a central bus control unit. International Publication No. 2017 / 056132 describes that the central bus control unit monitors the transmission volume of each master device and selects the master device to which the access rights are granted based on the reserved bandwidth of each master device, the monitored transmission volume, and the number of permissions that can be granted. In International Publication No. 2017 / 056132, requests of master devices that are not granted access rights are shielded in the bus between the memory controller and the master devices.

[0006] In International Publication No. 2017 / 056132, when a buffer in a memory controller is released, a central bus control unit receives a buffer release notification from the memory controller. Each time an access right is granted, the central bus control unit reduces the number of rights that can be granted by one, and each time a buffer is released, the number of rights that can be granted is increased by one. The situation where the buffer is full of unprocessed access requests can be avoided by granting access rights according to the processing conditions of the memory controller, and the situation where the memory controller cannot accept access requests that require low latency can be avoided. Summary of the invention

[0007] Here, the data size (access size) of the memory access required by the master device is not always constant, and the access size of a certain access request may be smaller than the access size of another access request. Generally speaking, the time required for memory access (access time) varies according to the access size, and the larger the access size, the longer the access time. In International Publication No. 2017 / 056132, this change in access time is not taken into account, and when the access size of the master device is not constant, low-latency and high-efficiency memory access may not be achieved.

[0008] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0009] According to an embodiment, a semiconductor device has an access control unit that performs access control that controls output of an access request issued by a master device to a memory controller by granting access rights to the master device for a memory. The access control unit manages the number of rights that can be granted based on the access size of the access request issued by the master device, and performs granting of access rights within the range of the number of rights that can be granted.

[0010] According to the embodiment, even under various conditions, the stay of a request on the bus is eliminated, and memory efficiency can also be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram showing an electronic device including a semiconductor device according to a first embodiment.

[0012] Figure 2 is a block diagram showing a configuration example of a central bus control unit.

[0013] Figure 3 is a block diagram showing a configuration example of an authority granting selection control unit.

[0014] Figure 4 is a flowchart showing a portion of the operation process related to management of the number of rights that can be granted.

[0015] Figure 5 : is a block diagram showing a configuration example of an authority granting selection control unit used in an electronic device including the semiconductor device according to the second embodiment.

[0016] Figure 6 is a block diagram showing a memory controller used in an electronic device including the semiconductor device according to the third embodiment.

[0017] Figure 7 is a block diagram showing a hardware configuration example of a bus generator.

[0018] Figure 8 is a flowchart showing the general flow of bus design.

[0019] Fig. 9 : is a diagram showing an example of a screen for inputting setting information.

[0020] Fig.10 is a block diagram showing input / output data to / from a bus generator. DETAILED DESCRIPTION

[0021] Before describing the embodiment, the process of generating the idea of ​​the embodiment described below will be described. In an actual product with a master device that accesses a DDR (double data rate) memory, the effective bandwidth of the DDR memory varies between about 50% and 70% depending on the situation, so it is hoped that its efficiency will be improved. Further, with respect to a master device that requires real-time characteristics, the access delay needs to be very short. However, the access delay will also change, so the access delay always needs to be very low. When delay is allowed to some extent, the memory access efficiency can be improved by the following: waiting until the memory access request is accumulated to a certain extent in the memory controller, and then performing scheduling to change the processing order of the access request by considering the type (read and write), address, etc. of the memory access. However, when giving priority to high-priority requests that require low latency, it is impossible to wait until a specific number of access requests are accumulated in the memory controller, so that the number of access requests to be scheduled is very small. Therefore, effective memory access cannot be achieved and bandwidth efficiency is reduced. Therefore, in a memory access system, it is necessary to respond to these conflicting requests.

[0022] As a result of the inventor's discussion, it was found that there is a time variation from granting access rights to the master device to releasing the buffer of the memory controller, thereby changing in bandwidth and delay. Further, it was found that the access size and type of each request are the cause of the variation. In International Publication No. 2017 / 056132, the amount of data transferred between the master device and the memory controller is represented by the product of the number of access requests to which access rights are granted and the access size. For example, the amount of data transferred when a predetermined number of access rights are granted to access requests with a smaller access size is less than the amount of data transferred when a predetermined number of access rights are granted to access requests with a larger access size. On the other hand, the same number of access rights are granted to access requests with a larger access size, which can improve memory access efficiency. However, the access time is long, so low latency may not be achieved. The inventor has discussed a bus system that can achieve efficient memory access with low latency even when the access size is not constant. As a result, the inventor has realized the conception of the embodiments described below.

[0023] Hereinafter, an embodiment of the device for applying the above-mentioned problem is described in detail with reference to the accompanying drawings. For the purpose of explanation, the following description and the accompanying drawings are appropriately omitted and simplified. The components shown in the accompanying drawings as functional blocks for performing various processes may be composed of a CPU (central processing unit), a memory and other circuits as hardware, and may be implemented by programs loaded in the memory as software, etc. Therefore, it should be understood by those skilled in the art that the functional blocks may be implemented in various forms by only hardware, only software or a combination of these, and the functional blocks are not limited to hardware, software, and a combination of these. In the accompanying drawings, the same components are represented by the same reference numerals, and redundant descriptions are appropriately omitted.

[0024] The above-mentioned program can be stored in various types of non-transitory computer-readable media and supplied to the computer. Non-transitory computer-readable media include various types of substantial recording media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., floppy disks, magnetic tapes, and hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (read-only memory), CD-Rs, CD-R / Ws, and semiconductor memories (e.g., mask ROMs, PROMs (programmable ROMs), EPROMs (erasable PROMs), flash ROMs, and RAMs (random access memories)). The program can be supplied to the computer via various types of transient computer-readable media. Examples of transient computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transient computer-readable media can supply the program to the computer via a wired communication path or a wireless communication path such as wires and optical fibers.

[0025] The following embodiments will be explained, and if necessary for convenience, they will be divided into multiple parts or embodiments. Except for the cases that are particularly clearly indicated, they are not independent of each other, and one has a relationship with another such as a modification example, an application example, a detailed description, and a partial or complete supplementary description. In the following embodiments, when the number of reference elements, etc. (including number, value, quantity, range, etc.) is used, they may not be limited to a specific number, but may be greater than or less than a specific number, except for the cases that are particularly clearly specified and the cases that are theoretically clearly limited to a specific number.

[0026] Further, in the following embodiments, elements (including operation steps, etc.) are not necessarily indispensable, except for cases that are particularly clearly specified and cases that are obviously indispensable from a theoretical point of view, etc. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of elements, etc., except for cases that are clearly specified and cases that are obviously wrong from a theoretical point of view, etc., shapes similar to or similar to the shapes should basically be included. This statement also applies to the number, etc. of the above-mentioned elements (including number, value, quantity, range, etc.).

[0027] [First embodiment]

[0028] Figure 1 An electronic device including a semiconductor device according to a first embodiment is shown. The electronic device 10 has a main device A 20, a main device B 30, a main device X 40, sub-bus controllers 22, 32 and 42, a central bus control unit 50, an interconnection 60, a memory controller 70, and a memory 80. Among the elements of the electronic device 1, for example, the main device A 20, the main device B 30, the main device X 40, the sub-bus controllers 22, 32 and 42, the central bus control unit 50, the interconnection 60, and the memory controller 70 configure the semiconductor device. Among the elements of the semiconductor device, for example, the sub-bus controllers 22, 32 and 42, the interconnection 60, and the memory controller 70 can be configured as a hardware circuit. The central bus control unit 50 can be configured as a circuit including a processor.

[0029] The master device A 20, the master device B 30, and the master device X 40 issue access requests to the memory 80. The memory 80 is configured as a memory device, such as, for example, DDR-SDRAM (double data rate synchronous dynamic random access memory). The master device A 20, the master device B 30, and the master device X 40 are bus masters, and are configured as processors, such as, for example, CPUs, GPUs (graphics processing units), etc. The master device A 20, the master device B 30, and the master device X 40 output access requests through corresponding buses 21, 31, and 41, respectively.

[0030] Here, the access request to the memory 80 includes an access type indicating read or write, address information of an access destination, and information indicating a data size (access size). The access size indicates the size of data to be read from the memory 80 or the size of data to be written to the memory 80. The access size includes, for example, 64 bytes, 128 bytes, and 256 bytes.

[0031] The master device A 20 is coupled to the corresponding sub-bus controller 22 through the bus 21. The sub-bus controller 22 is coupled to the interconnect 60 through the bus 24. The sub-bus controller 22 includes a request issuance control unit 23. The request issuance control unit 23 receives an access request issued and controlled by the master device A 20 through the bus 21, and controls the received access request to be output to the bus 24.

[0032] Master device B 30 is coupled to a corresponding sub-bus controller 32 via bus 31. Sub-bus controller 32 is coupled to interconnect 60 via bus 34. Sub-bus controller 32 includes a request issuance control unit 33. Likewise, master device X 40 is coupled to a corresponding sub-bus controller 42 via bus 41. Sub-bus controller 42 is coupled to interconnect 60 via bus 44. Sub-bus controller 42 includes a request issuance control unit 43.

[0033] The request issuance control unit 23 receives an access request from the master device A 20. When the access request issuance control unit 23 is granted an access right from the central bus control unit 50, the request issuance control unit 23 outputs the access request issued by the master device A 20 to the interconnect 60 through the bus 24. When the request issuance control unit 23 outputs an access request to the interconnect 60, the request issuance control unit 23 outputs information indicating an access size of the access request (hereinafter also referred to as access size information) to the central bus control unit 50. When the access right is not granted to the request issuance control unit 23, the request issuance control unit 23 prevents the access request issued by the master device A 20 from being output to the interconnect 60.

[0034] The functions of the request issuance control units 33 and 43 are similar to those of the request issuance control unit 23. When the request issuance control units 23, 33, and 43 are granted an access right and do not receive an access request from a corresponding master device, the request issuance control units 23, 33, and 43 may output an access right return signal to return the access right to the central bus control unit 50. The central bus control unit 50 may use the returned access right to grant an access right to another request issuance control unit.

[0035] The interconnect 60 receives access requests issued by the master device A 20, the master device B 30, and the master device X 40 through the buses 24, 34, and 44. The interconnect 60 is, for example, a bus arbiter, and arbitrates access requests input from a plurality of master devices. When the interconnect 60 receives access requests from, for example, the master device A 20, the master device B 30, and the master device X 40, the interconnect 60 outputs the access request issued by the master device with the highest priority to the memory controller 70 according to the priority set for each master device. When the interconnect 60 obtains a response to the access request output to the memory controller 70, the interconnect 60 selects the access request of the master device with the second highest priority, and outputs the access request to the memory controller 70.

[0036] The memory controller 70 is coupled to the master A 20, the master B 30, and the master X 40 through a bus, an interconnect 60, etc., and accesses the memory 80 according to an access request received through the interconnect 60. Figure 1An example is shown in which the electronic device 10 has three master devices, but the number of master devices is not particularly limited. The electronic device 10 only needs to have at least one master device that issues an access request to the memory 80 to the memory controller 70. When the number of master devices is 1, the interconnect 60 for arbitration is not required.

[0037] The memory controller 70 has a buffer (request buffer) 71. The buffer 71 stores access requests received by the memory controller 70 through the interconnect 60. The buffer 71 has a plurality of entries and is configured to be able to store a plurality of access requests. The memory controller 70 has, for example, a scheduler that selects one of the plurality of access requests stored in the buffer 71, and a memory command generation unit that generates a memory command (command signal) for accessing the memory 80 according to the selected memory command in addition to the buffer 71. When an access request is selected from the buffer 71 and the access request is processed, the memory controller 70 outputs a buffer release notification indicating that an entry of the buffer 71 is released to the central bus control unit 50. Further, the memory controller 70 outputs access size information of the access request that has been stored in the released buffer to the central bus control unit 50 as released access size information.

[0038] The central bus control unit 50 performs access control that controls output of an access request issued by each master device to the memory controller 70 by granting access rights to the master device using the sub-bus controllers 22, 32, and 42. The central bus control unit 50 grants access rights to the master device as the issuing source of the access request received by each request issuing control unit by granting access rights to the request issuing control unit 23, 33, and 43. The central bus control unit 50 and the sub-bus controllers 22, 32, and 42 configure the access control unit 90.

[0039] For example, the user sets the frequency band of each master device in the central bus control unit 50 in advance, and guarantees the QoS (Quality of Service) in a certain time (time slot). In the present embodiment, it is assumed that there is a master device for each access type. For example, a frequency band can be set for each of an access request whose access type is read (hereinafter referred to as a read request) and an access request whose access type is write (hereinafter referred to as a write request). The central bus control unit 50 grants access rights to each of the request issuing control units 23, 33 and 43 according to, for example, a predetermined access control content. The access control content may be the same as that described in International Publication No. 2017 / 056132. The contents described in International Publication No. 2017 / 056132 are incorporated herein by reference.

[0040] The central bus control unit 50 determines whether to grant an access right to the request issuance control units 23, 33, and 43 corresponding to each master device based on, for example, QoS information set for the read request and the write request of each master device. At this time, the central bus control unit 50 can monitor the transaction flowing through the bus through the request monitor (transaction monitor signal) acquired from the bus 24, 34, and 44, and grant the access right while performing correction for each time slot based on the transfer amount of the transaction. The central bus control unit 50 controls the output of the read request and the write request issued by each master device to the memory controller 70 by granting the access right.

[0041] The central bus control unit 50 manages the number of permissions that can be granted based on the access size of the access request issued by the master device that grants the access right, the number of permissions indicating the number of access rights that can be granted to the master device; and performs the granting of access rights within the range of the number of permissions that can be granted. For example, whenever the central bus control unit 50 grants access rights to the master device, the central bus control unit 50 reduces the number of permissions that can be granted by the weight according to the access size of the access request issued by the master device that grants the access right. When the central bus control unit 50 receives a buffer release notification from the memory controller 70, the central bus control unit 50 increases the number of permissions that can be granted by the weight according to the access size indicated by the release access size information. The weight of the access size (its value) is determined based on, for example, design and / or simulation results.

[0042] [Central bus control unit]

[0043] Figure 2 5 shows a configuration example of the central bus control unit 50. The central bus control unit 50 has an authority grant selection control unit 501, a QoS information register 502, and a grantable maximum number setting register 503. Figure 2 In, omitted Figure 1 Transaction monitoring signals shown in .

[0044] The QoS information register 502 stores the QoS information of each master device. The QoS information register 502 stores the reserved transmission amount of each sub-time slot of each master device and the priority level of each master device. Here, the sub-time slot is, for example, a time obtained by dividing a certain time (time slot) by a plurality of time periods. Alternatively, the QoS information register 502 may store the target transmission amount of each sub-time slot of each master device.

[0045] The authority granting selection control unit 501 grants access rights to the request issuing control units 23, 33, and 43 (see Figure 1). When the authority granting selection control unit 501 grants access rights, the authority granting selection control unit 501 determines (selects) the request issuing control unit to which the access rights are to be granted. The authority granting selection control unit 501 determines the request issuing control unit to which the access rights are to be granted by using, for example, the reserved bandwidth and priority level read from the QoS information register 502 and the transmission amount in the sub-time slot of each master device. Alternatively, the authority granting selection control unit 501 may determine the request issuing control unit to which the access rights are to be granted by using the target transmission amount read from the QoS information register 502.

[0046] The authority granting selection control unit 501 outputs an access right granting signal indicating acquisition of access right to the request issuing control unit to which access right is to be granted. For example, the authority granting selection control unit 501 asserts that the access right granting signal is to be output to the request issuing control unit to which access right is to be granted, and still denies that the access right granting signal is to be output to the request issuing control unit to which access right is not to be granted. For example, the authority granting selection control unit 501 determines the master device to which access right is to be granted for each sub-time slot.

[0047] The maximum grantable number setting register 503 stores the maximum number of grantable numbers of access rights (the maximum number of grantable rights), up to which the permission granting selection control unit 501 can grant access rights at the same time. When the permission granting selection control unit 501 grants the maximum number of access rights that can be granted to the access request with the largest access size, the maximum number of grantable rights is set to, for example, the number of access requests that do not remain in the bus. The permission granting selection control unit 501 calculates the number of grantable access rights using the maximum number of grantable rights stored in the maximum grantable number setting register 503 as the upper limit, and performs granting of access rights within the range of the calculated number of grantable rights.

[0048] In the present embodiment, the permission granting selection control unit 501 manages the number of permissions that can be granted based on the access size of the access request issued by each master device and the maximum number of permissions that can be granted. The permission granting selection control unit 501 manages the number of permissions to be granted access rights based on the access size (the number of permissions currently granted). The permission granting selection control unit 501 manages the difference between the maximum number of permissions that can be granted and the number of permissions currently granted set in the maximum number of permissions that can be granted setting register 503 as the remaining number of permissions that can be granted. The permission granting selection control unit 501 performs the granting of access rights within the range of the number of permissions that can be granted.

[0049] [Privilege Grant Selection Control Unit]

[0050] Figure 3 The configuration example of the permission granting selection control unit 501 is shown. The permission granting selection control unit 501 has an access permission granting destination determination unit 551, a grantability determination unit 552, an access permission granting unit 553, a correction amount calculation unit 554, a return amount calculation unit 555, an initial weight information register 581, a size-based weight information register 582, and a register 583 for storing the number of currently granted permissions. Figure 3 In the Figure 2 The signal output by the QoS information register 502, etc.

[0051] The initial weight information register 581 stores the master devices associated with each other and the weights of the access sizes of the access requests estimated to be issued by the master devices. For example, the initial weight information register 581 stores the master devices A 20 associated with each other and the weight "1", stores the master devices B 30 associated with each other and the weight "0.8", and stores the master devices X 40 associated with each other and the weight "0.9". The size-based weight information register 582 stores the access sizes associated with each other and the weights according to the access sizes. For example, the size-based weight information register 582 stores the access sizes 256 bytes associated with each other and the weight "1", stores the access sizes 128 bytes associated with each other and the weight "0.9", and stores the access sizes 64 bytes associated with each other and the weight "0.8". In the initial weight information register 581 and the size-based weight information register 582, the weight of each master device and the weight of each access size are set respectively by using a CPU, etc., not shown in the figure.

[0052] The access permission granting destination determining unit 551 determines a master device to which the access permission is granted. The access permission granting destination determining unit 551 acquires a weight corresponding to the determined master device from the initial weight information register 581. Instead of the initial weight information register 581, an initial size information register may be used, which stores a master device and an access size of an access request estimated to be issued by the master device. In this case, the access permission granting destination determining unit 551 may acquire an access size corresponding to the determined master device from the initial size information register, and acquire a weight corresponding to the acquired access size from the size-based weight information register 582.

[0053] The register 583 storing the number of currently granted permissions stores the number of granted access rights (the number of currently granted permissions). The grantability determination unit 552 refers to the maximum grantable number setting register 503 and the register 583 storing the number of currently granted permissions, and determines whether the access right can be granted to the master device determined by the access right granting destination determination unit 551 as the access right granting destination. More specifically, the grantability determination unit 552 calculates the difference (the number of grantable permissions) between the maximum number of grantable permissions stored in the maximum grantable number setting register 503 and the number of currently granted permissions stored in the register 583 storing the number of currently granted permissions. The grantability determination unit 552 compares the calculated number of grantable permissions with a weight according to an access size estimated to be issued by the master device determined as the access right granting destination, which is received from the access right granting destination determination unit 551. When the number of grantable permissions is greater than or equal to the weight received from the access right granting destination determination unit 551, the grantability determination unit 552 determines that the access right can be granted. When the number of grantable authorities is smaller than the weight received from the access authority grant destination determination unit 551 , the grantability determination unit 552 determines that the access authority cannot be granted.

[0054] When the grantability determination unit 552 determines that the access right can be granted, the grantability determination unit 552 instructs the access right granting unit 553 to grant the access right to the master device determined by the access right granting destination determination unit 551. Further, the grantability determination unit 552 updates the number of currently granted permissions by adding the weight received from the access right granting destination determination unit 551 to the number of currently granted permissions stored in the register 583 storing the number of currently granted permissions. Whenever granting access right to the master device, the grantability determination unit 552 adds a weight according to an estimated access size of an access request issued by the master device to which the access right is to be granted to the number of currently granted permissions.

[0055] In this embodiment, the number of currently granted permissions is weighted by weighting according to the access size. For example, when the number of granted access rights is "10", if all access sizes of access requests are 64 bytes, the number of currently granted permissions is 10×0.8=8. When the number of granted access rights is "10" and all access sizes of access requests are 256 bytes, the number of currently granted permissions is 10×1=10. In this embodiment, the number of permissions that can be granted varies according to the access size, which is represented by the difference between the maximum number of permissions that can be granted and the number of permissions currently granted. When the access rights are granted to access requests with a smaller access size, the number of permissions that can be granted increases compared to the case where the access rights are granted to access requests with a larger access size.

[0056] When the access authority granting unit 553 issues a request to the request issuing control units 23, 33, and 43 (see Figure 1 ) When the access right is granted and the access request is received from the corresponding master device, the request issuance control unit 23, 33, and 43 outputs the access request to the interconnect 60 by using the granted access right. At this time, the request issuance control unit outputs the access size information to the central bus control unit 50. In the central bus control unit 50, the correction amount calculation unit 554 of the permission grant selection control unit 501 corrects the number of currently granted permissions based on the access size indicated by the access size information output from the request issuance control unit, which is calculated using the weight stored in the initial weight information register 581 when the access right is granted. The correction amount calculation unit 554 corrects the number of currently granted permissions based on, for example, the difference between the weight according to the access size of the access request estimated to be issued by the master device and the weight according to the access size notified from the request issuance control unit, which weight according to the access size of the access request estimated to be issued by the master device is stored in the initial weight information register 581.

[0057] More specifically, for example, if the master device A 20 is the access right granting destination, when granting the access right, the grantability determination unit 552 adds the weight "1" stored in the initial weight information register 581 to the number of currently granted rights. When the access size of the access request actually issued by the master device A 20 is 128 bytes, the request issuance control unit 23 notifies the correction amount calculation unit 554 of the access size information 128 bytes. The correction amount calculation unit 554 acquires the weight "0.9" corresponding to 128 bytes from the size-based weight information register 582, and corrects the number of currently granted rights by the difference between the acquired weight "0.9" and the weight "1" stored in the initial weight information register 581. In this case, the weight corresponding to the estimated access size is greater than the weight corresponding to the actual access size, so that the number of currently granted rights is reduced by the difference "0.1" between the weights. When the weight corresponding to the estimated access size is less than the weight corresponding to the actual access size, the number of currently granted rights increases by the difference between the weights. By doing so, the number of currently granted permissions can be managed by weight according to the access size of the access request actually issued by the master device.

[0058] On the other hand, when the access right is granted from the access right granting unit 553 to the request issuance control unit 23, 33 and 43 and no access request is received from the corresponding master device, the request issuance control unit 23, 33 and 43 returns the granted access right to the central bus control unit 50 without using the access right. The request issuance control unit can return the access right to the central bus control unit 50 by asserting a dedicated access right return signal, or can return the access right by outputting access size information "0". In the central bus control unit 50, when returning the access right, the return amount calculation unit 555 of the authority granting selection control unit 501 subtracts the weight stored in the initial weight information register 581 from the number of rights currently granted, and when granting the access right, adds the weight stored in the initial weight information register 581 to the number of rights currently granted. By doing so, when returning the access right, the number of currently granted rights can be restored to the state before the access right is granted. The returned access right can be used as the access right of another master device.

[0059] When processing memory access based on the access request stored in the buffer 71 and releasing the entry of the buffer 71, the memory controller 70 (see Figure 1) outputs a release notification signal to the central bus control unit 50. Further, the memory controller 70 outputs release size information to the central bus control unit 50, the release size information indicating the access size of the processed access request. In the central bus control unit 50, when the return amount calculation unit 555 receives the release notification signal, the return amount calculation unit 555 subtracts the weight according to the access size indicated by the release size information from the register 583 storing the number of currently granted permissions. By doing so, the access permission for the access request whose processing is completed can be granted to another access request.

[0060] [Operation process]

[0061] Next, the operation procedure will be described. Figure 4 FIG. 5 shows a portion of the operation process related to the management of the number of permissions that can be granted. Before operating the electronic device 10, necessary information is set in the initial weight information register 581 and the size-based weight information register 582 (see FIG. 5 ). Figure 3 ). In the initial weight information register 581, a weight is set for each master device, which corresponds to the access size in one memory access (access request) expected (estimated) by each master device. In the size-based weight information register 582, a weight is set for each access size. The weights set in the initial weight information register 581 and the size-based weight information register 582 represent the number of access rights consumed by the access request of each master device and each access size.

[0062] The access permission granting destination determining unit 551 determines the master device (request issuance control unit) of the access permission granting destination (step A1). The access permission granting destination determining unit 551 acquires the weight corresponding to the master device of the access permission granting destination determined in step A1 from the initial weight information register 581 (step A2). The access permission granting destination determining unit 551 transmits the acquired weight to the grantability determining unit 552.

[0063] The grantability determination unit 552 determines whether the access right can be granted to the master device determined in step A1 based on the weight received from the access right grant destination determination unit 551, the maximum number of grantable rights stored in the grantable maximum number setting register 503, and the number of currently granted rights stored in the register 583 storing the number of currently granted rights (step A3). In step A3, for example, the grantability determination unit 552 determines whether the number of grantable rights is greater than or equal to the weight received from the access right grant destination determination unit 551, the number of grantable rights being obtained by subtracting the number of currently granted rights from the maximum number of grantable rights. When the number of grantable rights is greater than or equal to the weight received from the access right grant destination determination unit 551, the grantability determination unit 552 determines that the access right can be granted. When the number of grantable rights is less than the weight received from the access right grant destination determination unit 551, the grantability determination unit 552 determines that the access right cannot be granted.

[0064] When the grantability determination unit 552 determines in step A3 that the access right can be granted, the grantability determination unit 552 instructs the access right granting unit 553 to grant the access right. When the grantability determination unit 552 instructs the access right granting unit 553 to grant the access right, the access right granting unit 553 grants the access right to the master device determined in step A1 (step A4). When it is determined in step A1 that the access right to the master device is granted, the grantability determination unit 552 reduces the number of access rights that can be granted by the weight received from the access right granting destination determination unit 551 (step A5). In step A5, for example, the access right granting destination determination unit 551 reduces the number of access rights that can be granted by adding the weight received from the access right granting destination determination unit 551 to the number of currently granted rights stored in the register 583 storing the number of currently granted rights. In step A3, when it is determined that the number of rights that can be granted is less than the weight received from the access right granting destination determination unit 551, granting of the access right is suspended. When the number of grantable permissions changes and becomes greater than or equal to the weight received from the access permission grant destination determination unit 551, granting of the access permission is performed.

[0065] The master device outputs an access request to the request issuance control unit of the corresponding sub-bus controller. When the request issuance control unit is granted the access right and receives the access request from the master device, the request issuance control unit outputs the access request to the interconnect 60. At this time, the request issuance control unit transmits access size information indicating the access size of the access request output to the interconnect 60 to the central bus control unit 50. When the request issuance control unit is granted the access right and does not receive the access request from the master device, the request issuance control unit returns the granted access right to the central bus control unit 50.

[0066] The correction amount calculation unit 554 determines whether the access size information is received from the request issuance control unit corresponding to the master device that grants the access rights (step A6). When the correction amount calculation unit 554 receives the access size information, the correction amount calculation unit 554 corrects the number of permissions that can be granted that was reduced in step A5 based on the access size indicated by the access size information (step A7). In step A7, the correction amount calculation unit 554 obtains the weight corresponding to the access size indicated by the access size information from the size-based weight information register 582, and calculates the difference between the obtained weight and the weight obtained in step A2. The correction amount calculation unit 554 corrects the number of permissions that can be granted by increasing or decreasing the number of permissions currently granted stored in the register 583 by the difference between the calculated weights, which stores the number of permissions currently granted. When the difference between the calculated weights is zero, the number of permissions that can be granted is not corrected.

[0067] When the correction amount calculation unit 554 determines that the access size information is not received, the return amount calculation unit 555 receives the access permission return signal from the request issuance control unit. In this case, the return amount calculation unit 555 restores the number of permissions that can be granted that was reduced in step A5 (step A8). In step A8, the return amount calculation unit 555 increases the number of permissions that can be granted by the weight obtained in step A2 by reducing the number of permissions currently granted stored in the register 583 by the weight obtained in step A2, and the register 583 stores the number of permissions currently granted.

[0068] The access request output from the request issuance control unit is arbitrated by the interconnect 60 and stored in the buffer 71 of the memory controller 70. The memory controller 70 performs memory access to the memory 80 according to the access request stored in the buffer 71. When the memory access based on the access request is completed, the memory controller 70 releases the entry of the buffer 71. At this time, the memory controller 70 transmits a release notification signal to the central bus control unit 50. Further, the memory controller 70 notifies the central bus control unit 50 of release size information indicating the released access size of the access request.

[0069] The return amount calculation unit 555 determines whether a release notification signal is received from the controller 70 (step A9). When the return amount calculation unit 555 determines that the release notification signal is received, the return amount calculation unit 555 increases the number of permissions that can be granted by the weight corresponding to the access size indicated by the release size information output from the memory controller 70 (step A10). In step A10, the return amount calculation unit 555 obtains the weight corresponding to the access size indicated by the release size information from the size-based weight information register 582. The return amount calculation unit 555 can increase the number of permissions that can be granted by the weight corresponding to the access size indicated by the release size information by reducing the number of permissions currently granted stored in the register 583 by the weight obtained from the size-based weight information register 582, which stores the number of permissions currently granted.

[0070] [in conclusion]

[0071] In the present embodiment, the central bus control unit 50 manages the number of permissions that can be granted based on the access size of the access request to which the access rights are granted. For example, when the central bus control unit 50 grants access rights to a certain master device, the central bus control unit 50 weights the number of permissions consumed by the granted access rights according to the weight of the access size. For example, when the access size is larger, the weight is set larger, and the number of consumed permissions granted to access requests with smaller access sizes is smaller than the number of permissions granted to access requests with larger access sizes. In this way, by changing the number of consumed permissions according to the access size, when there are many access requests with smaller access sizes, the remaining number of permissions that can be granted can be increased, and these permissions are not consumed, so that access rights can be granted to a larger number of access requests. On the other hand, when there are many access requests with larger access sizes, the remaining number of permissions that can be granted can be reduced, and these permissions are not consumed, so that excessive granting of access rights to access requests can be suppressed.

[0072] An access request with a smaller access size accesses the memory 80 in a short time, so that the residence time in the buffer 7 is short. On the other hand, an access request with a larger access size accesses the memory 80 in a long time, so that the residence time of the access request in the buffer 7 is long. In the present embodiment, a weight according to the access size is used, and the number of access rights consumed by the access request is controlled according to the access size. By doing so, the number of access rights that can be granted can be dynamically controlled according to the length of the residence time of the access request in the buffer 71, so that the residence of the access request on the bus can be eliminated and the efficiency of the memory under various conditions can be improved.

[0073] Compared with International Publication No. 2017 / 056132, in International Publication No. 2017 / 0561, the number of all consumption rights of access rights is "1". For example, in International Publication No. 2017 / 056132, when the maximum number of rights that can be granted is stored in the maximum number of grantable setting register, the central bus control unit grants access rights to 32 access requests regardless of the access size. The time required for memory access varies according to the access size, for example, the time required for memory access with an access size of 64 bytes is shorter than the time required for memory access with an access size of 256 bytes. When the access size of the access request stored in the buffer of the memory controller is 64 bytes, the buffer is released earlier than the case where the access request stored in the buffer is 256 bytes. However, in International Publication No. 2017 / 056132, when 32 access rights are granted, no new access rights are granted before the buffer is actually released. There is a time lag from granting access rights to the actual storage of the access request in the buffer. Therefore, in International Publication No. 2017 / 056132, when there are many access requests with a small access size, memory access is completed quickly, so there is a possibility that a blank space appears in the buffer for a long period of time.

[0074] On the other hand, in the present embodiment, for example, the weight when the access size is 64 bytes is set to 0.8, the weight when the access size is 128 bytes is set to 0.9, and the weight when the access size is 256 is set to 1. In the present embodiment, for example, when all access sizes are 64 bytes, 40 access rights can be granted relative to the maximum number of rights that can be granted "32". When all access sizes are 256 bytes, access rights can be granted, the number of which is the same as the maximum number of rights that can be granted "32". In the present embodiment, when the maximum number of rights that can be granted is set to a value in which no access rights stay in the bus for access requests with a maximum access size of 256 bytes, access rights for access requests of 64 bytes and 128 bytes, the number of which exceeds the maximum number of rights that can be granted, can be granted, where the time required for memory access is short. By doing so, when the access size is small, the time period in which the blank space appears in the buffer can be shortened by increasing the number of granted access rights, and the memory efficiency can be improved. On the other hand, when the access size is large, excessive granting of access rights is suppressed, and the stay of access requests in the bus can be suppressed.

[0075] In the present embodiment, there is also the effect that the balance between the operation emphasizing efficiency and the operation improving latency can be adjusted by adjusting the weight according to the access size. For example, when memory efficiency is prioritized, the number of access rights that can be granted to access requests with a smaller access size can be increased by setting the weight of access requests with a smaller access size to a smaller value, thereby achieving an operation emphasizing memory efficiency. On the other hand, when the weight of access requests with a smaller access size is set to a value close to 1, the increase in the number of access rights that can be granted to access requests with a smaller access size can be suppressed, thereby reducing the possibility of access requests staying in the bus and achieving an operation emphasizing improvement of latency.

[0076] [Second embodiment]

[0077] Next, a second embodiment will be described. Figure 5 FIG. 1 shows an example of a configuration of a permission granting selection control unit used in an electronic device according to a second embodiment. Figure 1 The configuration of the central bus control unit can be the same as that shown in Figure 2 The authority granting selection control unit 501a used in this embodiment has the following configuration: the access size history storage unit 584 is added to the Figure 3In the configuration of the authority granting selection control unit 501 used in the first embodiment shown. Further, the initial weight information register 581 in the authority granting selection control unit 501 is replaced by the weight generating unit 557. Other points may be the same as those of the first embodiment.

[0078] The access size history storage unit 584 stores the history of the access size information notified from the request issuance control unit. The weight generation unit 557 refers to the access size history storage unit 584, and generates a weight according to the access size of the access request estimated to be issued by the master device based on the history of the access size information stored in the access size history storage unit 584. For example, the weight generation unit 557 and the access size history storage unit 584 are arranged corresponding to a plurality of master devices included in the electronic device 10, respectively. The access size history storage unit 584 corresponding to each master device stores the history of the access size information notified from the request issuance control unit corresponding to the master device. The weight generation unit 557 corresponding to each master device refers to the access size history storage unit 584 corresponding to the master device, and generates a weight according to the access size of the access request estimated to be issued by the master device.

[0079] When the request is issued to the control units 23, 33 and 43 (see Figure 1 ) When the access requests issued by the master device A 20, the master device B 30, and the master device X 40 are respectively output to the interconnect 60, the request issuance control units 23, 33, and 43 output the access size information to the central bus control unit 50. For example, the access size history storage unit 584 stores a predetermined number of multiple access size information of each master device. The number of the multiple access size information stored in the access size history storage unit 584 is not particularly limited, but the number is set to five, for example.

[0080] The weight generation unit 557 estimates the access size of the access request issued by the master device next time based on the history of the access size information stored in the access size history storage unit 584, for example. For example, the weight generation unit 557 statistically processes five pieces of access size information by a predetermined statistical method, and then estimates the access size of the access request issued by the master device next time. For example, the weight generation unit 557 uses the average value of the access size indicated by the five most recent access size information as the estimated value of the access size of the access request issued by the master device next time. Alternatively, the weight generation unit 557 can use the value calculated from the average value by using a predetermined calculation formula as the estimated value of the access size of the access request issued by the master device next time. Further, the weight generation unit 557 can use the access size indicated by the most recent access size information among the five pieces of access size information as the estimated value of the access size of the access request issued by the master device next time. The access size estimation method in the weight generation unit 557 can be configured to be switchable by using, for example, a register not shown in the figure.

[0081] The weight generation unit 557 generates a weight corresponding to the estimated access size. In the weight generation unit 557, for example, the initial weight information register 581 (see Figure 3 ) is set as an initial value. When the access permission granting destination determining unit 551 determines the master device of the access permission granting destination, the access permission granting destination determining unit 551 obtains a weight corresponding to an estimated value of the access size of the access request issued by the master device next time. When granting access permission, the grantability determining unit 552 updates the number of currently granted permissions stored in the register 583 storing the number of currently granted permissions by using the weight acquired from the weight generating unit 557.

[0082] When the correction amount calculation unit 554 receives the access size information from the request issuance control unit that grants the access right, the correction amount calculation unit 554 corrects the number of currently granted permissions stored in the register 583 based on the difference between the weight added to the register 583 when the access right is granted and the weight corresponding to the access size indicated by the access size information. Further, when the access right is returned from the request issuance control unit to which the access right is granted, the return amount calculation unit 555 subtracts the weight added to the register 583 when the access right is granted from the number of currently granted permissions stored in the register 583 that stores the number of currently granted permissions.

[0083] In this article, there is a predetermined time difference between the timing when the permission granting selection control unit 501a grants access rights to the request release control unit and the timing when the permission granting selection control unit 501a receives access size information from the request release control unit. Further, there is a predetermined time difference between the timing when the permission granting selection control unit 501a grants access rights to the request release control unit and the timing when the permission granting selection control unit 501a receives the access rights return signal from the request release control unit. In order to adjust the time difference, the correction amount calculation unit 554 and the return amount calculation unit 555 can receive the weight generated by the weight generation unit 557 by a FIFO (first in first out) or the like that delays data at a predetermined time. In this case, even when the weight generated by the weight generation unit 557 changes during the period between the granting of access rights and the reception of access size information, the correction amount calculation unit 554 can also correct the number of currently granted rights by using the weight used when granting access rights. Further, the return amount calculation unit 555 can increase the number of currently granted rights by the weight used when granting access rights.

[0084] [in conclusion]

[0085] In this embodiment, the weight generation unit 557 estimates the access size of the access request issued by the master device based on the access size of the access request actually generated, and generates a weight when granting access rights. By using the historical information of the access size, the access size of the access request issued by the master device can be estimated more accurately, and by using the weight according to the estimated access size, the degradation of latency and the reduction of memory efficiency can be prevented.

[0086] [Third embodiment]

[0087] Subsequently, a third embodiment will be described. Figure 6 FIG. 1 shows a memory controller used in an electronic device according to a third embodiment. In this embodiment, the configuration of the electronic device can be similar to Figure 1 The configuration of the central bus control unit can be the same as that shown in Figure 2 In this embodiment, the memory controller 70b has a cache 72, a prefetch control unit 73, and a control register 74 in addition to the buffer 71. Other points may be the same as those of the first embodiment or the second embodiment.

[0088] During memory access to the memory 80, when the memory controller 70b reads the memory 80, the memory controller 70b reads (pre-fetches) additional data in addition to the data of the actual access size, and stores the two data in the cache 72, so that when the additional data is read (read hit), the memory 80 is not read. Thus, the delay can be reduced. However, when the pre-fetched data is not used or the data is discharged from the cache before use, the pre-fetched data is wasted and the access efficiency of the memory 80 is reduced. In the present embodiment, the memory controller 70b controls pre-fetching based on information such as QoS.

[0089] When reading the memory 80, the prefetch control unit 73 of the memory controller 70b determines whether to perform prefetch. The control register 74 stores information identifying the master device as a prefetch object and the maximum access size when performing prefetch. When an access request to a continuous address occurs, prefetch is effective, and whether prefetch is effective is determined based on the characteristics of the memory access. In the control register 74, the master device that generates the access request to the continuous address is set as the prefetch master device. The prefetch control unit 73 determines whether to perform prefetch on the master device stored in the control register 74 as the prefetch master device. When the prefetch control unit 73 performs prefetch, the prefetch control unit 73 temporarily stores the prefetched data in the cache 72. When reading the access type of the access request, the prefetch control unit 73 improves the efficiency of memory access by reading the cache 72 in advance using the access size information.

[0090] More specifically, the prefetch control unit 73 obtains the access size information from the central bus control unit 50b and estimates the access size issued by the prefetch master next time. Further, the prefetch control unit 73 calculates the access size based on the information stored in the QoS information register 502 (see Figure 2 ) determines whether the prefetch master will issue many access requests based on the setting information of QoS in the buffer 71, and grants the latest information to the access authority. The prefetch control unit 73 checks the master of the issuing source of the access request stored in the buffer 71, and checks how many access requests issued by a master different from the prefetch master are stored in the buffer 71. The prefetch control unit 73 determines whether to perform prefetching by comprehensively checking the latest access size of each master, the next band of the prefetch master estimated from the QoS setting, the bands of other masters estimated from the QoS setting, the number of access requests issued by the prefetch master and stored in the buffer 71, and the number of access requests issued by other masters and stored in the buffer 71.

[0091] For example, when a large number of access requests issued by the prefetch master are stored in the buffer 71, the prefetch master has issued the large number of access requests, making it very likely that prefetching is effective. When the prefetch master has issued a large number of access requests, the prefetch control unit 73 can determine to perform prefetching. Further, the prefetch control unit 73 can check the ratio of the access sizes of the access requests currently issued by the prefetch master. There is a merging effect in the case where the prefetch master issues an access request of the maximum access size, so that the prefetch control unit 73 can determine to perform prefetching in this case.

[0092] Regarding QoS setting, when the frequency band of the prefetch master is large, it is likely that the prefetch data is used. When the frequency band of the master device other than the prefetch master device is low, the extension time until the data stored in the cache 72 is overwritten when prefetching is performed is long. When the frequency band of the prefetch master device is large or the frequency band of the master device other than the prefetch master device is low, the prefetch control unit 73 can determine to perform prefetching. The prefetch control unit 73 can determine whether to perform prefetching by comprehensively checking the above items, etc.

[0093] [in conclusion]

[0094] In the present embodiment, the pre-fetch control unit 73 determines whether to perform pre-fetch based on the access size of the access request issued by the master device and the grant status of the access rights to the master device. For example, when the master device is expected to output a large number of read requests of the same access size to consecutive addresses, memory access can be efficiently performed by performing pre-fetch. Specifically, in the case of DDR memory, etc., unless the read size is greater than a certain value, the efficiency may be significantly reduced.

[0095] [Fourth embodiment]

[0096] [Bus Generator]

[0097] Subsequently, a fourth embodiment will be described. In this embodiment, a bus generator generates bus circuit information in a semiconductor device based on various setting information. Figure 7 800. The bus generator 800 is configured as a computer device, which includes, for example, a CPU 801, a memory 802, a keyboard 804, a mouse 805, a monitor 806, and a bus 807. The memory 808 stores a bus generation tool 803 for causing the computer device to operate as the bus generator 800. In the computer device, the CPU 801 performs processing according to the bus generation tool 803 read from the memory 802, thereby causing the computer device to operate as the bus generator 800.

[0098] Figure 8The schematic process of bus design is shown. First, use cases in the market are considered (step S101), and the performance required by the bus is discussed (step S103). Next, the bus structure is discussed based on the required performance (step S103). The discussion of the bus structure includes, for example, whether to use a central bus control unit 50 (see Figure 1 ) discussion.

[0099] When the bus structure is determined, the setting information required for the determined bus structure is input to the bus generator (step S104). The bus generator generates and outputs the circuit information of the bus (step S105). For example, the circuit information is described in RTL (register transfer level). Thereafter, the circuit information of the bus is logically synthesized (step S106), and then, the layout design is performed (step S107). Steps S104 and S105 represent the stage of performing the design by using the bus generator.

[0100] Fig. 9 An example of a screen for inputting setting information is shown. For example, a screen prompting input of setting information is displayed on the monitor 806 (see Figure 7 ), and the user gives various settings to the bus generator 800 by using the keyboard 804 and the mouse 805. For example, when the user Fig. 9 In the menu 901 on the screen shown, "QoS" is selected, and a submenu 902 is displayed. When the user selects "Initial Value" in the submenu 902, an input screen 903 for inputting the access size of each master device is displayed. On the input screen 903, for example, the user can select a central control method, and can also select the presence or absence of a cache, etc. On the input screen 903, the user can input, for example, the value to be set in the initial weight information register 581 (see Figure 3 ) and other information set in the

[0101] For example, the user inputs information of the access destination of the master device, information of the clock to be used, information related to the bus width, information related to functional safety, etc. into the bus generator 800 as information related to the master device that outputs the access request of the memory. Further, the user inputs information of the address area, information of the clock to be used, information related to the bus width, information related to functional safety, etc. as information related to the slave device accessed from the master device. Further, the user inputs information for specifying the QoS method, detailed settings of each method, etc. as information related to the arbitrator.

[0102] Fig.101 shows input / output data to / from the bus generator. The bus generator 800 has, for example, a bus structure information generating unit, a bus component generating unit, a central bus control unit generating unit, a sub-bus controller generating unit, a merging unit, etc. as functional blocks. Clock information 101, connection information 102, slave device information 103, master device information 104, QoS method selection information 105, and detailed setting information 106 of the QoS method are input to the bus generator 800. These multiple pieces of information are transmitted through the bus generator 800 as shown in FIG. Fig. 9 Enter the setting information on the input screen shown.

[0103] The bus generator 800 generates structural information of a bus coupled between a master device and a slave device by using the clock information 101, the connection information 102, the slave device information 103, the master device information 104, etc. Further, the bus generator 800 generates circuit information of various bus components based on the generated structural information of the bus and circuit information of various functional blocks provided from, for example, a vendor providing various IP cores.

[0104] The bus generator 800 generates circuit information of a central bus control unit that performs access control on access requests output by a master device by using the structural information of the bus, the QoS method selection information 105, circuit information of various functional blocks, etc. The circuit information of the central bus control unit generated by the bus generator 800 shows, for example, Figure 2 The circuit configuration of the central bus control unit 50 is shown in FIG.

[0105] The bus generator 800 generates circuit information of a sub-bus controller, which operates based on the control of the central bus control unit, by using the circuit information of the central bus control unit. The circuit information of the sub-bus controller represents, for example, Figure 1 The bus generator 800 combines the circuit information of the bus components, the circuit information of the central bus control unit, and the circuit information of the sub-bus controllers, and outputs the bus circuit information 113. The bus circuit information 113 is, for example, described in RTL with the circuit information between the master device and the sub-bus controller. Figure 1 The information is obtained by the circuit parts related to the bus between the memory 80 in the electronic device 10 shown.

[0106] [in conclusion]

[0107] In this embodiment, the bus generator 800 is used to generate a bus system. By inputting various setting information, etc. into the bus generator 800, for example, a bus system between a master device and a Figure 1 A bus system between the memories 80 of the electronic device 10 is shown.

[0108] Although the invention made by the inventors has been specifically described based on the embodiments, it goes without saying that the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention.

Claims

1. A semiconductor device, comprising: The master device issues access requests to the memory; a memory controller coupled to the master device via a bus and accessing the memory according to the access request; as well as an access control unit, controlling output of the access request issued by the master device to the memory controller by granting access rights to the memory to the master device, wherein the access control unit manages the number of permissions, the number of permissions indicating the number of the access permissions that can be granted, and the access control unit performs granting of the access permissions within the range of the number of permissions that can be granted, The access control unit comprises: The sub-bus controller has a request issuing control unit, the request issuing control unit receiving the access request issued by the master device; as well as a central bus control unit that grants access rights to the master device, the master device being an issuing source of the access request received by the request issuing control unit, by granting the access rights to the request issuing control unit, and wherein when the access right is granted from the central bus control unit to the request issuance control unit, the request issuance control unit outputs the access request to the memory controller, and when the access right is not granted to the request issuance control unit, the request issuance control unit prevents the access request from being output to the memory controller, wherein the central bus control unit calculates a difference between a maximum number of times that access rights are to be granted, indicating a maximum number of times that access rights are to be granted, and a current number of times that access rights are to be granted as the number of times that access rights can be granted, wherein when the request issuance control unit outputs the access request to the memory controller, the request issuance control unit notifies the central bus control unit of an access size of the access request to be output to the memory controller, the access size indicating the size of data to be read from the memory or the size of data to be written to the memory, and wherein the central bus control unit corrects the number of currently granted permissions based on the access size notified from the request issuance control unit.

2. The semiconductor device according to claim 1 , wherein each time the central bus control unit grants the access right to the master device, the central bus control unit is configured to perform the correction by adding a weight according to the access size notified from the request issuance control unit to the number of currently granted rights.

3. The semiconductor device according to claim 2, wherein when granting the access right, the central bus control unit generates a weight according to an access size estimated to be issued by the master device and the number of currently granted rights, and wherein the central bus control unit corrects the number of currently granted permissions based on a difference between the weight generated according to the estimated access size of the access request and the weight according to the access size notified from the request issuance control unit.

4. The semiconductor device according to claim 1, further comprising: a size-based weight information storage unit storing the access size and the weight in association with each other, and The central bus control unit obtains the weight according to the notified access size by referring to the weight information storage unit.

5. The semiconductor device according to claim 3, The central bus control unit acquires a history of access sizes notified from the request issuance control unit, and generates a weight according to an access size estimated to be issued by the master device based on the acquired history of access sizes.

6. The semiconductor device according to claim 1, wherein the memory controller has a request buffer that receives and stores the access request, and when a memory access based on the access request stored in the request buffer is processed and an entry of the request buffer is released, the memory controller outputs a release notification signal that indicates that the request buffer is released to the central bus control unit and notifies the central bus control unit of an access size of the processed access request, and When the central bus control unit receives the release notification signal from the memory controller, the central bus control unit subtracts a weight according to the access size notified from the memory controller from the number of currently granted permissions.

7. The semiconductor device according to claim 1, wherein when the access right is granted from the central bus control unit to the request issuance control unit and the access request from the master device is not received, the request issuance control unit returns the access right to the central bus control unit, and When the access rights are returned to the central bus control unit, the central bus control unit subtracts a weight according to the estimated access size of the access request from the number of currently granted rights.

8. The semiconductor device according to claim 1, The master device comprises a first master device, The sub-bus controller comprises a first sub-bus controller, The request issuing control unit includes a first request issuing control unit, and The semiconductor device further comprises: a second master device that issues the access request to the memory; A second sub-bus controller, comprising a second request issuing control unit, the second request issuing control unit receiving the access request issued by the second master device; as well as interconnect, arbitrate the access requests output from the first master device and the second master device, and output the arbitrated access requests to the memory controller, wherein the first sub-bus controller is arranged between the first master device and the interconnection via a first bus, and The second sub-bus controller is arranged between the second master device and the interconnection via a second bus.

9. The semiconductor device according to claim 1, The memory controller comprises: Cache; as well as a prefetch control unit that controls prefetching for acquiring data larger in size than the access size data of the access request from the memory, and when the access request is a read, stores the acquired data in the cache, The prefetch control unit determines whether to perform prefetch based on an access size of an access request issued by the master device and a grant status of the access right to the master device.

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