Semiconductor device package and manufacturing method thereof

Abstract

A semiconductor device package includes a first dielectric layer, a first conductive layer, an electronic component, a second dielectric layer, a second conductive layer, and a package body. The first dielectric layer has a top surface, a bottom surface opposite the top surface, and lateral surfaces extending between the top and bottom surfaces. The first conductive layer is disposed on the top surface of the first dielectric layer. The electronic component is disposed on the top surface of the first dielectric layer. The second dielectric layer covers the bottom surface and a first portion of the lateral surface of the first dielectric layer and exposes a second portion of the lateral surface of the first dielectric layer. The second conductive layer is disposed on the bottom surface of the second dielectric layer and is electrically connected to the first conductive layer. The package body covers the electronic component, the top surface of the second dielectric layer, and the second portion of the lateral surface of the first dielectric layer.

Description

Technical Field

[0001] The present invention generally relates to semiconductor device packages and methods of manufacturing the same, and more particularly to semiconductor device packages including conductive pillar structures and methods of manufacturing the same. Background Art

[0002] In some existing processes for forming connection structures (e.g., fan-out structures) for semiconductor device packages, a circuit layer is placed on a carrier with fine-pitch conductive traces (e.g., line spacing (L / S) equal to or less than 7 micrometers (μm) / 7 μm) on one side of the circuit layer (e.g., the chip side), and then coarse-pitch conductive traces are formed on the other side of the circuit layer (e.g., the ball side). However, due to misalignment (x- and y-directions) and horizontal errors (z-direction), the conductive traces will not be accurately formed on the circuit layer, which will cause electrical problems (e.g., short circuits or open circuits).

[0003] In other existing processes for forming connection structures, coarse-pitch conductive traces can be formed on the ball side of the circuit layer, and then fine-pitch conductive traces are formed on the chip side of the circuit layer. However, due to warpage issues, forming conductive traces on the chip side of the circuit layer is difficult. Summary of the Invention

[0004] In one or more embodiments, a semiconductor device package includes a first dielectric layer, a first conductive layer, an electronic component, a second dielectric layer, the second conductive layer, and a package body. The first dielectric layer has a top surface, a bottom surface opposite the top surface, and lateral surfaces extending between the top and bottom surfaces. The first conductive layer is disposed on the top surface of the first dielectric layer. The electronic component is disposed on the top surface of the first dielectric layer. The second dielectric layer covers the bottom surface and a first portion of the lateral surface of the first dielectric layer and exposes a second portion of the lateral surface of the first dielectric layer. The second conductive layer is disposed on the bottom surface of the second dielectric layer and is electrically connected to the first conductive layer. The package body covers the electronic component, the top surface of the second dielectric layer, and the second portion of the lateral surface of the first dielectric layer.

[0005] In one or more embodiments, a semiconductor device package includes a first circuit layer, a second circuit layer, an electronic component, and a package body. The first circuit layer includes a first dielectric layer and a first conductive layer. The second circuit layer includes a second dielectric layer covering at least a portion of the first dielectric layer and a second conductive layer electrically connected to the first conductive layer. The electronic component is disposed on the first circuit layer. The package body covers the electronic component, the first circuit layer, and the second circuit layer. The first dielectric and the second dielectric satisfy the following inequality: 0 < |AB| ≦ 1 μm, where A is the maximum distance between the lateral surfaces of the first dielectric layer and the second dielectric layer, and B is the minimum distance between the lateral surfaces of the first dielectric layer and the second dielectric layer.

[0006] In one or more embodiments, a method for manufacturing a semiconductor device package includes: (a) providing a first carrier; (b) placing a photosensitive material on the first carrier; (c) exposing and developing the photosensitive material and removing a portion of the photosensitive material to form a first circuit layer, the first circuit layer defining a groove; (d) forming a dielectric layer on the first circuit layer and in the groove; (e) forming a second circuit layer on the dielectric layer and electrically connected to the first circuit layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that various features may not be drawn to scale and that the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A Cross-sectional views illustrating semiconductor device packages according to some embodiments of the present invention are shown.

[0009] Figure 1B Some embodiments of the present invention are described Figure 1A A top view of a semiconductor device package in FIG.

[0010] Figure 2A Cross-sectional views illustrating semiconductor device packages according to some embodiments of the present invention are shown.

[0011] Figure 2B Cross-sectional views illustrating semiconductor device packages according to some embodiments of the present invention are shown.

[0012] Figure 2C Cross-sectional views illustrating semiconductor device packages according to some embodiments of the present invention are shown.

[0013] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3G 、 Figure 3G '、 Figure 3G "、 Figure 3H and Figure 3I Methods of manufacturing semiconductor device packages according to some embodiments of the present invention are described.

[0014] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D and Figure 4E Methods of manufacturing semiconductor device packages according to some embodiments of the present invention are described.

[0015] Figure 5A Describing various types of semiconductor device packages according to some embodiments of the present invention; and

[0016] Figure 5B Various types of semiconductor device packages according to some embodiments of the present invention are described.

[0017] Throughout the drawings and detailed description, common reference numerals are used to refer to the same or similar elements.The present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0018] Figure 1A A cross-sectional view of a semiconductor device package 1 according to some embodiments of the present invention is illustrated. The semiconductor device package 1 includes dielectric layers 10 and 11, an electronic component 12, a package body 13, and electrical contacts 14.

[0019] The dielectric layer 10 has a surface 101 (also referred to as a "top surface"), a surface 102 opposite to the surface 101 (also referred to as a "bottom surface"), and a surface 103 extending between the surfaces 101 and 102 (also referred to as a "lateral surface"). One or more conductive layers 10r1 are disposed on the surface 101 of the dielectric layer 10. One or more conductive layers 10r2 are disposed on the surface 102 of the dielectric layer 10. In some embodiments, conductive vias 10v penetrate the dielectric layer 10 to provide electrical connections between the surfaces 101 and 102 of the dielectric layer 10. For example, the conductive vias 10v can electrically connect the conductive layers 10r1 to the conductive layers 10r2. In some embodiments, the conductive vias 10v taper from the surface 101 toward the surface 102 (or in a direction away from the electronic component 12). In some embodiments, conductive layer 10r1 includes a plurality of conductive traces, and the line spacing (L / S) of the conductive traces is equal to or less than 2 micrometers (μm) / 2 μm. In some embodiments, conductive layer 10r2 includes a plurality of conductive traces, and the L / S of the conductive traces is equal to or greater than 5 μm / 5 μm. In some embodiments, the thickness of dielectric layer 10 ranges from approximately 5 μm to approximately 10 μm. In some embodiments, dielectric layer 10, conductive layer 10r1, and conductive vias 10v may be collectively referred to as a circuit layer.

[0020] Dielectric layer 11 covers surface 102 of dielectric layer 10 and portions of surface 103 of dielectric layer 10. For example, dielectric layer 11 may cover a first portion of surface 103 of dielectric layer 10 and expose a second portion of surface 103 of dielectric layer 10. For example, surface 111 of dielectric layer 11 (also referred to as the "top surface") is not coplanar with surface 101 of dielectric layer 10. For example, surface 111 of dielectric layer 11 and surface 101 of dielectric layer 10 are discontinuous. One or more conductive layers 11r are disposed on surface 112 (also referred to as the "bottom surface") of dielectric layer 11. In some embodiments, conductive vias 11v penetrate dielectric layer 11 to electrically connect conductive layer 11r to conductive layer 10r2. In some embodiments, conductive vias 11v taper from surface 112 toward surface 111 (or in the direction of electronic component 12). In some embodiments, dielectric layer 11 has a thickness ranging from approximately 10 μm to approximately 30 μm. In some embodiments, the dielectric layer 11, the conductive layer 11r, and the conductive vias 11v may be collectively referred to as circuit layers. In some embodiments, the semiconductor device package 1 may include any number of circuit layers. For example, the semiconductor device package 1 may include N circuit layers, where N is an integer greater than 1.

[0021] In some embodiments, conductive layer 10r1, 10r2, or 11r is formed of or includes gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or a combination of two or more thereof. In some embodiments, dielectric layer 10 or dielectric layer 11 may include molding compound, pre-impregnated composite fiber (e.g., prepreg), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), glass, ceramic, any combination of two or more thereof, or the like. Examples of molding compound include, but are not limited to, epoxy resin (including fillers dispersed therein). Examples of prepreg material include, but are not limited to, a multilayer structure formed by stacking or laminating multiple prepreg materials / sheets. In some embodiments, dielectric layer 10 and dielectric layer 11 include the same material. Alternatively, dielectric layer 10 and dielectric layer 11 may comprise different materials. In some embodiments, dielectric layer 10 comprises a photosensitive material. In some embodiments, conductive layer 10r1 may be formed by photolithography.

[0022] Electronic component 12 is disposed on surface 101 of dielectric layer 10 and is electrically connected to a conductive layer (or conductive pad) 10r1 on surface 101 of dielectric layer 10 via conductive contacts 12c (e.g., microbumps). In some embodiments, a chip backside layer (not shown) may be disposed on backside surface 122. In some embodiments, the chip backside layer may comprise Cu, Ni, Ti, W, or Pt, other metals or alloys, or a combination of two or more thereof. In other embodiments, the chip backside layer may comprise PI, ABF, epoxy, CPD, or solder mask. Electronic component 12 may comprise a chip or die, including a semiconductor substrate, one or more integrated circuit devices, and / or one or more overlying interconnect structures disposed therein. The integrated circuit devices may comprise active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or a combination of two or more thereof. In some embodiments, any number of electronic components may be disposed on surface 101 of dielectric layer 10, depending on the design specifications.

[0023] The package body 13 is disposed on the dielectric layer 10 and the dielectric layer 11. The package body 13 covers the surface 101, the portion (e.g., the second portion) of the surface 103 of the dielectric layer 10 exposed from the dielectric layer 11, the surface 111 of the dielectric layer 11, and the electronic component 12. For example, the interface between the package body 13 and the dielectric layer 11 is located on or adjacent to the surface 103 of the dielectric layer 10, which will avoid cracking or delamination at the interface. In some embodiments, the surface 131 of the package body 13 is substantially coplanar with the backside surface 122 of the electronic component 12. For example, the backside surface 122 of the electronic component 12 is exposed from the package body 13. Alternatively, the package body 13 may cover the backside surface 122 of the electronic component 12. In some embodiments, the surface 133 of the package body 13 is substantially coplanar with the surface 113 of the dielectric layer 11. In some embodiments, package body 13 includes, for example, an organic material (e.g., molding compound, bismaleimide triazine (BT), PI, polybenzoxazole (PBO), solder resist, ABF, polypropylene (PP), epoxy-based materials, or a combination of two or more thereof), an inorganic material (e.g., silicon, glass, ceramic, quartz, or a combination of two or more thereof), a liquid film material, or a dry film material, or a combination of two or more thereof. In some embodiments, package body 13 may be a coating gel. In some embodiments, solder layer 13 has a thickness ranging from approximately 100 μm to approximately 350 μm.

[0024] Electrical contacts 14 are disposed on surface 112 of dielectric layer 11 and electrically connected to conductive layer 11r or conductive vias 11v. In some embodiments, electrical contacts 14 are controlled collapse chip connections (C4), ball grid arrays (BGAs), land grid arrays (LGAs), or bumps. In some embodiments, electrical contacts 14 can be used in fan-in structures, fan-out structures, or a combination of fan-in and fan-out structures. In some embodiments, the diameter of electrical contacts 14 ranges from approximately 0.2 millimeters (mm) to approximately 0.3 mm.

[0025] Figure 1B A top view of a semiconductor device package 1 according to some embodiments of the present invention is illustrated. In some embodiments, due to process limitations of photolithography, the lateral surface of dielectric layer 10 (e.g., surface 103) may not be parallel to the lateral surface of dielectric layer 11 (e.g., surface 113). For example, the distance between surface 103 of dielectric layer 10 and surface 113 of dielectric layer 11 may vary. In some embodiments, the distance between surface 103 of dielectric layer 10 and surface 113 of dielectric layer 11 satisfies the following inequality:

[0026] 0<|D11-D12|≦1μm,

[0027] Wherein D11 is the maximum distance between the surface 103 of the dielectric layer 10 and the surface 113 of the dielectric layer 11 , and D12 is the minimum distance between the surface 103 of the dielectric layer 10 and the surface 113 of the dielectric layer 11 .

[0028] In some existing processes for forming connection structures (e.g., fan-out structures) of semiconductor device packages, a circuit layer is placed on a carrier, with fine-pitch conductive traces (e.g., line spacing (L / S) equal to or less than 7 micrometers (μm) / 7 μm) on one side of the circuit layer (e.g., the chip side), and then coarse-pitch conductive traces are formed on the other side of the circuit layer (e.g., the ball side). However, due to the accuracy limitations of the bonder (or bonding machine), misalignment in the x-direction and / or y-direction will be greater than 2 μm, which will cause electrical problems (e.g., short circuits or opens) in the conductive traces, especially when the pitch of the conductive traces is scaled down (e.g., L / S equal to or less than 7 μm / 7 μm). According to Figure 1A and Figure 1B In the embodiment, since the conductive traces (eg, conductive layer 10r1) are formed by photolithography, the maximum misalignment in the x-direction and / or the y-direction is equal to or less than 1 μm, which facilitates the formation of the conductive traces with a large pitch.

[0029] Figure 2A A cross-sectional view illustrating a semiconductor device package 2A according to some embodiments of the present invention. The semiconductor device package 2A is similar to Figure 1A The semiconductor device package 1 in FIG. 2A further includes an underfill material 23 between the electronic component 12 and the dielectric layers 10 and 11. In some embodiments, the underfill material 23 includes an epoxy resin, a molding compound (e.g., epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material containing silicone dispersed therein, or a combination of two or more thereof. In some embodiments, depending on the specifications of different embodiments, the underfill material 23 may be a capillary underfill (CUF), a molded underfill (MUF), or an applied gel.

[0030] Figure 2B A cross-sectional view illustrating a semiconductor device package 2B according to some embodiments of the present invention. The semiconductor device package 2B is similar to Figure 1A The semiconductor device package 1, except in Figure 2B , backside surface 122 of electronic component 12 is attached to dielectric layer 10 by adhesive layer 12h (eg, glue or tape), while adhesive surface 12h of electronic component 12 is electrically connected to conductive traces or conductive vias 10v by bonding wires 12w.

[0031] Figure 2BA cross-sectional view illustrating a semiconductor device package 2C according to some embodiments of the present invention. The semiconductor device package 2C is similar to Figure 1A 1 , except that semiconductor device package 2C further includes an electronic component 22 disposed on surface 112 of dielectric layer 11 and electrically connected to the conductive traces on the surface of dielectric layer 11. In some embodiments, semiconductor device package 2C may further include an underfill 22u between electronic component 22 and dielectric layer 11.

[0032] Figure 4E The cross-sectional view of a plurality of semiconductor device packages including a semiconductor device package 4 according to some embodiments of the present invention is illustrated. The semiconductor device package 4 includes a circuit layer 40, an electronic component 42, and a package body 43.

[0033] Circuit layer 40 may include conductive layers 40r1, 40r2, and 41r for providing electrical connections, and dielectric layers 40d and 41d covering portions of conductive layers 40r1, 40r2, and 41r. In some embodiments, dielectric layer 40d and / or dielectric layer 41d include a photosensitive material. In some embodiments, top surface 40d1 of dielectric layer 40d is lower than top surface 41d1 of dielectric layer 41d. For example, top surface 40d1 of dielectric layer 40d is recessed into top surface 41d1 of dielectric layer 41d.

[0034] Electronic component 42 is disposed on circuit layer 40 and contacts the portion of conductive layer 40r1 exposed from dielectric layer 40d. For example, electronic component 42 is disposed within a recess defined by dielectric layers 40d and 41d. Package body 43 is disposed on dielectric layers 40d and 41d to cover conductive layer 40r1 and electronic component 42.

[0035] Figure 3A 、 3B 3C, 3D, 3E, 3F, 3G, 3H, and 3I are cross-sectional views of semiconductor structures fabricated at various stages according to some embodiments of the present invention. The various figures have been simplified to better understand aspects of the present invention.

[0036] refer to Figure 3AA carrier 39 is provided and an adhesive layer (or isolation film) 39h is disposed on the carrier 39. A plurality of separate seed layers 30s and metal layers 30m are then formed on the adhesive layer 39h. In some embodiments, the seed layer 30s and metal layer 30m can be formed by the following operations: (i) disposing the seed layer and the metal layer on the adhesive layer 39h by, for example, physical vapor deposition (PVD); (ii) disposing a photoresist (e.g., a mask) on the metal layer by, for example, a coating process; and (iii) performing exposure, development, and etching processes to separate the seed layer and the metal layer into several separate seed layers 30s and metal layers 30m. In some embodiments, the metal layer 30m and the seed layer 30s may include Ti, Cu, or an alloy. A dielectric layer 30 (or passivation layer) is then disposed on the metal layer 30m by, for example, a coating process. In some embodiments, the dielectric layer 30 may have properties that are the same as or similar to those of the dielectric layer 10 in FIG. 1 .

[0037] refer to Figure 3B , a conductive layer 30r1 is formed on the dielectric layer 30, and conductive vias 30v are formed to pass through the dielectric layer 30 to electrically connect to the metal layer 30m. In some embodiments, the patterned conductive layer 30r1 and the conductive vias 30v can be formed by a photolithography process. For example, the patterned conductive layer 30r1 and the conductive vias 30v can be formed by the following operations: (i) performing a development process to form one or more openings on the dielectric layer 30; (ii) forming a metal layer (or multiple metal layers) on the dielectric layer 30 and within the openings by, for example, PVD; (iii) disposing a photoresist (e.g., a mask) on the metal layer by, for example, coating; and (iv) performing exposure, development, and etching processes to form multiple openings in the photoresist to expose portions of the metal layer; (v) filling the openings with metal by, for example, electroplating; and (vi) removing the photoresist. In some embodiments, portions of the dielectric layer 30 can be removed to form the plurality of interconnect structures 300.

[0038] refer to Figure 3C, carrier 39 and adhesive layer 39h are removed from interconnect structure 300. Then, interconnect structure 300 is attached to another carrier 39' having adhesive layer 39h' thereon. In some embodiments, adhesive layer 39h' is formed of or includes a soft adhesive material (e.g., glue), and conductive layer 30r1 may be immersed in adhesive layer 39h'. For example, conductive layer 30r1 is embedded within adhesive layer 39h'. For example, conductive layer 30r1 may be substantially coplanar with surface 391 of carrier 39'. In some embodiments, adhesive layer 39h' is disposed within the gap between two adjacent interconnect structures 300. In other embodiments, adhesive layer 39h' may include a hard adhesive material, and conductive layer 30r1 may be substantially coplanar with the surface of adhesive layer 39h'. In this embodiment, photoresist may be disposed within the gap between two adjacent interconnect structures 300.

[0039] refer to Figure 3D , a conductive layer 30r2 is formed on the surface 302 of the dielectric layer 30. In some embodiments, the conductive layer 30r2 is electrically connected to the conductive via 30v. The dielectric layer 31 is disposed on the dielectric layer 30 to cover the conductive layer 30r2 by, for example, lamination. In some embodiments, the dielectric layer 31 is also disposed between the gaps between two adjacent interconnect structures 300 and in contact with the adhesive layer 39h'. In some embodiments, the dielectric layer 31 may have a Figure 1A The conductive layer 30r2 may have the same or similar properties as the dielectric layer 11 in the conductive layer 30r2. In some embodiments, the conductive layer 30r2 may be formed by: (i) removing the seed layer 30s by, for example, an etching process to expose the metal layer 30m; (ii) disposing a photoresist (e.g., a mask) on the metal layer 30m by, for example, coating; and (iv) performing an exposure, development, and etching process to form a plurality of openings in the photoresist to expose portions of the metal layer 30m; (v) removing the exposed portions of the metal layer 30m by, for example, an etching process; and (vi) removing the photoresist.

[0040] refer to Figure 3E One or more openings 31h are formed through dielectric layer 31 to expose portions of conductive layer 30r2 via a photolithography process. A seed layer 31s and a metal layer 31m are formed on dielectric layer 31 and extend within openings 31h to electrically connect to conductive layer 30r2. In some embodiments, seed layer 31s and metal layer 31m may be formed by PVD.

[0041] Referring to FIG. 3 , a photoresist 31PR is placed on the metal layer 31m. One or more openings are formed in the photoresist 31PR to expose portions of the metal layer 31m through, for example, exposure, development, and etching processes. The openings are then filled with solder 34′. In some embodiments, the solder 34′ may be formed by electroplating.

[0042] refer to Figure 3G , the carrier 39' and the adhesive layer 39h' are removed to expose the conductive layer 30r1 and the conductive vias 30v. The photoresist 31PR and the solder 34' are attached to the carrier 39" having the adhesive layer 39h".

[0043] In some embodiments, such as Figure 3G 'shown in Figure 3F After the operation in FIG. 3 , the carrier 39′ and the adhesive layer 39h′ are removed to expose the conductive layer 30r1 and the conductive via 30v. Then, the photoresist 31PR and the metal layer 31m and the seed layer 31s covered by the photoresist 31PR are also removed. In some embodiments, the solder 34′ may be removed, such as in FIG. Figure 3G " is shown in.

[0044] refer to Figure 3H ,exist Figure 3G After the operations in FIG. 3 , electronic component 32 is bonded to conductive layer 30r1. Package body 33 is formed on dielectric layers 30 and 31 to cover conductive layer 30r1, conductive vias 30v, and electronic component 32. In some embodiments, package body 33 can be formed using a MUF process. Carrier 39″ and adhesive layer 39H″ are then removed to expose photoresist 31PR and solder 34′.

[0045] refer to Figure 3I , singulation may be performed to separate the individual semiconductor device packages comprising the semiconductor device package 3. That is, singulation may be performed through the package body 33 and the dielectric layer 31. For example, singulation may be performed by using a dicing saw, a laser, or other suitable cutting techniques. In some embodiments, the semiconductor device package 3 is similar to Figure 1A A semiconductor device package 1 is provided.

[0046] Figure 4A 、 4B 4C, 4D and 4E are cross-sectional views of semiconductor structures fabricated at various stages according to some embodiments of the present invention. The various figures have been simplified to better understand aspects of the present invention.

[0047] refer to Figure 4A A carrier 49 is provided, which has an adhesive layer 49h thereon. A circuit layer 40 is formed on the adhesive layer 49h by a photolithography process. The circuit layer 40 includes a seed layer 40s, a conductive layer 40r1, and a dielectric layer 40d (or passivation layer) covering the seed layer 40s and the conductive layer 40r. In some embodiments, the dielectric layer 40d includes a photosensitive material.

[0048] refer to Figure 4BFor example, a plurality of openings 40h1 and 40h2 are formed on the dielectric layer 40d by a photolithography process (eg, exposure, development, etching, etc.). In some embodiments, the opening 40h1 is formed to expose a portion of the conductive layer 40r1 and the opening 40h2 is formed to expose a portion of the conductive layer 40r1. Figure 4A The circuit layer 40' shown in FIG is divided into a plurality of circuit layers 40. Figure 4B As shown in FIG, there is a gap between two adjacent circuit layers 40.

[0049] refer to Figure 4C A conductive layer 40r2 is formed on the circuit layer 40 and within the opening 40h1 to be electrically connected to the conductive layer 40r1. A dielectric layer (or passivation layer) 41d is formed on the adhesive layer 49h to cover the circuit layer 40 and the conductive layer 40r2. One or more openings are formed in the dielectric layer 41d to expose portions of the conductive layer 40r2, and then a conductive layer 41r is formed on the dielectric layer 41d and within the openings to be electrically connected to the conductive layer 40r2.

[0050] refer to Figure 4D , so that the dielectric layer 41d and the conductive layer 41r are attached to the carrier 49' having the adhesive layer 49h' thereon. The carrier 49 and the adhesive layer 49h are removed from the circuit layer 40. The seed layer 40s is then removed to expose the conductive layer 40r1. Figure 4D As shown in FIG. , conductive layer 40r1 is substantially coplanar with surface 40d1 of dielectric layer 40d. In some embodiments, surface 40d1 of dielectric layer 40d is recessed from dielectric layer 40d. For example, surface 40d1 of dielectric layer 40d is lower than surface 41d1 of dielectric layer 41d.

[0051] refer to Figure 4E , electronic component 42 is bonded to conductive layer 40r1. Package body 43 is formed on dielectric layers 40d and 41d to cover conductive layer 40r1 and electronic component 42. Carrier 49' and adhesive layer 49h' are then removed. Singulation can be performed to separate the individual semiconductor device packages comprising semiconductor device package 4. That is, singulation is performed through package body 43 and dielectric layer 41d. For example, singulation can be performed using a dicing saw, laser, or other suitable cutting technique.

[0052] Figure 5A and 5B Different types of semiconductor device packages according to some embodiments of the present invention are described.

[0053] As in Figure 5A , a plurality of chips 50 and / or dies are disposed on a square carrier 51. In some embodiments, at least one of the chips 50 may include a semiconductor device package 1, 2A, 2B, 2C, or 4, as shown in FIG. Figure 1A 、 2A , 2B, 2C, or 4E. In some embodiments, the carrier 51 may include an organic material (e.g., molding compound, BT, PI, PBO, solder resist, ABF, PP, epoxy-based material, or a combination of two or more thereof) or an inorganic material (e.g., silicon, glass, ceramic, quartz, or a combination of two or more thereof).

[0054] As in Figure 5B , a plurality of chips 50 and / or dies are disposed on a circular carrier 52. In some embodiments, at least one of the chips 50 may include a semiconductor device package 1, 2A, 2B, 2C, or 4, as shown in FIG. Figure 1A 、 2A , 2B, 2C, or 4E. In some embodiments, carrier 52 may include an organic material (e.g., molding compound, BT, PI, PBO, solder resist, ABF, PP, epoxy-based material, or a combination of two or more thereof) or an inorganic material (e.g., silicon, glass, ceramic, quartz, or a combination of two or more thereof).

[0055] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms may refer to instances in which the event or circumstance occurred exactly as well as instances in which the event or circumstance occurred approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the mean of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the values ​​may be considered to be "substantially" or "approximately" the same. For example, "substantially" parallel may refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, "substantially" perpendicular may refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0056] Two surfaces may be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

[0057] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to transmit an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, a conductive material is one having a conductivity greater than about 10 4 S / m conductivity of the material, for example at least 10 5 S / m or at least 10 6 S / m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

[0058] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly indicates otherwise. In the description of some embodiments, providing that a component is "on" or "over" another component may encompass situations where the latter component is directly on (e.g., physically contacting) the former component, as well as situations where one or more intervening components may be located between the former and latter components.

[0059] Although the present invention has been described and illustrated with reference to specific embodiments of the present invention, these descriptions and illustrations do not limit the present invention. It will be clearly understood by those skilled in the art that various changes may be made and equivalent components may be substituted within the embodiments without departing from the true spirit and scope of the present invention as defined by the accompanying claims. The descriptions may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the exquisite presentation of the present invention and the actual device. There may be other embodiments of the present invention that are not specifically described. The description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the purpose, spirit and scope of the present invention. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it will be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present invention. Therefore, unless otherwise specified herein, the order and grouping of operations are not limitations of the present invention.

Claims

1. A semiconductor device package, comprising: a first dielectric layer having a top surface, a bottom surface opposite the top surface, and lateral surfaces extending between the top surface and the bottom surface; a first conductive layer disposed on the top surface of the first dielectric layer; an electronic component disposed on the top surface of the first dielectric layer; a second dielectric layer covering the bottom surface and a first portion of the lateral surface of the first dielectric layer and exposing a second portion of the lateral surface of the first dielectric layer; a second conductive layer disposed on a bottom surface of the second dielectric layer and electrically connected to the first conductive layer; and A package body covers the electronic component, a top surface of the second dielectric layer, and the second portion of the lateral surface of the first dielectric layer. 2 . The semiconductor device package of claim 1 , wherein the top surface of the first dielectric layer is discontinuous with the top surface of the second dielectric layer. 3 . The semiconductor device package according to claim 1 , wherein the first conductive layer comprises a plurality of conductive traces and a line pitch L / S of the conductive traces is equal to or less than 2 μm / 2 μm. The semiconductor device package of claim 1 , wherein the first dielectric layer comprises a photosensitive material. 5 . The semiconductor device package of claim 1 , further comprising a third conductive layer disposed on the bottom surface of the first dielectric layer.

6. The semiconductor device package according to claim 5, further comprising: a first conductive via electrically connecting the first conductive layer to the third conductive layer; and a second conductive via electrically connecting the second conductive layer to the third conductive layer. 7 . The semiconductor device package according to claim 6 , wherein the first conductive via is tapered in a direction away from the electronic component, and the second conductive via is tapered in a direction toward the electronic component.

8. The semiconductor device package according to claim 1, wherein The second dielectric layer has a lateral surface; a distance between the lateral surface of the first dielectric layer and the lateral surface of the second dielectric layer varies; and A difference between a maximum distance from the lateral surface of the first dielectric layer to the lateral surface of the second dielectric layer and a minimum distance from the lateral surface of the first dielectric layer to the lateral surface of the second dielectric layer is less than or equal to 1 μm.

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