A residual pressure locking method and circuit for dual-path verification

Abstract

The present invention belongs to the field of power line fault protection, and in particular, relates to a residual voltage locking method and circuit with dual-path verification. A dual-path verification residual voltage locking circuit includes a PT, a feeder terminal, a feeder switch and a residual voltage circuit. The feeder terminal is installed on a 10kV line and has a built-in current transformer; a PT is installed on the power supply side and the load side of the feeder switch; the feeder terminal is connected to the feeder switch and the PT through an aviation plug cable interface; the residual voltage circuit is built into the feeder terminal, and each feeder terminal is configured with 2 residual voltage circuits; the feeder terminal collects the voltage signal of the PT, the current signal of the current transformer, and the residual voltage signal of the residual voltage circuit; the feeder terminal issues instructions. 1. This patent adopts a dual-path verification residual voltage locking circuit to ensure that the feeder terminal can correctly detect the residual voltage and ensure the isolation of the fault area. 2. The circuit is simple and reliable, and the cost is low.

Description

Technical Field

[0001] The invention belongs to the field of power line fault protection, and in particular relates to a residual pressure locking method and circuit for dual-path verification. Background Art

[0002] When a short circuit occurs in a line and the fault isolation is completed, the residual voltage is detected by the residual voltage circuit module. However, line overvoltage, device aging, etc. may cause the residual voltage module to erroneously detect the residual voltage. In the above fault, if the residual voltage is detected incorrectly, the circuit breaker will be locked incorrectly, causing all downstream lines to lose power, expanding the fault isolation area. Summary of the invention

[0003] In view of the above-mentioned deficiencies of the prior art, the present invention designs a circuit, which configures two residual pressure modules for mutual verification at the feeder terminal, identifies the residual pressure more accurately and reliably, and outputs a locking signal. After the terminal is powered on, the residual pressure locking signal and the voltage signal are detected. If there is no reset, the circuit is locked and closed to isolate the fault area. The specific technical scheme is as follows:

[0004] A residual voltage locking circuit for dual-path verification comprises a PT, a feeder terminal, a feeder switch and a residual voltage circuit, wherein the feeder terminal is installed on a 10kV line and has a built-in current transformer; a PT is installed on the power supply side and the load side of the feeder switch respectively; the feeder terminal is connected to the feeder switch and the PT through an aviation plug cable interface; the residual voltage circuit is built into the feeder terminal, and each feeder terminal is configured with two residual voltage circuits; the feeder terminal collects the voltage signal of the PT, the current signal of the current transformer, and the residual voltage signal of the residual voltage circuit; and the feeder terminal issues an instruction.

[0005] Based on this structure, the feeder terminal collects signals from the PT, power transformer and two residual voltage locking circuits, and controls the feeder switch. Under normal conditions, the pin state collected by the first residual voltage circuit is high level, and the pin state collected by the second residual voltage circuit is low level.

[0006] Furthermore, in the two residual voltage circuits, the locking signal input terminal of the first residual voltage circuit is connected to the power converted by the transformer built into the primary PT and the feeder terminal, and the locking signal output terminal is grounded; the locking signal input terminal of the second residual voltage circuit is grounded, and the locking signal input terminal is connected to the power converted by the transformer built into the primary PT and the feeder terminal. The locking signal output circuits of the two residual voltage circuits are wired in opposite ways, so that the levels of the two residual voltage circuits can be ensured to be one high and one low.

[0007] Furthermore, the feeder terminal is connected to the two residual voltage circuits through different I / O interfaces.

[0008] Furthermore, the feeder terminal collects the pin states of the two residual voltage circuits through different I / O interfaces.

[0009] A residual voltage locking method for dual-path verification, wherein a feeder terminal collects the pin states of two residual voltage circuits, a voltage signal of a PT and a current signal of a current transformer, wherein the current signal includes a power supply direction, and performs the following judgment: the pin states of a first residual voltage circuit and a second residual voltage circuit are low level and high level respectively, and the power supply direction collected by the current transformer is opposite to the original power supply direction, and the feeder terminal sends a locking signal to a feeder switch, thereby ensuring that the feeder terminal accurately detects the residual voltage through the two residual voltage circuits and realizes locking.

[0010] Furthermore, the startup logic of each residual voltage circuit acquisition pin state is:

[0011] Voltage ≥30%Un, duration ≥80ms, that is, the locking circuit does not start when the voltage is normal, and starts when the voltage is unstable, ensuring the stability and life of the residual voltage circuit.

[0012] Furthermore, the pin status of each residual voltage circuit and the power supply direction of the current transformer are collected, and the following judgment is made;

[0013] The pin states of the first residual voltage circuit and the second residual voltage circuit are not high level and low level respectively. At the same time, the pin states of the first residual voltage circuit and the second residual voltage circuit are not low level and high level respectively and the power supply direction is opposite to the original power supply direction. The feeder terminal outputs a residual voltage circuit fault alarm.

[0014] Beneficial effects of the present invention:

[0015] 1. This patent adopts a residual voltage locking circuit with dual-path verification to ensure that the feeder terminal can correctly detect the residual voltage and ensure the isolation of the fault area.

[0016] 2. The circuit is simple, reliable and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of a residual voltage locking circuit for dual-path verification of the present invention;

[0018] Figure 2 It is a locking flow chart of a residual pressure locking method for dual-path verification of the present invention;

[0019] Figure 3 The invention discloses an original circuit diagram of a locking circuit of a residual pressure locking method for dual-path verification. DETAILED DESCRIPTION

[0020] The present invention is described in detail below with reference to the accompanying drawings and attached tables:

[0021] A residual voltage locking circuit for dual-path verification comprises a PT, a feeder terminal, a feeder switch and a residual voltage circuit. The feeder terminal is installed on a 10kV line and has a built-in current transformer. A PT is installed on the power supply side and the load side of the feeder switch. The 10kV line voltage is converted into a 220V low voltage by the primary PT and then converted into a 24V DC voltage by a built-in power storage module in the terminal and connected to the feeder terminal power supply. The feeder terminal is connected to the feeder switch and the PT through an aviation plug cable interface. The residual voltage circuit is built into the feeder terminal, and each feeder terminal is configured with two residual voltage circuits. The feeder terminal collects the voltage signal of the PT, the current signal of the current transformer, and the residual voltage signal of the residual voltage circuit. The feeder terminal issues instructions. Each feeder switch in the line is equipped with two residual voltage circuits, and each residual voltage circuit is connected in parallel on both sides of the feeder switch. The feeder terminal collects the pin status of the two residual voltage circuits through different I / O interfaces; in the two residual voltage circuits, the locking signal input terminal of the first residual voltage circuit is connected to the 25V AC voltage converted by the primary PT and the built-in transformer of the feeder terminal; the locking signal output terminal is grounded; the locking signal input terminal of the second residual voltage circuit is grounded, and the locking signal input terminal is connected to the 25V AC voltage converted by the primary PT and the built-in transformer of the feeder terminal; the locking signal output circuits of the two residual voltage circuits are wired in opposite ways, so that the levels of the two residual voltage circuits can be guaranteed to be one high and one low; at the same time, when the line is in normal state, the pin status of the first residual voltage circuit is high level, and the pin status of the second residual voltage circuit is low level. Figure 3 As shown, interface 6 in the first residual voltage circuit is connected to the power supply, interface 8 is grounded, interface 6 in the second residual voltage circuit is grounded, and interface 8 is connected to the power supply; the feeder terminal is connected to the feeder terminal through different I / O interfaces, and the feeder terminal collects the pin states CYJC_JD1 and CYJC_JD2 of the two residual voltage circuits through the I / O interface.

[0022] like Figure 2 A residual pressure locking method for dual-path verification is shown, and Figure 3 The schematic diagram of the locking circuit shown in the figure has the following specific process:

[0023] (1) Under normal conditions, the first latch circuit pin CYJC_JD1 is at a high level, the second latch circuit pin CYJC_JD2 is at a low level, and the two latch circuits are not enabled;

[0024] (2) When the residual voltage parameter voltage detected by the PT signal collected by the feeder terminal is ≥30%Un and the duration is ≥80ms, the two residual voltage circuits are started, and the residual voltage can be detected on both sides at the same time; that is, after a fault occurs, the feeder switch on the power supply side adjacent to the fault point trips, and the feeder switch on the load side of the fault point loses pressure and opens. The residual voltage circuit is enabled when the above conditions are met;

[0025] (3) When the feeder switch on the power supply side near the fault point is reclosed, the first path: through transformer J2 and rectifier REC1, it is set to DC. Capacitor C3 is charged through resistors R2 and R3 in parallel, and the capacitor voltage rises slowly; at the same time, the base of transistor Q1 begins to conduct after passing through resistor R1 and voltage regulator Z3, and the collector and emitter of Q1 are turned on. The voltage is directly applied to the coil of K2 magnetic latching relay, and 3 and 4 of magnetic latching relay K2 are turned on and maintained. (Normally K2 and K3 are not turned on)

[0026] The voltage of capacitor C3 slowly increases from 0V to the maximum voltage. At this time, the collector and emitter of transistor Q2 are turned on, so that the collector voltage of Q2 is approximately pulled to 0V, the transistor Q1 is turned off, and the coil voltage of magnetic latching relay K2 is released. Only then can the K2 reset operation be executed.

[0027] Similarly, in the second circuit, 3 and 4 of the magnetic latching relay K3 are turned on and maintained. After the voltage of C6 rises to the maximum voltage, the voltage of the magnetic latching K3 coil is released, and only then can the K2 reset operation be performed.

[0028] When the power supply is normal, since 3 and 4 of K2 and K3 are turned on, CYJC_JD1 is at a low level and CYJC_JD2 is at a high level, and the power supply direction is opposite to this, it is judged as residual pressure, and the feeder terminal sends a locking signal to the feeder switch. The feeder switch enables the locking logic and pulls CYFG_DY and CYFG_FH high at the same time, so that 3 and 4 of K2 and K3 are disconnected and maintained, returning to the initial state.

[0029] (3) The feeder terminal checks the status of the two circuit pins. If the pin status is not in the normal state (the pin status of the first residual voltage circuit is high level and the pin status of the second residual voltage circuit is low level) and the fault lockout state (the pin status of the first residual voltage circuit and the second residual voltage circuit are low level and high level respectively and the power supply direction collected by the current transformer is opposite to the original power supply direction), the residual voltage module fault alarm is output.

[0030] Although the specific embodiments of the present invention have been described and illustrated in detail above, it should be noted that various changes and modifications may be made to the above embodiments without departing from the spirit of the present invention and the scope of the appended claims.

Claims

1. A residual voltage locking circuit for dual-path verification, characterized in that: It includes PT, feeder terminal, feeder switch and residual voltage circuit. The feeder terminal is installed on the 10kV line and has a built-in current transformer. A PT is installed on the power supply side and the load side of the feeder switch. The feeder terminal is connected to the feeder switch and PT through the aviation plug cable interface. The residual voltage circuit is built into the feeder terminal, and each feeder terminal is equipped with 2 residual voltage circuits. The feeder terminal collects the voltage signal of the PT, the current signal of the current transformer, and the residual voltage signal of the residual voltage circuit. The feeder terminal issues instructions. The feeder terminal collects the pin status of the two residual voltage circuits, the voltage signal of the PT and the current signal of the current transformer, the current signal includes the power supply direction, and makes the following judgments: The pin states of the first residual voltage circuit and the second residual voltage circuit are low level and high level respectively, and the power supply direction collected by the current transformer is opposite to the original power supply direction, and the feeder terminal sends a locking signal to the feeder switch.

2. A residual voltage locking circuit for dual-path verification according to claim 1, characterized in that: In the two residual voltage circuits, the locking signal input terminal of the first residual voltage circuit is connected to the power converted by the transformer built into the primary PT and the feeder terminal, and the locking signal output terminal is grounded; the locking signal input terminal of the second residual voltage circuit is grounded, and the locking signal input terminal is connected to the power converted by the transformer built into the primary PT and the feeder terminal.

3. A residual voltage locking circuit for dual-path verification according to claim 1, characterized in that: The feeder terminal is connected to two residual voltage circuits via different I / O interfaces.

4. A residual voltage locking circuit for dual-path verification according to claim 3, characterized in that: The feeder terminal collects the pin states of the two residual voltage circuits through different I / O interfaces.

5. A residual voltage locking circuit for dual-path verification according to claim 4, characterized in that: The startup logic of each residual voltage circuit is: Voltage ≥ 30% Un, at the same time, duration ≥ 80ms.

6. A residual voltage locking circuit for dual-path verification according to claim 5, characterized in that: The feeder terminal also makes the following determinations: The pin states of the first residual voltage circuit and the second residual voltage circuit are not high level and low level respectively. At the same time, the pin states of the first residual voltage circuit and the second residual voltage circuit are not low level and high level respectively and the power supply direction is opposite to the original power supply direction. The feeder terminal outputs a residual voltage circuit fault alarm.

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