A bidirectional ESD protection device

Abstract

A bidirectional ESD protection device, which is a chip composed of an N+ substrate layer 101, a P-type epitaxial layer 102, and an N+ doped layer 103; the P-type epitaxial layer 102 is disposed above the N+ substrate layer 101, and the N+ doped layer 103 is disposed above the P-type epitaxial layer 102; deep isolation trenches 104 are located on the left and right sides of the chip, and a doped polycrystalline floating island 108 is disposed in the deep isolation trench 104 close to the central region of the chip, an isolation dielectric layer 105 is interposed between the deep isolation trench 104 and the front electrode 106, the front electrode 106 is located above the N+ doped layer 103 and the isolation dielectric layer 105, and a back electrode 107 is formed under the N+ substrate layer 101. The present invention is directed to ESD protection for ordinary capacitors and applications with high current discharge capacity, and adopts a vertical triode structure with trench isolation, solving the problem of electrostatic discharge in integrated circuits.

Description

Technical Field

[0001] The present invention belongs to the field of electronic science and technology, mainly relates to the field of integrated circuit electrostatic discharge (ESD - Electrostatic Discharge) protection, and specifically relates to a bidirectional ESD protection device. Background Art

[0002] The electrostatic discharge (ESD) phenomenon widely exists in the daily environment. It is a fatal threat to precision integrated circuits and is one of the important reasons for damage or even failure of integrated circuit products. Integrated circuit products are extremely vulnerable to ESD during their production, manufacturing, assembly, and operation processes, resulting in internal damage to the products and reduced reliability. And their application environments also have corresponding requirements for parameters such as capacitance, breakdown voltage, and clamping characteristics.

[0003] For different applications, the system has different parameter requirements for ESD protection devices. According to different working voltages, the corresponding ESD protection levels are also divided into voltage levels such as 3V, 5V, 7V, 12V, 24V, 36V, etc. Different requirements for capacitance are also imposed according to the speed of data transmission. For direct current transmission or low - speed data transmission, ordinary capacitor series ESD protection devices can be used to reduce costs. During the manufacturing process of ESD devices, it is extremely important to improve the breakdown voltage stability and reliability of the devices from the device structure aspect to improve the yield of the final protection device products. Summary of the Invention

[0004] What the present invention solves is the problems of uneven chip stress, voltage consistency, etc. encountered by ordinary capacitor bidirectional protection devices using trench isolation. Without affecting the electrical characteristic parameters, a bidirectional ESD protection device is proposed to improve the voltage consistency of the bidirectional ESD protection device and improve the reliability of the device from the device structure aspect.

[0005] The technical solution adopted by the present invention is a bidirectional ESD protection device, which is a chip composed of an N + substrate layer, a P - type epitaxial layer, and an N + doped layer; the P - type epitaxial layer is provided above the N + substrate layer, and the N + doped layer is provided above the P - type epitaxial layer; deep isolation trenches are located around the chip, and doped polycrystalline floating islands are provided in the deep isolation trenches close to the central area of the chip. An isolation dielectric layer is between the deep isolation trenches and the front electrode, and the front electrode is located above the N + doped layer and the isolation dielectric layer, and the back electrode is formed under the N + substrate layer.

[0006] Furthermore, there are multiple polycrystalline floating islands, which are arranged longitudinally along the deep isolation trenches and have different charge types. Among them, the polycrystalline floating islands on both sides of the N + doped layer and the N + substrate carry negative charges, and the polycrystalline floating islands on both sides of the P - type epitaxial layer carry positive charges.

[0007] Further, the charge density of the deep isolation trench can also show a gradual change, specifically manifested as the charge density of the floating islands far from the PN junction boundary decreasing in sequence.

[0008] Further, as a bidirectional protection device, the front electrode and the back electrode do not distinguish between the anode and the cathode.

[0009] Further, the N+ substrate layer and the P-type epitaxial layer form a back PN junction;

[0010] Further, by adjusting the resistivity and the final effective thickness of the P-type epitaxial layer, electrical characteristics such as the final breakdown voltage and the amplification factor of the NPN transistor are adjusted.

[0011] Further, the P-type epitaxial layer and the N+ doped layer form a front PN junction;

[0012] Further, the deep isolation trench penetrates through the entire N+ doped layer to the N+ substrate layer. The opening of the deep isolation trench is 1 um, and 2 to 5 groups of deep isolation trenches are arranged in parallel. The etching depth is 10 to 20 um; an interleaved interconnection method is adopted between the deep isolation trenches, effectively reducing the problem of excessive stress caused by independent isolation trenches and improving the reliability of the device.

[0013] Further, the front electrode is a metal layer deposited on the surface of the isolation dielectric layer and the N+ doped layer.

[0014] Further, the back electrode is a metal layer deposited on the surface of the N+ substrate layer.

[0015] The present invention aims at ESD protection for applications of ordinary capacitors and high-current discharge capabilities, adopts a vertical triode structure with trench isolation, maximally improves the voltage consistency of the device, and has high reliability.

[0016] In the deep isolation trench of the present invention, multiple charged polycrystalline floating islands are provided. The positively charged floating islands induce negative charges on the surface of the P-type epitaxial layer, and the negatively charged floating islands induce positive charges on the surfaces of the N+ doped layer and the N+ substrate region, thereby adjusting the charge distribution at the edge of the PN junction in the trench, reducing the electric field strength at the trench boundary, keeping the breakdown point of the device at the planar junction of the PN junction, reducing the trench edge failure rate of the ESD device, and improving the voltage consistency and reliability of the device.

[0017] The multi-column interleaved interconnected deep isolation trenches of the present invention effectively release the trench stress, reduce the overall stress of the chip, and improve the reliability of the device.

[0018] The two-way ESD protection device of the present invention solves the problem of electrostatic discharge in integrated circuits, and its front and back electrodes do not distinguish between the anode and the cathode. One end is connected to the signal transmission line of the integrated circuit, and the other end is grounded. When an electrostatic pulse is generated at one end, it conducts and discharges through the longitudinal triode structure formed by the combination of the N+ substrate layer, the P-type epitaxial layer, and the N+ doping layer in the device. The breakdown voltage of its longitudinal triode is the avalanche breakdown voltage BVceo of the collector-base junction of the triode in its common-emitter configuration. After the triode breaks down, its electrostatic charge is released to the ground after being conducted by the triode, playing a role in electrostatic protection for the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a sectional structure diagram of the present invention.

[0020] Figure 2 It is a top view of the present invention.

[0021] Figure 3 It is a layout schematic diagram of the deep isolation trench of the present invention.

[0022] Figure 4 It is an implementation case of the unidirectional protection device of the present invention.

[0023] Figure 5 It is an implementation case of the SCR structure of the present invention.

[0024] In the figure, 101. N+ substrate layer, 102. P-type epitaxial layer, 103. N+ doping layer, 104. Deep isolation trench, 105. Dielectric isolation layer, 106. Front electrode, 107. Back electrode, 108. Polycrystalline floating island, 109. P+ short-circuit region, 110. P-type layer. DETAILED DESCRIPTION OF THE INVENTION

[0025] The following further describes the present invention in detail in conjunction with the drawings and embodiments.

[0026] The technical solutions described in the present invention are only a part of the embodiments of the present invention. Other embodiments related to achieving the purpose of voltage controllability of the triode by adding a charge control region in the isolation trench of the longitudinal triode based on the present invention all fall within the protection scope of the present invention.

[0027] Such as Figure 1As shown in the figure, a bidirectional ESD protection device has a structure including an N+ substrate layer 101, a P-type epitaxial layer 102 located above the N+ substrate layer 101, and an N+ doped layer 103 located above the P-type epitaxial layer 102. The N+ substrate layer 101, the P-type epitaxial layer 102, and the N+ doped layer 103 combine to form a vertical triode structure. Deep isolation trenches 104 are located around the chip, and doped polycrystalline floating islands 108 are provided in the deep isolation trenches 104 close to the central area of the chip. An isolation dielectric layer 105 is located above the N+ doped layer 103, between the deep isolation trenches 104 and the front electrode 106. The front electrode 106 is located above the N+ doped layer 103 and the isolation dielectric layer 105, and a back electrode 107 is provided on the back of the chip.

[0028] Multiple charged polycrystalline floating islands 108 are provided in the deep isolation trenches 104. The polycrystalline floating islands 108 are arranged longitudinally along the deep isolation trenches 104 and have different charge types. Among them, the polycrystalline floating islands 108 on both sides of the N+ doped layer 103 and the N+ substrate layer 101 are negatively charged, and the polycrystalline floating islands 108 on both sides of the P-type epitaxial layer 102 are positively charged. The charge density of the polycrystalline floating islands 108 can be distributed in a gradient manner, specifically manifested as the charge density of the floating islands decreasing sequentially from near to far from the PN junction boundary.

[0029] As a bidirectional protection device, the front electrode 106 and the back electrode 107 do not distinguish between the anode and the cathode.

[0030] The N+ substrate layer 101 and the P-type epitaxial layer 102 form a back PN junction; the final breakdown voltage, the amplification factor of the NPN transistor, and other electrical characteristics can be adjusted by adjusting the resistivity and the final effective thickness of the P-type epitaxial layer 102. The P-type epitaxial layer 102 and the N+ doped layer 103 form a front PN junction; the deep isolation trenches 104 penetrate through the entire N+ doped layer 103 to the N+ substrate layer 101. The opening of the deep isolation trenches 104 is 1um, and multiple groups of trenches are arranged in parallel. The etching depth is 10 - 20um, and 2 - 5 groups of trenches can be arranged in parallel. The dielectric isolation layer 105 is located between the deep isolation trenches 104 and the front electrode 106; the front electrode 106 is a metal layer deposited on the surface of the device, and the back electrode 107 is formed under the N+ substrate layer 101. The back electrode 107 is a metal layer deposited on the surface of the N+ substrate layer 101.

[0031] As Figure 2 shown in the front top view of this bidirectional protection device, only partial area positions are given in the figure. The center is the contact area, and the front metal 106 covers the contact holes and the deep isolation trenches 104. Multiple columns of deep isolation trenches 104 are located in the edge area of the chip but have a certain distance from the edge. The specific details of the deep isolation trenches 104 outlined by the dashed box on the right side of the figure are as Figure 3 shown.

[0032] As Figure 3As shown, an interleaved interconnection method is adopted between multiple columns of deep isolation trenches 104, which can effectively reduce the problem of excessive stress caused by independent isolation trenches and improve the reliability of the device. A charged polycrystalline floating island 108 is built in the rightmost deep isolation trench 104. The polycrystalline floating island 108 can be formed in the following way: etching a deep trench, depositing an oxide layer, removing the sidewall oxide layer by plasma etching and retaining the bottom oxide layer, thermally growing a layer of thermal oxide layer, depositing a charged polycrystalline floating island 108 with a certain thickness, and repeating the previous steps by depositing an oxide layer to complete the fabrication of multiple polycrystalline floating islands 108.

[0033] Figure 4 This is an implementation case of the unidirectional protection device of the present invention, in which the material wafer uses a P-type layer 110, and the others are Figure 1 the same.

[0034] Figure 5 This is an implementation case of the SCR of the present invention, in which a P+ short-circuit region 109 is provided above the N+ doped layer 103, effectively increasing its dv / dt capability. The concentration of the P+ short-circuit region 109 is higher than that of the N+ doped layer 103.

[0035] The present invention can be used in bidirectional ESD protection devices with a voltage range of 3V to 72V. Due to the charge regulation effect of the polycrystalline floating island on the trench boundary, the device has a lower electric field at the trench boundary. Therefore, the device will break down in the planar junction region with a higher electric field, and this structure is not restricted by the electric field concentration effect at the junction boundary.

Claims

1. A bidirectional ESD protection device, characterized in that: A chip composed of an N+ substrate layer, a P-type epitaxial layer, and an N+ doped layer; the P-type epitaxial layer is disposed above the N+ substrate layer, and the N+ doped layer is disposed above the P-type epitaxial layer; Deep isolation trenches are located around the chip. Among them, a doped polycrystalline floating island is provided in the deep isolation trench close to the central area of the chip. An isolation dielectric layer is between the deep isolation trench and the front electrode. The front electrode is located above the N+ doped layer and the isolation dielectric layer. The back electrode is formed under the N+ substrate layer; there are multiple polycrystalline floating islands, and the polycrystalline floating islands are arranged longitudinally along the deep isolation trench.

2. The bidirectional ESD protection device according to claim 1, characterized in that: The N+ substrate layer and the P-type epitaxial layer form a back PN junction.

3. A bidirectional ESD protection device according to claim 1, characterized in that: The P-type epitaxial layer and the N+ doped layer form a front PN junction.

4. A bidirectional ESD protection device according to claim 1, characterized in that: The deep isolation trench penetrates through the entire N+ doped layer to the N+ substrate layer. The opening of the deep isolation trench is 1um, and 2 to 5 groups of deep isolation trenches are arranged in parallel. The etching depth is 10 to 20um; an interleaved interconnection method is adopted between the deep isolation trenches. According to a two-way ESD protection device as described in claim 1, wherein: the front electrode is a metal layer deposited on the surfaces of the isolation dielectric layer and the N+ doped layer.

5. A bidirectional ESD protection device according to claim 1, characterized in that: The back electrode is a metal layer deposited on the surface of the N+ substrate layer.

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