A DC-DC circuit and control method thereof

Abstract

The present invention relates to a DC-DC circuit and a control method thereof, which are used in the field of electronics. The circuit includes an oscillator that provides a clock signal CLK to a system, a PWM comparator that compares an output voltage feedback signal VFB with a reference voltage VREF and outputs a level signal Y1, a PFM controller that generates a duty cycle control signal PWM based on the CLK signal and the Y1 signal, a power tube driving circuit that generates a DRV1 signal and a DRV2 signal based on the PWM signal, a power tube that is turned on and off by the DRV1 signal, and a synchronous tube that is turned on and off by the DRV2 signal, and a zero-crossing comparator that generates a level signal Y2 by comparing voltage drops across the synchronous tube to control the turn-off time of the synchronous tube in a discontinuous mode. The circuit is characterized in that the circuit also includes a dynamic bias circuit that controls the bias current output to the PWM comparator and the zero-crossing comparator based on the length of the power tube turn-off time.

Description

Technical Field

[0001] The present invention relates to the field of electronics, and in particular to a DC-DC circuit and a control method thereof. Background Art

[0002] DC-DC is widely used in various electronic devices to provide a stable power supply to the system. Among them, PFM type DC-DC is widely used in battery-powered electronic systems due to its simple structure, low power consumption and low cost. Although DC-DC is easy to use and highly efficient, it cannot meet the ultra-low power consumption requirements of the system in some emerging applications. For example, in the emerging field of Internet of Things, many applications are battery-powered and require extremely long working time. For example, smart wearable devices are also battery-powered and require extremely long standby time. Although traditional PFM type DC-DC has a small quiescent current of usually a few uA or tens of uA, it may still not meet the more stringent low power consumption requirements. Summary of the Invention

[0003] The purpose of the present invention is to solve the problem of excessive static power consumption in traditional DC-DC circuits and to provide a DC-DC circuit and a control method.

[0004] The technical solution of the present invention is a DC-DC circuit, including an oscillator that provides a clock signal CLK to the system, a PWM comparator that compares the output voltage feedback signal VFB with the reference voltage VREF and outputs a level signal Y1, a PFM controller that generates a duty cycle control signal PWM based on the CLK signal and the Y1 signal, a power tube driving circuit that generates a DRV1 signal and a DRV2 signal respectively based on the PWM signal, a power tube that is driven on and off by the DRV1 signal, and a synchronous tube that is driven on and off by the DRV2 signal, and also includes a zero-crossing comparator that generates a level signal Y2 to control the shutdown time of the synchronous tube in a discontinuous mode by comparing the voltage drop across the synchronous tube. The special feature of the circuit is that it also includes a dynamic bias circuit, which controls the bias current output to the PWM comparator and the zero-crossing comparator according to the length of the shutdown time of the power tube.

[0005] A control method for the DC-DC circuit is characterized in that the bias current of the dynamic bias circuit remains constant at a fixed value I1 during the TON stage;

[0006] The bias current of the dynamic bias circuit changes with the off time of the power tube in the TOFF stage. When the power tube is turned off within the first time length t1, the bias current is I1;

[0007] When the off time exceeds t1 and is less than the second time length t2, the bias current decreases, and the lowest bias current is I2;

[0008] When the off time exceeds t2, the bias current is I2.

[0009] Furthermore, the on-off state of the power tube is the TON stage, and the off state of the power tube is the TOFF stage.

[0010] Furthermore, the first time length t1 is selected to be greater than a switching period Ts.

[0011] Compared with the prior art, the present invention has the following beneficial effects:

[0012] ⑴It can significantly reduce the system's operating current when it is lightly loaded or no-loaded, thereby achieving ultra-low power consumption.

[0013] ⑵ By receiving feedback on the opening and closing of the power tube, the bias current of the PWM comparator and the zero-crossing comparator is controlled through the dynamic bias circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 1 is a circuit structure diagram of a DC-DC circuit of the present invention;

[0015] Figure 2 1 is a bias current waveform diagram of the dynamic bias circuit of the DC-DC circuit of the present invention in the TON stage;

[0016] Figure 3 This is a bias current waveform diagram of the dynamic bias circuit of the DC-DC circuit of the present invention in the TOFF stage.

[0017] Description of main component symbols:

[0018] DETAILED DESCRIPTION

[0019] The present invention will be further described below in conjunction with the accompanying drawings:

[0020] See also Figure 1As shown, a DC-DC circuit includes an oscillator 1 that provides a clock signal CLK to the system, a PWM comparator 4 that compares the output voltage feedback signal VFB of the output voltage sampling resistor divider network 2 with the reference voltage VREF of the reference circuit 3 and outputs a level signal Y1, a PFM controller 5 that generates a duty cycle control signal PWM based on the CLK signal and the Y1 signal, a power transistor drive circuit 6 that generates a DRV1 signal and a DRV2 signal based on the PWM signal, the power transistor drive circuit 6 drives the power transistor 7 to be turned on and off via the DRV1 signal, and the power transistor drive circuit 6 drives the synchronous transistor 8 to be turned on and off via the DRV2 signal, and also includes a zero-crossing comparator 9 that generates a level signal Y2 to control the turn-off time of the synchronous transistor 8 in a discontinuous mode by comparing the voltage drop across the synchronous transistor 8. The circuit is special in that it also includes a dynamic bias circuit 10 that controls the bias current output to the PWM comparator 4 and the zero-crossing comparator 9 based on the length of the turn-off time of the power transistor 7.

[0021] See also Figure 1-3 As shown, a control method of a DC-DC circuit:

[0022] The bias current of the dynamic bias circuit 10 remains constant at a fixed value I1 during the TON stage;

[0023] The bias current of the dynamic bias circuit 10 changes with the off time of the power tube 7 in the TOFF stage. When the power tube 7 is turned off within the first time length t1, the bias current is I1.

[0024] When the off time exceeds t1 and is less than the second time length t2, the bias current decreases, and the lowest bias current is I2;

[0025] When the off time exceeds t2, the bias current is I2.

[0026] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention shall fall within the scope of the claims of the present invention.

Claims

1. A DC-DC circuit, comprising an oscillator that provides a clock signal CLK to a system, a PWM comparator that compares an output voltage feedback signal VFB with a reference voltage VREF and outputs a level signal Y1, a PFM controller that generates a duty cycle control signal PWM based on the CLK signal and the Y1 signal, a power transistor driver circuit that generates a DRV1 signal and a DRV2 signal based on the PWM signal, a power transistor that is turned on and off by the DRV1 signal, and a synchronous transistor that is turned on and off by the DRV2 signal, and a zero-crossing comparator that generates a level signal Y2 by comparing a voltage drop across the synchronous transistor to control the turn-off timing of the synchronous transistor in a discontinuous mode, characterized in that: The system further includes a dynamic bias circuit, which controls the bias current output to the PWM comparator and the zero-crossing comparator according to the length of the power tube shutdown time. The oscillator is electrically connected to the PFM controller, the PWM comparator is electrically connected to the PFM controller, the PFM controller is electrically connected to the power tube drive circuit, the power tube drive circuit is electrically connected to the power tube and the synchronous tube, the synchronous tube is electrically connected to the zero-crossing comparator, the power tube is electrically connected to the dynamic bias circuit, and the dynamic bias circuit is electrically connected to the zero-crossing comparator and the PWM comparator.

2. A control method for a DC-DC circuit according to claim 1, characterized in that: The dynamic bias circuit maintains a bias current of a fixed value I1 during the TON stage; The bias current of the dynamic bias circuit changes with the off time of the power tube in the TOFF stage. When the power tube is turned off within the first time length t1, the bias current is I1; When the off time exceeds t1 and is less than the second time length t2, the bias current decreases, and the lowest bias current is I2; When the off time exceeds t2, the bias current is I2.

3. The control method of the DC-DC circuit according to claim 2, characterized in that: The on-off state of the power tube is the TON stage, and the off state of the power tube is the TOFF stage.

4. The control method of the DC-DC circuit according to claim 2, characterized in that: The first time length t1 is selected to be greater than a switching period Ts.

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