Method of forming a semiconductor device

Abstract

In one embodiment, the device includes: a substrate; a first semiconductor layer extending from the substrate, and the first semiconductor layer includes silicon; a second semiconductor layer located on the first semiconductor layer, and the second semiconductor layer includes silicon germanium, wherein an edge portion of the second semiconductor layer has a first germanium concentration, a central portion of the second semiconductor layer has a second germanium concentration, the second germanium concentration is less than the first germanium concentration, and the edge portion of the second semiconductor layer includes side portions and an upper surface of the second semiconductor layer; a gate stack located on the second semiconductor layer; lightly doped source / drain regions located in the second semiconductor layer, and the lightly doped source / drain regions are adjacent to the gate stack; and source and drain regions extending into the lightly doped source / drain regions.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to a method of increasing the germanium concentration in a fin channel region. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. The manufacturing method of semiconductor devices generally deposits materials of insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate in sequence, and uses lithography to pattern the various material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce the minimum feature size to continuously improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like) to integrate more components into a given area. However, as the minimum feature size shrinks, additional problems need to be solved. Summary of the Invention

[0004] A method of forming a semiconductor device provided by an embodiment of the present invention includes: growing a semiconductor layer on a substrate, the substrate includes silicon, and the semiconductor layer includes silicon germanium; etching a plurality of trenches in the semiconductor layer and the substrate to form fins from portions of the semiconductor layer and the substrate between the trenches; performing a hydrogen radical treatment process on the upper surface and sides of the fins, and reducing the silicon concentration on the upper surface and sides of the fins after the hydrogen radical treatment process; and forming a metal gate stack along the upper surface and sides of the fins.

[0005] A method of forming a semiconductor device provided by an embodiment of the present invention includes: forming fins extending from a substrate, and the fins include a silicon-containing lower side portion and a silicon germanium-containing upper side portion; removing silicon and germanium simultaneously from the sides and upper surface of the fins, which removes silicon at a first rate and removes germanium at a second rate, and the second rate is less than the first rate; and forming source and drain regions in the fins.

[0006] A semiconductor device provided by an embodiment of the present invention includes: a substrate; a first semiconductor layer extending from the substrate, and the first semiconductor layer includes silicon; a second semiconductor layer located on the first semiconductor layer, and the second semiconductor layer includes silicon germanium, wherein an edge portion of the second semiconductor layer has a first germanium concentration, a central portion of the second semiconductor layer has a second germanium concentration, the second germanium concentration is less than the first germanium concentration, and the edge portion of the second semiconductor layer includes the sides and upper surface of the second semiconductor layer; a gate stack located on the second semiconductor layer; lightly doped source / drain regions located in the second semiconductor layer, and the lightly doped source / drain regions are adjacent to the gate stack; and source and drain regions extending into the lightly doped source / drain regions. Brief Description of the Drawings

[0007] Figure 1 In some embodiments, it is a three-dimensional view of a fin field-effect transistor.

[0008] Figure 2 、 3 、4, 5, 6, 7, 8, 9, 10A, 10B, 11A, 11B, 11C, 11D, 12A, 12B, 13A, 13B, 14A, 14B, 15, 16A, 16B, 17A, and 17B are cross-sectional views of intermediate stages of forming a fin field-effect transistor in some embodiments.

[0009] Figure 18 In some other embodiments, it is a cross-sectional view of a fin field-effect transistor.

[0010] Figure 19 、 20 、21, and 22 are cross-sectional views of a fin field-effect transistor in some other embodiments.

[0011] Among them, the reference numerals are explained as follows:

[0012] A-A, B-B, C / D-C / D reference profiles

[0013] D1 distance

[0014] T1 thickness

[0015] W1 first width

[0016] W2 second width

[0017] W3 third width

[0018] 10, 12 regions

[0019] 50 substrate

[0020] 52 semiconductor layer

[0021] 56 trench

[0022] 60 fin

[0023] 60A first part

[0024] 60B second part

[0025] 62 insulating material

[0026] 64 shallow trench isolation region

[0027] 66 germanium condensation process

[0028] 68 germanium-rich layer

[0029] 74 dummy dielectric layer

[0030] 76 dummy gate layer

[0031] 78 Mask layer

[0032] 80 Mask

[0033] 82 dummy gate

[0034] 84 dummy gate dielectric layer

[0035] 90 lightly doped source / drain region

[0036] 92 gate seal spacer

[0037] 94 gate spacer

[0038] 96 source / drain region

[0039] 100, 110 interlayer dielectric layer

[0040] 102 recess

[0041] 104 gate dielectric layer

[0042] 106 gate

[0043] 112 source / drain contact

[0044] 114 gate contact Detailed implementation manners

[0045] The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of the following specific components and arrangements are used to simplify the content of the present invention rather than limit the present invention. For example, the description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where there are other additional components between the two rather than in direct contact. On the other hand, the same reference numerals may be repeatedly used in multiple examples of the present invention for the sake of simplicity, but the components with the same reference numerals in multiple embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0046] In addition, in the embodiments of the present invention, a structure is formed on another structure, connected to another structure, and / or coupled to another structure. The structure can be in direct contact with another structure, or an additional structure can be formed between the structure and another structure. In addition, spatial relative terms such as "below", "beneath", "lower", "above", "higher", or similar terms can be used to simplify the description of the relative relationship between one element and another element in the drawing. The spatial relative terms can extend to elements used in other directions, rather than being limited to the directions in the drawing. The element can also be rotated 90° or other angles, so the directional terms are only used to describe the directions in the drawing.

[0047] In some embodiments, a substrate of a first semiconductor material such as silicon is provided, and a layer of a second semiconductor material such as silicon germanium is formed on the substrate. The second semiconductor material may have a low germanium concentration. Trenches are etched to form fins from the first semiconductor material and the second semiconductor material. A germanium condensation process is performed, including exposing the first semiconductor material and the second semiconductor material of the fins to hydrogen radicals. During the germanium condensation process, the germanium concentration along the sidewalls of the fins can be increased. Condensing germanium along the sidewalls of the fins can increase the germanium concentration in the fin channel region. Since the fins initially formed have a low germanium concentration, they have a lower compressive stress, so fin deformation can be reduced during trench etching.

[0048] Figure 1 In some embodiments, a three-dimensional view of a fin field-effect transistor is shown. The fin field-effect transistor includes fins 60 on a substrate 50 (such as a semiconductor substrate). Shallow trench isolation regions 64 are located in the substrate 50, and the fins 60 protrude above the adjacent shallow trench isolation regions 64. A gate dielectric layer 104 is along the sidewalls and the upper surface of the fins 60, and a gate 106 is located on the gate dielectric layer 104. Source / drain regions 96 are located on both sides of the fins 60 (relative to the gate dielectric layer 104 and the gate 106).

[0049] Figure 1 Also shown are reference cross-sections used in subsequent figures. Reference cross-section A-A is along the channel of the fin field-effect transistor, the gate dielectric layer 104, and the gate 106. Reference cross-section B-B is perpendicular to reference cross-section A-A and along the longitudinal axis of the fins 60 and the current direction between the source / drain regions 96 of the fin field-effect transistor. Reference cross-section C / D-C / D is parallel to reference cross-section A-A and extends through the source / drain regions 96 of the fin field-effect transistor. Subsequent figures will be based on these reference cross-sections for the purpose of clarity of the figures.

[0050] Some of the embodiments described herein are fin field-effect transistors formed by a post-gate process. In other embodiments, a gate-first process may be employed. In addition, some embodiments may be implemented in planar devices such as planar field-effect transistors.

[0051] The fins can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fins, such as double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography with self-alignment processes, and the resulting pattern pitch can be smaller than that obtained by a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a photolithography process. Using a self-alignment process, spacers are formed along the sides of the patterned sacrificial layer. Then the sacrificial layer is removed, and the remaining spacers can be used to pattern the fins.

[0052] Figures 2 to 17B In some embodiments, it is a cross-sectional view of an intermediate stage of forming a fin field-effect transistor. Figures 2 to 9 Along Figure 1 reference section A-A in Figures 2 to 9 which has multiple fins or fin field-effect transistors. In Figures 10A to 17B , those with reference label A at the end of the drawing are along Figure 1 reference section A-A, those with reference label B at the end of the drawing are along Figure 1 reference section B-B, and those with reference label C or D at the end of the drawing are along Figure 1 reference section C / D-C / D in Figures 10A to 17B which has multiple fins or fin field-effect transistors.

[0053] In Figure 2 , a substrate 50 is provided. The substrate 50 can be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator substrate, or the like, which can be doped (such as doped with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer can be a buried oxide layer, a silicon oxide layer, or the like. An insulating layer is provided on the substrate, and the substrate is usually a silicon or glass substrate. Other substrates such as multi-layer substrates or compositional gradient substrates can also be used. In some embodiments, the substrate 50 can include silicon, such as a silicon substrate (silicon wafer). In some embodiments, the semiconductor material of the substrate 50 can also include germanium, semiconductor compounds (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (including silicon germanium, gallium phosphide arsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, and / or gallium arsenide phosphide indium), or a combination of the above.

[0054] The figure shows a region of the substrate 50. The illustrated region can be used to form n-type devices such as n-type metal-oxide semiconductor transistors (such as n-type fin field-effect transistors), or to form p-type devices such as p-type metal-oxide semiconductor transistors (such as p-type fin field-effect transistors). Some of the embodiments described herein are for forming p-type devices in the illustrated region. N-type devices can be formed in other regions of the substrate 50. When forming p-type devices, a mask such as a photoresist can cover the regions used to form n-type devices.

[0055] In some embodiments, the substrate 50 is doped to have appropriate doped regions (sometimes referred to as well regions). In embodiments where p-type devices are formed in the indicated regions, n-type doped regions can be formed in the substrate 50. In some embodiments, the n-type doped regions can be formed by implanting n-type impurities into regions of the substrate 50. In some embodiments, the substrate 50 can be pre-doped with n-type impurities. The n-type impurities can be phosphorus, arsenic, or the like, and the concentration of n-type impurities formed in the regions can be less than or equal to 10 18 cm -3 , for example, between about 10 17 cm -3 and about 10 18 cm -3 . In embodiments where n-type devices are formed in the indicated regions, p-type doped regions can be formed in the substrate 50. In some embodiments, the p-type doped regions can be formed by implanting p-type impurities into regions of the substrate 50. In some embodiments, the substrate 50 can be pre-doped with p-type impurities. The p-type impurities can be boron, boron difluoride, or the like, and the concentration of p-type impurities formed in the regions can be less than or equal to 10 18 cm -3 , for example, between about 10 17 cm -3 and about 10 18 cm -3 .

[0056] In Figure 3 , a semiconductor layer 52 is formed on the substrate 50. The semiconductor layer 52 can be epitaxially grown on the substrate 50. In embodiments where p-type devices are formed, the semiconductor material of the semiconductor layer 52 includes germanium, such as silicon germanium (Si x Ge 1-x , where x can be from 0 to 1). Silicon and silicon germanium can have different lattice constants. In this way, the semiconductor layer 52 and the substrate 50 have mismatched lattice constants. The lattice constant mismatch depends on the germanium concentration in the semiconductor layer 52, and the greater the germanium concentration, the greater the lattice constant mismatch. The lattice constant mismatch induces compressive stress in the semiconductor layer 52, which can increase the carrier mobility in the semiconductor layer 52, thereby improving the mobility in the channel regions of subsequently formed p-type devices. Due to the low germanium concentration in the semiconductor layer 52, the degree of compressive stress and lattice mismatch is also low.

[0057] In some embodiments, in-situ doping is performed during the growth of the semiconductor layer 52 to make the semiconductor layer 52 have appropriate doped regions (sometimes referred to as well regions). The doped regions of the semiconductor layer 52 can have the same dopant type as the doped regions of the underlying substrate 50. The doped regions of the semiconductor layer 52 and the underlying substrate 50 can have the same or different doping concentrations.

[0058] In Figure 4In [description], a trench 56 is formed in the semiconductor layer 52 and may optionally be formed in the substrate 50. The trench 56 can be formed by one or more etching processes using a photoresist as an etching mask. The etching process can include wet etching, dry etching, reactive ion etching, neutral beam etching, combinations of the above, or similar methods, and can be non-isotropic. The trench 56 can partially extend into the semiconductor layer 52 or can extend through the semiconductor layer 52 to the substrate 50. The portions of the semiconductor layer 52 remaining between the trenches 56 (and optionally the substrate 50 remaining between the trenches 56) are referred to as fins 60. The fin 60 includes a first portion 60A and a second portion 60B. The first portion 60A includes a portion of the substrate 50 (such as the first layer of the first semiconductor material), and the second portion 60B includes a portion of the semiconductor layer 52 (such as the second layer of the second semiconductor material). The initially formed fin 60 has a first width W1. In some embodiments, the first width W1 is between about 7 nm and about 15 nm. This fin width can allow the fin to maintain a sufficient thickness after etching the fin (as described below). It can be understood that the fin 60 can be formed by other methods. For example, a patterned mask (such as a photoresist, a hard mask, or the like) can be formed on the substrate 50, and an epitaxial region corresponding to the fin 60 can be grown in the opening of the patterned mask.

[0059] The fin 60 can be a semiconductor strip. When etching the second portion 60B of the semiconductor layer 52 to form the fin 60, the sidewalls of the fin 60 that are exposed and not laterally restricted will be exposed (for example, the sidewalls of the fin 60 are exposed to free space, and the exposed sidewalls are not supported by other structures or materials). As emphasized above, the semiconductor layer 52 has stress. Since the sidewalls of the fin 60 are not restricted during etching, the stress in the semiconductor layer 52 will be released during etching. When releasing the stress, the shape of the semiconductor material will be changed, causing the fin 60 to deform and not have the desired fin shape. Specifically, the fin 60 will deform such that the top view shape of the semiconductor strip is not a straight strip. The deformed fin 60 will bend when extending along the substrate 50. The degree of deformation of the fin 60 depends on the amount of stress released from the semiconductor layer 52. When the width of the fin is narrower and the height is larger, the risk of deformation of the fin 60 may deteriorate. Excessive deformation will reduce the yield of the fin 60 and also reduce the carrier mobility of the fin 60. The semiconductor layer can be formed to have a low initial germanium concentration. Since the semiconductor layer 52 is formed to have a low germanium concentration, the amount of stress release is low. In some embodiments, the initial germanium concentration can be between about 15% and about 40%, which can provide sufficient channel mobility without causing significant deformation. The carrier mobility gained by forming the semiconductor layer 52 with a low initial germanium concentration to avoid fin deformation can be greater than the carrier mobility lost by reducing the germanium concentration.

[0060] In Figure 5In [description], an insulating material 62 is formed on a substrate 50 and between adjacent fins 60. An additional portion of the insulating material 62 may cover the fins 60. The insulating material 62 may be an oxide such as silicon oxide, a nitride, the like, or a combination of the above, and the method of forming it may be high-density plasma chemical vapor deposition, flowable chemical vapor deposition, the like, or a combination of the above. Flowable chemical vapor deposition may deposit a chemical vapor deposition-based material in a remote plasma system and then harden the deposited material to transform it into another material such as an oxide. Additionally, other insulating materials formed by any acceptable process may also be used. In the described embodiment, the insulating material 62 is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process may be performed.

[0061] In Figure 6 [description], the insulating material 62 is recessed to form a shallow trench isolation region 64. The insulating material 62 is recessed, so that the upper side portion of the second part 60B of the fin 60 protrudes between adjacent shallow trench isolation regions 64. The method of recessing the insulating material 62 may be to perform an acceptable etching process after a planarization process. In some embodiments, the planarization process includes chemical mechanical polishing, a re-etching process, a combination of the above, or the like. The planarization process may expose the fins 60. After the planarization process, the upper surfaces of the fins 60 and the insulating material 62 may be flush. Then, an acceptable etching process such as an etching process selective to the material of the insulating material 62 may be used to recess the shallow trench isolation region 64. For example, chemical oxide removal using a hydrogen source (such as ammonia) and a fluorine source (such as nitrogen trifluoride), or chemical oxide removal using diluted hydrofluoric acid may be employed. Through the etching process, the shallow trench isolation region 64 may have a flat, protruding, and / or recessed upper surface.

[0062] In Figure 7 [description], a germanium condensation process 66 is performed on the fins 60. Figure 8 is Figure 7Detailed view of region 10 in which shows additional structure of fin 60 after germanium condensation process 66. Germanium condensation process 66 forms germanium-rich layer 68 in the second portion 60B of fin 60. The final germanium-rich layer 68 is in the sidewall of the second portion 60B of fin 60. In this way, the germanium concentration in the edge portion of the second portion 60B of fin 60 is higher than that in the central portion of the second portion 60B of fin 60. The edge portion includes the sidewall and the upper surface of the second portion 60B of fin 60. In some embodiments, the germanium concentration of the germanium-rich layer 68 in the second portion 60B of fin 60 is between about 20% and about 45% to improve the carrier mobility of the final fin field-effect transistor. In some embodiments, germanium condensation process 66 increases the germanium concentration of the germanium-rich layer 68 of fin 60 by up to 4%. In a device, the germanium concentration of the entire fin 60 before processing is about 29%, the germanium concentration of the central portion of fin 60 after processing is about 29%, and the germanium concentration of the edge portion of fin 60 after processing is about 35%.

[0063] The germanium condensation process 66 is a hydrogen radical treatment process in which the second portion 60B of the fin 60 is exposed to hydrogen radicals. Hydrogen radicals can react significantly with group-IV materials to form tetrahydride compounds. The hydrogen radical treatment process can be carried out in a chamber such as an etching chamber. A gas source is delivered to each chamber. The gas source includes a precursor gas and an inert gas. The precursor gas includes hydrogen, and the inert gas can include argon, helium, or a combination of the above. However, other inert gases such as xenon, neon, krypton, radon, analogs, or a combination of the above can also be used. In some embodiments, the precursor gas is about 3% to about 20% of the gas source, and the carrier gas can be about 80% to about 97% of the gas source. The delivery flow rate of the gas source can be between about 10 standard cubic centimeters per minute (sccm) and about 5000 sccm. When delivering the gas, a plasma can be generated from hydrogen, argon, and / or helium. In the plasma generation process, a plasma can be generated by a plasma generator (such as a transformer-coupled plasma generator, an inductively coupled plasma system, a magnetically enhanced reactive ion etching system, an electron cyclotron resonance system, a remote plasma generator, or the like). The plasma generator can generate radio frequency power to generate a plasma from hydrogen, argon, and / or helium, such as applying a voltage higher than the breakdown voltage to an electrode in a chamber (containing argon, helium, argon and helium, or helium and hydrogen). When generating the plasma, hydrogen will be split into two hydrogen radicals H·. When the silicon-germanium material on the surface of the second portion 60B of the fin 60 is exposed to the hydrogen plasma, it will break and recombine with the hydrogen radicals H· to form silane and germane, so the surface material of the fin 60 can be removed. The above silane and germane are gases, and silane and germane can be removed from the etching chamber when forming silane and germane, such as by vacuum removal. The reaction rate between silicon and hydrogen is greater than the reaction rate between germanium and hydrogen. For example, the reaction rate between silicon and hydrogen is about 2 to 10 times the reaction rate between germanium and hydrogen. It can be understood that the difference in the reaction rate can vary depending on the process parameters and the initial germanium concentration. The germanium surface is more prone to desorb hydrogen than the silicon surface. Therefore, the silicon on the surface of the fin 60 is removed faster than the germanium on the surface of the fin 60. In this way, after the germanium condensation process 66, the surface silicon concentration of the fin 60 decreases, and the surface germanium concentration of the fin 60 increases. In some embodiments, the temperature of the hydrogen radical treatment process is between about 100°C and about 600°C, the time is less than about 100 seconds (such as less than about 50 seconds), and the pressure is between about 0.1 Torr and about 6 Torr. Compared with other germanium condensation processes (such as thermal oxidation processes), the advantage of the hydrogen radical treatment process is that it can be carried out at a lower temperature, a shorter time, and a lower pressure. These improved process parameters can also improve the process speed and reduce the consideration of the thermal budget.

[0064] Since the hydrogen radical treatment process removes some material from the surface of the fin 60 to form silane and germanane, it also etches some of the fin 60. As a result, the upper side portion of the fin 60 after germanium condensation has a second width W2, and the second width W2 is smaller than the first width W1 of the lower side portion of the fin 60. Additionally, when the second portion 60B of the fin 60 extends between adjacent shallow trench isolation regions 64, the second portion 60B of the fin 60 can have different upper and lower side widths. The width reduction of the fin 60 depends on the parameters of the germanium condensation process 66. In some embodiments, the second width W2 is between about 7 nm and about 15 nm. The thickness of the germanium-rich layer 68 also depends on the parameters of the germanium condensation process 66. By varying the parameters of the germanium condensation process 66, the thickness T1 of the germanium-rich layer 68 can be changed from a few monolayers to substantially the entire width of the fin 60. In some embodiments, the thickness T1 is less than about 2 nm, such as between about 0.5 nm and about 1 nm, thereby increasing the hole mobility. The more germanium condensation processes are performed, the greater the thickness T1 of the germanium-rich layer 68, the greater the germanium concentration of the germanium-rich layer 68, and the smaller the second width W2 of the fin 60.

[0065] Although the germanium-rich layer 68 in the figures is a separate region of the fin 60, it should be understood that the germanium-rich layer 68 and the second portion 60B of the fin 60 comprise the same elements, with the difference being that the germanium-rich layer 68 has a higher germanium concentration. Additionally, it should be understood that the germanium concentration of the fin 60 can gradually increase, and the increasing direction extends from the central portion of the fin 60 to the edge portion of the fin 60.

[0066] Although the semiconductor layer 52 has a low germanium concentration when formed, forming the germanium-rich layer 68 can increase the germanium concentration of the fin 60. Forming the fin 60 with a low initial germanium concentration helps to avoid deformation of the fin 60 when forming the fin 60 and also helps to improve the crystalline quality of the semiconductor layer 52. After forming the fin 60, increasing the germanium concentration of the fin 60 can increase the carrier mobility of the fin 60 without increasing the drawback of fin deformation. Additionally, since the germanium-rich layer 68 is close to the sidewall of the fin 60, it can be close to the gate of a subsequently formed p-type device to increase the channel region mobility of the subsequently formed p-type device. The final stress of the fin 60 is also higher than the initial stress of the fin 60.

[0067] In Figure 9In this case, a dummy dielectric layer 74 is formed on the fin 60, for example, on the second portion 60B of the fin 60. For example, the dummy dielectric layer 74 can be silicon oxide, silicon nitride, a combination of the above, or the like, and the method for forming it can be deposition or thermal growth according to acceptable techniques. A dummy gate layer 76 is formed on the dummy dielectric layer 74, and a mask layer 78 is formed on the dummy gate layer 76. The dummy gate layer 76 can be deposited on the dummy dielectric layer 74, and then the dummy gate layer 76 is planarized (such as chemical mechanical polishing). The dummy gate layer 76 can be a conductive material, which can include polysilicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide, or metal. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon. The deposition method of the dummy gate layer 76 can be physical vapor deposition, chemical vapor deposition, sputtering deposition, or other known techniques in the art for depositing conductive materials. The composition of the dummy gate layer 76 can be other materials that have high etch selectivity for the step of etching the isolation region. The mask layer 78 can be deposited on the dummy gate layer 76.

[0068] In Figure 10A and 10B this case, acceptable photolithography and etching techniques can be used to pattern the mask layer 78 to form a mask 80. Then, acceptable etching techniques can be used to transfer the pattern of the mask 80 to the dummy gate layer 76 and the dummy dielectric layer 74 respectively to form a dummy gate 82 and a dummy gate dielectric layer 84. The dummy gate 82 and the dummy gate dielectric layer 84 cover the individual channel regions of the fin 60. The pattern of the mask 80 can be used to physically separate adjacent dummy gates 82 from each other. The longitudinal direction of the dummy gate 82 can also be substantially perpendicular to the longitudinal direction of the individual fin 60.

[0069] In Figure 11A , 11B , 11C, and 11D, implantation for the lightly doped source / drain regions 90 can be performed. Impurities of a suitable type (such as n-type or p-type) can be implanted into the exposed fin 60. The n-type impurities can be any of the aforementioned n-type impurities, and the p-type impurities can be any of the aforementioned p-type impurities. The impurity concentration of the lightly doped source / drain regions 90 can be between about 10 15 cm -3 to about 10 16 cm -3 . Annealing can be used to activate the implanted impurities.

[0070] In addition, a gate seal spacer 92 may be formed on the exposed surfaces of the dummy gate 82 and / or the fin 60. The method of forming the gate seal spacer 92 may be anisotropic etching after thermal oxidation or deposition. In some embodiments, the composition of the gate seal spacer 92 may be a nitride such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination of the foregoing. The gate seal spacer 92 seals the sidewalls of the subsequently formed gate stack and may serve as an additional gate spacer layer.

[0071] In addition, a gate spacer 94 is formed on the gate seal spacer 92 along the sidewalls of the dummy gate 82 and on the lightly doped source / drain regions 90. The method of forming the gate spacer 94 may be conformal deposition of a material followed by anisotropic etching of the material. In some embodiments, the material of the gate spacer 94 may be silicon nitride, silicon carbonitride, a combination of the foregoing, or the like. The etching step may be selective to the material of the gate spacer 94, such that the lightly doped source / drain regions 90 are not etched when forming the gate spacer 94.

[0072] In addition, an epitaxial source / drain region 96 is formed in the fin 60. The epitaxial source / drain region 96 is formed in the fin 60 such that each dummy gate 82 is located between an individual and adjacent pair of epitaxial source / drain regions 96. In some embodiments, the epitaxial source / drain region 96 may extend through the lightly doped source / drain regions 90. In some embodiments, the gate seal spacer 92 and the gate spacer 94 are used to separate the epitaxial source / drain region 96 from the dummy gate 82 by a suitable lateral distance to prevent the epitaxial source / drain region 96 from shorting out to the subsequently formed gate of the final fin field effect transistor.

[0073] The method of forming the epitaxial source / drain region 96 may be to etch the source / drain regions of the fin 60 to form recesses in the fin 60. These recesses may be limited to the second portion 60B of the fin 60 or may extend into the first portion 60A of the fin 60. Then, an epitaxial source / drain region 96 is grown in the recesses. The epitaxial source / drain region 96 may comprise any acceptable material, such as materials suitable for p-type or n-type fin field effect transistors. For example, in some embodiments of forming a p-type device, the epitaxial source / drain region 96 may include silicon germanium, boronated silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain region 96 may have a surface that bulges from the individual surfaces of the fin 60 and may have crystal planes.

[0074] In-situ doping may be performed during the growth of the epitaxial source / drain region 96 to form the source / drain regions. The epitaxial source / drain region 96 and the individual lightly doped source / drain regions 90 may have the same doping type and may be doped with the same or different dopants. The impurity concentration of the epitaxial source / drain region 96 may be between about 1019 cm -3 to about 10 21 cm -3 Between. The n-type and p-type impurities used for the source / drain regions can be any of the aforementioned impurities. Since in-situ doping is performed when growing the epitaxial source / drain region 96, implantation doping is not required. However, in some embodiments, the doping profile and concentration of the lightly doped source / drain region 90 formed can be similar to those generated by implanting and doping the epitaxial source / drain region 96. Improving the doping concentration and profile of the lightly doped source / drain region can improve the performance and reliability of the final semiconductor device.

[0075] An epitaxial source / drain region 96 is formed by an epitaxial process, causing the upper surface of the epitaxial source / drain region to have crystal planes that laterally expand beyond the sidewalls of the fin 60. In some embodiments, these crystal planes cause adjacent epitaxial source / drain regions 96 of the same fin field-effect transistor to merge, as shown in the embodiment of Figure 11C shown. In other embodiments, after completing the epitaxial process, adjacent epitaxial source / drain regions 96 remain separate, as shown in the embodiment of Figure 11D shown.

[0076] In Figure 12A and 12B a interlayer dielectric layer 100 is deposited on the fin 60. The composition of the interlayer dielectric layer 100 can be a dielectric material, and the deposition method thereof can be any suitable method such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material can include phosphosilicate glass, borosilicate glass, undoped silicate glass, or the like. In addition, other insulating materials formed by any acceptable process can also be used. In some embodiments, a contact etch stop layer is located between the interlayer dielectric layer 100 and the epitaxial source / drain region 96, the gate spacer 94, the gate seal spacer 92, and the mask 80.

[0077] In Figure 13A and 13B a planarization process such as chemical mechanical polishing can be performed to make the upper surface of the interlayer dielectric layer 100 flush with the upper surfaces of the dummy gate 82 and the gate seal spacer 92. The planarization process can also remove the mask 80 on the dummy gate 82 and portions of the gate seal spacer 92 and the gate spacer 94 along the sidewalls of the mask 80. After the planarization process, the upper surfaces of the dummy gate 82, the gate seal spacer 92, the gate spacer 94, and the interlayer dielectric layer 100 are flush. In summary, the upper surface of the dummy gate 82 is exposed from the interlayer dielectric layer 100.

[0078] In Figure 14A and 14BIn [the figure], in the etching step, the dummy gate 82 and the dummy gate dielectric layer 84 directly under the exposed dummy gate 82 are removed to form a recess 102. In some embodiments, the dummy gate 82 is removed by an anisotropic dry etching process without removing the gate seal spacer 92 or the interlayer dielectric layer 100. For example, the etching process may include a dry etching process that uses a reactive gas that can selectively etch the dummy gate 82 without etching the interlayer dielectric layer 100 or the gate spacer 94. Each recess 102 exposes the channel region of an individual fin 60. Each channel region may be confined to the second portion 60B of an individual fin 60. Each channel region is located between a pair of adjacent epitaxial source / drain regions 96. In the etching step of removing the dummy gate 82, the dummy gate dielectric layer 84 may act as an etch stop layer. After removing the dummy gate 82, the dummy gate dielectric layer 84 may then be removed.

[0079] Figure 15 Yes Figure 14B is a detailed view of region 12 in [the figure], which shows other structures of the fin 60 after the recess 102 is formed. The germanium-rich layer 68 is located over the entirety of what will be the channel region in the final fin field-effect transistor and extends between the lightly doped source / drain regions 90. The lightly doped source / drain regions 90 are also formed in the portion of the fin 60 having the germanium-rich layer 68. In this way, the germanium concentration in the upper side portion of the lightly doped source / drain region 90 is higher than the germanium concentration in the lower side portion of the lightly doped source / drain region 90. The thickness T1 (as described above) of the germanium-rich layer 68 in the lightly doped source / drain region 90 and the channel region may be consistent.

[0080] In Figure 16A and 16BTherein, a gate dielectric layer 104 and a gate 106 are formed in the recess 102. An interface layer is conformally formed on the fin 60 and in the recess 102. The interface layer may also cover the upper surface of the interlayer dielectric layer 100. The interface layer may be formed by a deposition process such as chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, or a similar process. The gate dielectric layer 104 may be formed on the interface layer. The gate dielectric layer 104 may be conformally deposited in the recess 102, such as on the upper surface and sidewalls of the fin 60. The gate dielectric layer 104 may also be formed along the upper surface of the interlayer dielectric layer 100. The gate dielectric layer 104 may be a high-k dielectric material having a dielectric constant greater than about 7.0 and may include hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or a metal oxide or metal silicate of a combination of the foregoing. The formation method of the gate dielectric layer 104 may include molecular beam deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, or a similar method. Then, a gate layer is deposited on the gate dielectric layer 104 and in the recess 102. The gate layer may be a metal-containing material such as titanium nitride, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, a combination of the foregoing, or multiple layers of the foregoing. The gate layer may include any number of work function adjustment layers. A planarization process such as chemical mechanical polishing may be performed to remove the excess portions of the gate dielectric layer 104 and the gate layer on the upper surface of the interlayer dielectric layer 100. The remaining portion of the gate layer forms the gate 106, which may be combined with other layers to form the replacement gate of the final fin field effect transistor. The gate dielectric layer 104 and the gate 106 may be collectively referred to as the gate or gate stack of the final fin field effect transistor. The gate stack may extend along the sidewalls of the channel region of the fin 60.

[0081] In Figure 17A and 17B Therein, an interlayer dielectric layer 110 is deposited on the gate stack and the interlayer dielectric layer 100. In one embodiment, the interlayer dielectric layer 110 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the composition of the interlayer dielectric layer 110 is a dielectric material, such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and the deposition method thereof may be any suitable method such as chemical vapor deposition or plasma enhanced chemical vapor deposition.

[0082] In addition, source / drain contacts 112 and gate contacts 114 are formed to pass through the interlayer dielectric layers 100 and 110. Openings are formed through the interlayer dielectric layers 100 and 110 for the source / drain contacts 112, and an opening is formed through the interlayer dielectric layer 110 for the gate contacts 114. The openings can be formed by acceptable photolithography and etching techniques. A liner layer (such as a diffusion barrier layer, an adhesion layer, or the like) and a conductive material are formed in the openings. The liner layer can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process can be performed to remove excess material from the surface of the interlayer dielectric layer 110. The remaining liner layer and conductive material form the source / drain contacts 112 and the gate contacts 114 in the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain regions 96 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 96, and the gate contacts 114 are physically and electrically coupled to the gate 106. The source / drain contacts 112 and the gate contacts 114 can be formed by different processes, or by the same process. Although the source / drain contacts 112 and the gate contacts 114 in the drawings are formed in the same cross-section, it should be understood that they can be formed in different cross-sections to avoid contact short-circuiting.

[0083] In the above embodiments, the germanium condensation process 66 is performed after the formation of the shallow trench isolation regions 64. However, it should be understood that the germanium condensation process 66 can be performed after other process steps used for forming p-type devices.

[0084] In some embodiments, the germanium condensation process 66 is performed before the formation of the shallow trench isolation regions 64. Figure 18 Yes Figure 7 is a detailed view of region 10 in, showing additional structures of the fin 60 where the germanium condensation process 66 is performed before the formation of the shallow trench isolation regions 64. In these embodiments, the second portion 60B of the fin 60 can have a uniform second width W2, and the first portion 60A of the fin 60 can have a uniform third width W3. Under the upper surface of the shallow trench isolation regions 64, the fin width may change. Since the first portion 60A can also be etched during the germanium condensation process 66, the third width W3 can be less than the first width W1 (see Figure 8 ) and can be greater than the second width W2.

[0085] In some other embodiments, after the removal of the dummy gate 82 and the dummy gate dielectric layer 84, the germanium condensation process 66 is performed. Figure 19 Yes Figure 14BDetail view of the middle region 12, showing additional structures of the fin 60 after the formation of the recess 102 and then the germanium condensation process 66. In these embodiments, the germanium-rich layer 68 only extends along the part of the fin 60 exposed by the recess 102 (e.g., along the channel region of the final fin field-effect transistor), and the lightly doped source / drain regions 90 may have a uniform germanium concentration. In addition, only the part of the fin 60 exposed by the recess 102 has a second width W2 (see Figure 20 ). Other regions of the fin 60 (e.g., other regions under the gate spacer seal 92 and the gate spacer 94) still maintain the first width W1 (see Figure 21 ). Finally, the germanium condensation process 66 can extend the recess 102 by a distance D1 to reduce the height of the fin 60 in the channel region of the final fin field-effect transistor. In this way, the lower surface of the gate dielectric layer 104 is lower than the topmost surface of the fin 60 (e.g., the topmost surface of the lightly doped source / drain region 90), see Figure 22 .

[0086] Some advantages can be achieved in the embodiments. Forming the semiconductor layer 52 with a low germanium concentration (see Figure 3 ) helps to avoid the deformation of the fin sidewalls during the etching process for forming the fin 60 (see Figure 4 ). Performing the germanium condensation process 66 after the etching process for forming the fin 60 (see Figure 7 ) to increase the germanium concentration of the fin 60 can increase the carrier mobility of the fin 60. Therefore, the channel region mobility of the final p-type device can be increased, and the risk of fin deformation during fin formation can be reduced.

[0087] In one embodiment, the method includes: growing a semiconductor layer on a substrate, the substrate including silicon and the semiconductor layer including silicon germanium; etching trenches in the semiconductor layer and the substrate to form fins from the portions of the semiconductor layer and the substrate between the trenches; performing a hydrogen radical treatment process on the upper surface and sides of the fins, and reducing the silicon concentration on the upper surface and sides of the fins after the hydrogen radical treatment process; and forming a metal gate stack along the upper surface and sides of the fins.

[0088] In some embodiments of the method, the steps of performing a hydrogen radical treatment process include: delivering a gas source including a first gas and a second gas to the upper surface and sides of the fin, the first gas being hydrogen and the second gas being an inert gas; and generating a hydrogen plasma to convert the first gas into hydrogen radicals. In some embodiments of the method, the steps of performing a hydrogen radical treatment process further include: forming silane from the hydrogen radicals and the silicon germanium of the fin, and forming germane from the hydrogen radicals and the silicon germanium of the fin, and the second rate of forming germane is less than the first rate of forming silane. In some embodiments of the method, the steps of performing a hydrogen radical treatment process further include: etching the upper surface and sides of the fin with the hydrogen plasma. In some embodiments of the method, the hydrogen radical treatment process is performed in an etching chamber, and the steps of performing a hydrogen radical treatment process further include: removing silane and germane from the etching chamber when forming silane and germane. In some embodiments of the method, the temperature of the hydrogen radical treatment process is between about 100 °C and about 600 °C. In some embodiments of the method, the time of the hydrogen radical treatment process is less than about 100 seconds. In some embodiments of the method, the pressure of the hydrogen radical treatment process is between about 0.1 Torr and about 6 Torr.

[0089] In one embodiment, the method includes: forming a fin extending from a substrate, and the fin includes a silicon-containing lower side portion and a silicon germanium-containing upper side portion; simultaneously removing silicon and germanium from the sides and upper surface of the fin, which removes silicon at a first rate and germanium at a second rate, and the second rate is less than the first rate; and forming source and drain regions in the fin.

[0090] In some embodiments, the method further includes: forming an isolation region around the fin before removing silicon and germanium. In some embodiments, the method further includes: forming an isolation region around the fin after removing silicon and germanium. In some embodiments, the method further includes: forming a metal gate stack along the upper surface and sides of the fin before removing silicon and germanium. In some embodiments, the method further includes: forming a metal gate stack along the upper surface and sides of the fin after removing silicon and germanium. In some embodiments of the method, the step of removing silicon and germanium includes: exposing the upper surface and sides of the fin to hydrogen radicals, and the hydrogen radicals react with the silicon of the fin at a first rate to form silane, and the hydrogen radicals react with the germanium of the fin at a second rate to form germane.

[0091] In one embodiment, the device includes: a substrate; a first semiconductor layer extending from the substrate, and the first semiconductor layer includes silicon; a second semiconductor layer located on the first semiconductor layer, and the second semiconductor layer includes silicon germanium, wherein an edge portion of the second semiconductor layer has a first germanium concentration, a central portion of the second semiconductor layer has a second germanium concentration, the second germanium concentration is less than the first germanium concentration, and the edge portion of the second semiconductor layer includes a side portion and an upper surface of the second semiconductor layer; a gate stack located on the second semiconductor layer; a lightly doped source / drain region located in the second semiconductor layer, and the lightly doped source / drain region is adjacent to the gate stack; and a source and a drain region extending into the lightly doped source / drain region.

[0092] In some embodiments of the device, the entire lightly doped source / drain region has the second germanium concentration. In some embodiments of the device, an upper side portion of the lightly doped source / drain region has the first germanium concentration, and a lower side portion of the lightly doped source / drain region has the second germanium concentration. In some embodiments of the device, the first semiconductor layer has a first width, a lower side portion of the second semiconductor layer has the first width, an upper side portion of the second semiconductor layer has a second width, and the second width is less than the first width. In some embodiments of the device, the first semiconductor layer has a first width, and the upper side portion and the lower side portion of the second semiconductor layer have the second width, and the second width is less than the first width. In some embodiments of the device, the gate stack includes: a gate dielectric layer located on the second semiconductor layer, and a lower surface of the gate dielectric layer is lower than an upper surface of the lightly doped source / drain region; and a gate located on the gate dielectric layer.

[0093] The features of the above embodiments are beneficial for those skilled in the art of the present technology to understand the present invention. Those skilled in the art of the present technology should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art of the present technology should also understand that these equivalent replacements do not depart from the spirit and scope of the present invention, and can be changed, replaced, or varied without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: Growing a semiconductor layer on a substrate, the substrate comprising silicon, and the semiconductor layer comprising silicon germanium; Etching a plurality of trenches in the semiconductor layer and the substrate to form a fin having a first portion and a second portion, the first portion comprising a portion of the substrate between the trenches, the second portion comprising a portion of the semiconductor layer between the trenches, the first portion having a first width, and the second portion having a second width; After etching the trenches in the semiconductor layer and the substrate, performing a hydrogen radical treatment process on the upper surface and sides of the fin, and reducing the silicon concentration on the upper surface and sides of the fin after the hydrogen radical treatment process, and reducing the second width of the second portion of the fin after the hydrogen radical treatment process; and Forming a metal gate stack along the upper surface and sides of the fin.

2. The method for forming a semiconductor device according to claim 1, wherein the step of performing the hydrogen radical treatment process comprises: Delivering a gas source comprising a first gas and a second gas to the upper surface and sides of the fin, the first gas being hydrogen gas, and the second gas being an inert gas; and Generating a hydrogen plasma to convert the first gas into a plurality of hydrogen radicals.

3. The method for forming a semiconductor device according to claim 2, wherein the step of performing the hydrogen radical treatment process further comprises: Forming silane from the hydrogen radicals and the silicon germanium of the fin at a first rate, and Forming germane from the hydrogen radicals and the silicon germanium of the fin at a second rate, and the second rate is less than the first rate.

4. The method for forming a semiconductor device according to claim 3, wherein the step of performing the hydrogen radical treatment process further comprises: Etching the upper surface and sides of the fin with the hydrogen plasma.

5. The method for forming a semiconductor device according to claim 3, wherein the hydrogen radical treatment process is performed in an etching chamber, and the step of performing the hydrogen radical treatment process further comprises: Removing silane and germane from the etching chamber when forming silane and germane.

6. The method for forming a semiconductor device according to claim 1, wherein the temperature of the hydrogen radical treatment process is between 100°C and 600°C.

7. The method for forming a semiconductor device according to claim 1, wherein the time of the hydrogen radical treatment process is less than 100 seconds.

8. The method for forming a semiconductor device according to claim 1, wherein the pressure of the hydrogen radical treatment process is between 0.1 Torr and 6 Torr.

9. The method for forming a semiconductor device according to claim 1, further comprising: Forming a plurality of lightly doped source / drain regions in the semiconductor layer, and the metal gate stack is formed between the lightly doped source / drain regions, wherein an upper side portion of the lightly doped source / drain regions has a first germanium concentration, a lower side portion of the lightly doped source / drain regions has a second germanium concentration, and the second germanium concentration is less than the first germanium concentration.

10. The method of forming a semiconductor device as claimed in claim 1, wherein after the hydrogen radical treatment process, the first width of the first portion of the fin is reduced.

11. A method of forming a semiconductor device, comprising: forming a fin extending from a substrate by an etching process, and the fin includes a silicon-containing lower side portion and a silicon germanium-containing upper side portion; simultaneously removing silicon and germanium from the side portion and the upper surface of the fin by a hydrogen radical treatment process, and the hydrogen radical treatment process is different from the etching process, the hydrogen radical treatment process removes silicon at a first rate and removes germanium at a second rate, and the second rate is less than the first rate; forming a lightly doped source / drain region in the fin, wherein an upper side portion of the lightly doped source / drain region has a first germanium concentration, a lower side portion of the lightly doped source / drain region has a second germanium concentration, and the second germanium concentration is less than the first germanium concentration; and forming a source region and a drain region in the fin, and the source region or the drain region extends into the lightly doped source / drain region.

12. The method of forming a semiconductor device as claimed in claim 11, further comprising: forming an isolation region around the fin before removing silicon and germanium.

13. The method of forming a semiconductor device as claimed in claim 11, further comprising: forming an isolation region around the fin after removing silicon and germanium.

14. The method of forming a semiconductor device as claimed in claim 11, further comprising: forming a dummy gate stack along the upper surface and the side portion of the fin before removing silicon and germanium; and replacing the dummy gate stack with a metal gate stack.

15. The method of forming a semiconductor device as claimed in claim 11, further comprising: forming a dummy gate stack along the upper surface and the side portion of the fin after removing silicon and germanium; and replacing the dummy gate stack with a metal gate stack.

16. The method of forming a semiconductor device as claimed in claim 11, wherein the radical treatment process comprises: exposing the upper surface and the side portion of the fin to a hydrogen radical, the hydrogen radical reacts with the silicon of the fin at the first rate to form silane, and the hydrogen radical reacts with the germanium of the fin at the second rate to form germane.

17. A semiconductor device, comprising: a substrate; a first semiconductor layer extending from the substrate, and the first semiconductor layer includes silicon; a second semiconductor layer located on the first semiconductor layer, and the second semiconductor layer includes silicon germanium, wherein an edge portion of the second semiconductor layer has a first germanium concentration, a central portion of the second semiconductor layer has a second germanium concentration, the second germanium concentration is less than the first germanium concentration, and the edge portion of the second semiconductor layer includes the side portion and the upper surface of the second semiconductor layer; a gate stack located on the second semiconductor layer; a plurality of lightly doped source / drain regions located in the second semiconductor layer, and the lightly doped source / drain regions are adjacent to the gate stack, wherein an upper side portion of the lightly doped source / drain regions has the first germanium concentration, and a lower side portion of the lightly doped source / drain regions has the second germanium concentration; and Multiple source and drain regions extend into the lightly doped source / drain regions.

18. The semiconductor device according to claim 17, wherein the first semiconductor layer has a first width, a lower portion of the second semiconductor layer has the first width, an upper portion of the second semiconductor layer has a second width, and the second width is less than the first width.

19. The semiconductor device according to claim 17, wherein the first semiconductor layer has a first width, an upper portion and a lower portion of the second semiconductor layer have a second width, and the second width is less than the first width.

20. The semiconductor device according to claim 17, wherein the gate stack includes: A gate dielectric layer located on the second semiconductor layer, and a lower surface of the gate dielectric layer is lower than an upper surface of the lightly doped source / drain regions; And A gate located on the gate dielectric layer.

21. A semiconductor device includes: An isolation region located on a substrate; A fin including a silicon layer and a silicon germanium layer, a lower portion of the silicon layer and the silicon germanium layer is located in the isolation region, an upper portion of the silicon germanium layer protrudes above the isolation region, and a germanium concentration of an edge portion of the upper portion of the silicon germanium layer is greater than a germanium concentration of an edge portion of the lower portion of the silicon germanium layer, wherein the germanium concentration of the edge portion of the upper portion of the silicon germanium layer is greater than a germanium concentration of a central portion of the upper portion of the silicon germanium layer; and A gate stack located on the upper portion of the silicon germanium layer.

22. The semiconductor device according to claim 21, wherein the silicon layer under the gate stack has a first width, the upper portion of the silicon germanium layer under the gate stack has a second width, and the second width is less than the first width.

23. The semiconductor device according to claim 22, wherein a lower portion of the silicon germanium layer under the gate stack has the first width.

24. The semiconductor device according to claim 21, wherein a thickness of an edge portion of the upper portion of the silicon germanium layer is from 0.5 nm to 1 nm.

25. The semiconductor device according to claim 21, further includes: A source / drain region located in the silicon germanium layer; And A spacer located between the source / drain region and the gate stack, an upper portion of the silicon germanium layer under the spacer has a first width, and an upper portion of the silicon germanium layer under the gate stack has a second width, and the first width is greater than the second width.

26. The semiconductor device according to claim 21, further includes: A source / drain region located in the silicon germanium layer; And A spacer located between the source / drain region and the gate stack, and widths of an upper portion of the silicon germanium layer under the spacer and an upper portion of the silicon germanium layer under the gate stack are the same.

27. The semiconductor device according to claim 21, wherein the germanium concentration of the edge portion of the upper portion of the silicon germanium layer is from 20% to 45%.

28. A semiconductor device includes: An isolation region located on a substrate; A fin extending from a substrate, the fin including a first semiconductor portion and a second semiconductor portion on the first semiconductor portion, the second semiconductor portion including silicon germanium, a bottom of the second semiconductor portion being lower than an upper surface of the isolation region, a top of the second semiconductor portion protruding above the upper surface of the isolation region, and a germanium concentration in a channel region at the top of the second semiconductor portion being greater than a germanium concentration at the bottom of the second semiconductor portion; A source / drain region adjacent to the channel region; and A gate stack located on the channel region.

29. The semiconductor device according to claim 28, further comprising: A lightly doped source / drain region in the second semiconductor portion, the lightly doped source / drain region being adjacent to the channel region, and a germanium concentration in an upper side portion of the lightly doped source / drain region being greater than a germanium concentration in a lower side portion of the lightly doped source / drain region.

30. The semiconductor device according to claim 29, wherein an upper surface of the lightly doped source / drain region is coplanar with an upper surface of the channel region.

31. The semiconductor device according to claim 28, further comprising: A lightly doped source / drain region in the second semiconductor portion, the lightly doped source / drain region being adjacent to the channel region, and a germanium concentration in an upper side portion of the lightly doped source / drain region being equal to a germanium concentration in a lower side portion of the lightly doped source / drain region.

32. The semiconductor device according to claim 31, wherein an upper surface of the lightly doped source / drain region is higher than an upper surface of the channel region.

33. The semiconductor device according to claim 28, wherein the germanium concentration in the channel region is from 20% to 45%.

34. The semiconductor device according to claim 28, wherein a width of the second semiconductor portion decreases at the upper surface of the isolation region.

35. A semiconductor device, comprising: A fin extending from a substrate, the fin including a first portion and a second portion on the first portion, the second portion of the fin having a lower side portion and an upper side portion above the lower side portion, a sidewall of the upper side portion of the second portion of the fin having a first germanium concentration, a sidewall of the lower side portion of the second portion of the fin and a center of the upper side portion having a second germanium concentration, and the first germanium concentration being greater than the second germanium concentration; An isolation region surrounding the lower side portion of the second portion of the fin, and the upper side portion of the second portion of the fin protruding above the isolation region; A gate stack located above the isolation region and the upper side portion of the second portion of the fin; And A source / drain region adjacent to the gate stack.

36. The semiconductor device according to claim 35, wherein the source / drain region extends partially into the second portion of the fin.

37. The semiconductor device according to claim 35, wherein the first germanium concentration is from 20% to 45%.

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