Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device includes forming a fin protruding from a substrate, the fin having multiple sacrificial layers and multiple channel layers, wherein the sacrificial layers and the channel layers are arranged alternately, removing a portion of the sacrificial layers from a channel region of the fin, depositing a spacer material in an area where the portion of the sacrificial layers has been removed, selectively removing a portion of the spacer material to expose the channel layers in the channel region of the fin, wherein other portions of the spacer material remain as spacer components, and forming a gate structure bonded to the exposed channel layers.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same, and more particularly to multi-gate semiconductor devices and methods for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth, with technological advances in integrated circuit materials and design resulting in multiple generations of integrated circuits, each with smaller and more complex circuits than the previous one. As integrated circuits evolve, as the geometry size (i.e., the smallest component or line that can be created using a manufacturing process) decreases, the functional density (i.e., the number of interconnected devices per chip area) generally increases. While this process of size reduction generally provides benefits through increased production efficiency and associated cost reductions, such size reductions also increase the complexity of the integrated circuit process and manufacturing.

[0003] Multi-gate devices have recently been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). One such multi-gate device is the gate-all-around (GAA) transistor. The GAA device derives its name from a gate structure that extends around the channel region, providing access to the channel from two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows for significant size reductions while maintaining gate control and reducing short-channel effects (SCEs). In conventional processes, GAA devices provide a channel configured using stacked nanosheets. The integration of GAA components around these stacked nanosheets is challenging. For example, in the stacked nanosheet GAA process flow, the formation of internal spacers can be a critical step in reducing capacitance and preventing leakage between the gate stack and the source / drain (S / D) region. However, misalignment of the internal spacers can introduce non-uniformity to the GAA device and can degrade the performance of the integrated chip.Thus, while current approaches are satisfactory in many respects, the challenges to the resulting device performance are not satisfactory in all respects. Summary of the Invention

[0004] According to some embodiments, a method for manufacturing a semiconductor device is provided. The method includes forming a fin protruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are arranged alternately. The method also includes removing a portion of the sacrificial layer from the channel region of the fin, and depositing a spacer material in the region where the portion of the sacrificial layer has been removed. The method also includes removing a portion of the spacer material to expose the channel layer in the channel region of the fin, wherein the remaining portion of the spacer material remains as a spacer component. The method also includes forming a gate structure bonded to the exposed channel layer.

[0005] According to some embodiments, a method for manufacturing a semiconductor device is provided. The method includes forming a stack of first and second type epitaxial layers on a semiconductor substrate, the first and second type epitaxial layers having different material compositions, and the first and second type epitaxial layers being arranged alternately in a vertical direction. The method also includes forming a dummy gate covering a portion of the stack in a channel region, and forming an external spacer layer covering the sidewalls of the dummy gate. The method also includes removing the dummy gate to form a gate trench, wherein the gate trench exposes two opposing sidewalls of the external spacer layer. The method also includes etching the second type epitaxial layer in the gate trench, and depositing a dielectric layer in the gate trench along two opposing sidewalls of the external spacer layer and surrounding the first type epitaxial layer. The method also includes performing a treatment process on a portion of the dielectric layer between the two opposing sidewalls of the external spacer layer, wherein the treatment process uses the external spacer layer as a treatment mask, and removing the portion of the dielectric layer to form an internal spacer layer. The method also includes forming a gate stack in the gate trench and surrounding the first type epitaxial layer.

[0006] According to some embodiments, a multi-gate semiconductor device is provided. The multi-gate semiconductor device includes a fin element extending upward from a substrate, and a gate structure above the fin element. The multi-gate semiconductor device also includes an epitaxial source / drain (S / D) component adjacent to the fin element. The multi-gate semiconductor device further includes a dielectric spacer between the gate structure and the epitaxial S / D component, wherein a sidewall surface of the dielectric spacer facing the gate structure has a convex shape in a plane parallel to the top surface of the substrate, and the convex shape has an apex extending toward the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To facilitate understanding of the embodiments of the present invention, the following detailed description is accompanied by accompanying drawings. It should be noted that, in accordance with standard industry practices, various features are not necessarily drawn to scale and are used for illustrative purposes only. In practice, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A and Figure 1BFlowchart of a method for forming a multi-gate semiconductor device including an internal spacer feature according to one or more aspects of an embodiment of the present invention.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A and Figure 13A According to various aspects of the present invention, Figure 1A and Figure 1B A perspective view of a semiconductor structure during a manufacturing process.

[0010] Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 13B 、 Figure 13C and Figure 13D According to various aspects of the present invention, Figure 1A and Figure 1B A schematic cross-sectional view of a semiconductor structure during a manufacturing process of the method.

[0011] Figure 14A and Figure 14B FIG. 1 is a flow chart of another method of forming a multi-gate semiconductor device including internal spacer features according to one or more aspects of an embodiment of the present invention.

[0012] Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21A 、 Figure 22A 、 Figure 23A 、 Figure 24A 、 Figure 25A and Figure 26A According to various aspects of the present invention, Figure 14A and Figure 14BA perspective view of a semiconductor structure during a manufacturing process.

[0013] Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26B 、 Figure 26C and Figure 26D According to various aspects of the present invention, Figure 14A and Figure 14B A schematic cross-sectional view of a semiconductor structure during a manufacturing process of the method.

[0014] Description of reference numerals:

[0015] 100, 1400 ~ method;

[0016] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 124, 126, 128, 1402, 1404, 1406, 1408, 1410, 1412, 1414, 1416, 1418, 1420, 1424, 1426, 1428 ~ steps;

[0017] 200, 201~ semiconductor devices;

[0018] 202~base;

[0019] 204~ epitaxial stacking;

[0020] 206, 208~ epitaxial layer;

[0021] 210~ fins;

[0022] 212~hard mask (HM) layer;

[0023] 214, 230~ oxide layer;

[0024] 216, 232~ nitride layer;

[0025] 218~groove;

[0026] 220 ~ shallow trench isolation (STI) components;

[0027] 222~dummy gate stack;

[0028] 224~dummy dielectric layer;

[0029] 226~dummy electrode layer;

[0030] 228~Hard mask;

[0031] 234~spacer material layer (sidewall spacer); S 234 ~ side wall;

[0032] 236~dielectric material layer;

[0033] 238~Extended S / D components;

[0034] 240~interlayer dielectric (ILD) layer;

[0035] 242~Contact Etch Stop Layer (CESL);

[0036] 246~gate trench;

[0037] 248~gap;

[0038] 252~internal spacer material layer;

[0039] 252a~middle part;

[0040] 252b~ part (internal spacer);

[0041] 260~Processing technology;

[0042] 264, 266~ area;

[0043] 268~apex;

[0044] 280~HK MG stack (gate structure);

[0045] 282~interface layer;

[0046] 284~high-K gate dielectric layer;

[0047] 286~gate electrode layer;

[0048] 298~gap;

[0049] d1, d2 ~ distance;

[0050] d3~thickness;

[0051] d4~extra width. DETAILED DESCRIPTION

[0052] The following content provides many different embodiments or examples to implement the different features provided by the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the following description refers to forming a first component above or on a second component, which may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the embodiments of the present invention may repeat reference numerals and / or letters in each example. This repetition is for the purpose of simplicity and clarity and is not itself used to specify the relationship between the various embodiments and / or configurations discussed.

[0053] In addition, in order to easily describe the relationship between one element or component and another element or component of the illustrated embodiments of the present invention, spatial relative terms may be used herein, such as "below", "beneath", "lower", "above", "above", "higher" and other derivatives of spatial relative terms. These spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the figures. The device can be positioned in other orientations (rotated 90 degrees or in other orientations), and the spatial relative terms used in this description should be interpreted accordingly. In addition, when "about", "approximately", etc. are used to describe a number or a range of numbers, unless otherwise specified, the meaning of such terms should include numbers within + / -10% of the stated number. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0054] Embodiments of the present invention generally relate to semiconductor devices and manufacturing methods, and more particularly to the manufacture of gate-all-around (GAA) transistors with self-aligned internal spacers. It should also be noted that embodiments of the present invention present embodiments in the form of multi-gate transistors, which include those transistors in which gate structures are formed on at least two sides of a channel region. These multi-gate semiconductor devices may include p-type metal oxide semiconductor devices or n-type metal oxide semiconductor devices. Due to the fin-like structure of these multi-gate semiconductor devices, specific examples can be presented and they are referred to herein as fin field effect transistors (FINFETs). Also presented herein are embodiments of multi-gate transistors referred to as gate-all-around (GAA) devices, which include any device having a gate structure or a portion thereof formed on four sides of a channel region (e.g., surrounding a portion of a channel region). The devices presented herein also include embodiments having a channel region arranged in a nanowire channel, a strip channel, and / or other suitable channel configurations. Presented herein are embodiments of devices that may have one or more channel regions (e.g., multiple nanowires) associated with a single continuous gate structure. However, one skilled in the art will appreciate that this teaching can be applied to a single channel (e.g., a single nanowire) or any number of channels. One skilled in the art will appreciate that other examples of semiconductor devices can also benefit from various aspects of the present invention.

[0055] As the fin width in FinFETs decreases in size, changes in channel width can lead to undesirable variations and mobility losses. GAA transistors, such as nanosheet transistors, are currently being studied as alternatives to FinFETs. In a nanosheet transistor, the gate of the transistor is fabricated completely around the channel (e.g., a nanowire channel or a strip channel), so that the channel is surrounded or sealed by the gate. This transistor has the advantage of improved electrostatic control of the channel via the gate, which also reduces leakage current. A nanosheet transistor includes internal spacers and sidewall spacers (also called external spacers), as well as other components. The internal spacers are typically formed by a process additional to the sidewall spacers. For example, after fabricating the sidewall spacers and epitaxially growing the source / drain (S / D) components, space for the internal spacers is created by wet or vapor etching removal. The internal spacers are then formed by deposition of a dielectric material. However, during wet or vapor etching removal, for example due to loading effects, fine control of the spacing of the internal spacers can be challenging. Therefore, the resulting internal spacers may have non-uniform sizes across different layers of the nanosheet, further leading to channel length variations. An object of embodiments of the present invention is to design a self-aligned internal spacer formation method to precisely control the size and position of the internal spacers and improve the uniformity of the channel length across different layers of the nanosheet.

[0056] Figure 1A and Figure 1B Illustrated is a method 100 for fabricating a multi-gate semiconductor device. The term "multi-gate device" as used herein describes a device (e.g., a semiconductor transistor) having at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, the multi-gate device may be referred to as a GAA device or a nanosheet device, having gate material disposed on at least four sides of at least one channel of the device. The channel region may be referred to as a "nanowire," and the term "channel region" as used herein encompasses channel regions of various geometries (e.g., cylindrical, bar-shaped) and various sizes.

[0057] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A and Figure 13A is based on Figure 1A and Figure 1B A perspective view of an embodiment of a semiconductor device 200 at various stages of method 100 is provided. Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B and Figure 13B is along the first tangent (e.g., Figure 8A BB in FIG), a corresponding cross-sectional view of an embodiment of the semiconductor device 200, which is along the length direction of the channel and perpendicular to the top surface of the substrate. Figure 8C 、 Figure 9C 、 Figure 10C 、 Figure 11C 、 Figure 12C and Figure 13C is along the second tangent (e.g., Figure 8A A corresponding cross-sectional view of an embodiment of the semiconductor device 200 is taken along the cut line CC in FIG. 2 , which is located in the gate region and perpendicular to the length direction of the channel. Figure 8D 、 Figure 9D 、 Figure 10D 、 Figure 11D 、 Figure 12D and Figure 13D is along the third tangent (e.g., Figure 8A DD in FIG), a corresponding cross-sectional view of an embodiment of the semiconductor device 200, which is along the length direction of the channel and parallel to the top surface of the substrate.

[0058] As with other method embodiments and exemplary devices discussed herein, it should be understood that some portions of the semiconductor device 200 may be fabricated using a CMOS technology process flow, and therefore only some processes are briefly described herein. In addition, the exemplary semiconductor device may include various other devices and components, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM), and / or other logic circuits, but are simplified for a better understanding of the inventive concepts of the embodiments of the present invention. In some embodiments, the exemplary device includes a plurality of semiconductor devices (e.g., transistors), including P-type field effect transistors (PFETs), N-type field effect transistors (NFETs), etc., which may be interconnected. In addition, it should be noted that the process steps of method 100 include reference to Figure 2-13D Any description thereof, and the rest of the methods and exemplary drawings provided in the embodiments of the present invention are merely exemplary and are not intended to limit them beyond the contents specifically stated in the appended patent claims.

[0059] refer to Figure 1A , method 100 begins at step 102, where a substrate is provided. Figure 2In an embodiment of step 102, a substrate 202 is provided. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon substrate. The substrate 202 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. According to design requirements known in the technical field to which the present invention belongs, the substrate 202 may include various doping configurations. For example, different doping profiles (e.g., n-type wells, p-type wells) may be formed on the substrate 202 in areas designed for different device types (e.g., n-type field effect transistors (NFETs), p-type field effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 202 may have isolation features (e.g., shallow trench isolation (STI) features) between areas providing different device types. The substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. In addition, the substrate 202 may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 202 may optionally include an epitaxial layer (epi-layer), which may be strained to improve performance, may include a silicon-on-insulator (SOI) structure, and / or may have other suitable enhancement features.

[0060] In one embodiment of method 100, an anti-junction punchthrough (APT) implant is performed in step 102. For example, an APT implant may be performed in a region below a channel region of a device to prevent junction punchthrough or undesired diffusion.

[0061] Back to Figure 1A Then, the method 100 proceeds to step 104, where one or more epitaxial layers are grown on the substrate. Figure 2 As an example, in an embodiment of step 104, an epitaxial stack 204 is formed on a substrate 202. The epitaxial stack 204 includes epitaxial layers 206 of a first composition and epitaxial layers 208 of a second composition interposed between the epitaxial layers 206. The first composition and the second composition may be different. In one embodiment, the epitaxial layers 206 are silicon germanium (SiGe) and the epitaxial layers 208 are silicon (Si). However, other embodiments are possible, including those that provide first and second compositions with different oxidation rates and / or etch selectivities. In some embodiments, the epitaxial layers 206 include SiGe and the epitaxial layers 208 include Si, and the Si oxidation rate of the epitaxial layers 208 is less than the SiGe oxidation rate of the epitaxial layers 206.

[0062] Epitaxial layer 208, or a portion thereof, can form a nanosheet channel of multi-gate semiconductor device 200. As used herein, the term nanosheet is intended to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions having circular and substantially circular cross-sections, as well as beam or strip-shaped material portions having, for example, cylindrical or substantially rectangular cross-sections. The use of epitaxial layer 208 to define one or more channels of a device is discussed further below.

[0063] It should be noted that if Figure 2 The illustrated alternating arrangement of seven epitaxial layers 206 and six epitaxial layers 208 is for illustrative purposes only and is not intended to limit the present invention beyond the specific description of the claims. It will be appreciated that any number of epitaxial layers may be formed in epitaxial stack 204, depending on the number of channel regions desired for semiconductor device 200. In some embodiments, the number of epitaxial layers 208 is between two and ten.

[0064] In some embodiments, the thickness of each epitaxial layer 206 ranges from approximately 2 nanometers (nm) to approximately 6 nm. The thickness of the stacked epitaxial layers 206 is substantially uniform. However, in the illustrated embodiment, the top epitaxial layer 206 is thinner than the other underlying epitaxial layers 206 (e.g., half the thickness of the other epitaxial layers 206). The top epitaxial layer 206 serves as a capping layer, protecting the other epitaxial layers during subsequent processing. In some embodiments, the thickness of each epitaxial layer 208 ranges from approximately 6 nm to approximately 12 nm. In some embodiments, the thickness of the stacked epitaxial layers 208 is substantially uniform. As described in more detail below, the epitaxial layers 208 may serve as channel regions for a subsequently formed multi-gate semiconductor device, and their thickness is selected based on device performance considerations. The epitaxial layers 206 in the channel regions may eventually be removed and used to define the vertical distance between adjacent channel regions of a subsequently formed multi-gate semiconductor device, and their thickness is selected based on device performance considerations. Therefore, the epitaxial layers 206 may also be referred to as sacrificial layers, and the epitaxial layers 208 may also be referred to as channel layers.

[0065] For example, the epitaxial growth of each layer of epitaxial stack 204 can be performed via a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth process. In some embodiments, the epitaxially grown layers, such as epitaxial layer 208, comprise the same material as substrate 202. In some embodiments, the epitaxially grown layers 206 and 208 comprise a different material than substrate 202. As described above, in at least some examples, epitaxial layer 206 comprises an epitaxially grown silicon germanium (SiGe) layer, and epitaxial layer 208 comprises an epitaxially grown silicon (Si) layer. In addition, in some embodiments, any of the epitaxial layers 206 and 208 may include other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. As discussed above, the materials of the epitaxial layers 206 and 208 may be selected based on providing different oxidation rates and etching selectivity characteristics. In some embodiments, the epitaxial layers 206 and 208 are substantially free of dopants (i.e., having a thickness from about 0 cm -3 to about 1×10 17 cm -3 of the extrinsic dopant concentration), wherein no intentional doping is performed, for example, during the epitaxial growth process.

[0066] Then, the method 100 proceeds to step 106 to form fin elements (referred to as fins) by patterning. Figure 3In an embodiment of step 106, a plurality of fins 210 are formed extending from the substrate 202. In various embodiments, each fin 210 includes a substrate portion formed from the substrate 202 and a portion of each epitaxial layer of the epitaxial stack including epitaxial layers 206 and 208. The fins 210 can be manufactured using a suitable process, including a double patterning or multiple patterning process. Generally speaking, the double patterning or multiple patterning process combines photolithography and self-alignment processes, which enables the resulting pattern to have, for example, a smaller pitch than that which can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed on the sides of the patterned sacrificial layer using a self-alignment process, and the sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins 210 by etching the initial epitaxial stack 204. The etching process can include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes.

[0067] In the illustrated embodiment, a hard mask (HM) layer 212 is formed over the epitaxial stack 204 before patterning the fins 210. In some embodiments, the HM layer 212 includes an oxide layer 214 (e.g., a pad oxide layer that may include SiO2) and a nitride layer 216 (e.g., a pad nitride layer that may include Si3N4) formed on the oxide layer 214. The oxide layer 214 may serve as an adhesion layer between the epitaxial stack 204 and the nitride layer 216 and may serve as an etch stop layer for etching the nitride layer 216. In some examples, the HM layer 212 includes a thermally grown oxide, an oxide deposited by chemical vapor deposition (CVD), and / or an oxide deposited by atomic layer deposition (ALD). In some embodiments, the HM layer 212 includes a nitride layer deposited by CVD and / or other suitable techniques.

[0068] The fins 210 may then be fabricated using a suitable process including a photolithography and etching process, the photolithography process including forming a photoresist layer (not shown) on the HM layer 212, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask element comprising the photoresist. In some embodiments, the patterning of the photoresist may be performed using an electron beam (e-beam) lithography process to form the mask element. The mask element may then be used to protect areas of the substrate 202 and layers formed thereon, and an etching process may be performed to form trenches 218 through the HM layer 212, through the epitaxial stack 204, and into the substrate 202 in the unprotected areas, thereby leaving a plurality of extended fins 210. The trenches 218 may be etched using dry etching (e.g., reactive ion etching), wet etching, and / or a combination thereof.

[0069] Fins may also be formed on a substrate using many other embodiments, including, for example, defining fin regions (e.g., via masks or isolation regions) and epitaxially growing epitaxial stack 204 in the form of fins 210. In some embodiments, forming fins 210 may include a trimming process to reduce the width of fins 210. The trimming process may include a wet and / or dry etching process.

[0070] refer to Figure 1A and Figure 4 , method 100 proceeds to step 108 to form shallow trench isolation (STI) features 220 between fins 210. For example, in some embodiments, a dielectric layer is first deposited on substrate 202 to fill trenches 218 with a dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations of the foregoing, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, and / or other suitable processes. In some embodiments, after depositing the dielectric layer, the semiconductor device 200 may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer (and subsequently formed STI features 220 ) may comprise a multi-layer structure, for example, having one or more liner layers.

[0071] In some embodiments of forming shallow trench isolation (STI) features, after depositing the dielectric layer, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. In some embodiments, the HM layer 212 ( Figure 3 ) as a CMP stop layer. Figure 4 In an example, the STI features 220 between the fins 210 are recessed, and the STI features 220 are recessed to provide the fins 210 extending above the STI features 220. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and / or a combination of the foregoing. The HM layer 212 may also be removed before, during, and / or after the recessing of the STI features 220, for example, the HM layer 212 may be removed by a wet etching process using H3PO4 or other suitable etchant. In some embodiments, the HM layer 212 is removed by the same etchant used to recess the STI features 220. In some embodiments, the depth of the recess is controlled (e.g., by controlling the etching time) to produce a desired height of the exposed upper portion of the fin 210. In the illustrated embodiment, the desired height exposes each layer of the epitaxial stack 204.

[0072] Then, the method 100 proceeds to step 110 to form a sacrificial layer or sacrificial component, particularly a dummy gate structure. Although the present embodiment is discussed with respect to a replacement gate process, and thus a dummy gate structure is formed and subsequently replaced, other configurations are possible.

[0073] refer to Figure 5 , forming a gate stack 222. In one embodiment, the gate stack 222 is a dummy (sacrificial) gate stack, which is subsequently removed (see step 118). Therefore, in some embodiments using a gate-last process, the gate stack 222 is a dummy gate stack and will be replaced by a final gate stack in a subsequent process stage of the semiconductor device 200. In detail, as described below, the dummy gate stack 222 can be replaced with a high dielectric constant (K) dielectric layer (HK) and a metal gate electrode (MG) in a later process stage. In some embodiments, the dummy gate stack 222 is formed above the substrate 202 and is at least partially disposed above the fin 210. The portion of the fin 210 located below the dummy gate stack 222 can be referred to as a channel region. The dummy gate stack 222 can also define the source / drain (S / D) region of the fin 210, such as the region of the fin 210 adjacent to the channel region and on both sides of the channel region.

[0074] In the illustrated embodiment, step 110 first forms a dummy dielectric layer 224 on the fin 210. In some embodiments, the dummy dielectric layer 224 may include SiO2, silicon nitride, a high-k dielectric material, and / or other suitable materials. In various examples, the dummy dielectric layer 224 may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. For example, the dummy dielectric layer 224 may be used to prevent damage to the fin 210 during subsequent processes (e.g., the subsequent formation of a dummy gate stack). Subsequently, step 110 forms the remaining portions of the dummy gate stack 222, including a dummy electrode layer 226 and a hard mask 228. The hard mask 228 may include multiple layers 230 and 232 (e.g., an oxide layer 230 and a nitride layer 232). In some embodiments, the dummy gate stack 222 is formed by various process steps, such as layer deposition, patterning, etching, and other suitable process steps. Example layer deposition processes include CVD (including low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques, or combinations thereof. When forming the gate stack, for example, the patterning process includes a photolithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the dummy electrode layer 226 may include polysilicon. In some embodiments, the hard mask 228 includes an oxide layer 230, such as a pad oxide layer that may include SiO2. In some embodiments, the hard mask 228 includes a nitride layer 232, such as a pad nitride layer that may include Si3N4, silicon oxynitride, and / or silicon carbide.

[0075] Still refer to Figure 5 In some embodiments, after forming the dummy gate stack 222, the dummy dielectric layer 224 is removed from the S / D regions of the fin 210. The etching process may include wet etching, dry etching, and / or a combination thereof. The etching process is selected to selectively etch the dummy dielectric layer 224 while substantially not etching the fin 210, the hard mask 228, and the dummy electrode layer 226.

[0076] Reference Figure 1A and Figure 6, the method 100 then proceeds to step 112, where a spacer material layer is deposited on the substrate. The spacer material layer can be a compliant layer that is subsequently etched back to form sidewall spacers. In the illustrated embodiment, the spacer material layer 234 is conformally disposed on the top and sidewalls of the dummy gate stack 222. The term "conformally" may be used herein to describe a layer having substantially the same thickness in various regions. The spacer material layer 234 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the spacer material layer 234 comprises multiple layers, such as main spacer walls, a liner layer, and the like. For example, the spacer material layer 234 may be formed by depositing a dielectric material over the dummy gate stack 222 using, for example, a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. It should be noted that in the illustrated embodiment, for example, during the ALD process, the spacer material layer 234 also conformally covers the sidewalls of the fins 210 in the exposed S / D regions and partially fills the spaces between adjacent fins 210. If gaps remain between adjacent fins 210 after filling the spacer material layer 234, step (block) 112 may further deposit other dielectric materials, such as a dielectric material layer 236, to fill the gaps between adjacent fins 210 in the S / D regions. The dielectric material layer 236 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In various embodiments, the spacer material layer 234 and the dielectric material layer 236 include different material compositions, for example, the spacer material layer 234 includes silicon nitride and the dielectric material layer 236 includes silicon carbide.

[0077] Step 112 may then be followed by a non-isotropic etching process to expose portions of the fin 210 (e.g., in the source / drain regions) adjacent to and not covered by the dummy gate stack 222. This non-isotropic etching process may completely remove portions of the spacer material layer directly above the dummy gate stack 222. Portions of the spacer material layer may remain on the sidewalls of the dummy gate stack, forming sidewall spacers, which are represented as sidewall spacers 234 for simplicity.

[0078] Still refer to Figure 1A and Figure 6, the method 100 then proceeds to step 114 where epitaxial S / D features 238 are formed on the substrate. The epitaxial S / D features 238 may be formed by performing an epitaxial growth process that provides epitaxial material on the fins 210 in the source / drain regions. During the epitaxial growth process, the dummy gate stack 222 and the sidewall spacers 234 confine the epitaxial S / D features 238 to the S / D regions. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. The epitaxial growth process may use gaseous and / or liquid precursors that interact with the composition of the substrate 102. In some embodiments, the epitaxial S / D features 238 grown on adjacent semiconductor fins 210 are spaced apart from each other. In some embodiments, the epitaxial S / D features 238 are grown in a merged manner, e.g. Figure 6 In the illustrated embodiment, the height of the fin 210 in the source / drain region is also recessed prior to epitaxially growing the epitaxial S / D features 238. As an example, the fin 210 in the source / drain region may become equal to or lower than the top surface of the STI features 220, and the epitaxial S / D features 238 may extend upward from the top surface of the fin 210 to a height above the STI features 220.

[0079] In various embodiments, epitaxial S / D features 238 may comprise Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. Epitaxial S / D features 238 may be in-situ doped during the epitaxial growth process by introducing dopants including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If epitaxial S / D features 238 are not doped in-situ, an implantation process (i.e., a junction implantation process) may be performed to dope epitaxial S / D features 238. In exemplary embodiments, epitaxial S / D features 238 in NMOS devices comprise SiP, and epitaxial S / D features 238 in PMOS devices comprise GeSnB and / or SiGeSnB. Furthermore, silicide or silicon-germanide may be formed on epitaxial S / D features 238. For example, a silicide, such as nickel silicide, can be formed by depositing a metal layer on the epitaxial S / D features 238, annealing the metal layer so that the metal layer reacts with silicon in the epitaxial S / D features 238 to form a metal silicide, and then removing the unreacted metal layer.

[0080] Reference Figure 1A and Figure 7Method 100 then proceeds to step 116 where an interlayer dielectric (ILD) layer 240 is formed on the substrate. In some embodiments, a contact etch stop layer (CESL) 242 is formed before forming the ILD layer 240. In some examples, the CESL comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL can be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 240 comprises, for example, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 240 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 240 , the semiconductor device 200 may be subjected to a high thermal budget process to anneal the ILD layer.

[0081] In some examples, after the ILD layer is deposited, a planarization process may be performed to remove excess dielectric material. For example, the planarization process includes a chemical mechanical planarization (CMP) process that removes portions of the ILD layer 240 (and CESL, if present) covering the dummy gate stack 222 and planarizes the top surface of the semiconductor device 200. In some embodiments, the CMP process also removes the hard mask 228 ( Figure 6 ), and expose the dummy electrode layer 226.

[0082] Then, the method 100 proceeds to step 118 ( Figure 1B ), by removing the dummy gate stack 222, a gate trench 246 is formed in the channel region, and the resulting structure is as shown Figures 8A-8D As shown, Figure 8A is a perspective view of a semiconductor device 200. Figure 8B is a cross-sectional view taken along the length direction of the channel (e.g., along line BB), Figure 8Cis a cross-sectional view taken in the channel region and perpendicular to the length direction of the channel (e.g., along line CC), Figure 8D is a cross-sectional view taken through one of the epitaxial layers 206 and parallel to the top view (e.g., along line DD). As described below, a final gate structure (e.g., including a high-K dielectric layer and a metal gate electrode) can then be formed in the gate trench 246. Step 118 can include one or more etching processes that are selective to the materials in the dummy gate stack 222. For example, a selective etching process, such as a selective wet etch, a selective dry etch, or a combination thereof, can be used to perform the removal of the dummy gate stack 222. The epitaxial layers 206 and 208 of the fin 210 are exposed in the gate trench 246, and the two opposing sidewalls S of the sidewall spacer 234 are exposed. 234 It is also exposed in the gate trench 246 .

[0083] Then, the method 100 proceeds to step 120 ( Figure 1B ), the epitaxial layer 206 is removed from the fin 210 in the gate trench 246. The resulting structure is Figures 9A-9D As shown in Figures 9A-9D 1 and 2 are perspective views and cross-sectional views of the semiconductor device 200 along lines BB, CC, and DD, respectively. In one embodiment, the epitaxial layer 206 is removed by a selective wet etching process. In one embodiment, the epitaxial layer 206 is SiGe and the second epitaxial layer 208 is silicon, which allows for selective removal of the epitaxial layer 206. In some embodiments, the selective wet etching comprises an APM etch (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal comprises oxidation of SiGe followed by removal of SiGeO. x For example, oxidation can be provided by an O3 clean followed by removal of SiGeO via an etchant such as NH4OH. x It should be noted that, as shown in the figure, due to the removal process of the epitaxial layer 206, the second epitaxial layer 208 (e.g., nanowire) has a substantially circular shape (e.g., cylindrical). It should be noted that during the temporary process phase of step 120, gaps 248 are provided between adjacent nanowires in the channel region (e.g., gaps 248 between the epitaxial layers 208). The gaps 248 can be filled with ambient material (e.g., air, nitrogen).

[0084] Then, the method 100 proceeds to step 122 ( Figure 1B ), a dielectric material layer 252 is deposited in the gate trench 246. More details are shown below, and the dielectric material layer 252 is etched to form an inner spacer feature. Therefore, the dielectric material layer 252 is also referred to as the inner spacer material layer 252. The resulting structure is as shown in FIG. Figures 10A-10D As shown, Figures 10A-10DThe inner spacer material layer 252 is deposited on two opposite sidewalls S of the sidewall spacer 234. 234 On and above the substrate 202, an inner spacer material layer 252 also wraps around each epitaxial layer 208 in the channel region. The inner spacer material layer 252 can fill the gap 248 provided by the removal of the epitaxial layer 206 described in step 120 above. The inner spacer material layer 252 can include a dielectric material, such as SiN, SiOC, SiOCN, SiCN, SiO2 and / or other suitable materials. In various embodiments, the sidewall spacers 234 and the inner spacer material layer 252 include different material compositions, such as the sidewall spacers 234 including SiN and the inner spacer material layer 252 including SiOC. It should be noted that in the illustrated embodiment, the inner spacer material layer 252 is conformally deposited on the sidewalls S of the sidewall spacers 234 via, for example, an ALD process. 234 On each nanowire of the fin 210 in the upper and channel regions.

[0085] Then, the method 100 proceeds to step 124 ( Figure 1B ), a treatment process 260 is performed. In various embodiments, the treatment process 260 passes through the gate trench 246 using the sidewall spacers 234 as a treatment mask. The resulting structure is as shown in FIG. Figures 11A-11D As shown, Figures 11A-11D The two opposite sidewalls S of the sidewall spacer 234 are respectively a perspective view of the semiconductor device 200 and a cross-sectional view along lines BB, CC, and DD. 234A central portion of the inner spacer material layer 252 (designated as portion 252a) is subjected to treatment process 260, resulting in a change in its material composition such that it exhibits etch selectivity compared to other portions of the inner spacer material layer 252 (designated as portion 252b). In some embodiments, treatment process 260 comprises oxygen (O2) ashing, such as plasma oxygen ashing. During plasma oxygen ashing, oxygen radicals react with components in the central portion 252a, such as carbon, hydrogen, sulfur, and nitrogen, to produce volatile oxides of the respective components. In a specific example, the inner spacer material layer 252 comprises SiCN. During plasma oxygen ashing, carbon and nitrogen are released from the central portion 252a in the form of carbon oxides and nitrogen oxides, while silicon is oxidized and remains in the central portion 252a in the form of silicon oxide. In contrast, in portion 252b, which is covered by sidewall spacers 234 and not subjected to treatment process 260, the SiCN is substantially retained. Consequently, etch selectivity exists between portions 252a and 252b. As described in further detail below, portion 252a will subsequently be removed in a selective etching process, and portion 252b will remain as an internal spacer. In some embodiments, plasma oxygen ashing includes a gaseous combination of C2F6 and O2 in a first ashing step, followed by pure O2 in a second ashing step. The gaseous combination of C2F6 and O2 is more effective than pure O2 in removing ions, if any, from the dielectric material layer. Similarly, plasma oxygen ashing can include a gaseous combination of CF4 and O2 in a first plasma ashing step, followed by a pure O2 plasma in a second step to complete the ashing process.

[0086] In some embodiments, the treatment process 260 includes a nitrogen treatment, such as a nitrogen plasma treatment. During the nitrogen plasma treatment, oxygen in the middle portion 252a is released, and the oxide component is converted into a nitride component. In a specific example, the inner spacer material layer 252 includes silicon oxide, which releases oxygen and is converted into silicon nitride after the nitrogen plasma treatment. The nitrogen plasma treatment can use a pure nitrogen plasma source, or a N2 and O2 mixture source having a volume ratio of N2 to O2 of about 60:1 to about 90:1. The nitrogen plasma treatment includes exposure to a plasma source for about 10 to 50 seconds at a temperature of about 350°C to about 450°C and a power of about 180 to about 220 watts under a vacuum of about 4 to 8 Torr.

[0087] In some embodiments, treatment process 260 includes an annealing process. The annealing process can weaken bonds within the molecular structure or even create dangling bonds, which helps release components such as carbon, nitrogen, sulfur, hydrogen, and oxygen. In at least some embodiments, semiconductor device 200 is exposed to a temperature ranging from approximately 500°C to approximately 800°C for approximately 0.5 to approximately 2 hours. If the annealing process is below 500°C, in some cases, component release may be insufficient. If the annealing process is above 800°C, in some cases, device performance variations may increase due to dopant diffusion. The annealing process can further include water vapor or steam as an oxidant at a pressure of approximately 1 atmosphere. In a specific example, inner spacer material layer 252 includes SiOC, where the annealing process weakens carbon bonds and further releases carbon in the form of carbon oxides. After the annealing process, central portion 252a primarily comprises silicon oxide, while SiOC in portion 252b remains substantially unchanged.

[0088] refer to Figure 11B , for detailed illustration, region 264 of the cut along line BB, which includes the interface between portions 252a and 252b, is magnified. Portion 252a may extend into the area directly below sidewall spacer 234, for example due to diffusion during processing 260. Thus, the interface between portions 252a and 252b cut along line BB may have a curved shape. In some embodiments, portion 252a may extend into portion 252b by a distance d1 of about 0.5 nm to about 5 nm. Figure 11D , for detailed illustration, the region 266 cut along line DD is enlarged, which includes the interface between portions 252a and 252b. Similarly, in some embodiments, portion 252a may extend beyond the sidewall surface S of sidewall spacer 234 in the Y direction, for example due to diffusion. 234 The distance d2 is about 0.5 nm to about 5 nm. The inventors of the present invention have observed that, from a top view, diffusion is more likely to occur in areas closer to sidewall spacer 234. Therefore, the interface between portions 252a and 252b cut along line DD can have two curved segments, the vertex of which intersects approximately in the middle of the width of portion 252b (width along the X direction). In some embodiments, distance d1 is equal to distance d2.

[0089] Then, the method 100 proceeds to step 126 ( Figure 1B ), which selectively removes the middle portion 252a of the inner spacer material layer 252. The resulting structure is as shown Figures 12A-12D As shown, Figures 12A-12D3D images of semiconductor device 200 and cross-sectional views along lines BB, CC, and DD, respectively. In various embodiments, central portion 252a is removed during an etching process that is tuned to be selective for central portion 252a and substantially leave portion 252b unetched. The etching process may include wet etching, dry etching, reactive ion etching, or other suitable etching methods. For example, the dry etching process may be performed using an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid (DHF), a potassium hydroxide (KOH) solution, ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH), or other suitable wet etchants. In a specific example, the middle portion 252a comprises nitride, and the etching process is a wet etching process using H3PO4 or other suitable etchant. After removing the middle portion 252a, a gap 248 appears between adjacent nanowires in the channel region (i.e., the epitaxial layer 208). Along the Y direction, one end of the portion 252b abuts the epitaxial S / D component 238, and the other end of the portion 252b faces the gate trench 246 and the gap 248. As described in further detail below, a high-k dielectric layer and a metal gate (HKMG) will be formed in the gate trench 246 and abut the portion 252b. Therefore, the portion 252b provides isolation between the HKMG and the epitaxial S / D component 238. Therefore, the portion 252b is also referred to as an inner spacer 252b.

[0090] The enlarged area 264 is Figure 12B As shown in FIG, after removing the middle portion 252a, the inner spacer 252b has a concave surface facing the gate trench 246 and the gap 248 cut along the BB line. The concave surface extends inward toward the epitaxial S / D feature 238. In some embodiments, the concave surface has a distance (depth) d1 of about 0.5 nm to about 5 nm. Similarly, the enlarged region 266 is Figure 12DAs shown in FIG, after removing the middle portion 252a, the inner spacer 252b has a convex surface facing the gate trench 246 and the gap 248 cut along the DD line. The convex surface includes two curved segments that intersect at a vertex 268, which is approximately midway along the width of the portion 252b (width along the X direction). Vertex 268 extends outward toward the gate trench 246 and the gap 248, while the two curved segments on either side of vertex 268 curve inward away from the gate trench 246 and the gap 248. In some embodiments, the convex surface has a distance (height) d2 of approximately 0.5 nm to approximately 5 nm. In some embodiments, distance d1 is equal to distance d2. The thickness d3 of portion 252b is defined as the distance along the Y direction from vertex 268 to the epitaxial S / D feature 238. In some embodiments, thickness d3 is approximately the same as the thickness of the sidewall spacer 234. Thickness d3 can be between approximately 5 nm and approximately 12 nm.

[0091] Because the dimensions of the inner spacers 252b are primarily defined by the sidewall spacers 234, which cover the inner spacers 252b and shield them from the previous processing steps 260, each inner spacer 252b has substantially the same dimensions from top to bottom due to the compliant thickness of the sidewall spacers 234. Compared to conventional etching processes for forming the inner spacers 252b, the inner spacers 252b at lower layers (e.g., closer to the substrate 202) may become larger than the inner spacers 252b in upper layers, for example, due to a loading effect during the etching process. In the illustrated embodiment, the inner spacers 252b having substantially the same dimensions improve device uniformity, such as uniform gate length of the HKMG formed in the gate trench 246 in a subsequent step.

[0092] Then, the method 100 proceeds to step 128 ( Figure 1B ), forming a gate structure. The resulting structure is as follows Figures 13A-13D As shown, Figures 13A-13D 1 and 2 are perspective views and cross-sectional views along lines BB, CC, and DD of semiconductor device 200, respectively. The gate structure may be a gate of a multi-gate transistor. The gate structure may be a high-K dielectric layer / metal gate (HKMG) stack, although other compositions are also possible. In some embodiments, the gate structure forms a gate associated with multiple channels provided by multiple nanowires in the channel region (now with gaps therebetween).

[0093] In one embodiment of step 128, a HKMG stack 280 is formed in a trench of the semiconductor device 200, the trench being provided by removing a middle portion (i.e., middle portion 252a) of the inner spacer material layer 252 and / or releasing the nanowires 208, as previously described with reference to step 126. In various embodiments, the HKMG stack 280 includes an interfacial layer 282, a high-K gate dielectric layer 284 formed on the interfacial layer, and / or a gate electrode layer 286 formed on the high-K gate dielectric layer 284. The high-K gate dielectric layer 284 used and described herein comprises a dielectric material having a high dielectric constant, for example, a dielectric material having a dielectric constant greater than that of thermal silicon oxide (approximately 3.9). The gate electrode layer 286 used within the HKMG stack 280 may comprise a metal, a metal alloy, or a metal silicide. Furthermore, the formation of the HKMG stack 280 may include deposition to form various gate materials and one or more liner layers, as well as one or more CMP processes to remove excess gate material and thereby planarize the top surface of the semiconductor device 200. Providing isolation between the HKMG stack 280 and the epitaxial S / D features 238 is an inner spacer 252b. Because the dimensions of the inner spacer 252b are uniform from the top to the bottom of the semiconductor device 200, gate length uniformity is improved.

[0094] In some embodiments, the interfacial layer 282 of the HKMG stack 280 may include a dielectric material, such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer 282 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer 284 of the high-K / metal gate stack 280 may include a high-K dielectric material, such as hafnium oxide (HfO2). In addition, the high-K gate dielectric layer 284 of the HKMG stack 280 may include other high-K dielectric materials, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer 284 may be formed by ALD, PVD, CVD, oxidation, and / or other suitable methods. Figure 13DAs shown, in some embodiments, the high-k gate dielectric layer 284 is conformally deposited on the sidewalls of the inner spacer 252b and the sidewall spacer 234. Therefore, the high-k gate dielectric layer 284 may also have a convex surface with its apex extending outward toward the gate electrode layer 286.

[0095] The gate electrode layer 286 of the HKMG stack 280 can include a single layer or multiple layers, such as various combinations of a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or a metal silicide. For example, the gate electrode layer 286 of the HKMG stack 280 can include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In various embodiments, the gate electrode layer 286 of the HKMG stack 280 can be formed using ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, the gate electrode layer 286 can be formed separately for NFET and PFET transistors, which can use different metal layers (e.g., to provide an N-type or P-type work function). In various embodiments, a CMP process may be performed to remove excess metal from the gate electrode layer 286 of the HK MG stack 280, thereby providing a substantially planar top surface of the HK MG stack 280. The HK MG stack 280 includes a portion between each epitaxial layer (nanowire) 208, which forms a channel of the multi-gate semiconductor device 200.

[0096] The semiconductor device 200 may undergo further processes to form various components and regions known in the art to which the present invention pertains. For example, subsequent processes may form contact openings, contact metal, and various contacts / vias / lines and multi-layer interconnect structures (e.g., metal layers and interlayer dielectrics) on the substrate 202, which are configured to connect the various components to form a functional circuit, which may include one or more multi-gate semiconductor devices. In further illustration of the examples, the multi-layer interconnects may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnect structures may be made of various conductive materials, including copper, tungsten, and / or silicide. In one example, a copper-related multi-layer interconnect structure is formed using a damascene and / or dual damascene process. In addition, additional process steps may be performed before, during, and after the method 100, and some of the process steps described above may be replaced or eliminated according to various embodiments of the method 100.

[0097] Now refer to Figure 14A and Figure 14B, which illustrates a method 1400 for fabricating a multi-gate semiconductor device. Method 1400 is substantially similar to method 100 in many respects, and the description of method 100 above also applies to method 1400. Embodiments of method 1400 additionally begin with a bottom sacrificial layer that is thicker than other sacrificial layers above it, which will be replaced by an inner sidewall material layer to provide better isolation between the gate stack and the S / D components, and between the substrate and the S / D components, as will be discussed in further detail below.

[0098] Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21A 、 Figure 22A 、 Figure 23A 、 Figure 24A 、 Figure 25A and Figure 26A is based on Figure 14A and Figure 14B is a perspective view of an embodiment of a semiconductor device 201 at various stages of method 1400 . Figure 21B 、 Figure 22B 、 Figure 23B 、 Figure 24B 、 Figure 25B and Figure 26B is along the first tangent (e.g., Figure 21A BB in FIG) is a corresponding cross-sectional view of an embodiment of the semiconductor device 201, which is along the length direction of the channel and perpendicular to the top surface of the substrate. Figure 21C 、 Figure 22C 、 Figure 23C 、 Figure 24C 、 Figure 25C and Figure 26C is along the second tangent (e.g., Figure 21A A corresponding cross-sectional view of an embodiment of the semiconductor device 201 is shown along a cut line CC in FIG. 2 , which is in the gate region and perpendicular to the length direction of the channel. Figure 21D 、 Figure 22D 、 Figure 23D 、 Figure 24D 、 Figure 25D and Figure 26D is along the third tangent (e.g., Figure 21A , which is along the length of the channel and parallel to the top surface of the substrate. Many aspects of semiconductor device 201 are substantially similar to those of semiconductor device 200. For convenience, reference numbers are repeated to facilitate understanding. Some differences are discussed below.

[0099] Method 1400 begins at step 1402 by providing a substrate. Step 1402 may be substantially similar to the method described in reference Figure 1A The method 100 is discussed above as step 102. Figure 15 , providing a substrate 202 as described above.

[0100] Method 1400 proceeds to step 1404 where an epitaxial stack is provided. Step 1404 may be substantially similar to that described in reference to FIG. Figure 1A The method 100 is discussed above as step 104. Figure 15 , growing epitaxial stack 204. The various material compositions of the interleaved epitaxial layers 206 and 208 are similar to those of reference Figure 2 . One difference is that the bottom epitaxial layer 206 is thicker than the other epitaxial layers 206 above it in the epitaxial stack 204, for example, its thickness is thicker by about 1 nm to about 5 nm. For example, the other epitaxial layers 206 above it can have a uniform thickness of about 5 nm, while the bottom epitaxial layer 206 can have a thickness of about 6 nm to about 10 nm. In comparison, the thickness of the epitaxial layers 208 of the stack is substantially uniform, for example, about 6 nm to about 12 nm. As will be shown in the figure, the bottom epitaxial layer 206 acts as a space keeper for the inner sidewall material layer to replace the inner sidewall material layer extending under the S / D features, and the relatively large thickness of the bottom epitaxial layer 206 helps to fill it with dielectric material and other benefits, such as better gate to S / D isolation and better leakage suppression.

[0101] Method 1400 proceeds to step 1406 where one or more fins are patterned and formed. Step 1406 may be substantially similar to the method of reference 1400. Figure 1A The method 100 is discussed above as step 106. Figure 16 In an example, one or more fins 210 as described above are provided.

[0102] Method 1400 proceeds to step 1408 where an STI feature is formed. Step 1408 may be substantially similar to the method of FIG. Figure 1A The method 100 is discussed above as step 108. Figure 17 In an example, as described above, the STI features 220 are deposited between the fins 210 and then recessed to expose the epitaxial stack 204 .

[0103] The method 1400 proceeds to step 1410 to form a dummy gate structure. Step 1410 may be substantially similar to the reference Figure 1A The method 100 is discussed above as step 110. Figure 18 In the example, as described above, the dummy gate structure 222 is disposed above the channel region of the fin 210 .

[0104] Method 1400 proceeds to step 1412 where sidewall spacers are formed. Step 1410 may be substantially similar to the step of FIG. Figure 1A The method 100 is discussed above as step 112. Figure 19 In an example, as described above, the sidewall spacers 234 are conformally deposited and then non-isotropically etched to cover the sidewalls of the dummy gate structure 222 .

[0105] The method 1400 proceeds to step 1414 where an epitaxial S / D feature 238 is formed in the source / drain region of the semiconductor device 201. Forming the epitaxial S / D feature 238 may include recessing the fin 210 in the S / D region prior to epitaxially growing the S / D feature 238, similar to the method of reference 1400. Figure 1A 14 as discussed above for method 100. One difference is that during the recessing of the fins 210, the bottom epitaxial layer 206 of the epitaxial stack 204 is substantially retained, separating the epitaxial S / D features 238 from the substrate 202. For example, the alternating pattern between the different semiconductor materials of the epitaxial layers 206 and 208 allows an end mode etch to stop at the bottom epitaxial layer 206. Additionally, a time mode etch may be applied so that the etch process stops at the bottom epitaxial layer 206. The relatively large thickness of the bottom epitaxial layer 206 also helps this layer remain during the time mode etch process. In some embodiments, in the S / D region, the top of the bottom epitaxial layer 206 may be recessed during the etch process (e.g., Figure 21B shown).

[0106] Method 1400 proceeds to step 1416 where an interlayer dielectric layer is formed. Step 1416 may be substantially similar to that described in reference Figure 1A The method 100 is discussed above as step 116. Figure 20 In an example of FIG. 1 , an interlayer dielectric (ILD) layer 240 is formed as described above. A contact etch stop layer (CESL) 242 may be formed before forming the ILD layer 240 .

[0107] Method 1400 proceeds to step 1418 where dummy gate removal is performed. Step 1418 may be substantially similar to the method of FIG. Figure 1B The method 100 is discussed above as step 118. Figures 21A-21D In the example described above, the dummy gate structure 222 is removed to form a spacer between two opposite sidewalls S of the sidewall spacer 234. 234 A gate trench 246 is formed therebetween.

[0108] Method 1400 proceeds to step 1420 where the sacrificial epitaxial layer is removed. Step 1420 may be substantially similar to the method of FIG. Figure 1B The method 100 is discussed above as step 120. Figures 22A-22DIn the example of FIG. 1 , the epitaxial layer 206 in the channel region, including the bottom epitaxial layer, is removed during the etching process. As described above, the removal process "releases" the nanowires (e.g., epitaxial layer 208) in the channel region. Furthermore, the bottom epitaxial layer 206 in the S / D region is removed, forming a cavity beneath the S / D feature 238 that extends continuously from one S / D region to the opposite S / D region.

[0109] Method 1400 proceeds to step 1422 where an inner spacer material layer is conformally deposited in the gate trench. Step 1422 may be substantially similar to that described in reference to FIG. Figure 1B The method 100 is discussed above as step 122. Figures 23A-23D In the example of the embodiment, the inner spacer material layer 252 is conformally deposited on two opposite sidewalls S of the sidewall spacer 234. 234 2 and above the substrate 202. An inner spacer material layer 252 also wraps around each epitaxial layer 208 in the channel region. In addition, the inner spacer material layer 252 also fills the cavity directly below the S / D feature 238. Notably, due to the relatively large gap between the bottom epitaxial layer 208 and the substrate 202 (due to the thicker bottom epitaxial layer 206 as described above), a void 298 can remain in the channel region between the bottom epitaxial layer 208 and the substrate 202. In some other embodiments, the area of the void 298 is filled with the inner spacer material layer 252 (not shown).

[0110] The method 1400 proceeds to step 1424 where a treatment process is performed toward the inner spacer material layer. Step 1424 may be similar to the method described in reference to FIG. Figure 1B The method 100 is discussed above as step 124. Figures 24A-24D For example, the treatment process may be an oxygen ashing process, a nitridation process, or an annealing process using the sidewall spacers 234 as a treatment mask. 234 The middle portion of the inner spacer material layer 252 (denoted as portion 252a) is subjected to the treatment process 260, resulting in a change in its material composition so that it exhibits an etch selectivity compared to other portions of the inner spacer material layer 252 (denoted as portion 252b). Figure 24B As shown, the middle portion 252a between the bottom epitaxial layer 208 and the substrate 202 has a greater width than the other portions 252a above it due to its larger reformed area and, therefore, wider lateral diffusion. In some embodiments, the middle portion 252a between the bottom epitaxial layer 208 and the substrate 202 has an additional width d4 of about 0.5 nm to about 5 nm on each side in the Y direction.

[0111] Method 1400 proceeds to step 1426, which selectively removes the middle portion of the inner spacer material layer subjected to the treatment process. Step 1426 may be similar to that described in reference Figure 1B The method 100 is discussed above as step 126. Figures 25A-25D In the example of FIG. 2 , a portion 252 b of the inner spacer material layer 252 remains as an inner spacer. The inner spacer provides isolation between the epitaxial S / D features 238 and the high-K / metal gate to be formed in the gate trench 246. In addition, the portion 252 b also remains vertically between the epitaxial S / D features 238 and the substrate 202 to provide isolation therebetween.

[0112] The method 1400 proceeds to step 1428 where a gate structure (eg, a replacement gate structure, a HK MG structure) is formed. Step 1428 may be substantially similar to the method of FIG. Figure 1B The method 100 is discussed above as step 128. Figures 26A-26D In one embodiment, a gate structure (HKMG stack) 280 is formed, comprising an interfacial layer 282, a high-k gate dielectric layer 284, and a gate electrode layer 286. In one embodiment, the portion of the gate structure (HKMG stack) 280 located between the bottom epitaxial layer 208 and the substrate 202 is laterally wider than the remaining portion above it, for example, by approximately 0.5 nm to approximately 5 nm (d4) at each end. Internal spacers 252b provide isolation between the epitaxial S / D features 238 and the HKMG stack 280, as well as between the epitaxial S / D features 238 and the substrate 202.

[0113] Without intending to be limiting, one or more embodiments of the present invention provide many benefits to semiconductor devices and their formation. For example, embodiments of the present invention provide a self-aligned internal spacer formation method to precisely control the uniformity of the internal spacer. As a benchmark for uniformity, in some embodiments, the total thickness variation (from top to bottom) of the internal spacer can be within ±5% (also known as a substantially uniform thickness). The uniformity of the internal spacer helps improve the channel length uniformity across different layers of the nanosheet in a multi-gate semiconductor device (e.g., a GAA device). The internal spacer can also provide isolation between the S / D region and the gate stack, and also provide isolation between the S / D region and the substrate. In addition, the internal spacer formation method can be easily integrated into existing semiconductor manufacturing processes.

[0114] In one exemplary aspect, embodiments of the present invention relate to a method for fabricating a semiconductor device. The method includes forming a fin protruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are arranged alternately; removing a portion of the sacrificial layers from a channel region of the fin; depositing a spacer material in the region where the portion of the sacrificial layers has been removed; removing a portion of the spacer material to expose the channel layer in the channel region of the fin, wherein other portions of the spacer material remain as spacer components; and forming a gate structure bonded to the exposed channel layer. In some embodiments, the method further includes, before removing the portion of the spacer material, performing a treatment process on the portion of the spacer material such that the portion of the spacer material has an etch selectivity relative to other portions of the spacer material. In some embodiments, the treatment process includes an oxygen ashing process or a nitridation process. In some embodiments, the treatment process includes an annealing process. In some embodiments, the method further includes, before removing the portion of the sacrificial layers, forming an outer spacer layer, wherein the spacer material is in physical contact with the outer spacer layer, and wherein the thickness of the spacer component is substantially equal to the thickness of the outer spacer layer. In some embodiments, the sidewall surface of the spacer component has a convex shape in a plane parallel to the top surface of the substrate, the convex shape having an apex extending toward the gate structure. In some embodiments, the sidewall surface of the spacer component has a concave shape in a plane perpendicular to the top surface of the substrate and along the length direction of the fin, the concave shape curving away from the gate structure. In some embodiments, the method further includes forming a source / drain (S / D) component, wherein the spacer component is between the S / D component and the gate structure. In some embodiments, the S / D component is formed on the bottommost one of the multiple sacrificial layers. In some embodiments, the bottommost one of the multiple sacrificial layers has a greater thickness than any other sacrificial layer. In some embodiments, the multiple sacrificial layers include silicon germanium and the multiple channel layers include silicon.

[0115] In another exemplary aspect, embodiments of the present invention relate to a method for fabricating a semiconductor device. The method includes forming a stack of first and second epitaxial layers on a semiconductor substrate, the first and second epitaxial layers having different material compositions and alternating in a vertical direction; forming a dummy gate overlying a portion of the stack in a channel region; forming an outer spacer layer overlying the sidewalls of the dummy gate; removing the dummy gate to form a gate trench, wherein the gate trench exposes two opposing sidewalls of the outer spacer layer; etching the second epitaxial layer in the gate trench; depositing a dielectric layer in the gate trench along two opposing sidewalls of the outer spacer layer and surrounding the first epitaxial layer; performing a treatment process on a portion of the dielectric layer between the two opposing sidewalls of the outer spacer layer, wherein the treatment process uses the outer spacer layer as a treatment mask; removing the portion of the dielectric layer to form an inner spacer layer; and forming a gate stack in the gate trench and surrounding the first epitaxial layer. In some embodiments, the treatment process includes an oxidation process or a nitridation process. In some embodiments, the treatment process includes an annealing process. In some embodiments, the dielectric layer is conformally deposited in the gate trench. In some embodiments, after depositing the dielectric layer, a void remains beneath the bottom first type epitaxial layer. In some embodiments, the outer spacer layer and the inner spacer layer comprise different dielectric materials.

[0116] In another exemplary aspect, embodiments of the present invention relate to a multi-gate semiconductor device. The multi-gate semiconductor device includes a fin element extending upward from a substrate; a gate structure above the fin element; an epitaxial source / drain (S / D) component adjacent to the fin element; and a dielectric spacer between the gate structure and the epitaxial S / D component, wherein a sidewall surface of the dielectric spacer facing the gate structure has a convex shape in a plane parallel to the top surface of the substrate, and the convex shape has an apex extending toward the gate structure. In some embodiments, the multi-gate semiconductor device further includes a gate spacer covering the sidewall of the gate structure, wherein the thickness of the dielectric spacer is substantially equal to the thickness of the gate spacer. In some embodiments, the dielectric spacer has a substantially uniform thickness.

[0117] The above summarizes the components of several embodiments so that those of ordinary skill in the art to which the present invention belongs can more clearly understand the concepts of the embodiments of the present invention. Those of ordinary skill in the art to which the present invention belongs should understand that the embodiments of the present invention can be used as a basis to design or modify other processes and structures to achieve the same purposes and / or the same benefits as the embodiments introduced herein. Those of ordinary skill in the art to which the present invention belongs should also understand that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions and other options can be made herein without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a fin protruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the plurality of sacrificial layers and the plurality of channel layers are alternately arranged; removing a portion of the plurality of sacrificial layers from a channel region of the fin; depositing a spacer material in the region where the portion of the plurality of sacrificial layers has been removed; removing a portion of the spacer material to expose the plurality of channel layers in the channel region of the fin, wherein other portions of the spacer material remain as a spacer component; forming a gate structure connected to the exposed channel layers; as well as A source / drain feature is formed, wherein the spacer feature is between the source / drain feature and the gate structure.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising: Prior to removing a portion of the spacer material, a treatment process is performed on the portion of the spacer material such that the portion of the spacer material has an etch selectivity compared to other portions of the spacer material. 3 . The method for manufacturing a semiconductor device as claimed in claim 2 , wherein the treatment process comprises an oxygen ashing process or a nitridation process. 4 . The method for manufacturing a semiconductor device as claimed in claim 2 , wherein the treatment process comprises an annealing process.

5. The method for manufacturing a semiconductor device according to claim 1 , further comprising: Prior to removing a portion of the plurality of sacrificial layers, an outer spacer layer is formed, wherein the spacer material is in physical contact with the outer spacer layer, and wherein a thickness of the spacer member is substantially equal to a thickness of the outer spacer layer. 6 . The method for manufacturing a semiconductor device according to claim 1 , wherein a sidewall surface of the spacer member has a convex shape in a plane parallel to a top surface of the substrate, the convex shape having an apex extending toward the gate structure. 7 . The method for manufacturing a semiconductor device according to claim 1 , wherein a sidewall surface of the spacer component has a concave shape in a plane perpendicular to a top surface of the substrate and along a length direction of the fin, and the concave shape is bent away from the gate structure. 8 . The method for fabricating a semiconductor device as claimed in claim 7 , wherein the source / drain features are formed before the spacer material is deposited. 9 . The method for manufacturing a semiconductor device according to claim 1 , wherein the plurality of sacrificial layers comprise silicon germanium, and the plurality of channel layers comprise silicon.

10. A method for manufacturing a semiconductor device, comprising: forming a stack of a plurality of first-type and second-type epitaxial layers on a semiconductor substrate, wherein the plurality of first-type and second-type epitaxial layers have different material compositions and are alternately arranged in a vertical direction; forming a dummy gate covering a portion of the stack in a channel region; forming an outer spacer layer to cover the sidewall of the dummy gate; removing the dummy gate to form a gate trench, wherein the gate trench exposes both sidewalls of the outer spacer layer; etching the plurality of second type epitaxial layers in the gate trench; Depositing a dielectric layer in the gate trench along both sidewalls of the outer spacer layer and surrounding the plurality of first type epitaxial layers; performing a treatment process on a portion of the dielectric layer between the two sidewalls of the outer spacer layer, wherein the treatment process uses the outer spacer layer as a treatment mask; removing the portion of the dielectric layer, thereby forming an inner spacer layer; as well as A gate stack is formed in the gate trench and surrounds the plurality of first type epitaxial layers. 11 . The method for manufacturing a semiconductor device according to claim 10 , wherein the treatment process comprises an oxidation treatment or a nitridation treatment.

12. The method for manufacturing a semiconductor device as claimed in claim 11, wherein the treatment process comprises an annealing process. 13 . The method for manufacturing a semiconductor device as claimed in claim 10 , wherein the dielectric layer is conformally deposited in the gate trench. 14 . The method for fabricating a semiconductor device as claimed in claim 10 , wherein the outer spacer layer and the inner spacer layer comprise different dielectric materials.

15. A method for manufacturing a semiconductor device, comprising: forming a fin protruding from a substrate, the fin having a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; forming a sacrificial gate structure above the fin structure; removing the sacrificial gate structure to form a gate trench; etching the plurality of second semiconductor layers exposed in the gate trench; depositing a dielectric layer in the gate trench, wherein the dielectric layer surrounds the plurality of first semiconductor layers; performing a treatment process on a middle portion of the dielectric layer; removing the middle portion of the dielectric layer from the gate trench, wherein end portions of the dielectric layer remain; and A gate structure is formed in the gate trench and coupled to the plurality of first semiconductor layers. 16 . The method for fabricating a semiconductor device as claimed in claim 15 , wherein the treatment process changes an etching selectivity of the middle portion of the dielectric layer. 17 . The method for manufacturing a semiconductor device as claimed in claim 15 , wherein the treatment process comprises an oxidation treatment or a nitridation treatment.

18. The method for manufacturing a semiconductor device as claimed in claim 15, wherein the treatment process comprises an annealing process.

19. The method for manufacturing a semiconductor device according to claim 15, further comprising: Before removing the sacrificial gate structure, source / drain features are formed, wherein the ends of the dielectric layer are in physical contact with the source / drain features.

20. A semiconductor device comprising: a base; a channel member on the substrate; a gate structure surrounding the channel member; a source / drain feature abutting the channel member; and an inner spacer disposed between the source / drain component and the gate structure, wherein a first sidewall of the inner spacer facing the gate structure has a curved surface along a length direction of the channel component in a cross-sectional view perpendicular to a top surface of the substrate, and wherein the curved surface is a concave surface that curves inwardly away from the gate structure. The semiconductor device according to claim 20 , wherein a depth of the concave surface is 0.5 nm to 5 nm. 22 . The semiconductor device of claim 20 , wherein a second sidewall of the inner spacer facing the source / drain feature is substantially perpendicular to the top surface of the substrate. 23 . The semiconductor device of claim 20 , wherein the first sidewall of the inner spacer has a convex surface extending outward toward the gate structure and along the length direction of the channel member in a cross-sectional view parallel to the top surface of the substrate.

24. The semiconductor device of claim 23, wherein the convex surface comprises two curved segments tangent to each other at a vertex. The semiconductor device of claim 24 , wherein each of the two curved sections bends inwardly away from the gate structure. The semiconductor device of claim 20 , wherein the channel member is a nanosheet.

27. The semiconductor device of claim 20, wherein the inner spacer comprises a dielectric material selected from the group consisting of SiN, SiOC, SiCN, and SiO2.

28. The semiconductor device according to claim 20, further comprising: A gate spacer is over the sidewalls of the gate structure and over the sidewalls and top surface of the channel member and the inner spacer, wherein a portion of the gate structure extends directly under the gate spacer.

29. The semiconductor device of claim 20, wherein the inner spacer extends directly below the source / drain feature.

30. A semiconductor device comprising: a base; a plurality of nanosheets vertically stacked on each other and on the substrate; a gate structure over a channel region of the plurality of nanosheets and surrounding each of the plurality of nanosheets; an epitaxial source / drain region component adjacent to the plurality of nanosheets; as well as A dielectric layer is sandwiched between the epitaxial source / drain component and the gate structure and surrounds each of the plurality of nanosheets, wherein the dielectric layer between two adjacent nanosheets has a concave surface facing the gate structure.

31. The semiconductor device of claim 30, wherein the dielectric layer extends directly below the epitaxial source / drain region.

32. The semiconductor device of claim 31, wherein the dielectric layer separates the epitaxial source / drain region from the substrate.

33. The semiconductor device of claim 30, wherein a portion of the dielectric layer below a bottommost nanosheet is recessed further toward the epitaxial source / drain feature than another portion of the dielectric layer above the bottommost nanosheet. 34 . The semiconductor device of claim 30 , wherein a sidewall of the gate structure between two adjacent nanosheets is curved inwardly away from the dielectric layer in a top view.

35. The semiconductor device according to claim 30, further comprising: A gate spacer is provided on the sidewall of the gate structure, wherein the thickness of the dielectric layer between two adjacent nanosheets is substantially the same as that of the gate spacer.

36. A multi-gate semiconductor device comprising: a fin element extending upward from a base; a gate structure bonded to the fin element; an epitaxial source / drain feature in physical contact with the fin element; and A dielectric spacer is disposed between the gate structure and the epitaxial source / drain component, wherein a sidewall surface of the dielectric spacer facing the gate structure has a convex shape in a plane parallel to a top surface of the substrate, and the convex shape has an apex extending toward the gate structure.

37. The multi-gate semiconductor device of claim 36, further comprising: A gate spacer covers the sidewall of the gate structure, wherein the thickness of the dielectric spacer is substantially equal to the thickness of the gate spacer.

38. The multi-gate semiconductor device of claim 37, wherein a portion of the gate structure extends directly beneath the gate spacer.

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