A low dropout linear regulator

Abstract

The present invention discloses a low voltage difference linear regulator, which includes an N-type field effect tube M1, the source of which is respectively connected to the source of an N-type field effect tube M7, the source of an N-type field effect tube M8, one end of a resistor R1, one end of a capacitor CL, one end of a resistor RL and grounded; the gate of the N-type field effect tube M1 is connected to a VBIAS voltage; the drain of the N-type field effect tube M1 is respectively connected to the source of an N-type field effect tube M2 and the source of an N-type field effect tube M3. The present invention can output a high-precision voltage under light load and no-load conditions.

Description

Technical Field

[0001] The invention relates to the field of voltage stabilizers, and in particular to a low voltage difference linear voltage stabilizer. Background Art

[0002] With the advent of the Internet of Things era, the market requires LDO (low dropout linear regulator) with lower quiescent current and stronger load capacity. LDO circuit design sometimes cannot have good output accuracy while taking both into account, especially the output voltage accuracy of LDO will deteriorate under light load or no load. In addition, the leakage of some advanced processes has become serious, which will also make the LDO output voltage accuracy unable to be guaranteed under light load and no load conditions. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the present invention provides a low voltage dropout linear regulator that achieves high precision of output voltage under light load and no-load conditions.

[0004] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is:

[0005] A low voltage difference linear regulator is provided, which includes an N-type field effect tube M1, wherein the source of the N-type field effect tube M1 is respectively connected to the source of the N-type field effect tube M7, the source of the N-type field effect tube M8, one end of the resistor R1, one end of the capacitor CL, one end of the resistor RL and grounded; the gate of the N-type field effect tube M1 is connected to the VBIAS voltage; the drain of the N-type field effect tube M1 is respectively connected to the source of the N-type field effect tube M2 and the source of the N-type field effect tube M3;

[0006] The drain of the N-type field effect transistor M2 is respectively connected to the drain of the P-type field effect transistor M4, the gate of the P-type field effect transistor M4 and the gate of the P-type field effect transistor M5; the source of the P-type field effect transistor M4 is respectively connected to the source of the P-type field effect transistor M5, the source of the P-type field effect transistor M6, the source of the P-type field effect transistor M10, the source of the P-type field effect transistor M9, the source of the P-type field effect transistor MP and an external power supply;

[0007] The drain of the N-type field effect transistor M3 is respectively connected to the positive input terminal of the comparator CMP, the gate of the P-type field effect transistor M6 and the gate of the P-type field effect transistor M10; the drain of the P-type field effect transistor M6 is respectively connected to one end of the switch S, the drain of the N-type field effect transistor M7, the gate of the N-type field effect transistor M7 and the gate of the M-type field effect transistor M8; the drain of the P-type field effect transistor M10 is connected to the other end of the switch S; the negative input terminal of the comparator CMP is connected to the reference voltage OUT-REF, and the output terminal of the comparator CMP is connected to the control terminal of the switch S; when the output of the comparator CMP is low, the switch S is closed; when the output of the comparator CMP is high, the switch S is opened;

[0008] The drain of the N-type field effect transistor M8 is respectively connected to the drain of the P-type field effect transistor M9, the gate of the P-type field effect transistor M9 and the gate of the P-type field effect transistor MP; the drain of the P-type field effect transistor MP is respectively connected to one end of the resistor R2, the other end of the capacitor CL and the other end of the resistor RL and serves as the output end of the low voltage difference linear regulator; the other end of the resistor R2 is respectively connected to the other end of the resistor R1 and the gate of the N-type field effect transistor M2.

[0009] The beneficial effect of the present invention is that the present invention can output a high-precision voltage under light-load and no-load conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A circuit diagram of the present invention;

[0011] Figure 2 The simulation results of the load regulation rate of the existing low-dropout linear regulator at FF Corner and high temperature;

[0012] Figure 3 It is the simulation result of the load regulation rate of the present invention at FF Corner and high temperature. DETAILED DESCRIPTION

[0013] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0014] like Figure 1 As shown, the low voltage difference linear regulator includes an N-type field effect transistor M1, the source of the N-type field effect transistor M1 is respectively connected to the source of the N-type field effect transistor M7, the source of the N-type field effect transistor M8, one end of the resistor R1, one end of the capacitor CL, one end of the resistor RL and grounded; the gate of the N-type field effect transistor M1 is connected to the VBIAS voltage; the drain of the N-type field effect transistor M1 is respectively connected to the source of the N-type field effect transistor M2 and the source of the N-type field effect transistor M3;

[0015] The drain of the N-type field effect transistor M2 is respectively connected to the drain of the P-type field effect transistor M4, the gate of the P-type field effect transistor M4 and the gate of the P-type field effect transistor M5; the source of the P-type field effect transistor M4 is respectively connected to the source of the P-type field effect transistor M5, the source of the P-type field effect transistor M6, the source of the P-type field effect transistor M10, the source of the P-type field effect transistor M9, the source of the P-type field effect transistor MP and an external power supply;

[0016] The drain of the N-type field effect transistor M3 is respectively connected to the positive input terminal of the comparator CMP, the gate of the P-type field effect transistor M6 and the gate of the P-type field effect transistor M10; the drain of the P-type field effect transistor M6 is respectively connected to one end of the switch S, the drain of the N-type field effect transistor M7, the gate of the N-type field effect transistor M7 and the gate of the M-type field effect transistor M8; the drain of the P-type field effect transistor M10 is connected to the other end of the switch S; the negative input terminal of the comparator CMP is connected to the reference voltage OUT-REF, and the output terminal of the comparator CMP is connected to the control terminal of the switch S; when the output of the comparator CMP is low, the switch S is closed; when the output of the comparator CMP is high, the switch S is opened;

[0017] The drain of the N-type field effect transistor M8 is respectively connected to the drain of the P-type field effect transistor M9, the gate of the P-type field effect transistor M9 and the gate of the P-type field effect transistor MP; the drain of the P-type field effect transistor MP is respectively connected to one end of the resistor R2, the other end of the capacitor CL and the other end of the resistor RL and serves as the output end of the low voltage difference linear regulator; the other end of the resistor R2 is respectively connected to the other end of the resistor R1 and the gate of the N-type field effect transistor M2.

[0018] In the specific implementation process, tubes M1 to M5 form an error amplifier, and the VBIAS voltage provides a gate voltage for tube M1, so that tube M1 provides a tail current to the error amplifier. Tubes M2 and M3 are input pairs of tubes of the error amplifier, and their gates are connected to the feedback voltage VFB and the reference voltage VREF respectively. Tubes M6 to M9 are current mirror drive stages, which provide a certain gain for the entire loop, and at the same time sample the MP tube current to reduce the equivalent impedance of the MP tube gate.

[0019] The present invention first determines a reference voltage OUT-REF, which can ensure that the M5 tube can work in the saturation region under different PVTs to ensure the gain of the error amplifier. The output voltage (OUT-EA) of the error amplifier and the reference voltage OUT_REF are used as the positive and negative inputs of the comparator CMP respectively, and the output of the comparator CMP is in phase with the output voltage of the error amplifier. Under normal circumstances, the output voltage of the error amplifier is lower than the reference voltage OUT_REF, the comparator output is low, the gates of the M6 ​​tube and the M10 tube are connected to the output voltage of the error amplifier, the switch S is closed, and all the tubes of the error amplifier are in the saturation region, providing a sufficiently large gain for the loop. In certain extreme cases, the output voltage of the error amplifier is higher than the reference voltage OUT_REF, at which time the M5 tube has entered the linear region, the output of the comparator CMP becomes high, the switch S is disconnected, and at this time only the M6 ​​tube is connected to the output of the error amplifier. When the current of M7 tube remains unchanged, the current of M6 tube is larger than that before the output of comparator CMP is flipped, so the |VGS| of M6 tube becomes larger, that is, the output voltage of the error amplifier becomes lower, so that M5 tube returns from the linear region to the saturation region, thereby ensuring the loop gain at this time and improving the output accuracy of VOUT (MP tube drain voltage).

[0020] like Figure 2 and Figure 3 As shown in the figure, the simulation results of the load regulation rate of the existing low dropout linear regulator at FF corner and 125℃, the ideal output voltage is 1.5V. Figure 2 It can be seen that when the load resistance is small, the output voltage value of the existing LDO is very accurate. When the load resistance becomes larger and larger, the deviation between the output value of VOUT and the ideal value becomes larger and larger. When RL = 1 megohm, VOUT has already deviated from the ideal value by nearly 20 millivolts. This deviation may be even greater under certain process extreme conditions. Figure 3 It can be seen that under the same simulation conditions, the VOUT of the present invention does not change much under different loads, and the deviation is within ±1mV, and a high-precision voltage can be output under light load and no-load conditions.

Claims

1. A low voltage dropout linear regulator, characterized in that: It includes an N-type field effect transistor M1, the source of which is respectively connected to the source of the N-type field effect transistor M7, the source of the N-type field effect transistor M8, one end of the resistor R1, one end of the capacitor CL, one end of the resistor RL and grounded; the gate of the N-type field effect transistor M1 is connected to the VBIAS voltage; The drain of the N-type field effect transistor M1 is connected to the source of the N-type field effect transistor M2 and the source of the N-type field effect transistor M3 respectively; The drain of the N-type field effect transistor M2 is respectively connected to the drain of the P-type field effect transistor M4, the gate of the P-type field effect transistor M4 and the gate of the P-type field effect transistor M5; the source of the P-type field effect transistor M4 is respectively connected to the source of the P-type field effect transistor M5, the source of the P-type field effect transistor M6, the source of the P-type field effect transistor M10, the source of the P-type field effect transistor M9, the source of the P-type field effect transistor MP and an external power supply; The drain of the N-type field effect transistor M3 is respectively connected to the positive input terminal of the comparator CMP, the drain of the P-type field effect transistor M5, the gate of the P-type field effect transistor M6 and the gate of the P-type field effect transistor M10; the drain of the P-type field effect transistor M6 is respectively connected to one end of the switch S, the drain of the N-type field effect transistor M7, the gate of the N-type field effect transistor M7 and the gate of the M-type field effect transistor M8; the drain of the P-type field effect transistor M10 is connected to the other end of the switch S; the negative input terminal of the comparator CMP is connected to the reference voltage OUT-REF, and the output terminal of the comparator CMP is connected to the control terminal of the switch S; when the output of the comparator CMP is low, the switch S is closed; when the output of the comparator CMP is high, the switch S is opened; The drain of the N-type field effect transistor M8 is respectively connected to the drain of the P-type field effect transistor M9, the gate of the P-type field effect transistor M9 and the gate of the P-type field effect transistor MP; the drain of the P-type field effect transistor MP is respectively connected to one end of the resistor R2, the other end of the capacitor CL and the other end of the resistor RL and serves as the output end of the low voltage difference linear regulator; the other end of the resistor R2 is respectively connected to the other end of the resistor R1 and the gate of the N-type field effect transistor M2.

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