Semiconductor packaging

Abstract

A semiconductor package can be provided, comprising: a first master-slave state circuit, configured to store one of a first signal or a second signal independently of a second master-slave state circuit, and to store the first signal in response to receiving the first initialization signal from a first initialization circuit; a second master-slave state circuit, configured to store one of the first signal or the second signal, and to store the first signal in response to receiving the second initialization signal from the second initialization circuit; the first initialization circuit, configured to provide the first initialization signal to the first master-slave state circuit; the second initialization circuit, configured to provide the second initialization signal to the second master-slave state circuit; and a first master-slave determination circuit, connected to the second master-slave state circuit, the first master-slave determination circuit being configured to provide the second signal to the second master-slave state circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2018-0076997, filed on Jul. 3, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a semiconductor package and more particularly to a semiconductor package including a through silicon via and an initialization circuit for distinguishing a master chip from a slave chip, a master-slave state circuit, and a master-slave determination circuit. Background Art

[0004] In order to implement a large-capacity memory system, a multi-chip package (MCP) including a plurality of memory chips is widely used.

[0005] In such a multi-chip package, bonding wires may be used to wire a plurality of memory chips individually from one another. However, wiring using such bonding wires may have limitations on high-speed input / output operations.

[0006] To solve these problems, through silicon via (TSV) technology has been used recently. In a multi-chip package formed by using the through silicon via (TSV) technology, not every chip stacked in the multi-chip package is connected to the outside of the package. For example, a master chip in the stacked chips is connected to the outside, and a slave chip stacked on the master chip in the stacked chips is not connected to the outside.

[0007] As described above, in a multi-chip package using through silicon via technology, since only the master chip is connected to the outside, different controls are expected for the master chip and the slave chip. However, since the constituent elements included in the master chip and the slave chip are identical or substantially similar to each other, it may be difficult to distinguish the master chip from the slave chip based on the presence or absence of one or more specific constituent elements. Therefore, a specific configuration for distinguishing the master chip from the slave chip may be required. Summary of the invention

[0008] Some example embodiments of the inventive concepts provide a semiconductor package with reduced power consumption.

[0009] Some example embodiments of the inventive concepts provide a semiconductor package with reduced operation delay.

[0010] According to an example embodiment of the present invention, a semiconductor package includes: a first master-slave state circuit configured to store one of a first signal of a first level or a second signal of a second level, the first master-slave state circuit configured to store the first signal in response to receiving a first initialization signal from a first initialization circuit, the first master-slave state circuit configured to store one of the first signal or the second signal independently of one of the first signal or the second signal stored in a second master-slave state circuit; a second master-slave state circuit configured to store one of the first signal or the second signal, the second master-slave state circuit configured to store the first signal in response to receiving the second initialization signal from the second initialization circuit; the first initialization circuit configured to provide the first initialization signal to the first master-slave state circuit; the second initialization circuit configured to provide the second initialization signal to the second master-slave state circuit; and a first master-slave determination circuit connected to the second master-slave state circuit, the first master-slave determination circuit configured to provide the second signal to the second master-slave state circuit.

[0011] According to an example embodiment conceived in the present invention, a semiconductor package includes: a first chip, the first chip includes: a first master-slave state circuit, configured to store one of a first signal of a first level or a second signal of a second level; and a first initialization circuit, configured to initialize the first master-slave state circuit; and a second chip, the second chip includes: a second master-slave state circuit, configured to store one of the first signal or the second signal; a second initialization circuit, configured to initialize the second master-slave state circuit; and a second master-slave determination circuit, connected to the first master-slave state circuit, receiving one of the first signal or the second signal stored in the first master-slave state circuit, inverting one of the first signal or the second signal received from the first master-slave state circuit, and providing the inverted one of the first signal or the second signal to the first master-slave state circuit.

[0012] According to an example embodiment of the present invention, a semiconductor package includes: a first chip, the first chip including: a first master-slave state circuit, configured to store one of a first signal of a first level or a second signal of a second level; a first master-slave determination circuit, configured to receive one of the first signal or the second signal from a second master-slave state circuit, invert one of the first signal or the second signal, and provide the inverted one of the first signal or the second signal to the second master-slave state circuit, the first master-slave determination circuit being connected to the second master-slave state circuit; a first input buffer, configured to store first data; a first internal circuit, configured to process the first data; and a first switch, configured to The invention is configured to control the connection between the first input buffer and the first internal circuit based on the signal from the first master-slave state circuit; and a second chip, the second chip is on the first chip, the second chip includes: a second master-slave state circuit, configured to store one of the first signal or the second signal; a second input buffer, configured to store second data; a second internal circuit, configured to process the second data; a second switch, configured to control the connection between the second input buffer and the second internal circuit based on the signal from the second master-slave state circuit; and a third switch, configured to control the connection between the first input buffer and the second internal circuit based on the signal from the second master-slave state circuit.

[0013] Aspects of the inventive concept are not limited to those mentioned above, and other aspects not mentioned may be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects and features of the inventive concept will become more apparent by describing in detail some example embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0015] Figure 1 is an example diagram for illustrating a semiconductor package according to example embodiments.

[0016] Figure 2 is used to explain the Figure 1 An example flow chart of the operations of a semiconductor package.

[0017] Figure 3 is used to describe the Figure 1 An example timing diagram of the operation of a semiconductor package is shown in FIG.

[0018] Figure 4 is an exemplary diagram illustrating a process of determining a first master-slave state signal according to an exemplary embodiment.

[0019] Figure 5is an example diagram illustrating a process of determining a second master-slave state signal and a third master-slave state signal according to an example embodiment.

[0020] Figure 6 is used to explain another exemplary embodiment Figure 1 An example timing diagram of the operation of a semiconductor package is shown in FIG.

[0021] Figures 7 to 9 is an example diagram for explaining application of first to third master-slave state signals to a semiconductor package according to some example embodiments. DETAILED DESCRIPTION

[0022] Figure 1 is an example diagram for illustrating a semiconductor package 1000 according to example embodiments.

[0023] refer to Figure 1 , a semiconductor package 1000 according to some embodiments includes a package substrate 100 , a first chip 110 , a second chip 210 , a third chip 310 , first to third bumps B1 to B3 , and package balls PKGB.

[0024] According to example embodiments, the first to third chips 110, 210, and 310 may be sequentially disposed on the package substrate 100. For example, the first chip 110 may be disposed on the package substrate 100. In addition, the second chip 210 may be disposed on the first chip 110. In addition, the third chip 310 may be disposed on the second chip 210. The package substrate 100 and the first chip 110 may be connected by a first bump B1. The first chip 110 may be connected to the second chip 210 by a second bump B2. The second chip 210 may be connected to the third chip 310 by a third bump B3. A detailed description thereof will be provided later.

[0025] The constituent elements included in the first to third chips 110, 210, and 310 may be identical or substantially similar to each other. The expression "the constituent elements are identical or substantially similar to each other" means that the shape, form, function, position, etc. of each constituent element are identical or substantially similar to each other in consideration of process errors or manufacturing errors in the manufacturing process.

[0026] The first chip 110 may include a first master-slave state circuit 111 ( MSS1 ), a first initialization circuit 112 ( INT1 ), a first master-slave determination circuit 113 ( MD1 ), a first pad 114 ( PAD1 ), and a first through silicon via 115 ( TSV1 ).

[0027] The first master-slave status circuit 111 may provide a first master-slave status signal MS STATUS_1 to other components within the first chip 110. The first master-slave status signal MS STATUS_1 may be a signal received at a specific time point (eg, Figure 3 The first master-slave state circuit 111 may include, for example, a latch circuit.

[0028] The first initialization circuit 112 may be connected to the first master-slave state circuit 111. The first initialization circuit 112 may initialize the first master-slave state circuit 111. For example, the first initialization circuit 112 may provide a first initial signal to the first master-slave state circuit 111 to initialize the first master-slave state circuit 111. The signal stored in the initialized first master-slave state circuit 111 may be, for example, a first signal of a first level. In other words, when the first initialization circuit 112 initializes the first master-slave state circuit 111, the first master-slave state circuit 111 may store a first signal of a first level. For example, the first level may be a logic low level (0) or a logic high level (1).

[0029] In some example embodiments, if the power supplied to the first chip 110 reaches a desired first power level ( Figure 3 If the first initialization circuit 112 is L1, the first initialization circuit 112 can initialize the first master-slave state circuit 111. For example, the first initialization circuit 112 can be a power level detection (PLD) device.

[0030] That is, when the first chip 110 is provided with a power level equal to or greater than the desired first power level ( Figure 3 When the power L1 is supplied, the first initialization circuit 112 may initialize the first master-slave state circuit 111 to store a first signal of a first level.

[0031] The first master-slave determination circuit 113 may invert the received signal and may also provide the inverted signal to another component. For example, the first master-slave determination circuit 113 may receive a signal from the second master-slave state circuit 211. In addition, the first master-slave determination circuit 113 may provide the inverted signal to the second master-slave state circuit 211. In some example embodiments, the inverted signal may be a second signal of a second level. For example, the second level may be a logic high level (1) or a logic low level (0). For example, the first master-slave determination circuit 113 may include an inverter.

[0032] In some example embodiments, the first master-slave state circuit 111 and the first master-slave determination circuit 113 may be implemented as digital circuits. Therefore, the semiconductor package 1000 according to some embodiments may have relatively low power consumption and low operation delay.

[0033] The first chip 110 may be connected to the package substrate 100 . For example, the first chip 110 may be connected to the package substrate 100 via the first bumps B1 . The first master-slave state circuit 111 may be connected to the first pads 114 . Furthermore, the first master-slave determination circuit 113 may be connected to the first through silicon vias 115 .

[0034] The second chip 210 may include a second master-slave state circuit 211 (MSS2), a second initialization circuit 212 (INT2), a second master-slave determination circuit 213 (MSD2), a second pad 214 (PAD2), and a second through silicon via 215 (TSV2). As described above, since the constituent elements included in the second chip 210 are the same as or substantially similar to the constituent elements included in the first chip 110, the repeated description will be omitted or briefly explained.

[0035] The second master-slave status circuit 211 may provide a second master-slave status signal MS STATUS_2 to other components inside the second chip 210 .

[0036] The second initialization circuit 212 may be connected to the second master-slave state circuit 211. In some example embodiments, when a power level greater than or equal to a desired first power level ( Figure 3 When the power of L1 is supplied, the second initialization circuit 212 may initialize the second master-slave state circuit 211 to store the first signal of the first level.

[0037] The second master-slave determination circuit 213 may invert the received signal. In addition, the second master-slave determination circuit 213 may provide the inverted signal to another constituent element.

[0038] The second master-slave state circuit 211 may be connected to the second pad 214. The second master-slave determination circuit 213 may be connected to the second through silicon via 215. The second chip 210 may be connected to the first chip 110 via the second bump B2. For example, the first through silicon via 115 included in the first chip 110 may be connected to the second bump B2. In addition, the second pad 214 included in the second chip 210 may be connected to the second bump B2. Therefore, by connecting each of the first through silicon via 115 and the second pad 214 to the second bump B2, the first chip 110 and the second chip 210 may be connected to each other. Therefore, the first master-slave determination circuit 113 may be connected to the second master-slave state circuit 211 through the first through silicon via 115, the second bump B2 and the second pad 214.

[0039] In some example embodiments, the first master-slave determination circuit 113 receives a signal from the second master-slave state circuit 211, and may invert the signal to provide the inverted signal to the second master-slave state circuit 211. For example, the first master-slave determination circuit 113 may receive a first signal of a first level stored in the second master-slave state circuit 211 through the second pad 214, the second bump B2, and the first through silicon via 115. The first master-slave determination circuit 113 may invert the first signal of the first level received from the second master-slave state circuit 211 to generate a second signal of a second level. The second signal of the second level generated by the first master-slave determination circuit 113 may be provided to the second master-slave state circuit 211 through the first through silicon via 115, the second bump B2, and the second pad 214.

[0040] The third chip 310 may include a third master-slave state circuit 311 (MSS3), a third initialization circuit 312 (INT3), a third master-slave determination circuit 313 (MSD3), a third pad 314 (PAD3), and a third through silicon via 315 (TSV3). As described above, since the constituent elements included in the third chip 310 are the same as or substantially similar to the constituent elements included in the first chip 110, the repeated description will be omitted or briefly explained.

[0041] The third master-slave status circuit 311 may provide a third master-slave status signal MS STATUS_3 to other components inside the third chip 310 .

[0042] The third initialization circuit 312 may be connected to the third master-slave state circuit 311. In some embodiments, when the third chip 310 is provided with a power level greater than or equal to the desired first power level ( Figure 3 When the power of L1 is supplied, the third initialization circuit 312 may initialize the third master-slave state circuit 311 to store the first signal of the first level.

[0043] The first to third initialization circuits 112, 212, and 312 can independently initialize the first to third master-slave state circuits 111, 211, and 311, respectively. For example, regardless of whether the second initialization circuit 212 or the third initialization circuit 312 operates, the first initialization circuit 112 can initialize the first master-slave state circuit 111. That is, even if the second chip 210 and the third chip 310 do not receive power, the first initialization circuit 112 can initialize the first master-slave state circuit 111. In addition, the second initialization circuit 212 and the third initialization circuit 312 can respectively initialize the second master-slave state circuit 211 and the third master-slave state circuit 311, regardless of whether the other initialization circuits operate. Because the first to third initialization circuits 112, 212, and 312 independently initialize the first to third master-slave state circuits 111, 211, and 311, respectively, the first to third master-slave state circuits 111, 211, and 311 can be initialized in parallel. For example, when power is supplied from the outside to the first to third chips 110, 210, and 310, the first to third master-slave state circuits 111, 211, and 311 can be initialized substantially at the same time. The expression "substantially at the same time" used in this article takes into account operating errors and / or measurement errors. Because the first to third master-slave state circuits 111, 211, and 311 can perform their respective initialization operations in parallel, the operation delay of the semiconductor package 1000 can be reduced.

[0044] The third master-slave determination circuit 313 may invert the received signal. In addition, the third master-slave determination circuit 313 may provide the inverted signal to another constituent element.

[0045] The third master-slave state circuit 311 may be connected to the third pad 314. In addition, the third master-slave determination circuit 313 may be connected to the third through silicon via 315.

[0046] The third chip 310 may be connected to the second chip 210 via a third bump B3. Since the connection relationship between the second chip 210 and the third chip 310 is the same as the connection relationship between the first chip 110 and the second chip 210, the repeated content will be omitted or briefly explained. The second master-slave determination circuit 213 may be connected to the second through silicon via 215. The third master-slave state circuit 311 may be connected to the third pad 314. Therefore, the second master-slave determination circuit 213 may be connected to the third master-slave state circuit 311. In some example embodiments, the second master-slave determination circuit 213 may receive a signal from the third master-slave state circuit 311, and may invert the signal to provide the inverted signal to the third master-slave state circuit 311.

[0047] In some example embodiments, each of the signals stored in the first to third master-slave state circuits 111, 211, and 311 may be independently determined. For example, the first master-slave state circuit 111 may be initialized regardless of the operation of the second initialization circuit 212 and the third initialization circuit 312, or regardless of the signals stored in the second master-slave state circuit 211 and the third master-slave state circuit 311. In addition, for example, receiving the signal of the first master-slave determination circuit 113 from the second master-slave state circuit 211 may be independently performed regardless of the operation of the second master-slave determination circuit 213, or regardless of the signals stored in the first master-slave state circuit 111 and the third master-slave state circuit 311. In addition, the inverted signal of the first master-slave determination circuit 113 may be independently provided to the second master-slave state circuit 211 regardless of the operation of the second master-slave determination circuit 213, or regardless of the signals stored in the first master-slave state circuit 111 and the third master-slave state circuit 311. Therefore, the signals stored in the first to third master-slave state circuits 111, 211, and 311 can be determined in parallel (i.e., substantially simultaneously). Since the signals stored in the first to third master-slave state circuits 111, 211, and 311 are determined in parallel, the delay of the semiconductor package 1000 can be reduced.

[0048] The package substrate 100 may be connected to the outside. For example, the package substrate 100 may be connected to the outside via the package ball PKGB. According to some example embodiments, a specific signal may be provided from the outside to the package ball PKGB. The specific signal provided to the package ball PKGB may be provided to the package substrate 100.

[0049] Figure 2 is an example flow chart for explaining the operation of the semiconductor package 1000 according to example embodiments. Figure 3 According to an example embodiment Figure 2 An example timing diagram of the operation of

[0050] refer to Figures 1 to 3 , power may be supplied from the outside to the semiconductor package 1000 ( S210 ). When the semiconductor package 1000 receives power, the power may be provided to each of the first to third chips 110 , 210 , and 310 .

[0051] The first to third initialization circuits 112, 212, and 312 may respectively and independently initialize the first to third master-slave state circuits 111, 211, and 311 (S220). For example, when the power supplied from the outside to the first to third chips 110, 210, and 310 reaches the first power level L1 or higher, the first to third initialization circuits 112, 212, and 312 may respectively and independently generate the first to third initial signals. The first to third initial signals may be respectively and independently supplied to the first to third master-slave state circuits 111, 211, and 311. When the first to third master-slave state circuits 111, 211, and 311 receive the first to third initial signals, the first to third master-slave state circuits 111, 211, and 311 may respectively and independently store the first signal of the first level. For example, the first master-slave state circuit 111 may independently store a first signal of a first level upon receiving a first initial signal, the second master-slave state circuit 211 may independently store a first signal of a first level upon receiving a second initial signal, and the third master-slave state circuit 311 may independently store a first signal of a first level upon receiving a third initial signal. For example, the first level may be a logic low level (0). In some example embodiments, the first to third initial signals may be identical or substantially identical to one another, but example embodiments are not limited thereto.

[0052] According to some example embodiments, before a first time point Ti, the first to third master-slave state circuits 111, 211, and 311 may be in an unknown state or in a disabled state, wherein the first to third master-slave state circuits 111, 211, and 311 are initialized at the first time point Ti.

[0053] For ease of explanation, Figure 3 A state is shown in which the first to third initialization circuits 112, 212, and 312 generate first to third initialization signals, respectively, and simultaneously initialize the first to third master-slave state circuits 111, 211, and 311. However, example embodiments are not limited thereto.

[0054] In addition, despite Figure 3 The first to third initial signals are shown in the form of pulse signals, but example embodiments are not limited thereto. For example, the first to third initial signals may be step signals, or may be signals in other forms.

[0055] In an example embodiment, each of the first to third master-slave state circuits 111, 211, and 311 stores a desired first signal of a first level upon receiving the first to third initial signals. However, example embodiments are not limited thereto. A person of ordinary skill in the art of the inventive concept may initialize the first to third master-slave state circuits 111, 211, and 311 in various ways.

[0056] The first master-slave determination circuit 113 and the second master-slave determination circuit 213 may respectively and independently receive signals stored in the initialized second master-slave state circuit 211 and the third master-slave state circuit 311 (S230). For example, the first master-slave determination circuit 113 may receive a signal stored in the initialized second master-slave state circuit 211. For example, the first master-slave determination circuit 113 may receive a first signal of a first level stored in the second master-slave state circuit 211. For example, the second master-slave determination circuit 213 may receive a signal stored in the third master-slave state circuit 311. For example, the second master-slave determination circuit 213 may receive a first signal of a first level stored in the third master-slave state circuit 311.

[0057] For ease of explanation, Figure 3 It is shown that the first time point Ti at which the second master-slave state circuit 211 and the third master-slave state circuit 311 are initialized is the same as the first time point Ti at which the first master-slave determination circuit 113 and the second master-slave determination circuit 213 receive signals stored in the second master-slave state circuit 211 and the third master-slave state circuit 311, respectively. However, example embodiments are not limited thereto. For example, the time point at which the second master-slave state circuit 211 and the third master-slave state circuit 311 are initialized may be slightly different from the time point at which the first master-slave determination circuit 113 and the second master-slave determination circuit 213 receive signals stored in the second master-slave state circuit 211 and the third master-slave state circuit 311, respectively.

[0058] The first master-slave determination circuit 113 and the second master-slave determination circuit 213 may invert the received signals, respectively (S240). For example, the first master-slave determination circuit 113 may invert the signal received from the second master-slave state circuit 211. For example, the first master-slave determination circuit 113 may receive a first signal of a first level from the second master-slave state circuit 211, and may generate a second signal of a second level, the second signal of the second level being an inverted signal of the first signal of the first level. In addition, independent of the operation of the first master-slave determination circuit 113, the second master-slave determination circuit 213 may invert the signal received from the third master-slave state circuit 311. For example, the second master-slave determination circuit 213 may receive a first signal of a first level from the third master-slave state circuit 311, and may generate a second signal of a second level. For example, the second level may be a logic high level (1).

[0059] The first master-slave determination circuit 113 and the second master-slave determination circuit 213 may provide the inverted signals to the second master-slave state circuit 211 and the third master-slave state circuit 311, respectively, independently (S250). For example, the first master-slave determination circuit 113 may provide the second signal of the second level to the second master-slave state circuit 211, and independently of this operation, the second master-slave determination circuit 213 may provide the second signal of the second level to the third master-slave state circuit 311.

[0060] The second master-slave state circuit 211 and the third master-slave state circuit 311 may receive the inverted signal independently from the first master-slave determination circuit 113 and the second master-slave determination circuit 213, respectively (S260). For example, the second master-slave state circuit 211 may receive the second signal of the second level from the first master-slave determination circuit 113, and independently of this operation, the third master-slave state circuit 311 may receive the second signal of the second level from the second master-slave determination circuit 213.

[0061] For ease of explanation, Figure 3 It is shown that the second time point Ts at which the first master-slave determination circuit 113 and the second master-slave determination circuit 213 respectively invert the received signal, the second time point Ts at which the first master-slave determination circuit 113 and the second master-slave determination circuit 213 respectively provide the inverted signal, and the second time point Ts at which the second master-slave state circuit 211 and the third master-slave state circuit 311 respectively receive the inverted signal are the same. However, exemplary embodiments are not limited thereto.

[0062] The first to third master-slave state circuits 111, 211, and 311 may respectively output first to third master-slave state signals (MS STATUS_1 to MS STATUS_3) (S270). For example, after the second time point Ts, the signals stored in the first to third master-slave state circuits 111, 211, and 311 may respectively be the first to third master-slave state signals (MS STATUS_1 to MS STATUS_3).

[0063] The signal stored in the first master-slave state circuit 111 may be a first signal of a first level. In other words, the first master-slave state circuit 111 may output a first signal of a first level as the first master-slave state signal MS STATUS_1.

[0064] Between the first time point Ti and the second time point Ts, the signal stored in the second master-slave state circuit 211 and the third master-slave state circuit 311 may be a first signal of a first level. After the second time point Ts, the signal stored in the second master-slave state circuit 211 and the third master-slave state circuit 311 may be a second signal of a second level. In other words, the second master-slave state circuit 211 and the third master-slave state circuit 311 may output a second signal of a second level as the second master-slave state signal and the third master-slave state signal STATUS_2 and MS STATUS_3, respectively. Figure 4 and Figure 5 A process of determining the first to third master-slave status signals (MS STATUS_1 to MS STATUS_3) is described.

[0065] Figure 4 is an example diagram illustrating a process of determining a first master-slave state signal MS STATUS_1 according to an example embodiment. Figure 5 is an example diagram illustrating a process of determining a second master-slave status signal and a third master-slave status signal (MSSTATUS_2 and MSSTATUS_3) according to an example embodiment.

[0066] refer to Figure 4 , the first initialization circuit 112 may initialize the first master-slave state circuit 111. When the first master-slave state circuit 111 is initialized, the first master-slave state circuit 111 may store the first signal of the first level. Thereafter, since no other signal is provided to the first master-slave state circuit 111, the first master-slave state circuit 111 may maintain the first signal of the first level. Therefore, the first master-slave state signal MS STATUS_1 may be the first signal of the first level.

[0067] refer to Figure 5, the second initialization circuit 212 may initialize the second master-slave state circuit 211. When the second master-slave state circuit 211 is initialized, the second master-slave state circuit 211 may store a first signal of a first level. The second master-slave state circuit 211 may provide an initial signal (e.g., a first signal of a first level) to the first master-slave determination circuit 113. The first master-slave determination circuit 113 may invert the received first signal of a first level, and may again provide a second signal of a second level to the second master-slave state circuit 211. Since no other signal is provided to the second master-slave state circuit 211, the second master-slave state signal MS STATUS_2 may be a second signal of a second level. The process of generating the third master-slave state signal MS STATUS_3 may be similar to the process of generating the second master-slave state signal MS STATUS_2. Therefore, the third master-slave state signal MS STATUS_3 may be a second signal of a second level. In some example embodiments, the second master-slave state signal MS STATUS_2 may be determined independently of the third master-slave state signal MS STATUS_3 and in parallel with the third master-slave state signal MS STATUS_3.

[0068] In some example embodiments, assuming that all external influences such as noise are ignored, the signal finally stored in the first master-slave state circuit 111 (e.g., the first master-slave state signal MS STATUS_1) may be determined only by the first initialization circuit 112. In addition, the signals finally stored in the second master-slave state circuit 211 and the third master-slave state circuit 311 (e.g., the second master-slave state signal MS STATUS_2 and the third master-slave state signal MS STATUS_3) may be determined by the first master-slave determination circuit 113 and the second master-slave determination circuit 213, respectively.

[0069] refer to Figures 1 to 5, no other chip may be connected to the lower part of the first chip 110. Therefore, no master-slave determination circuit may be connected to the first master-slave state circuit 111. Therefore, after the first time point Ti (at which the first master-slave state circuit 111 is initialized), no other signal may be provided to the first master-slave state circuit 111. On the other hand, the first chip 110 may be connected to the lower part of the second chip 210, and the second chip 210 may be connected to the lower part of the third chip 310. Therefore, at the second time point Ts, the second master-slave state circuit 211 may receive a second signal of a second level from the first master-slave determination circuit 113, and the third master-slave state circuit 311 may receive a second signal of a second level from the second master-slave determination circuit 213. Therefore, the first master-slave state signal MS STATUS_1 may have a different level from the second master-slave state signal MSSTATUS_2 and the third master-slave state signal MS STATUS_3.

[0070] According to some embodiments, when the master-slave status signal is a first signal of a first level, a chip including a master-slave status circuit for outputting the master-slave status signal may be identified as a master chip. According to some example embodiments, when the master-slave status signal is a second signal of a second level, a chip including a master-slave status circuit for outputting the master-slave status signal may be identified as a slave chip. According to the example embodiments disclosed above, since the first master-slave status circuit 111 outputs a first signal of a first level as the first master-slave status signal MS STATUS_1, the first chip 110 may be identified as a master chip. In addition, since the second master-slave status circuit 211 and the third master-slave status circuit 311 output a second signal of a second level as the second master-slave status signal MS STATUS_2 and the third master-slave status signal MS STATUS_3, respectively, the second chip 210 and the third chip 310 may be identified as slave chips.

[0071] Figure 6 1 is an example timing diagram for explaining the operation of the semiconductor package 1000 according to another example embodiment. For convenience of explanation, repeated contents will be omitted or briefly explained.

[0072] refer to Figure 6In an example embodiment, at a first time point Ti, the first master-slave state circuit to the third master-slave state circuit 111, 211, and 311 may be initialized by the first initial signal to the third initial signal to store a first signal of a first level. At a second time point Ts, the second master-slave state circuit 211 and the third master-slave state circuit 311 may store a second signal of a second level. In addition, at the first time point Ti, each of the first master-slave determination circuit 113 and the second master-slave determination circuit 213 may receive a first signal of a first level from each of the second master-slave state circuit 211 and the third master-slave state circuit 311, and may invert the first signal to output a second signal of a second level, and may provide the second signal to each of the second master-slave state circuit 211 and the third master-slave state circuit 311. The first level may be, for example, a logic high level (e.g., "1"). The second level may be, for example, a logic low level (e.g., "0").

[0073] Figures 7 to 9 1 is an example diagram for explaining application of the first to third master-slave state signals MS STATUS_1 to MS STATUS_3 to the semiconductor package 1000 according to some example embodiments. For ease of explanation, Figures 7 to 9 Shown omitted Figure 1 An illustration of the constituent elements shown in .

[0074] refer to Figure 7 , a semiconductor package 1000 according to example embodiments may include a package substrate 100 , first to third chips 110 , 210 , and 310 , package balls PKGB, and fourth, fifth, and sixth bumps B4 , B5 , and B6 .

[0075] The first chip 110 may include a first input buffer 116 , a first internal circuit 117 , a first input switch ISW_1 , and a first receiving switch RSW_1 .

[0076] The first input buffer 116 may be connected to the first input switch ISW_1. In addition, the first input buffer 116 may be connected to the package substrate 100 via the fourth bump B4. One end of the first input switch ISW_1 may be connected to the first input buffer 116, and the other end of the first input switch ISW_1 may be connected to the first node N1. The first internal circuit 117 may be connected to the first node N1. The first node N1 may be connected to the fifth bump B5.

[0077] The second chip 210 may include a second input buffer 216, a second internal circuit 217, a second input switch ISW_2, and a second receiving switch RSW_2. The second chip 210 may be connected to the first chip 110 via a fifth bump B5.

[0078] The second input buffer 216 may be connected to the second input switch ISW_2. One end of the second input switch ISW_2 may be connected to the second input buffer 216, and the other end of the second input switch ISW_2 may be connected to the second node N2. One end of the second receiving switch RSW_2 may be connected to the second node N2, and the other end of the second receiving switch RSW_2 may be connected to the fifth bump B5. The second internal circuit 217 may be connected to the second node N2. The second node N2 may be connected to the sixth bump B6. The second node N2 may be connected to the fifth bump B5 via the second receiving switch RSW_2.

[0079] The third chip 310 may include a third input buffer 316, a third internal circuit 317, a third input switch ISW_3, and a third receiving switch RSW_3. The third chip 310 may be connected to the second chip 210 through a sixth bump.

[0080] The third input buffer 316 may be connected to the third input switch ISW_3. One end of the third input switch ISW_3 may be connected to the third input buffer 316, and the other end of the third input switch ISW_3 may be connected to the third node N3. One end of the third receiving switch RSW_3 may be connected to the third node N3, and the other end of the third receiving switch RSW_3 may be connected to the sixth bump B6. The third internal circuit 317 may be connected to the third node N3. The third node N3 may be connected to the sixth bump B6 via the third receiving switch RSW_3.

[0081] In some embodiments, the first input switch ISW_1 to the third input switch ISW_3 and the first receiving switch RSW_1 to the third receiving switch RSW_3 may be controlled to be turned on / off by a control signal. For example, the first input switch ISW_1 to the third input switch ISW_3 and the first receiving switch RSW_1 to the third receiving switch RSW_3 may be implemented as NMOS, PMOS and / or CMOS, and the first input switch ISW_1 to the third input switch ISW_3 and the first receiving switch RSW_1 to the third receiving switch RSW_3 may be controlled to be turned on / off according to a control signal input to a gate. The control signal may be provided by a processing device (not shown) included in the semiconductor package 1000. In some example embodiments, the control signal may be provided by a processing device disposed outside the semiconductor package 1000.

[0082] The processing device can be implemented using one or more hardware devices configured to execute and / or implement program codes by performing arithmetic, logic and input / output operations. The processing device may include a processor, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a field programmable array, a programmable logic unit, a microprocessor, or any other device that can respond to instructions and execute instructions in a defined manner. The processing device can run an operating system (OS) and one or more software applications running on the OS. The processing device can also access, store, manipulate, process and create data in response to the execution of the software. For the purpose of simplicity, the processing device is described in the singular; however, it should be understood by those skilled in the art that the processing device may include multiple processing elements and multiple types of processing elements. For example, the processing device may include multiple processors or a processor and a controller. In addition, different processing configurations are feasible, such as parallel processors, multi-core processors, distributed processing, etc.

[0083] Software may include a computer program, a piece of code, instructions, or some combination thereof, to independently or collectively instruct and / or configure a processing device to operate as desired, thereby converting the processing device into a special-purpose processor. Software and data may be embodied permanently or temporarily in any type of machine, component, physical or virtual device, and / or computer storage medium or device. Software may also be distributed on network-coupled computer systems so that the software is stored and executed in a distributed manner. Software and data may be stored by one or more computer-readable recording media.

[0084] refer to Figure 8 , the first input switches ISW_1 to the third input switches ISW_3 and the first receiving switches RSW_1 to the third receiving switches RSW_3 can be respectively controlled to be turned on / off by the first master-slave status signal to the third master-slave status signal (MS STATUS_1 to MS_STATUS_3). For example, the first input switch ISW_1 and the first receiving switch RSW_1 can be controlled to be turned on / off by the first master-slave status signal MS STATUS_1, the second input switch ISW_2 and the second receiving switch RSW_2 can be controlled to be turned on / off by the second master-slave status signal MSSTATUS_2, and the third input switch ISW_3 and the third receiving switch RSW_3 can be controlled to be turned on / off by the third master-slave status signal MS STATUS_3.

[0085] refer to Figure 7In the example embodiment shown in , the first input switch ISW_1 may be turned on by the first master-slave state signal MS STATUS_1, and thus the first input buffer 116 and the first internal circuit 117 may be connected to each other by the first master-slave state signal MS STATUS_1. In addition, the second input switch ISW_2 may be turned off by the second master-slave state signal MS STATUS_2, and thus the second input buffer 216 and the second internal circuit 217 may be disconnected from each other by the second master-slave state signal MS STATUS_2, thereby blocking the signal or noise from the second input buffer 216 from being provided to the second node N2. In addition, the third input switch ISW_3 may be turned off by the third master-slave state signal MS STATUS_3, and thus the third input buffer 316 and the third internal circuit 317 may be disconnected from each other by the third master-slave state signal MS STATUS_3, thereby blocking the signal or noise from the third input buffer 316 from being provided to the third node N3.

[0086] According to this example embodiment, since the first master-slave state signal MS STATUS_1 is a signal having a different level from the second and third master-slave state signals MS STATUS_2 and MS STATUS_3 , the first input switch ISW_1 may perform an operation opposite to that of the second and third input switches ISW_2 and ISW_3 .

[0087] refer to Figure 8 In another example embodiment shown in , the first receiving switch RSW_1 can be disconnected by the first master-slave state signal MS STATUS_1. Therefore, the signal or noise received from the outside through the first node N1 can be blocked by the first master-slave state signal MS STATUS_1. In addition, the second receiving switch RSW_2 can be turned on by the second master-slave state signal MS STATUS_2, so the first node N1 and the second node N2 can be connected to each other by the second master-slave state signal MS STATUS_2. In addition, the second receiving switch RSW_3 can be turned on by the third master-slave state signal MS STATUS_3, so the second node N2 and the third node N3 can be connected to each other by the third master-slave state signal MS STATUS_3.

[0088] According to the above example embodiment, since the first master-slave state signal MS STATUS_1 is a signal having a different level from the second and third master-slave state signals MS STATUS_2 and MS STATUS_3 , the first reception switch RSW_1 may perform an operation opposite to that of the second and third reception switches RSW_2 and RSW_3 .

[0089] refer to Fig. 9 In another example embodiment shown in , data D input from the outside may be provided to the package substrate 100 via the package ball PKGB. The data D may be provided to the first input buffer 116 via the fourth bump B4. The data D provided to the first input buffer 116 may be provided to the first internal circuit 117 via the first node N1. At this time, because the first receiving switch RSW_1 is turned off, the data D may be provided to the first internal circuit 117 without damage that may be caused by the signal and noise transmitted from the outside.

[0090] In addition, data D may be provided to the second node N2 via the fifth bump B5 and the second receiving switch RSW_2. At this time, since the second input switch TSW_2 is turned off, the damage to the data D due to the second input buffer 216 and noise may be mitigated or prevented. The data D provided to the second node N2 may be provided to the second internal circuit 217.

[0091] In addition, data D may be provided to the third node N3 via the sixth bump B6 and the third receiving switch RSW_3. At this time, because the third input switch ISW_3 is turned off, the damage to the data D due to the third input buffer 316 and noise may be mitigated or prevented. The data D provided to the third node N3 may be provided to the third internal circuit 317.

[0092] At the end of the detailed description, it should be understood by those skilled in the art that many changes and modifications may be made to the disclosed exemplary embodiments without departing substantially from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments of the inventive concept are used only in a general and descriptive sense and not for a limiting purpose.

Claims

1. A semiconductor package, comprising: a first master-slave state circuit configured to store one of a first signal at a first level or a second signal at a second level, the first master-slave state circuit configured to store the first signal in response to receiving a first initialization signal from a first initialization circuit, the first master-slave state circuit configured to store one of the first signal or the second signal independently of one of the first signal or the second signal stored in a second master-slave state circuit; a second master-slave state circuit configured to store one of the first signal or the second signal, the second master-slave state circuit configured to store the first signal in response to receiving a second initialization signal from a second initialization circuit; a first initialization circuit, configured to provide the first initialization signal to the first master-slave state circuit; a second initialization circuit, configured to provide the second initialization signal to the second master-slave state circuit; as well as The first master-slave determination circuit is connected to the second master-slave state circuit, and the first master-slave determination circuit is configured to provide the second signal to the second master-slave state circuit.

2. The semiconductor package according to claim 1, wherein In response to the power received from the outside being equal to or higher than a desired level, The first initialization circuit is configured to generate the first initialization signal independently of the second initialization circuit and provide the first initialization signal to the first master-slave state circuit, and The second initialization circuit is configured to generate the second initialization signal independently of the first initialization circuit and provide the second initialization signal to the second master-slave state circuit.

3. The semiconductor package according to claim 2, wherein: In response to the power received from the outside being equal to or higher than the desired level, The first master-slave determination circuit is configured to receive the first signal from the second master-slave state circuit, invert the received first signal, and output the inverted first signal as the second signal to the second master-slave state circuit, and The second master-slave state circuit is configured to receive the second signal from the first master-slave determination circuit and store the second signal.

4. The semiconductor package according to claim 1, further comprising: A first chip, comprising the first master-slave state circuit, the first initialization circuit and the first master-slave determination circuit; as well as A second chip is on the first chip, wherein the second chip includes the second master-slave state circuit and the second initialization circuit.

5. The semiconductor package according to claim 4, further comprising: a third chip, on the second chip, the third chip comprising a third master-slave state circuit and a third initialization circuit, the third master-slave state circuit being configured to store one of the first signal or the second signal, and the third initialization circuit being configured to provide a third initialization signal to the third master-slave state circuit, wherein the third master-slave state circuit is configured to store the first signal in response to receiving the third initialization signal from the third initialization circuit, and The second chip further includes a second master-slave determination circuit connected to the third master-slave state circuit and configured to provide the second signal to the third master-slave state circuit.

6. The semiconductor package according to claim 5, wherein: The first chip further includes a first through silicon via, the first through silicon via connecting the first master-slave determination circuit to the second master-slave state circuit, and The second chip further includes a second through silicon via connecting the second master-slave determination circuit to the third master-slave state circuit.

7. The semiconductor package according to claim 6, further comprising: a first bump, between the first chip and the second chip; as well as a second bump, between the second chip and the third chip, The second chip further includes a first pad connected to the second master-slave state circuit. The third chip further includes a second pad connected to the third master-slave state circuit, and The first master-slave determination circuit is connected to the first through silicon via, the second master-slave determination circuit is connected to the second through silicon via, the first through silicon via and the first pad are connected to the first bump, and the second through silicon via and the second pad are connected to the second bump.

8. The semiconductor package according to claim 4, wherein: The semiconductor package is configured to identify the first chip as a master chip in response to the first signal being stored in the first master-slave status circuit, and to identify the first chip as a slave chip in response to the second signal being stored in the first master-slave status circuit, and The semiconductor package is configured to identify the second chip as the master chip in response to the first signal being stored in the second master-slave state circuit, and to identify the second chip as the slave chip in response to the second signal being stored in the second master-slave state circuit.

9. The semiconductor package according to claim 8, wherein: The first level is a logic low level, and the second level is a logic high level.

10. The semiconductor package according to claim 8, wherein The first level is a logic high level, and the second level is a logic low level.

11. A semiconductor package, comprising: A first chip, the first chip comprising: a first master-slave state circuit configured to store one of a first signal of a first level or a second signal of a second level, and A first initialization circuit is configured to initialize the first master-slave state circuit; as well as A second chip, the second chip comprising: a second master-slave state circuit configured to store one of the first signal or the second signal, a second initialization circuit configured to initialize the second master-slave state circuit, and A first master-slave determination circuit is connected to the first master-slave state circuit, and the first master-slave determination circuit is configured to receive one of the first signal or the second signal stored in the first master-slave state circuit, invert one of the first signal or the second signal received from the first master-slave state circuit, and provide the inverted one of the first signal or the second signal to the first master-slave state circuit.

12. The semiconductor package according to claim 11, wherein In response to the power received from the outside being equal to or higher than a desired level, The first initialization circuit is configured to initialize the first master-slave state circuit. The second initialization circuit is configured to initialize the second master-slave state circuit, and The initialization of the first master-slave state circuit by the first initialization circuit and the initialization of the second master-slave state circuit by the second initialization circuit are performed independently.

13. The semiconductor package according to claim 12, wherein: In response to the first master-slave state circuit and the second master-slave state circuit being initialized, each of the first master-slave state circuit and the second master-slave state circuit is configured to store the first signal.

14. The semiconductor package according to claim 13, wherein: In response to the power received from the outside being equal to or higher than the desired level, The first master-slave determination circuit is configured to receive the first signal from the first master-slave state circuit, invert the first signal, and provide the inverted first signal as the second signal to the first master-slave state circuit, and The first master-slave state circuit is configured to receive the second signal from the first master-slave determination circuit and store the second signal.

15. The semiconductor package according to claim 11, wherein The semiconductor package is configured to identify the first chip as a master chip in response to the first signal being stored in the first master-slave status circuit, and to identify the first chip as a slave chip in response to the second signal being stored in the first master-slave status circuit, and The semiconductor package is configured to identify the second chip as the master chip in response to the first signal being stored in the second master-slave state circuit, and to identify the second chip as the slave chip when the first signal is stored in the second master-slave state circuit.

16. A semiconductor package, comprising: A first chip, the first chip comprising: a first master-slave state circuit configured to store one of a first signal of a first level or a second signal of a second level, a first master-slave determination circuit configured to receive one of the first signal or the second signal from a second master-slave state circuit, invert one of the first signal or the second signal, and provide the inverted one of the first signal or the second signal to the second master-slave state circuit, the first master-slave determination circuit being connected to the second master-slave state circuit, a first input buffer configured to store first data, a first internal circuit configured to process the first data, and a first switch configured to control a connection between the first input buffer and the first internal circuit based on a signal from the first master-slave state circuit; as well as A second chip, on the first chip, the second chip comprising: a second master-slave state circuit configured to store one of the first signal or the second signal, a second input buffer configured to store second data, a second internal circuit configured to process the second data, a second switch configured to control a connection between the second input buffer and the second internal circuit based on a signal from the second master-slave state circuit, and A third switch is configured to control a connection between the first input buffer and the second internal circuit based on a signal from the second master-slave state circuit.

17. The semiconductor package according to claim 16, wherein: The first chip further includes a first initialization circuit configured to initialize the first master-slave state circuit in response to determining that the power received by the first chip is equal to or higher than a desired level, and The second chip further includes a second initialization circuit configured to initialize the second master-slave state circuit in response to determining that the power received by the second chip is equal to or higher than the expected level.

18. The semiconductor package according to claim 17, wherein: In response to the first master-slave state circuit and the second master-slave state circuit being initialized, each of the first master-slave state circuit and the second master-slave state circuit is configured to store the first signal.

19. The semiconductor package according to claim 16, wherein: In response to the power received from the outside being equal to or higher than a desired level, The first master-slave determination circuit is configured to receive the first signal from the second master-slave state circuit, invert the first signal, and provide the inverted first signal as the second signal to the second master-slave state circuit, and The second master-slave state circuit is configured to receive the second signal from the first master-slave determination circuit and store the second signal.

20. The semiconductor package according to claim 16, wherein In response to the first signal being stored in the first master-slave state circuit, the first switch is configured to connect the first input buffer to the first internal circuit, and In response to the second signal being stored in the second master-slave state circuit, the second switch is configured to disconnect the second input buffer from the second internal circuit, and the third switch is configured to connect the first input buffer to the second internal circuit.

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