Dynamic D flip-flop, data operation unit, chip, computing board and computing equipment

Abstract

The present invention provides a dynamic D flip-flop, a data operation unit, a chip, a computing board, and a computing device. The dynamic D flip-flop includes an input terminal, an output terminal, and a clock signal terminal; a first data transmission unit; a first latch unit; a second data transmission unit; and a second latch unit. The first data transmission unit, the first latch unit, the second data transmission unit, and the second latch unit are sequentially connected in series between the input terminal and the output terminal, a first node is defined between the first data transmission unit and the first latch unit, and a second node is defined between the second data transmission unit and the second latch unit. The device further includes a leakage compensation unit, which is electrically connected between the first node, the second node, and the output terminal. This can increase the equivalent capacitance of the node, compensate for the dynamic leakage current of the node, and improve the security and accuracy of the data.

Description

Technical Field

[0001] The present invention relates to a clock-controlled storage device, and in particular to a dynamic D-type flip-flop, a data operation unit, a chip, a computing board, and a computing device used in large-scale data computing equipment. Background Art

[0002] Dynamic D flip-flops are widely used and can be used to store digital signals. Figure 1 The circuit structure diagram of the existing dynamic D flip-flop is shown in FIG. Figure 1 As shown, the dynamic D flip-flop includes a transmission gate 101, an inverter 102, a transmission gate 103, and an inverter 104 connected in series between an input terminal D and an output terminal Q. A node S0 is formed between transmission gate 101 and inverter 102, and a node S1 is formed between transmission gate 103 and inverter 104. Data is temporarily stored at node S0 and / or node S1 via parasitic capacitances of transistors in inverter 102 and inverter 104. However, nodes S0 and S1 are prone to dynamic leakage, resulting in loss of the temporarily stored data.

[0003] Therefore, how to effectively reduce the dynamic leakage of the dynamic D flip-flop is a problem that needs to be solved. Summary of the Invention

[0004] In order to solve the above problems, the present invention provides a dynamic D flip-flop, which can effectively increase the equivalent capacitance of the node, compensate for the dynamic leakage current of the node, and improve the security and accuracy of data.

[0005] In order to achieve the above-mentioned objectives, the present invention provides a dynamic D flip-flop, comprising an input end for inputting data; an output end for outputting the data; a clock signal end for providing a clock signal; a first data transmission unit for transmitting the data under the control of the clock signal; a first latch unit for latching the data transmitted by the first data transmission unit; a second data transmission unit for transmitting the data latched by the first latch unit under the control of the clock signal; a second latch unit for latching the data transmitted by the second data transmission unit; the first data transmission unit, the first latch unit, the second data transmission unit, and the second latch unit are connected in series between the input end and the output end in sequence, a first node is provided between the first data transmission unit and the first latch unit, and a second node is provided between the second data transmission unit and the second latch unit; wherein, a leakage compensation unit is also included, and the leakage compensation unit is electrically connected between the first node, the second node and the output end.

[0006] The above-mentioned dynamic D trigger, wherein the leakage compensation unit has a first end, a second end and a control end, the first end is electrically connected to the output end, the second end is electrically connected to the first node, and the control end is electrically connected to the second node.

[0007] In the above-mentioned dynamic D flip-flop, the leakage compensation unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the output terminal and the first node.

[0008] The above-mentioned dynamic D trigger, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, the source terminal of the NMOS transistor is electrically connected to the first node, and the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the second node.

[0009] The above-mentioned dynamic D trigger, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the NMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the PMOS transistor, the source terminal of the PMOS transistor is electrically connected to the first node, and the PMOS transistor and the gate terminal of the NMOS transistor are connected in parallel and electrically connected to the second node.

[0010] In the above-mentioned dynamic D flip-flop, the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in opposite phases.

[0011] In the above-mentioned dynamic D flip-flop, the first data transmission unit and / or the second data transmission unit is a transmission gate.

[0012] In the above-mentioned dynamic D flip-flop, the first latch unit and / or the second latch unit is an inverter.

[0013] The use of the dynamic D trigger of the present invention can effectively increase the equivalent capacitance of the node, and can feed back leakage current from the output end to the node to compensate for the dynamic leakage current of the node, improve the stability of data storage, and thus enhance the security and accuracy of the data.

[0014] In order to better achieve the above-mentioned purpose, the present invention also provides a data operation unit, including a control circuit, an operation circuit, and multiple dynamic D flip-flops interconnected, wherein the multiple dynamic D flip-flops are connected in series and / or in parallel; wherein the multiple dynamic D flip-flops are any one of the above-mentioned dynamic D flip-flops.

[0015] In order to better achieve the above-mentioned purpose, the present invention also provides a chip, which includes at least one of the above-mentioned data operation units.

[0016] In order to better achieve the above-mentioned purpose, the present invention also provides a computing power board for a computing device, which includes at least one of the above-mentioned chips.

[0017] In order to better achieve the above-mentioned purpose, the present invention also provides a computing device, including a power board, a control board, a connection board, a radiator, and multiple computing boards, wherein the control board is connected to the computing board through the connection board, the radiator is arranged around the computing board, and the power board is used to provide power to the connection board, the control board, the radiator, and the computing board, wherein the computing board is the above-mentioned computing board.

[0018] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this does not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the circuit structure of an existing dynamic D flip-flop;

[0020] Figure 2 Schematic diagram of the circuit structure of a dynamic D flip-flop according to an embodiment of the present invention;

[0021] Figure 3 Schematic diagram of the circuit structure of a dynamic D flip-flop according to another embodiment of the present invention;

[0022] Figure 4 Schematic diagram of the structure of the data operation unit of the present invention;

[0023] Figure 5 Schematic diagram of the structure of the chip of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure of the hashboard of the present invention;

[0025] Figure 7 Schematic diagram of the structure of the computing device of the present invention.

[0026] Wherein, the reference numerals:

[0027] 100, 200: Dynamic D flip-flop

[0028] 101, 103: Transmission gate

[0029] 102, 104: Inverter

[0030] 201: First data transmission unit

[0031] 202: First latch unit

[0032] 203: Second data transmission unit

[0033] 204: Second latch unit

[0034] 205: Leakage compensation unit

[0035] 201P, 203P, 205P: PMOS transistors

[0036] 201N, 203N, 205N: NMOS transistors

[0037] 400: Data processing unit

[0038] 401: Control circuit

[0039] 402: Operational Circuit

[0040] 500: Chip

[0041] 501: Control unit

[0042] 600: Hash board

[0043] 700: Computing Equipment

[0044] 701: Connecting plate

[0045] 702: Control Panel

[0046] 703: Radiator

[0047] 704: Power board

[0048] D: Input terminal

[0049] Q: Output

[0050] CKP, CKN: clock signal

[0051] S0, S1: nodes DETAILED DESCRIPTION

[0052] The structural principle and working principle of the present invention are described in detail below with reference to the accompanying drawings:

[0053] Certain terms are used throughout this specification and the following claims to refer to specific components. A person skilled in the art will understand that manufacturers may use different terms to refer to the same component. This specification and the following claims do not distinguish components by name, but rather by their functional differences.

[0054] Throughout this specification and the following claims, the words "include" and "comprising" are open-ended terms and should be interpreted as meaning "including, but not limited to." Furthermore, the word "connect" is intended to encompass both direct and indirect electrical connections. Indirect electrical connections include connection through other devices.

[0055] Example 1:

[0056] Figure 2 FIG. 1 is a schematic diagram of the circuit structure of a dynamic D flip-flop according to an embodiment of the present invention. Figure 2 As shown, the dynamic D flip-flop 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, a first data transmission unit 201, a first latch unit 202, a second data transmission unit 203, a second latch unit 204, and a leakage compensation unit 205. The first data transmission unit 201, the first latch unit 202, the second data transmission unit 203, and the second latch unit 204 are sequentially connected in series between the input terminal D and the output terminal Q. A first node S0 is formed between the first data transmission unit 201 and the first latch unit 202, and a second node S1 is formed between the second data transmission unit 203 and the second latch unit 204. The leakage compensation unit 205 is electrically connected between the first node S0, the second node S1, and the output terminal Q. The input terminal D is used for inputting data, the output terminal is used for outputting data, the clock signal terminal CKN and the clock signal terminal CKP are used to provide clock signals CKN and CKP, respectively. The clock signals CKN and CKP are inverted clock signals.

[0057] Specifically, such as Figure 2As shown, the first data transmission unit 201 of the dynamic D flip-flop 200 has a transmission gate structure. The data transmission unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel. The source terminal of the PMOS transistor 201P is connected in parallel with the source terminal of the NMOS transistor 201N and is electrically connected to the input terminal D of the dynamic D flip-flop 200. The drain terminal of the PMOS transistor 201P is connected in parallel with the drain terminal of the NMOS transistor 201N and is electrically connected to the first node S0. The gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate terminal of the PMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is low, CKN is high, and both the PMOS transistor 201P and the NMOS transistor 201N are turned on. Data at the input terminal D of the dynamic D flip-flop 200 is transmitted to the first node S0 through the first data transmission unit 201. When CKP is high and CKN is low, both the PMOS transistor 201P and the NMOS transistor 201N are in a non-conducting state, and data at the input terminal D of the dynamic D flip-flop 200 cannot be transmitted to the first node S0 via the first data transmission unit 201. In this embodiment, the first data transmission unit 201 is exemplified by a transmission gate structure. Of course, other forms of data transmission units may also be used as long as they can implement a switching function under the control of a clock signal, and the present invention is not limited thereto.

[0058] Continue to refer to Figure 2 As shown, the first latch unit 202 of the dynamic D flip-flop 200 is an inverter structure. The first latch unit 202 can use its parasitic capacitance to temporarily store the data transmitted from the first data transmission unit 201, that is, the data at the first node S0, and can also invert the data at the first node S0 and transmit it to the second data transmission unit 203.

[0059] like Figure 2As shown, the second data transmission unit 202 of the dynamic D flip-flop 200 has a transmission gate structure. The second data transmission unit 203 includes a PMOS transistor 203P and an NMOS transistor 203N connected in parallel. The source terminal of the PMOS transistor 203P is connected in parallel with the source terminal of the NMOS transistor 203N and is electrically connected to the first latch unit 202. The drain terminal of the PMOS transistor 203P is connected in parallel with the drain terminal of the NMOS transistor 203N and is electrically connected to the second node S1. The gate terminal of the NMOS transistor 203N is electrically connected to the clock signal CKP, and the gate terminal of the PMOS transistor 203P is electrically connected to the clock signal CKN. When CKN is low, CKP is high, and both the PMOS transistor 203P and the NMOS transistor 203N are turned on. Data output by the first latch unit 202 is transmitted to the second node S1 via the second data transmission unit 203. When CKN is high, CKP is low, and both the PMOS transistor 203P and the NMOS transistor 203N are in a non-conducting state. Data at the input terminal D of the dynamic D flip-flop 200 cannot be transmitted to the second node S1 via the second data transmission unit 203. In this embodiment, the second data transmission unit 203 is exemplified by a transmission gate structure. Of course, other forms of data transmission units may also be used as long as they can implement a switching function under the control of a clock signal, and the present invention is not limited thereto.

[0060] Continue to refer to Figure 2 As shown, the second latch unit 204 of the dynamic D flip-flop 200 is an inverter structure. Like the first latch unit 202, the second latch unit 204 can use its parasitic capacitance to temporarily store the data transmitted from the second data transmission unit 203, that is, the data at the second node S1, and can also invert the data at the second node S1 and transmit it to the output terminal Q of the dynamic D flip-flop 200.

[0061] As can be seen, the first data transmission unit 201 and the second data transmission unit 203 are controlled by inverted clock signals, meaning that the first data transmission unit 201 and the second data transmission unit 203 are not simultaneously turned on and / or off. The first latch unit 202 and the second latch unit 204 in the dynamic D flip-flop 200 perform data storage according to the clock signal. Furthermore, the data at the input terminal D of the dynamic D flip-flop 200 is inverted by the first latch unit 202 and the second latch unit 204, making the data at the output terminal Q in phase with the data at the input terminal D. Furthermore, the first latch unit 202 and the second latch unit 204 also enhance data drive capability.

[0062] like Figure 2As shown, the dynamic D flip-flop 200 further includes a leakage compensation unit 205. In this embodiment, the leakage compensation unit 205 includes a PMOS transistor 205P and an NMOS transistor 205N. The PMOS transistor 205P and the NMOS transistor 205N are connected in series between the output terminal Q and a first node S0. The source terminal of the PMOS transistor 205P is electrically connected to the output terminal Q, the drain terminal of the PMOS transistor 205P is electrically connected to the drain terminal of the NMOS transistor 205N, the source terminal of the NMOS transistor 205N is electrically connected to the first node S0, and the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are connected in parallel and electrically connected to a second node S1.

[0063] Because the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are both electrically connected to the second node S1, when driven by a signal of the same level, the PMOS transistor 205P and the NMOS transistor 205N will not be turned on at the same time; only one of them can be turned on and the other can be turned off. For example, when the potential at the second node S1 is high, the PMOS transistor 205P is turned off, while the NMOS transistor 205N is turned on. When the potential at the second node S1 is low, the PMOS transistor 205P is turned on, while the NMOS transistor 205N is turned off. Therefore, the leakage compensation unit 205 can feed back the leakage current of the output terminal Q to the first node S0 while increasing the parasitic capacitance at the second node S1. This can both compensate for the leakage current at the first node S0 and increase the parasitic capacitance at the second node S1, thereby improving the stability of data storage at the first node S0 and the second node S1, and enhancing the accuracy and security of the data.

[0064] Example 2:

[0065] Figure 3 FIG. 4 is a schematic diagram of the circuit structure of a dynamic D flip-flop according to another embodiment of the present invention. Figure 3 FIG. 1 is a schematic diagram of the circuit structure of a dynamic D flip-flop according to an embodiment of the present invention. Figure 3As shown, the dynamic D flip-flop 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, a first data transmission unit 201, a first latch unit 202, a second data transmission unit 203, a second latch unit 204, and a leakage compensation unit 205. The first data transmission unit 201, the first latch unit 202, the second data transmission unit 203, and the second latch unit 204 are sequentially connected in series between the input terminal D and the output terminal Q. A first node S0 is formed between the first data transmission unit 201 and the first latch unit 202, and a second node S1 is formed between the second data transmission unit 203 and the second latch unit 204. The leakage compensation unit 205 is electrically connected between the first node S0, the second node S1, and the output terminal Q. The input terminal D is used for inputting data, the output terminal is used for outputting data, the clock signal terminal CKN and the clock signal terminal CKP are used to provide clock signals CKN and CKP, respectively. The clock signals CKN and CKP are inverted clock signals.

[0066] Specifically, such as Figure 3 As shown, the first data transmission unit 201 of the dynamic D flip-flop 200 has a transmission gate structure. The data transmission unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel. The source terminal of the PMOS transistor 201P is connected in parallel with the source terminal of the NMOS transistor 201N and is electrically connected to the input terminal D of the dynamic D flip-flop 200. The drain terminal of the PMOS transistor 201P is connected in parallel with the drain terminal of the NMOS transistor 201N and is electrically connected to the first node S0. The gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate terminal of the PMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is low, CKN is high, and both the PMOS transistor 201P and the NMOS transistor 201N are turned on. Data at the input terminal D of the dynamic D flip-flop 200 is transmitted to the first node S0 through the first data transmission unit 201. When CKP is high and CKN is low, both the PMOS transistor 201P and the NMOS transistor 201N are in a non-conducting state, and data at the input terminal D of the dynamic D flip-flop 200 cannot be transmitted to the first node S0 via the first data transmission unit 201. In this embodiment, the first data transmission unit 201 is exemplified by a transmission gate structure. Of course, other forms of data transmission units may also be used as long as they can implement a switching function under the control of a clock signal, and the present invention is not limited thereto.

[0067] Continue to refer to Figure 3As shown, the first latch unit 202 of the dynamic D flip-flop 200 is an inverter structure. The first latch unit 202 can use its parasitic capacitance to temporarily store the data transmitted from the first data transmission unit 201, that is, the data at the first node S0, and can also invert the data at the first node S0 and transmit it to the second data transmission unit 203.

[0068] like Figure 3 As shown, the second data transmission unit 202 of the dynamic D flip-flop 200 has a transmission gate structure. The second data transmission unit 203 includes a PMOS transistor 203P and an NMOS transistor 203N connected in parallel. The source terminal of the PMOS transistor 203P is connected in parallel with the source terminal of the NMOS transistor 203N and is electrically connected to the first latch unit 202. The drain terminal of the PMOS transistor 203P is connected in parallel with the drain terminal of the NMOS transistor 203N and is electrically connected to the second node S1. The gate terminal of the NMOS transistor 203N is electrically connected to the clock signal CKP, and the gate terminal of the PMOS transistor 203P is electrically connected to the clock signal CKN. When CKN is low, CKP is high, and both the PMOS transistor 203P and the NMOS transistor 203N are turned on. Data output by the first latch unit 202 is transmitted to the second node S1 via the second data transmission unit 203. When CKN is high, CKP is low, and both the PMOS transistor 203P and the NMOS transistor 203N are in a non-conducting state. Data at the input terminal D of the dynamic D flip-flop 200 cannot be transmitted to the second node S1 via the second data transmission unit 203. In this embodiment, the second data transmission unit 203 is exemplified by a transmission gate structure. Of course, other forms of data transmission units may also be used as long as they can implement a switching function under the control of a clock signal, and the present invention is not limited thereto.

[0069] Continue to refer to Figure 3 As shown, the second latch unit 204 of the dynamic D flip-flop 200 is an inverter structure. Like the first latch unit 202, the second latch unit 204 can use its parasitic capacitance to temporarily store the data transmitted from the second data transmission unit 203, that is, the data at the second node S1, and can also invert the data at the second node S1 and transmit it to the output terminal Q of the dynamic D flip-flop 200.

[0070] As can be seen, the first data transmission unit 201 and the second data transmission unit 203 are controlled by inverted clock signals, meaning that the first data transmission unit 201 and the second data transmission unit 203 are not simultaneously turned on and / or off. The first latch unit 202 and the second latch unit 204 in the dynamic D flip-flop 200 perform data storage according to the clock signal. Furthermore, the data at the input terminal D of the dynamic D flip-flop 200 is inverted by the first latch unit 202 and the second latch unit 204, making the data at the output terminal Q in phase with the data at the input terminal D. Furthermore, the first latch unit 202 and the second latch unit 204 also enhance data drive capability.

[0071] like Figure 3 As shown, the dynamic D flip-flop 200 further includes a leakage compensation unit 205. Figure 3 The embodiment shown differs in that, in this embodiment, the leakage compensation unit 205 includes a PMOS transistor 205P and an NMOS transistor 205N, which are connected in series between the output terminal Q and the first node S0. The source terminal of the PMOS transistor 205P is electrically connected to the first node S0, the drain terminal of the PMOS transistor 205P is electrically connected to the drain terminal of the NMOS transistor 205N, the source terminal of the NMOS transistor 205N is electrically connected to the output terminal Q, and the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are connected in parallel and electrically connected to the second node S1.

[0072] Because the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are both electrically connected to the second node S1, when driven by a signal of the same level, the PMOS transistor 205P and the NMOS transistor 205N will not be turned on at the same time; only one of them can be turned on and the other can be turned off. For example, when the potential at the second node S1 is high, the PMOS transistor 205P is turned off, while the NMOS transistor 205N is turned on. When the potential at the second node S1 is low, the PMOS transistor 205P is turned on, while the NMOS transistor 205N is turned off. Therefore, the leakage compensation unit 205 can feed back the leakage current of the output terminal Q to the first node S0 while increasing the parasitic capacitance at the second node S1. This can both compensate for the leakage current at the first node S0 and increase the parasitic capacitance at the second node S1, thereby improving the stability of data storage at the first node S0 and the second node S1, and enhancing the accuracy and security of the data.

[0073] The present invention also provides a data operation unit, Figure 4 Figure 1 is a schematic diagram of the structure of the data operation unit of the present invention. Figure 4As shown, the data operation unit 400 includes a control circuit 401, an operation circuit 402, and a plurality of dynamic registers 200. The control circuit 401 refreshes the data in the dynamic register 200 and reads data from the dynamic register 200. The operation circuit 402 operates on the read data, and the control circuit 401 outputs the operation result.

[0074] The present invention also provides a chip, Figure 5 FIG. 1 is a schematic diagram of the structure of the chip of the present invention. Figure 5 As shown, the chip 500 includes a control unit 501 and one or more data operation units 400. The control unit 501 inputs data to the data operation unit 400 and processes the data output by the data operation unit 400.

[0075] The present invention also provides a computing board. Figure 6 This is a schematic diagram of the structure of the hashboard of the present invention. Figure 6 As shown, each computing board 600 includes one or more chips 500 to perform large-scale operations on the working data sent by the computing device.

[0076] The present invention also provides a computing device, which can be used for any massive calculations. Figure 7 FIG. 1 is a schematic diagram of the structure of the computing device of the present invention. Figure 7 As shown, each computing device 700 includes a connection board 701, a control board 702, a heat sink 703, a power board 704, and one or more hash boards 600. The control board 702 is connected to the hash board 600 via the connection board 701, and the heat sink 703 is arranged around the hash board 600. The power board 704 is used to provide power to the connection board 701, control board 702, heat sink 703, and hash board 600.

[0077] It should be noted that, in the description of the present invention, the terms "horizontal", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0078] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A dynamic D flip-flop, characterized in that: include: An input terminal for inputting data; an output terminal, for outputting the data; A clock signal terminal, used for providing a clock signal; a first data transmission unit, configured to transmit the data under the control of the clock signal; a first latch unit, configured to latch the data transmitted by the first data transmission unit; a second data transmission unit, configured to transmit the data latched by the first latch unit under the control of the clock signal, wherein the second data transmission unit is controlled by the clock signal in an inverted phase relative to the first data transmission unit; a second latch unit, configured to latch the data transmitted by the second data transmission unit; The first data transmission unit, the first latch unit, the second data transmission unit, and the second latch unit are sequentially connected in series between the input end and the output end, a first node is defined between the first data transmission unit and the first latch unit, and a second node is defined between the second data transmission unit and the second latch unit; It also includes a leakage compensation unit for feeding back the leakage current of the output end to the first node for leakage compensation and increasing the parasitic capacitance at the second node; wherein the leakage compensation unit includes a PMOS transistor and an NMOS transistor, the PMOS transistor and the NMOS transistor are connected in series between the output end and the first node; and the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the second node.

2. The dynamic D flip-flop according to claim 1, wherein: The PMOS transistor has a source terminal, a drain terminal, and a gate terminal, and the NMOS transistor has a source terminal, a drain terminal, and a gate terminal. The source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the first node.

3. The dynamic D flip-flop according to claim 1, wherein: The PMOS transistor has a source terminal, a drain terminal, and a gate terminal, and the NMOS transistor has a source terminal, a drain terminal, and a gate terminal. The source terminal of the NMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the PMOS transistor, and the source terminal of the PMOS transistor is electrically connected to the first node.

4. The dynamic D flip-flop according to claim 1, wherein: The clock signal includes a first clock signal and a second clock signal, and the first clock signal is in opposite phase to the second clock signal.

5. The dynamic D flip-flop according to claim 1, wherein: The first data transmission unit and / or the second data transmission unit is a transmission gate.

6. The dynamic D flip-flop according to claim 1, wherein: The first latch unit and / or the second latch unit is an inverter.

7. A data operation unit comprising a control circuit, an operation circuit, and a plurality of dynamic D flip-flops interconnected, wherein the plurality of dynamic D flip-flops are connected in series and / or in parallel; characterized in that: The multiple dynamic D flip-flops are the dynamic D flip-flops described in any one of claims 1-6.

8. A chip, characterized in that: The device comprises at least one data operation unit as claimed in claim 7.

9. A hashboard for computing equipment, characterized in that: Comprising at least one chip according to claim 8.

10. A computing device comprising a power board, a control board, a connection board, a radiator, and a plurality of hash boards, wherein the control board is connected to the hash boards via the connection board, the radiator is disposed around the hash boards, and the power board is used to provide power to the connection board, the control board, the radiator, and the hash boards, characterized in that: The computing board is the computing board according to claim 9.

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