Data Reading Device and Data Reading Method for Design for Testability

Abstract

The present invention provides a data reading device and a data reading method for design for testability. The data reading device includes a buffer and a data serialization circuit. The data serialization circuit receives a clock positive edge trigger signal, a clock negative edge trigger signal, a trigger mask signal, and data under test. The data serialization circuit masks one of the clock positive edge trigger signal and the clock negative edge trigger signal according to the trigger mask signal, and provides a part of the data under test to the output end of the data serialization circuit as the output signal of the data reading device according to the unmasked clock positive edge trigger signal or clock negative edge trigger signal. Thereby, the data valid window of the data under test can be increased.

Description

Technical Field

[0001] The present invention relates to a Design for Testing (DFT) technology, and particularly to a data reading device and a data reading method for Design for Testing. Background Art

[0002] In the Design for Testing (DFT) technology, in order to facilitate the testing or verification of the functions of a chip or a circuit, relevant test circuits are usually implanted in the circuit design stage so as to perform tests after the circuit design is completed.

[0003] When a test machine measures signals of a chip or a circuit, due to the fact that the signal transmission speeds of each pin in the test circuit are different due to pin impedance, trace length, and logic gate response time, signals are delayed in the enabling / disabling process during transmission. This phenomenon can be referred to as data skew. Based on the technological progress of semiconductor manufacturing processes and the gradual improvement of communication specifications in terms of transmission capabilities, the signal transmission speed of circuits will predictably become faster and faster, but it also results in a smaller and smaller available data valid window. In addition, when a pin is adjacent to a power line, data skew of the signal in this pin may also occur due to the power transmission of the power line.

[0004] As a result, it becomes increasingly difficult to accurately obtain the signal to be tested from the data valid window at high speeds. Therefore, how to more easily obtain and test the signal to be tested is one of the problems that have long existed in the field of signal testing. Summary of the Invention

[0005] The present invention provides a data reading device and a data reading method for Design for Testing, which are used to increase the available data valid window in the signal to be tested.

[0006] The data reading device for Design for Testing according to an embodiment of the present invention includes a buffer and a data serialization circuit. The buffer is used to temporarily store the data to be tested. The data serialization circuit is coupled to the buffer. The data serialization circuit receives a positive clock edge trigger signal, a negative clock edge trigger signal, a trigger mask signal, and the data to be tested. The data serialization circuit masks one of the positive clock edge trigger signal and the negative clock edge trigger signal according to the trigger mask signal, and provides a part of the data to be tested to the output end of the data serialization circuit as the output signal of the data reading device according to the unmasked positive clock edge trigger signal or negative clock edge trigger signal.

[0007] The data reading method for testability design according to an embodiment of the present invention is applicable to a data reading device including a data serialization circuit. The data reading method includes the following steps: obtaining a clock positive edge trigger signal, a clock negative edge trigger signal, a trigger mask signal, and data to be tested; and masking one of the clock positive edge trigger signal and the clock negative edge trigger signal according to the trigger mask signal, and providing a part of the data to be tested to the output end of the data serialization circuit as the output signal of the data reading device according to the unmasked clock positive edge trigger signal or clock negative edge trigger signal.

[0008] Based on the above, the data reading device and the data reading method according to the embodiment of the present invention can, when reading the signal to be tested, use the additionally set trigger mask signal to block or mask one of the clock positive edge trigger signal and the clock negative edge trigger signal, and use the other unmasked trigger signal to obtain the corresponding part of the data to be tested. In this way, the output time of the data to be tested will increase from half of a clock cycle of the original clock to a clock cycle. Thereby, without adjusting the internal data type in the chip using this data reading device, without changing the clock or related configurations, the available data valid window can be increased, enabling the external test machine to more easily judge the correctness of the data to be tested obtained by the data reading device.

[0009] To make the above features and advantages of the present invention more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a data reading device according to an embodiment of the present invention;

[0011] Figure 2 is a waveform diagram for explaining the clock signal DQS, the clock positive edge trigger signal CLKOUT_T, the clock negative edge trigger signal CLKOUT_C, and the data to be tested D0~D3 and D<3:0>;

[0012] Figure 3 is a waveform diagram for explaining the clock signal DQS, the clock positive edge trigger signal CLKOUT_T, the clock negative edge trigger signal CLKOUT_C, the trigger mask signal DMASK, and the data to be tested D0~D3 and D<3:0> according to an embodiment of the present invention;

[0013] Figure 4 is Figure 1 a block diagram of the data serialization circuit 120 in

[0014] Figure 5 is a flowchart of a data reading method for testability design according to an embodiment of the present invention.

[0015] Description of the reference numerals in the drawings:

[0016] 100: Data reading circuit

[0017] 110: Buffer

[0018] 112: First-in first-out buffer

[0019] 114: Parallel-to-serial buffer

[0020] 120: Data serialization circuit

[0021] 130: External chip driver

[0022] 140: Pad

[0023] RWD: Data to be measured

[0024] D+: Positive-edge data to be measured

[0025] D-: Negative-edge data to be measured

[0026] D<3:0>, D0~D3: Data

[0027] CLKOUT_T: Clock positive-edge trigger signal

[0028] CLKOUT_C: Clock negative-edge trigger signal

[0029] DMASK: Trigger mask signal

[0030] DQS: Clock signal

[0031] 410: First switch

[0032] 415: First combinational logic

[0033] 420: Second switch

[0034] 425: Second combinational logic

[0035] SW1: First switch signal

[0036] SW2: Second switch signal

[0037] OUT: Output terminal

[0038] tCK: Clock period

[0039] DVW1, DVW2, DVW3: Data valid window

[0040] t1: Time Detailed implementation manners

[0041] As Figure 1As shown, the data reading circuit 100 can be applied to a dynamic random access memory (DRAM) device, especially to a low-power dynamic random access memory device. In order to reduce power consumption, the low-power dynamic random access memory device removes the delay lock loop (DLL) from the original DRAM architecture, thus reducing the data transmission stability in the DRAM device. The data reading circuit 100 of this embodiment can be disposed in a chip, and a testing machine outside the chip can use the data reading circuit 100 to read relevant signals or data to be measured.

[0042] Figure 1 The data reading circuit 100 in [description] mainly includes a buffer 110 and a data serialization circuit 120. The buffer 110 is used to temporarily store the data to be measured RWD obtained from the memory array. Specifically, the memory cell array can be located according to the memory address, and the data corresponding to the memory address in the memory cell array is read out through the read / write data line to become the data to be measured RWD, and the data to be measured RWD is temporarily stored in the buffer 110.

[0043] The buffer 110 of this embodiment includes a first-in first-out (FIFO) buffer 112 and a parallel-to-serial buffer 114. The first-in first-out buffer 112 provides the data obtained earlier to its output terminal earlier, and the data obtained later is output after all the previous data has been output for use by subsequent components. The parallel-to-serial buffer is coupled to the first-in first-out buffer 112 and converts the data to be measured transmitted in parallel form into the data to be measured transmitted in serial form. Those applying this embodiment can adjust the structure of the buffer 110 according to the internal data form of the DRAM device and the external output data form of the DRAM device.

[0044] The data serialization circuit 120 receives the clock positive-edge trigger signal CLKOUT_T, the clock negative-edge trigger signal CLKOUT_C, the trigger mask signal DMASK, and the data to be measured obtained from the buffer 110. In this embodiment, the data to be measured includes the positive-edge data to be measured D+ corresponding to the clock positive-edge trigger signal CLKOUT_T and the negative-edge data to be measured D- corresponding to the clock negative-edge trigger signal CLKOUT_C. The positive-edge data to be measured D+ and the negative-edge data to be measured D- are both parts of the data to be measured. In other words, the data serialization circuit 120 outputs the positive-edge data to be measured D+ to the pad 140 by using the enabled clock positive-edge trigger signal CLKOUT_T, and the data serialization circuit 120 also outputs the negative-edge data to be measured D- to the pad 140 by using the enabled clock negative-edge trigger signal CLKOUT_C.

[0045] The data serialization circuit 120 masks one of the clock positive edge trigger signal CLKOUT_T and the clock negative edge trigger signal CLKOUT_C according to the trigger mask signal DMASK, and provides a part of the data to be measured to the output end of the data serialization circuit 120 according to the unmasked clock positive edge trigger signal CLKOUT_T or the clock negative edge trigger signal CLKOUT_C as the output signal of the data reading device 100. The detailed operation mode of the data serialization circuit 120 will be described in detail in the following embodiments.

[0046] Figure 1 The data reading circuit 100 in [description] further includes an off-chip driver (OCD) 130 and a pad 140. The data reading circuit 100 uses the off-chip driver 130 and the pad 140 to output the output signal of the data reading device 100 to a device electrically coupled to the pad 140, such as a test machine, through the pad 140. The off-chip driver 130 is coupled to the data serialization circuit 120 to receive the output signal of the data reading device 100. The pad 140 is electrically connected to the off-chip driver 130. The off-chip driver 130 provides a part of the data to be measured to the pad 140 according to the output signal provided by the output end of the data serialization circuit 120.

[0047] Please refer to Figure 2 , when the clock signal DQS transitions from a negative edge to a positive edge, the clock positive edge trigger signal CLKOUT_T will be enabled; when the clock signal DQS transitions from a positive edge to a negative edge, the clock negative edge trigger signal CLKOUT_C will be enabled. Here, it is assumed that Figure 1 the data serialization circuit 120 of [description] does not use the trigger mask signal to implement the embodiments of the present invention. In order to output the data to be measured as soon as possible, the data serialization circuit 120 usually transmits a piece of data when the clock positive edge trigger signal CLKOUT_T is enabled, and transmits another piece of data when the clock negative edge trigger signal CLKOUT_C is enabled. The data in this embodiment is represented as D<3:0>, which is a combination of data D3, D2, D1, and D0, and the data to be measured transmitted after the positive edge trigger signal CLKOUT_T is enabled is called the positive edge data to be measured D+; the data to be measured transmitted after the negative edge trigger signal CLKOUT_C is enabled is called the negative edge data to be measured D-. In this embodiment, the output time of the positive edge data to be measured D+ or the negative edge data to be measured D- is half of a complete clock cycle tCK in the clock signal DQS. For the convenience of explanation, D<3:0> in the positive edge data to be measured D+ is [0, 1, 0, 1], and D<3:0> in the negative edge data to be measured D- is [1, 0, 1, 0].

[0048] However, as the transmission rate of the communication protocol used by low-power dynamic random access memory devices has gradually increased, for example, from the previous first-generation double data rate synchronous dynamic random access memory (DDR SDRAM) to the fourth-generation double data rate synchronous dynamic random access memory (DDR4 SDRAM), the change speed of data D<3:0> has become even faster. When the external test machine obtains the data to be tested in the chip using the data reading circuit 100, it may not be able to know the clock signal DQS and its rate inside the chip, resulting in the possibility of not being able to find the data valid window of data D<3:0>. For example, Figure 2 It will be difficult for the test machine to know the data valid window DVW1 corresponding to the positive-edge data to be tested D+ and the data valid window DVW2 corresponding to the negative-edge data to be tested D-. In other words, when the data transmission speed is faster, the test machine cannot find an appropriate timing from the change of data D<3:0> to find the time point (also known as the strobe point) for obtaining the signal, that is, it cannot effectively obtain the desired information within the data valid window of data D<3:0>.

[0049] Therefore, in this embodiment, Figure 1 Additional pins and related circuits are added to the data serialization circuit 120 to use the trigger mask signal DMASK to mask one of the clock positive-edge trigger signal CLKOUT_T and the clock negative-edge trigger signal CLKOUT_C, thereby increasing the data valid window of some of the data to be tested. The test machine can selectively mask one of the clock positive-edge trigger signal CLKOUT_T and the clock negative-edge trigger signal CLKOUT_C by adjusting the trigger mask signal DMASK. The following is an example to Figure 3 illustrate.

[0050] Figure 3 In the embodiment of, the enabled (i.e., logical "1") trigger mask signal DMASK is used to selectively mask the clock negative-edge trigger signal CLKOUT_C and not mask the clock positive-edge trigger signal CLKOUT_T, so that the data serialization circuit 120 will normally output the positive-edge data to be tested D+ when the clock positive-edge trigger signal CLKOUT_T is enabled, and will not output the negative-edge data to be tested D- due to the enabling of the clock negative-edge trigger signal CLKOUT_C. In this way, the data valid window DVW3 of the positive-edge data to be tested D+ will be larger than Figure 2 the data valid window DVW2 in. The output time of the positive-edge data to be tested D+ will increase from half of a complete clock cycle tCK of the clock signal DQS to a complete clock cycle tCK, so that the data valid window DVW3 of the positive-edge data to be tested D+ increases accordingly.

[0051] Figure 3In the embodiments, the negative-edge triggered clock signal CLKOUT_C is masked, so only a part of the data to be tested (i.e., the positive-edge data to be tested D+) will be output to Figure 1 the pad 140 of Figure 1 . Therefore, to obtain the complete data to be tested, the external test machine needs to adjust the trigger mask signal DMASK from enabled (i.e., logic "1") to disabled, so that the positive-edge triggered clock signal CLKOUT_T is masked and the positive-edge data to be tested D+ cannot be output. In this way, the negative-edge data to be tested D- corresponding to the negative-edge triggered clock signal CLKOUT_C will be output to

[0052] the pad 140 of Figure 4 . In other words, the external test machine can adjust the trigger mask signal DMASK to obtain the positive-edge data to be tested D+ and the negative-edge data to be tested D- in more time.

[0053] Please refer to Figure 4 , the data serialization circuit 120 mainly includes a first switch 410, a second switch 420, a first combinational logic 415, and a second combinational logic 425. The first combinational logic 415 receives the positive-edge triggered clock signal CLKOUT_T and the trigger mask signal DMASK, and generates a first switch signal SW1. The second combinational logic 425 receives the negative-edge triggered clock signal CLKOUT_C and the trigger mask signal DMASK, and generates a second switch signal SW2. The control terminal of the first switch 410 receives the first switch signal SW1. The receiving terminal of the first switch 410 receives the positive-edge data to be tested D+. The output terminal of the first switch 410 is coupled to the output terminal OUT of the data serialization circuit 120. The control terminal of the second switch 420 receives the second switch signal SW2. The receiving terminal of the second switch 420 receives the negative-edge data to be tested D-. The output terminal of the second switch 420 is also coupled to the output terminal OUT of the data serialization circuit 120. Therefore, when the trigger mask signal DMASK is enabled (i.e., logic "1"), the first combinational logic 415 enables the first switch signal SW1 according to the trigger mask signal DMASK and the positive-edge trigger signal CLKOUT_T. The second combinational logic 425 keeps the second switch signal SW2 disabled according to the trigger mask signal DMASK and the negative-edge trigger signal CLKOUT_C. Therefore, the receiving terminal of the first switch 410 will be coupled to the output terminal of the first switch 410 due to the enabling of the first switch signal SW1, thereby outputting the positive-edge data to be tested D+.

[0054] Conversely, when the trigger mask signal DMASK is disabled (i.e., logic "0"), the first combinational logic 415 keeps the first switch signal SW1 disabled based on the trigger mask signal DMASK and the positive-edge trigger signal CLKOUT_T. The second combinational logic 455 enables the second switch signal SW2 based on the trigger mask signal DMASK and the negative-edge trigger signal CLKOUT_C. Therefore, the receiving end of the second switch 420 is coupled to the output end of the second switch 420 due to the enabling of the second switch signal SW2, thereby outputting the negative-edge data under test D-.

[0055] Figure 5 is a flowchart of a data reading method for design for testability according to an embodiment of the present invention. Figure 5 The data reading method in Figure 1 is applicable to the data reading device 100 including the data serialization circuit 120 in Figure 5 , in step S510, the data serialization circuit 120 of the data reading device 100 obtains the clock positive-edge trigger signal CLKOUT_T, the clock negative-edge trigger signal CLKOUT_C, the trigger mask signal DMASK, and the data under test. In step S520, the data serialization circuit 120 masks one of the clock positive-edge trigger signal CLKOUT_T and the clock negative-edge trigger signal CLKOUT_C according to the trigger mask signal DMASK, and provides a part of the data under test to the output end of the data serialization circuit 120 as the output signal of the data reading device 100 according to the unmasked clock positive-edge trigger signal CLKOUT_T or the clock negative-edge trigger signal CLKOUT_C.

[0056] Step S520 can also be implemented by the following steps. When the clock positive-edge trigger signal CLKOUT_T is masked according to the trigger mask signal DMASK, the data serialization circuit 120 outputs the negative-edge data under test D-. When the clock negative-edge trigger signal CLKOUT_C is masked according to the trigger mask signal DMASK, the data serialization circuit 120 outputs the positive-edge data under test D+. The implementation manners of the above steps have been disclosed in the embodiments of the present invention.

[0057] In summary, when reading a signal to be measured, the data reading device and the data reading method according to the embodiments of the present invention can use an additionally provided trigger masking signal to block or mask one of the clock positive-edge trigger signal and the clock negative-edge trigger signal, and use the other unmasked trigger signal to obtain corresponding partial data to be measured. In this way, the output time of the data to be measured will be increased from half of a clock period of the original clock to a clock period. Thereby, without adjusting the internal data type in the chip using this data reading device, without changing the clock or related configurations, the available data valid window can be increased, enabling an external test machine to more easily determine the correctness of the data to be measured obtained by the data reading device.

[0058] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art within the technical field to which the present invention pertains, without departing from the spirit and scope of the present invention, may make some modifications and refinements. Therefore, the protection scope of the present invention shall be determined by the scope defined by the claims.

Claims

1. A data reading device for design for testability, characterized in that, Comprising: A buffer for temporarily storing data to be tested and outputting serial data to be tested associated with circuit testing; A data serialization circuit coupled to the buffer, wherein the data serialization circuit receives a clock positive edge trigger signal, a clock negative edge trigger signal, a trigger mask signal, and receives the serial data to be tested associated with circuit testing from the buffer; And An off-chip driver coupled to the data serialization circuit; Wherein, when performing high-speed data transmission from the data serialization circuit to the off-chip driver, the data serialization circuit masks one of the clock positive edge trigger signal and the clock negative edge trigger signal according to the trigger mask signal, and provides a part of the serial data to be tested associated with circuit testing to the off-chip driver according to the unmasked clock positive edge trigger signal or clock negative edge trigger signal, wherein the high-speed data transmission conforms to the data transmission rate of the fourth-generation double data rate synchronous dynamic random access memory (DDR4 SDRAM), Wherein the serial data to be tested associated with circuit testing includes positive edge data to be tested corresponding to the clock positive edge trigger signal and negative edge data to be tested corresponding to the clock negative edge trigger signal, and The data serialization circuit includes: A first switch, whose control terminal receives a first switch signal generated by the clock positive edge trigger signal and the trigger mask signal, the receiving terminal of the first switch receives the positive edge data to be tested, and the output terminal of the first switch is coupled to the output terminal of the data serialization circuit; and A second switch, whose control terminal receives a second switch signal generated by the clock negative edge trigger signal and the trigger mask signal, the receiving terminal of the second switch receives the negative edge data to be tested, and the output terminal of the second switch is coupled to the output terminal of the data serialization circuit, Wherein, when the clock positive edge trigger signal is masked according to the trigger mask signal, the second switch signal is enabled to couple the receiving terminal of the second switch to the output terminal of the second switch, thereby outputting the negative edge data to be tested, When the clock negative edge trigger signal is masked according to the trigger mask signal, the first switch signal is enabled to couple the receiving terminal of the first switch to the output terminal of the first switch, thereby outputting the positive edge data to be tested.

2. The data reading device according to claim 1, wherein The data reading device further includes: A pad electrically connected to the off-chip driver, Wherein the off-chip driver provides a part of the serial data to be tested associated with circuit testing to the pad according to the output signal of the data serialization circuit.

3. The data reading device according to claim 1, characterized in that Further comprising: A memory array, wherein the serial data to be tested associated with circuit testing is stored or generated by the memory array.

4. The data reading device according to claim 1, wherein The data serialization circuit masks one of the clock positive edge trigger signal and the clock negative edge trigger signal according to the trigger mask signal, thereby increasing the data valid window of a part of the serial data to be tested associated with circuit testing, Part of the serial data to be tested associated with the circuit test corresponds to the other one of the unmasked positive edge trigger signal and the negative edge trigger signal of the clock.

5. The data reading device according to claim 1, wherein The data reading device is applied to a dynamic random access memory device.

6. The data reading device according to claim 1, characterized in that The positive edge trigger signal of the clock is enabled when the clock transitions from a negative edge to a positive edge, and the negative edge trigger signal of the clock is enabled when the clock transitions from a positive edge to a negative edge.

7. A data reading method for design for testability, applicable to a data reading device including a data serialization circuit and an off-chip driver, characterized in that, The data reading method includes: Obtaining a positive edge trigger signal of a clock, a negative edge trigger signal of the clock, a trigger mask signal, and receiving serial data to be tested associated with a circuit test, where the serial data to be tested associated with the circuit test includes positive edge data to be tested corresponding to the positive edge trigger signal of the clock and negative edge data to be tested corresponding to the negative edge trigger signal of the clock; and When performing high-speed data transmission from the data serialization circuit to the off-chip driver, the data serialization circuit masks one of the positive edge trigger signal and the negative edge trigger signal of the clock according to the trigger mask signal, and provides part of the serial data to be tested associated with the circuit test to the off-chip driver according to the unmasked positive edge trigger signal or negative edge trigger signal of the clock, where the high-speed data transmission conforms to the data transmission rate of a fourth-generation double data rate synchronous dynamic random access memory (DDR4 SDRAM); The step of masking one of the positive edge trigger signal and the negative edge trigger signal of the clock and providing part of the serial data to be tested associated with the circuit test to the off-chip driver according to the unmasked positive edge trigger signal or negative edge trigger signal of the clock includes: Outputting the negative edge data to be tested when the positive edge trigger signal of the clock is masked according to the trigger mask signal; and Outputting the positive edge data to be tested when the negative edge trigger signal of the clock is masked according to the trigger mask signal.

8. The data reading method according to claim 7, wherein The data serialization circuit masks one of the positive edge trigger signal and the negative edge trigger signal of the clock according to the trigger mask signal, thereby increasing the data valid window of part of the serial data to be tested associated with the circuit test, Part of the serial data to be tested associated with the circuit test corresponds to the other one of the unmasked positive edge trigger signal and the negative edge trigger signal of the clock.

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