A DRAM memory chip three-dimensional integrated packaging method and structure

Abstract

The present invention discloses a DRAM memory chip three-dimensional integrated packaging method and structure, belonging to the technical field of integrated circuit packaging. A mother chip and a daughter chip are provided, and the mother chip and the daughter chip are stacked and bonded. The mother chip is formed by the following method: a glass substrate is provided, and a bonding layer is spin-coated on the glass substrate; a TSV adapter chip and a memory chip are placed on the bonding layer; a plastic encapsulation material is used to encapsulate and thin the chips to a target thickness; and a bonding layer is made on the memory chip. The daughter chip is formed by the following method: a TSV adapter chip and a memory chip are additionally provided and encapsulated; n layers of redistribution wiring are formed to connect the adapter chip and the memory chip in the daughter chip; and bumps are made. Finally, the bump gaps are filled with bottom fillers, and the chips are encapsulated and thinned to a target thickness by a plastic encapsulation material; a bonding layer is made on the back of the daughter chip, and another daughter chip is bonded; the above steps are repeated to complete multi-layer three-dimensional stacking; the last layer is formed by encapsulating the memory chip, and n layers of wiring and bumps are formed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a three-dimensional wafer-level integrated packaging method and structure for a DRAM memory chip. Background Art

[0002] DRAM (Dynamic Random Access Memory) has become the core chip of smart terminals, just like the central processing unit (CPU). As its name implies, DRAM is a random access memory that requires data regeneration. The programs and data currently executed by the PC are stored in the main storage system of the memory module composed of DRAM. The most commonly used storage unit is composed of a single-tube MOS device, which uses the integrated tiny gate capacitor to dynamically store charge to memorize binary data.

[0003] With the development of artificial intelligence (AI), 5G and the Internet of Things (IoT), the demand for system memory DRAM with high transmission rate, large capacity and low power consumption is increasing. As Moore's Law has reached its physical limit, improving DRAM performance through packaging has received increasing attention. DRAM packaging mainly includes dual in-line DIP package, J-type pin small outline SQJ package, thin small size TSOP package, bottom lead plastic package BLP, solder ball array BGA (F-BGA, W-BGA) package, as well as chip-level CSP and three-dimensional stacked package. At present, the more popular memories are DDR3 and DDR4, and DDR5 has also had a clear commercial timetable. Starting from DDR3, traditional DIP, SQJ, TSOP and BLP packages can no longer meet its performance requirements.

[0004] Advanced technology packaging based on CSP can significantly improve DRAM performance, and it is easy to produce more than 1,000 signal pins, which meets the packaging requirements of the new generation of high-frequency, high-speed and large-capacity memory chips. The three-dimensional stacking packaging technology developed on the basis of CSP assembles two or more memory chips vertically, multiplies the memory capacity in a limited space, realizes electronic design functions, and solves the problems of limited space and interconnection. For example, Samsung Electronics uses Via first manufacturing technology to complete DRAM vertical interconnection stacking, realizing high-capacity, high-bandwidth, high-speed HBM high-order packaging. Three-dimensional stacking packaging can effectively improve DRAM performance, but the current manufacturing method of three-dimensional stacking packaging structure is costly, the finished product yield is low, and the process difficulty is extremely high. Summary of the invention

[0005] The purpose of the present invention is to provide a three-dimensional integrated packaging method and structure for a DRAM memory chip, so as to solve the problems of high cost, low finished product yield and extremely high process difficulty in the existing manufacturing method of the three-dimensional stacked packaging structure.

[0006] In order to solve the above technical problems, the present invention provides a DRAM memory chip three-dimensional integrated packaging method, comprising: providing a mother chip and a daughter chip, and stacking and bonding the mother chip and the daughter chip; wherein,

[0007] The master sheet is formed by the following method:

[0008] Providing a glass substrate, and spin coating a bonding layer on the glass substrate;

[0009] Placing a TSV transfer chip and a memory chip on the bonding layer;

[0010] Plastic encapsulation with plastic encapsulation compound and thinning to target thickness;

[0011] Making an adhesive layer on the memory chip;

[0012] The sub-pieces are formed by the following method:

[0013] In addition, TSV adapter chips and memory chips are provided and plastic-sealed;

[0014] Forming n-layer rewiring to connect the transfer chip and the memory chip in the sub-chip;

[0015] Making convex points;

[0016] The stacking and bonding of the mother wafer and the daughter wafer comprises:

[0017] The mother wafer and the child wafer are bonded by C2W method;

[0018] Fill the gaps between the bumps with underfill, encapsulate with molding compound and thin to the target thickness;

[0019] Making an adhesive layer on the back of the sub-sheet, and bonding another sub-sheet; repeating the above steps to complete multi-layer three-dimensional stacking;

[0020] The last layer is formed by plastic packaging of the memory chip and is formed with n layers of wiring and bumps.

[0021] Optionally, after the mother chip and the daughter chip are stacked and bonded, the DRAM memory chip three-dimensional integrated packaging method further includes:

[0022] Removing the glass substrate and the bonding layer by a laser method or a thermomechanical method, and thinning to a target thickness;

[0023] Forming n-layer rewiring that connects the adapter chip and the memory chip in the mother chip;

[0024] Cut into individual packages.

[0025] Optionally, the metal pad of the storage chip in the mother slice faces inwards, opposite to the bonding layer.

[0026] Optionally, a TSV channel is provided in the TSV adapter chip, a conductive metal is provided in the TSV channel, and a material of the conductive metal includes Cu, Sn, Ag, Al, Ni and Au.

[0027] Optionally, the distance between the TSV adapter chip and the memory chip in the mother slice is greater than 1 μm, and the number of the TSV adapter chip and the memory chip is not less than 1; the placement positions of the TSV adapter chip and the memory chip in the daughter slice are consistent with those in the mother slice.

[0028] Optionally, the glass substrate has a thickness of more than 50 μm, and the bonding layer has a thickness of more than 0.1 μm.

[0029] Optionally, the bumps include copper pillar tin-silver bumps and tin balls.

[0030] Optionally, the bonding layer is a polymer passivation glue, and the thickness of the bonding layer is at least 0.5 μm greater than the height of the bumps in the sub-chip.

[0031] Optionally, the molding compound is a resin or polyimide polymer material.

[0032] The present invention also provides a three-dimensional integrated packaging structure of a DRAM memory chip, comprising a top layer, a plurality of middle layers and a bottom layer bonded in sequence; wherein:

[0033] The bottom layer includes a TSV transfer chip and a memory chip which are sealed in plastic, and n layers of redistribution wiring and bumps are formed on the front side of the bottom layer, and an adhesive layer is formed on the back side;

[0034] The middle layer includes a TSV transfer chip and a memory chip which are sealed in plastic, and n layers of redistribution wiring and bumps are formed on the front side of the middle layer, which is bonded to the back side of the bottom layer;

[0035] The top layer includes a plastic-encapsulated memory chip, and n layers of redistribution wiring and bumps are formed on the front side of the top layer, which is bonded to the back side of the middle layer;

[0036] The back side of each intermediate layer is provided with an adhesive layer, which is bonded to the front side of another intermediate layer or the front side of the top layer.

[0037] The present invention provides a DRAM memory chip three-dimensional integrated packaging method and structure, providing a mother chip and a daughter chip, and stacking and bonding the mother chip and the daughter chip. The mother chip is formed by the following method: providing a glass substrate, spin-coating a bonding layer on the glass substrate; placing a TSV adapter chip and a memory chip on the bonding layer; plastic-sealing them with a plastic sealing compound, and thinning them to a target thickness; making an adhesive layer on the memory chip. The daughter chip is formed by the following method: separately providing a TSV adapter chip and a memory chip, and plastic-sealing them; forming n layers of redistribution wiring connecting the adapter chip and the memory chip in the daughter chip; making bumps. Finally, fill the bump gaps with bottom filler, plastic-sealing them with a plastic sealing compound and thinning them to a target thickness; make an adhesive layer on the back of the daughter chip, and then bond another daughter chip; repeat the above steps to complete multi-layer three-dimensional stacking; the last layer is formed by plastic-sealing the memory chip, and is formed with n layers of wiring and bumps.

[0038] The present invention uses TSV adapter chips to complete vertical interconnection between each layer, fills the bump gaps with bottom fillers, and enhances the strength of the packaging structure; uses TSV adapter chips and memory chips to fan out to complete multi-chip three-dimensional stacking, which has low packaging cost, high packaging efficiency and yield, and is suitable for large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a schematic diagram of a glass substrate with a bonding layer spin-coated;

[0040] Figure 2 It is a schematic diagram of placing TSV transfer chips and memory chips on a glass substrate;

[0041] Figure 3 It is a schematic diagram of the plastic-encapsulated TSV adapter chip and memory chip;

[0042] Figure 4 is a schematic diagram of making a bonding layer on a memory chip;

[0043] Figure 5 It is a schematic diagram of TSV transfer chip and memory chip provided separately;

[0044] Figure 6 It is a schematic diagram of the plastic-encapsulated TSV adapter chip and memory chip;

[0045] Figure 7 It is a schematic diagram of forming n-layer redistribution and bumps;

[0046] Figure 8 This is a schematic diagram of the principle of C2W stack bonding;

[0047] Fig. 9 It is a schematic diagram of filling the gap of the bump with the underfill;

[0048] Fig.10It is a schematic diagram of plastic sealing and thinning with plastic sealing compound;

[0049] Fig.11 It is a schematic diagram of a plurality of sub-sheets forming a multi-layer three-dimensional stack;

[0050] Fig.12 This is a schematic diagram of the last layer;

[0051] Fig.13 It is a schematic diagram of the bonding of the last layer to the multi-layer three-dimensional stack;

[0052] Fig.14 It is a schematic diagram of removing and thinning the glass substrate and bonding layer;

[0053] Fig.15 It is a schematic diagram of forming n-layer rewiring and growing bumps at the bottom;

[0054] Fig.16 It is a schematic diagram of cutting to form a single package;

[0055] Fig.17 This is a schematic diagram of the principle of W2W stack bonding. DETAILED DESCRIPTION

[0056] The following is a further detailed description of a DRAM memory chip three-dimensional integrated packaging method and structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0057] Embodiment 1

[0058] The present invention provides a DRAM memory chip three-dimensional integrated packaging method, comprising: providing a mother chip and a daughter chip, and stacking and bonding the mother chip and the daughter chip. Specifically,

[0059] First, a master sheet is formed by the following method:

[0060] Provide a glass substrate 101, and spin-coat a bonding layer 102 on the glass substrate 101, such as Figure 1 ; The thickness of the glass substrate 101 is greater than 50 μm, and the thickness of the bonding layer 102 is greater than 0.1 μm;

[0061] like Figure 2As shown, a TSV adapter chip 105 and a memory chip 103 are placed on the bonding layer 102; the distance between the TSV adapter chip 105 and the memory chip 103 is more than 1 μm, and the number of the chips is not less than 1; a metal pad 104 is provided on the memory chip 103, and the pad faces inwards and is opposite to the bonding layer 102; a TSV channel 106 is provided in the TSV adapter chip 105, and a conductive metal is provided in the TSV channel 106, and the material of the conductive metal may be Cu, Sn, Ag, Al, Ni or Au; the memory chip 103 may be DRAM or Flash storage, etc.;

[0062] Then, the arranged reconstructed wafer is sealed with a plastic sealing material 107 and thinned to a target thickness, such as Figure 3 As shown; the plastic packaging material 107 is a resin type or polyimide polymer material;

[0063] like Figure 4 , use photolithography technology to make an adhesive layer 110 on the memory chip 103; the adhesive layer 110 is a polymer passivation glue, and its thickness is determined according to the size of the bumps 209 to be made later, and is more than 0.5μm higher than the height of the bumps 209; at this point, the mother chip is completed.

[0064] The sub-pieces are formed by the following method:

[0065] like Figure 5 , and a TSV adapter chip 205 and a memory chip 203 are provided again, and are placed on the substrate of the plastic packaging machine, in which the metal pad 204 of the memory chip 203 in the sub-chip faces outward, and the placement position is consistent with the TSV adapter chip 105 and the memory chip 103 in the mother chip; the TSV adapter chip 205 has a TSV channel 206, and the TSV channel 206 has a conductive metal, and the material thereof can be Cu, Sn, Ag, Al, Ni or Au; the memory chip 203 can use DRAM or Flash storage, etc.;

[0066] By plastic sealing material 107, such as Figure 6 As shown;

[0067] Form an n-layer rewiring 208, the n-layer rewiring 208 connects the TSV transfer chip 205 and the memory chip 203 in the sub-chip; finally, make a bump 209; the bump 209 includes a copper pillar tin-silver bump and a solder ball; so far, Figure 7 The sub-sheet shown is completed.

[0068] Then the mother wafer and the daughter wafer are stacked and bonded by C2W (chip to wafer) method, such as Figure 8 As shown, a single chip 12 is soldered onto the manufactured wafer 11 using flip-chip technology;

[0069] After C2W bonding, the gaps between the bumps are filled with underfill 111 to enhance the strength of the package structure, such as Fig. 9 ; By molding the molding compound 107 and thinning to the target thickness, such as Fig.10 ;

[0070] exist Fig.10 The adhesive layer is made on the back of the sub-chip, and then another sub-chip is bonded; the above steps are repeated, and each sub-chip is bonded and plastic-sealed, and each layer is thinned to the target thickness by grinding to obtain an ultra-thin three-dimensional stacked package. Fig.11 The multi-layer three-dimensional stack shown;

[0071] The last layer Fig.12 As shown, the memory chip 303 is plastic-encapsulated, and n-layer wiring 308 and bumps 309 are formed. The last layer is also bonded in a C2W manner to form a Fig.13 The stacking structure shown;

[0072] Finally, the glass substrate 101 and the bonding layer 102 are removed by laser or thermomechanical method, and thinned to a target thickness. Fig.14 ;

[0073] like Fig.15 , forming an n-layer rewiring 108 connecting the transfer chip and the memory chip in the mother chip at the bottom of the stacked structure and growing bumps 109; the bumps 109 include copper pillar tin-silver bumps and solder balls;

[0074] Cut into individual packages, such as Fig.16 .

[0075] In addition to C2W stack bonding, W2W (wafer to wafer) stack bonding can also be used. The principle is as follows Fig.17 As shown, the middle layer or top layer wafer 13 is bonded and stacked with the manufactured wafer 11 by wafer-level bonding technology.

[0076] Embodiment 2

[0077] The present invention provides a DRAM memory chip three-dimensional integrated packaging structure, which is prepared by the DRAM memory chip three-dimensional integrated packaging method provided in Example 1. The DRAM memory chip three-dimensional integrated packaging structure is as follows: Fig.16 As shown, it includes a top layer, several middle layers and a bottom layer bonded in sequence.

[0078] Specifically, the bottom layer includes a TSV adapter chip 105 and a memory chip 103 encapsulated by a molding compound 107, an n-layer redistribution wiring 108 and a bump 109 are formed on the front side of the bottom layer, and an adhesive layer 110 is made on the back side; the n-layer redistribution wiring 108 on the front side of the bottom layer connects the TSV adapter chip 105 and the memory chip 103 in the bottom layer; the distance between the TSV adapter chip 105 and the memory chip 103 in the bottom layer is above 1 μm.

[0079] The middle layer includes a TSV transfer chip 205 and a memory chip 203 encapsulated by a molding compound 107. The TSV transfer chip 205 and the memory chip 203 of the middle layer are placed in the same position as the TSV transfer chip 105 and the memory chip 103 in the bottom layer. The front side of the middle layer is formed with an n-layer redistribution 208 and a bump 209, which are bonded to the back side of the bottom layer; the n-layer redistribution 208 of the middle layer connects the TSV transfer chip 205 and the memory chip 203 in the middle layer. Furthermore, each of the middle layers is formed with an adhesive layer 110 on the back side, which is bonded to the front side of another middle layer or the front side of the top layer.

[0080] The top layer includes a memory chip 303 encapsulated by a molding compound 107 , and an n-layer redistribution wiring 308 and bumps 309 are formed on the front side of the top layer, which are bonded to the back side of the middle layer.

[0081] Specifically, a TSV channel is provided in the TSV adapter chip (including the TSV adapter chip 105 and the TSV adapter chip 205 ), and a conductive metal is provided in the TSV channel. The material of the conductive metal includes Cu, Sn, Ag, Al, Ni and Au.

[0082] Specifically, the bumps (including bumps 109, 209 and 309) include copper pillar tin-silver bumps and tin balls, and the gaps of the bumps are filled with bottom fillers 111. The bonding layer 110 is a polymer passivation glue, and its thickness is more than 0.5 μm greater than the height of the bumps. The plastic encapsulation material 107 is a resin or polyimide polymer material.

[0083] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A DRAM memory chip three-dimensional integrated packaging method, characterized in that: include: A mother wafer and a daughter wafer are provided, and the mother wafer and the daughter wafer are stacked and bonded; wherein, The master sheet is formed by the following method: Providing a glass substrate, and spin coating a bonding layer on the glass substrate; Placing a TSV transfer chip and a memory chip on the bonding layer; Plastic encapsulation with plastic encapsulation compound and thinning to target thickness; Making an adhesive layer on the memory chip; The sub-pieces are formed by the following method: In addition, TSV adapter chips and memory chips are provided and plastic-sealed; Forming n-layer rewiring to connect the transfer chip and the memory chip in the sub-chip; Making convex points; The stacking and bonding of the mother wafer and the daughter wafer comprises: The mother wafer and the child wafer are bonded by C2W method; Fill the gaps between the bumps with underfill, encapsulate with molding compound and thin to the target thickness; Making an adhesive layer on the back of the sub-sheet, and bonding another sub-sheet; repeating the above steps to complete multi-layer three-dimensional stacking; The last layer is formed by plastic packaging of the memory chip and is formed with n layers of wiring and bumps.

2. The DRAM memory chip three-dimensional integrated packaging method according to claim 1, characterized in that: After the mother chip and the daughter chip are stacked and bonded, the DRAM memory chip three-dimensional integrated packaging method further includes: Removing the glass substrate and the bonding layer by a laser method or a thermomechanical method, and thinning to a target thickness; Forming n-layer rewiring that connects the adapter chip and the memory chip in the mother chip; Cut into individual packages.

3. The DRAM memory chip three-dimensional integrated packaging method according to claim 1, characterized in that: The metal pads of the storage chip in the mother slice face inwards and are opposite to the bonding layer.

4. The DRAM memory chip three-dimensional integrated packaging method according to claim 1, characterized in that: The TSV switching chip is provided with a TSV channel, and the TSV channel is provided with a conductive metal, and the material of the conductive metal includes Cu, Sn, Ag, Al, Ni and Au.

5. The DRAM memory chip three-dimensional integrated packaging method according to claim 1, characterized in that: The distance between the TSV switching chip and the memory chip in the mother slice is greater than 1 μm, and the number of the TSV switching chip and the memory chip is not less than 1; the placement positions of the TSV switching chip and the memory chip in the daughter slice are consistent with those in the mother slice.

6. The DRAM memory chip three-dimensional integrated packaging method according to claim 1, characterized in that: The thickness of the glass substrate is greater than 50 μm, and the thickness of the bonding layer is greater than 0.1 μm.

7. The DRAM memory chip three-dimensional integrated packaging method according to claim 1, characterized in that: The bumps include copper pillar tin-silver bumps and tin balls.

8. The DRAM memory chip three-dimensional integrated packaging method according to claim 1, characterized in that: The bonding layer is a polymer passivation glue, and its thickness is more than 0.5 μm greater than the height of the bumps in the sub-sheet.

9. The DRAM memory chip three-dimensional integrated packaging method according to claim 1, characterized in that: The plastic packaging material is a resin type or polyimide polymer material.

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