Semiconductor devices

Abstract

A semiconductor device is provided, which may include a semiconductor substrate and a connection base pillar located on the semiconductor substrate. An insulating layer may be located on the semiconductor substrate, the insulating layer may include an opening located in the insulating layer, the connection base pillar extends through the opening, wherein a sidewall of the insulating layer defining the opening includes a horizontal step located at a level lower than an uppermost portion of the connection base pillar.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2018-0078250 filed on Jul. 5, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor chip and a semiconductor package including the semiconductor chip, and more particularly, to a semiconductor chip including a connection bump and a semiconductor package including the semiconductor chip. Background Art

[0003] In order to meet the requirements of miniaturization, multi-function and high-performance electronic products, semiconductor packages need to be thinner, lighter, and have high speed and high performance. Therefore, the demand for semiconductor chips and semiconductor packages including the semiconductor chips for realizing systems with high memory bandwidth is increasing. Since the memory bandwidth is proportional to the data transmission speed and the number of data transmission lines, the memory bandwidth can be increased by increasing the memory operating speed or increasing the number of data transmission lines. Therefore, the number and density of the connection bumps attached to the semiconductor chip will be increased. Summary of the invention

[0004] Embodiments of the inventive concept may provide a semiconductor chip including a plurality of connection bumps with an increased number and density and a semiconductor package including the semiconductor chip. According to these embodiments, a semiconductor device may include a semiconductor substrate and a connection base column located on the semiconductor substrate. An insulating layer may be located on the semiconductor substrate, the insulating layer may include an opening located in the insulating layer, and the connection base column extends through the opening, wherein a sidewall of the insulating layer defining the opening includes a horizontal step located at a level lower than the uppermost portion of the connection base column.

[0005] In some embodiments, the semiconductor device may include a semiconductor substrate. The microbump structure may be located on the semiconductor substrate, the connection base pillar may be included in the microbump structure, the insulating layer may be located on the semiconductor substrate, the insulating layer may include an opening located in the insulating layer, and the connection base pillar extends through the opening, wherein the sidewall of the insulating layer located on a first side of the opening includes a lower sidewall and an upper sidewall, wherein the lower sidewall is inclined downward toward the connection base pillar at a first angle relative to the semiconductor substrate, and the upper sidewall is located above the lower sidewall and is inclined downward toward the connection base pillar at a second angle different from the first angle relative to the semiconductor substrate.

[0006] In some embodiments, a semiconductor device may include a semiconductor package motherboard, a processor chip located on the semiconductor package motherboard, an interposer, a buffer chip, and a high-bandwidth dynamic random access memory chip. The interposer may be located between the processor chip and the semiconductor package motherboard, wherein the processor chip may be directly mounted on the interposer. The buffer chip may be directly mounted on the interposer separated from the processor chip, wherein the buffer chip may include a first connection base column located on the buffer chip, wherein the first connection base column may have a first aspect ratio, and an insulating layer may be located on the buffer chip, wherein the insulating layer includes an opening located in the insulating layer, and the first connection base column extends through the opening, wherein the sidewall of the insulating layer defining the opening may include a horizontal step, and the horizontal step is located at a level that is recessed relative to a portion of the insulating layer that protrudes from the buffer chip at a maximum distance. A high-bandwidth dynamic random access memory chip may be mounted on the buffer chip, wherein the high-bandwidth dynamic random access memory chip may include a second connection base column having a second aspect ratio lower than the first aspect ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a cross-sectional view showing a semiconductor chip according to an embodiment;

[0009] FIG. 2A to FIG. 2J is an enlarged cross-sectional view showing a connection bump of a semiconductor chip according to an embodiment;

[0010] FIG. 3A to FIG. 3D is an enlarged plan view showing a connection bump of a semiconductor chip according to an embodiment;

[0011] Figure 4 is a cross-sectional view showing a semiconductor package including a semiconductor chip according to an embodiment;

[0012] Figure 5A and Figure 5B is an enlarged cross-sectional view showing a connection bump of a semiconductor chip included in a semiconductor package according to an embodiment;

[0013] FIG. 6A to FIG. 6C is an enlarged cross-sectional view showing a connection bump of a semiconductor chip according to an embodiment;

[0014] 7A to 7C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor chip according to an embodiment;

[0015] FIG. 8A to FIG. 8C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor chip according to an embodiment;

[0016] FIG. 9A to FIG. 9G are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment; and

[0017] Fig.10 is a cross-sectional view showing a system including a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0018] Figure 1 is a cross-sectional view showing a semiconductor chip 100 according to an embodiment.

[0019] Reference Figure 1 The semiconductor chip 100 may include a semiconductor substrate 110 and a connection pad (also referred to as a bonding pad) 120 disposed on an effective surface that is an upper surface of the semiconductor substrate 110 .

[0020] In this specification, the upper surface and the lower surface of the semiconductor substrate may represent the effective surface and the ineffective surface of the semiconductor substrate, respectively. That is, even when the effective surface of the semiconductor substrate is disposed below the ineffective surface in the final product, the effective surface of the semiconductor substrate may be referred to as the upper surface of the semiconductor substrate, and the ineffective surface of the semiconductor substrate may be referred to as the lower surface of the semiconductor substrate. In addition, the terms "upper surface" and "lower surface" may be applied to an element disposed on the effective surface and an element disposed on the ineffective surface, respectively.

[0021] The semiconductor substrate 110 may include, for example, silicon (Si). Alternatively, the semiconductor substrate 110 may include a semiconductor element such as germanium (Ge), or may include a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP). The semiconductor substrate 110 may include an effective surface and an ineffective surface opposite to the effective surface. The semiconductor device may be arranged in the semiconductor chip 100, wherein the semiconductor device includes a plurality of individual devices of various types and is arranged on the effective surface.

[0022] The semiconductor chip 100 may be, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. The semiconductor chip 100 may be, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip.

[0023] In some embodiments, the semiconductor chip 100 may be a buffer chip including a serial-parallel conversion circuit. The buffer chip may be disposed between the memory chip and the controller chip. The buffer chip may serialize the data signal received from the memory chip to transmit the serialized data signal to the controller chip, and may parallelize the data signal received from the controller chip and transmit the parallelized data signal to the memory chip.

[0024] The connection pad 120 may include a conductive material. For example, the connection pad 120 may include at least one of nickel (Ni), aluminum (Al), copper (Cu), gold (Au), silver (Ag), platinum (Pt), and tungsten (W). Figure 1 , the connection pad 120 is shown as being buried in the semiconductor substrate 110, but is not limited thereto. In some embodiments, the connection pad 120 may protrude from the upper surface of the semiconductor substrate 110.

[0025] The insulating layer 140 may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140 may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140 may include, for example, photosensitive polyimide (PSPI). The insulating layer 140 may include a first horizontal portion ( Figure 2A 140P1) and a second horizontal portion ( Figure 2A 140P2). The first horizontal portion 140P1 and the second horizontal portion 140P2 may be integrally formed portions of the insulating layer 140. The first horizontal portion 140P1 may be a portion constituting one layer at the lower portion of the insulating layer 140, and the second horizontal portion 140P2 may be a portion constituting another layer on the first horizontal portion 140P1. FIG. 2A to FIG. 2J The shape of the insulating layer 140 is described in detail.

[0026] Passivation layer ( Figure 2A 130 or Figure 2B The passivation layer 130a) may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140. The passivation layer 130 or 130a may include, for example, an inorganic material such as an oxide or a nitride. For example, the passivation layer 130 or 130a may include at least one of silicon oxide and silicon nitride. In some embodiments, both the sidewall of the first horizontal portion of the insulating layer and the passivation layer may overlap a portion of the connection pad. Figure 2A and Figure 2B The passivation layer 130 or 130a is described in detail.

[0027] The connection bump 160 may be attached to the connection pad 120 and may include a conductive pillar 156 and a conductive cap 158 covering an upper surface of the conductive pillar 156. Here, the connection bump may also be referred to as a microbump structure, and the conductive pillar may also be referred to as a connection base pillar.

[0028] The conductive pillar 156 may include, for example, at least one of Ni, Cu, palladium (Pd), Pt, and Au. The conductive cap 158 may include, for example, at least one of tin (Sn), indium (In), bismuth (Bi), antimony (Sb), Cu, Ag, Au, zinc (Zn), and lead (Pb). An intermediate layer may be provided between the conductive pillar 156 and the conductive cap 158. The intermediate layer may include an intermediate metal compound generated by a reaction between a metal material of the conductive pillar 156 and a metal material of the conductive cap 158.

[0029] FIG. 2A to FIG. 2J is an enlarged cross-sectional view showing a connection bump of a semiconductor chip according to an embodiment. In detail, Figure 2A and Figure 2B It is shown Figure 1 An enlarged cross-sectional view of part A of Figure 2C to Figure 2J is shown with Figure 1 The enlarged cross-sectional view of the portion corresponding to the portion A of FIG. FIG. 2B to FIG. 2J In the description given, references to Figure 1 and Figure 2A The description given is a duplicate of the description.

[0030] Reference Figure 1 and Figure 2A , the connection bumps 160 may be attached to the connection pads 120 disposed on the effective surface which is the upper surface of the semiconductor substrate 110 .

[0031] The connection bump 160 may include a conductive pillar 156 disposed on the connection pad 120 and a conductive cap 158 covering an upper surface of the conductive pillar 156 .

[0032] In some embodiments, the conductive pillar 156 may include a base pillar 152 and a cover pillar 154 covering the upper surface of the base pillar 152. The base pillar 152 may include, for example, Cu. The cover pillar 154 may include, for example, at least one of Ni, Cu, Pd, Pt, and Au. In some embodiments, the cover pillar 154 may include Ni. In some other embodiments, the cover pillar 154 may have a multilayer structure including a first layer including Ni and a second layer covering the first layer and including Cu.

[0033] The conductive cap 158 may bond the semiconductor chip 100 to an external device to electrically connect the semiconductor chip 100 to the external device. The conductive cap 158 may include, for example, at least one of Sn, In, Bi, Sb, Cu, Ag, Au, Zn, and Pb.

[0034] The insulating layer 140 may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140 may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140 may be separated from the connection bump 160 and may surround the connection bump 160. The passivation layer 130 may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140.

[0035] The insulating layer 140 may include a first horizontal portion 140P1 adjacent to the semiconductor substrate 110 and a second horizontal portion 140P2 located on the first horizontal portion 140P1. The first horizontal portion 140P1 and the second horizontal portion 140P2 may be integrally provided portions of the insulating layer 140. The first horizontal portion 140P1 may be a portion constituting one layer at a lower portion of the insulating layer 140, and the second horizontal portion 140P2 may be a portion constituting another layer on the first horizontal portion 140P1. Figure 2A , the insulating layer 140 is illustrated as including a first horizontal portion 140P1 and a second horizontal portion 140P2 constituting two layers, but is not limited thereto. In other embodiments, the insulating layer 140 may include three or more horizontal portions constituting three or more layers.

[0036] The width of the second horizontal portion 140P2 may have a value smaller than that of the first horizontal portion 140P1. The first horizontal portion 140P1 and the second horizontal portion 140P2 may have a step height therebetween so that the insulating layer 140 is recessed in a direction from an upper surface 140H2 of the second horizontal portion 140P2 to an upper surface 140H1 of the first horizontal portion 140P1.

[0037] That is, the insulating layer 140 may include a first horizontal portion 140P1 and a second horizontal portion 140P2 having a step height therebetween and constituting different layers.

[0038] The side surface 140S1 of the first horizontal portion 140P1 and the side surface 140S2 of the second horizontal portion 140P2 may both extend in a direction perpendicular to the upper surface of the semiconductor substrate 110. The side surface 140S1 of the first horizontal portion 140P1 and the side surface 130S of the passivation layer 130 may be aligned in a direction perpendicular to the upper surface of the semiconductor substrate 110. The side surface 140S2 of the second horizontal portion 140P2 may connect the upper surface 140H2 of the second horizontal portion 140P2 to the upper surface 140H1 of the first horizontal portion 140P1. The upper surface of the conductive pillar 156 may be located at a level higher than the uppermost surface of the insulating layer 140 (i.e., the upper surface 140H2 of the second horizontal portion 140P2) in a direction perpendicular to the upper surface of the semiconductor substrate 110.

[0039] The side surface 140S2 of the second horizontal portion 140P2 may be farther away from the connection bump 160 than the side surface 140S1 of the first horizontal portion 140P1. Therefore, the width between the side surfaces 140S2 of the two second horizontal portions 140P2 facing each other and having the connection bump 160 therebetween may be greater than the width between the side surfaces 140S1 of the two first horizontal portions 140P1 facing each other and having the connection bump 160 therebetween. In addition, the widest space between the side surface 140S2 of the second horizontal portion 140P2 and the conductive pillar 156 may be approximately twice the widest space between the side surface 140S1 of the first horizontal portion 140P1 and the conductive pillar 156.

[0040] In the semiconductor chip 100 according to the embodiment, the interval between the conductive pillar 156 of the connection bump 160 and the insulating layer 140 may have a value that increases as the distance from the semiconductor substrate 110 increases. FIG. 9C to FIG. 9G The adhesive layer 20 is prevented from remaining in the space between the conductive pillar 156 and the insulating layer 140 during the process of separating the conductive pillar 156 from the semiconductor chip 100, wherein the adhesive layer fixes the semiconductor chip 100 to the carrier substrate ( FIG. 9C to FIG. 9G 10).

[0041] Specifically, since the insulating layer 140 includes the first horizontal portion 140P1 and the second horizontal portion 140P2 having a step height therebetween and constituting different layers, the height of the space having a relatively narrow width between the conductive pillar 156 and the side surface 140S1 of the first horizontal portion 140P1 can be set to be relatively smaller than the height of the space between the conductive pillar 156 and the insulating layer 140. Therefore, the insulating layer 140 for protecting the semiconductor substrate 110 can cover a relatively large portion of the upper surface of the semiconductor substrate 110, and further, the space between the conductive pillar 156 and the insulating layer 140 can be generously secured, thereby preventing defects due to a portion of the adhesive layer 20 remaining. Therefore, the reliability of the semiconductor chip 100 is ensured.

[0042] Reference Figure 2B , the connection bump 160 may be attached to the connection pad 120 disposed on the effective surface as the upper surface of the semiconductor substrate 110. The insulating layer 140 may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140 may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140 may be separated from the connection bump 160 and may surround the connection bump 160.

[0043] exist Figure 2B In, replace Figure 2A The passivation layer 130 of FIG. 1 is shown as a passivation layer 130a. The passivation layer 130a may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140. The passivation layer 130a may extend from the space between the upper surface of the semiconductor substrate 110 and the insulating layer 140 to the space between the connection pad 120 and the conductive pillar 156. The passivation layer 130a may cover all portions of the upper surface of the semiconductor substrate 110 except a portion of the upper surface of the connection pad 120.

[0044] The conductive pillar 156 may be in contact with a portion of the upper surface of the connection pad 120 that is not covered by the passivation layer 130 a .

[0045] The passivation layer 130 a may cover portions of the upper surface of the semiconductor substrate 110 not covered by the insulating layer 140 and the conductive pillars 156 and portions of the upper surface of the connection pad 120 not covered by the insulating layer 140 and the conductive pillars 156 .

[0046] Reference Figure 2C , the connection bumps 160 may be attached to the connection pads 120 disposed on the effective surface which is the upper surface of the semiconductor substrate 110. Figure 2C In, replace Figure 2A 1 and 2. The passivation layer 130 and the insulating layer 140 in FIG. 1 show the passivation layer 130b and the insulating layer 140a.

[0047] The insulating layer 140a may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140a may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140a may be separated from the connection bump 160 and may surround the connection bump 160. The passivation layer 130b may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140a.

[0048] The insulating layer 140a may include a first horizontal portion 140P1a as a lower portion adjacent to the semiconductor substrate 110 and a second horizontal portion 140P2a located on the first horizontal portion 140P1a. The first horizontal portion 140P1a and the second horizontal portion 140P2a may be portions of the insulating layer 140a that are provided as one body. The first horizontal portion 140P1a may be a portion constituting one layer at a lower portion of the insulating layer 140a, and the second horizontal portion 140P2a may be a portion constituting another layer on the first horizontal portion 140P1a. Figure 2C , the insulating layer 140a is illustrated as including a first horizontal portion 140P1a and a second horizontal portion 140P2a constituting two layers, but is not limited thereto. In other embodiments, the insulating layer 140a may include three or more horizontal portions constituting three or more layers.

[0049] The approximate width of the second horizontal portion 140P2a may have a value smaller than the value of the approximate width of the first horizontal portion 140P1a. The width of each of the first horizontal portion 140P1a and the second horizontal portion 140P2a may decrease as the distance from the semiconductor substrate 110 increases. The approximate width of the first horizontal portion 140P1a may represent an average width of the first horizontal portion 140P1a, and the approximate width of the second horizontal portion 140P2a may represent an average width of the second horizontal portion 140P2a. The first horizontal portion 140P1a and the second horizontal portion 140P2a may have a step height therebetween so that the insulating layer 140a is recessed in a direction from an upper surface 140H2a of the second horizontal portion 140P2a to an upper surface 140H1a of the first horizontal portion 140P1a.

[0050] That is, the insulating layer 140 a may include a first horizontal portion 140P1 a and a second horizontal portion 140P2 a having a step height therebetween and constituting different layers.

[0051] The side surface 140S1a of the first horizontal portion 140P1a and the side surface 140S2a of the second horizontal portion 140P2a may both extend to be inclined relative to the upper surface of the semiconductor substrate 110. The side surface 140S1a of the first horizontal portion 140P1a may be an inclined surface extending to have a slope of a first angle θ1 relative to the upper surface of the semiconductor substrate 110, and the side surface 140S2a of the second horizontal portion 140P2a may be an inclined surface extending to have a slope of a second angle θ2 relative to the upper surface of the semiconductor substrate 110. The first angle θ1 and the second angle θ2 may both have a value within a range of 90 degrees to 180 degrees. In some embodiments, the first angle θ1 and the second angle θ2 may have the same value.

[0052] The side surface 140S1a of the first horizontal portion 140P1a and the side surface 130Sb of the passivation layer 130b may be aligned in a direction corresponding to the first angle θ1 with respect to the upper surface of the semiconductor substrate 110. The side surface 140S2a of the second horizontal portion 140P2a may connect the upper surface 140H2a of the second horizontal portion 140P2a to the upper surface 140H1a of the first horizontal portion 140P1a. The upper surface of the conductive pillar 156 may be located at a level higher than the uppermost surface of the insulating layer 140a (i.e., the upper surface 140H2a of the second horizontal portion 140P2a) in a direction perpendicular to the upper surface of the semiconductor substrate 110.

[0053] Each of the side surface 140S1a of the first horizontal portion 140P1a and the side surface 140S2a of the second horizontal portion 140P2a may be an inclined surface extending to become farther from a portion of the connection bump 160 as a distance from the upper surface of the semiconductor substrate 110 increases.

[0054] The side surface 140S2a of the second horizontal portion 140P2a may be farther away from the connection bump 160 than the side surface 140S1a of the first horizontal portion 140P1a. Therefore, the width between the side surfaces 140S2a of the two second horizontal portions 140P2a facing each other with the connection bump 160 located therebetween may be greater than the width between the side surfaces 140S1a of the two first horizontal portions 140P1a facing each other with the connection bump 160 located therebetween.

[0055] Reference Figure 2D , the connection bumps 160 may be attached to the connection pads 120 disposed on the effective surface which is the upper surface of the semiconductor substrate 110 .

[0056] The insulating layer 140a may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140a may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140a may be spaced apart from the connection bump 160 and may surround the connection bump 160.

[0057] exist Figure 2D In, replace Figure 2C 1 and 14. The passivation layer 130b is shown, and the passivation layer 130a is shown. The passivation layer 130a may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140a. The passivation layer 130a may extend from the space between the semiconductor substrate 110 and the insulating layer 140a to the space between the connection pad 120 and the conductive pillar 156. The passivation layer 130a may cover all of the upper surface of the semiconductor substrate 110 except for a portion of the upper surface of the connection pad 120.

[0058] The conductive pillar 156 may be in contact with a portion of the upper surface of the connection pad 120 that is not covered by the passivation layer 130 a .

[0059] The passivation layer 130 a may cover portions of the upper surface of the semiconductor substrate 110 not covered by the insulating layer 140 a and the conductive pillars 156 and portions of the upper surface of the connection pad 120 not covered by the insulating layer 140 a and the conductive pillars 156 .

[0060] Reference Figure 2E , the connection bumps 160 may be attached to the connection pads 120 disposed on the effective surface which is the upper surface of the semiconductor substrate 110. Figure 2E In, replace Figure 2A 1 and 2. The passivation layer 130 and the insulating layer 140 are shown, and the passivation layer 130b and the insulating layer 140b are shown.

[0061] The insulating layer 140b may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140b may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140b may be spaced apart from the connection bump 160 and may surround the connection bump 160.

[0062] The passivation layer 130 b may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140 b .

[0063] The insulating layer 140b may include a first horizontal portion 140P1b as a lower portion adjacent to the semiconductor substrate 110 and a second horizontal portion 140P2b located on the first horizontal portion 140P1b. The first horizontal portion 140P1b and the second horizontal portion 140P2b may be portions of the insulating layer 140b that are provided as one body. The first horizontal portion 140P1b may be a portion constituting one layer at a lower portion of the insulating layer 140b, and the second horizontal portion 140P2b may be a portion constituting another layer on the first horizontal portion 140P1b. Figure 2E , the insulating layer 140b is illustrated as including a first horizontal portion 140P1b and a second horizontal portion 140P2b constituting two layers, but is not limited thereto. In other embodiments, the insulating layer 140b may include three or more horizontal portions constituting three or more layers.

[0064] The approximate width of the second horizontal portion 140P2b may have a value smaller than that of the approximate width of the first horizontal portion 140P1b. The first horizontal portion 140P1b and the second horizontal portion 140P2b may have a step height therebetween such that the insulating layer 140b is recessed in a direction from an upper surface 140H2b of the second horizontal portion 140P2b to an upper surface 140H1b of the first horizontal portion 140P1b.

[0065] That is, the insulating layer 140b may include the first and second horizontal portions 140P1b and 140P2b having a step height therebetween and constituting different layers. In some embodiments, the insulating layer 140b may not have a step height therebetween but only include the first and second horizontal portions 140P1b and 140P2b constituting different layers.

[0066] The side surface 140S1b of the first horizontal portion 140P1b and the side surface 140S2b of the second horizontal portion 140P2b may both extend to be inclined relative to the upper surface of the semiconductor substrate 110. The side surface 140S1b of the first horizontal portion 140P1b may be an inclined surface extending to have a slope of a first angle θ1b relative to the upper surface of the semiconductor substrate 110, and the side surface 140S2b of the second horizontal portion 140P2b may be an inclined surface extending to have a slope of an upper surface of a second angle θ2b relative to the upper surface of the semiconductor substrate 110. The first angle θ1b and the second angle θ2b may each have a value within a range of 90 degrees to 180 degrees. In some embodiments, the first angle θ1b and the second angle θ2b may have different values. For example, the first angle θ1b may have a value greater than the value of the second angle θ2b. In some embodiments, the first angle θ1b may have a value smaller than the value of the second angle θ2b.

[0067] The side surface 140S1b of the first horizontal portion 140P1b and the side surface 130Sb of the passivation layer 130b may be aligned in a direction corresponding to the first angle θ1b relative to the upper surface of the semiconductor substrate 110. The side surface 140S2b of the second horizontal portion 140P2b may connect the upper surface 140H2b of the second horizontal portion 140P2b to the upper surface 140H1b of the first horizontal portion 140P1b. The upper surface of the conductive pillar 156 may be located at a level higher than the uppermost surface of the insulating layer 140b (i.e., the upper surface 140H2b of the second horizontal portion 140P2b) in a direction perpendicular to the upper surface of the semiconductor substrate 110.

[0068] Each of the side surface 140S1 b of the first horizontal portion 140P1 b and the side surface 140S2 b of the second horizontal portion 140P2 b may be an inclined surface extending to become farther from a portion of the connection bump 160 as a distance from the upper surface of the semiconductor substrate 110 increases.

[0069] The side surface 140S2b of the second horizontal portion 140P2b may be farther away from the connection bump 160 than the side surface 140S1b of the first horizontal portion 140P1b. Therefore, the width between the side surfaces 140S2b of the two second horizontal portions 140P2b facing each other with the connection bump 160 located therebetween may be greater than the width between the side surfaces 140S1b of the two first horizontal portions 140P1b facing each other with the connection bump 160 located therebetween.

[0070] Reference Figure 2F , the connection bump 160 may be attached to the connection pad 120 disposed on the effective surface as the upper surface of the semiconductor substrate 110. The insulating layer 140b may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140b may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140b may be separated from the connection bump 160 and may surround the connection bump 160.

[0071] exist Figure 2F In, replace Figure 2E 14. The passivation layer 130b is shown as a passivation layer 130a. The passivation layer 130a may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140b. The passivation layer 130a may extend from the space between the upper surface of the semiconductor substrate 110 and the insulating layer 140b to the space between the connection pad 120 and the conductive pillar 156. The passivation layer 130a may cover all of the upper surface of the semiconductor substrate 110 except for a portion of the upper surface of the connection pad 120.

[0072] The conductive pillar 156 may be in contact with a portion of the upper surface of the connection pad 120 that is not covered by the passivation layer 130 a .

[0073] The passivation layer 130 a may cover portions of the upper surface of the semiconductor substrate 110 not covered by the insulating layer 140 b and the conductive pillars 156 and portions of the upper surface of the connection pad 120 not covered by the insulating layer 140 b and the conductive pillars 156 .

[0074] Reference Figure 2G , the connection bumps 160 may be attached to the connection pads 120 disposed on the effective surface which is the upper surface of the semiconductor substrate 110. Figure 2G In, replace Figure 2A 1 and 2. The passivation layer 130 and the insulating layer 140 in FIG. 1 show the passivation layer 130b and the insulating layer 140c.

[0075] The insulating layer 140c may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140c may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140c may be spaced apart from the connection bump 160 and may surround the connection bump 160.

[0076] The passivation layer 130 b may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140 c .

[0077] The insulating layer 140c may include a first horizontal portion 140P1c as a lower portion adjacent to the semiconductor substrate 110 and a second horizontal portion 140P2c located on the first horizontal portion 140P1c. The first horizontal portion 140P1c and the second horizontal portion 140P2c may be portions of the insulating layer 140c provided as one body. The first horizontal portion 140P1c may be a portion constituting one layer at a lower portion of the insulating layer 140c, and the second horizontal portion 140P2c may be a portion constituting another layer on the first horizontal portion 140P1c. Figure 2G , the insulating layer 140c is illustrated as including a first horizontal portion 140P1c and a second horizontal portion 140P2c constituting two layers, but is not limited thereto. In other embodiments, the insulating layer 140c may include three or more horizontal portions constituting three or more layers.

[0078] The approximate width of the second horizontal portion 140P2c may have a value smaller than that of the approximate width of the first horizontal portion 140P1c. The first horizontal portion 140P1c and the second horizontal portion 140P2c may have a step height therebetween such that the insulating layer 140c is recessed in a direction from an upper surface 140H2c of the second horizontal portion 140P2c to an upper surface 140H1c of the first horizontal portion 140P1c.

[0079] That is, the insulating layer 140c may include a first horizontal portion 140P1c and a second horizontal portion 140P2c having a step height therebetween and configuring different layers.

[0080] The side surface 140S1c of the first horizontal portion 140P1c may extend to be inclined relative to the upper surface of the semiconductor substrate 110. The side surface 140S1c of the first horizontal portion 140P1c may be an inclined surface extending to have a slope having a certain angle with a value ranging from 90 to 180 degrees relative to the upper surface of the semiconductor substrate 110.

[0081] The side surface 140S2c of the second horizontal portion 140P2c may be an inclined surface extending to be rounded between the upper surface 140H1c of the first horizontal portion 140P1c and the upper surface 140H2c of the second horizontal portion 140P2c. The side surface 140S2c of the second horizontal portion 140P2c may be rounded to have a convex shape protruding toward the second horizontal portion 140P2c.

[0082] A side surface 140S1 c of the first horizontal portion 140P1 c and a side surface 130Sb of the passivation layer 130 b may be aligned in a direction corresponding to a specific angle having a value in the range of 90 to 180 degrees with respect to the upper surface of the semiconductor substrate 110 .

[0083] An upper surface of the conductive pillar 156 may be located at a level higher than an uppermost surface of the insulating layer 140 c (ie, an upper surface 140H2 c of the second horizontal portion 140P2 c ) in a direction perpendicular to the upper surface of the semiconductor substrate 110 .

[0084] Each of the side surface 140S1c of the first horizontal portion 140P1c and the side surface 140S2c of the second horizontal portion 140P2c may be an inclined surface extending to become farther from a portion of the connection bump 160 as a distance from the upper surface of the semiconductor substrate 110 increases.

[0085] The side surface 140S2c of the second horizontal portion 140P2c may be farther away from the connection bump 160 than the side surface 140S1c of the first horizontal portion 140P1c. Therefore, the width between the side surfaces 140S2c of the two second horizontal portions 140P2c facing each other with the connection bump 160 located therebetween may be greater than the width between the side surfaces 140S1c of the two first horizontal portions 140P1c facing each other with the connection bump 160 located therebetween.

[0086] Reference Figure 2H, the connection bump 160 may be attached to the connection pad 120 disposed on the effective surface as the upper surface of the semiconductor substrate 110. The insulating layer 140c may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140c may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140c may be separated from the connection bump 160 and may surround the connection bump 160.

[0087] exist Figure 2H In, replace Figure 2G 14. The passivation layer 130b is shown, and the passivation layer 130a is shown. The passivation layer 130a may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140c. The passivation layer 130a may extend from the space between the upper surface of the semiconductor substrate 110 and the insulating layer 140c to the space between the connection pad 120 and the conductive pillar 156. The passivation layer 130a may cover all of the upper surface of the semiconductor substrate 110 except a portion of the upper surface of the connection pad 120.

[0088] The conductive pillar 156 may be in contact with a portion of the upper surface of the connection pad 120 that is not covered by the passivation layer 130 a .

[0089] The passivation layer 130 a may cover portions of the upper surface of the semiconductor substrate 110 not covered by the insulating layer 140 c and the conductive pillars 156 and portions of the upper surface of the connection pad 120 not covered by the insulating layer 140 c and the conductive pillars 156 .

[0090] Reference Fig.2I , the connection bumps 160 may be attached to the connection pads 120 disposed on the effective surface which is the upper surface of the semiconductor substrate 110. Fig.2I In, replace Figure 2C Insulating layer 140a in FIG. 1 , insulating layer 140d is shown.

[0091] The insulating layer 140d may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140d may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140d may be separated from the connection bump 160 and may surround the connection bump 160. The passivation layer 130b may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140d.

[0092] The insulating layer 140d may include a first horizontal portion 140P1d as a lower portion adjacent to the semiconductor substrate 110, a second horizontal portion 140P2d located on the first horizontal portion 140P1d, and a third horizontal portion 140P3d located on the second horizontal portion 140P2d. The first horizontal portion 140P1d, the second horizontal portion 140P2d, and the third horizontal portion 140P3d may be portions of the insulating layer 140d that are provided as one body. The first horizontal portion 140P1d may be a portion constituting a layer at a lower portion of the insulating layer 140d, the third horizontal portion 140P3d may be a portion constituting a layer at an upper portion of the insulating layer 140d, and the second horizontal portion 140P2d may be a portion constituting another layer between the first horizontal portion 140P1d and the third horizontal portion 140P3d. Fig.2I , the insulating layer 140d is illustrated as including the first horizontal portion 140P1d, the second horizontal portion 140P2d, and the third horizontal portion 140P3d constituting three layers, but is not limited thereto. In other embodiments, the insulating layer 140d may include four or more horizontal portions constituting four or more layers.

[0093] The approximate width of the third horizontal portion 140P3d may have a value smaller than that of the second horizontal portion 140P2d, and the approximate width of the second horizontal portion 140P2d may have a value smaller than that of the first horizontal portion 140P1d. The second horizontal portion 140P2d and the third horizontal portion 140P3d may have a step height therebetween so that the insulating layer 140d is recessed in a direction from an upper surface 140H3d of the third horizontal portion 140P3d to an upper surface 140H2d of the second horizontal portion 140P2d, and the first horizontal portion 140P1d and the second horizontal portion 140P2d may have a step height therebetween so that the insulating layer 140d is recessed in a direction from an upper surface 140H2d of the second horizontal portion 140P2d to an upper surface 140H1d of the first horizontal portion 140P1d.

[0094] That is, the insulating layer 140d may include a first horizontal portion 140P1d, a second horizontal portion 140P2d, and a third horizontal portion 140P3d having a step height therebetween and configuring different layers.

[0095] The side surface 140S1d of the first horizontal portion 140P1d, the side surface 140S2d of the second horizontal portion 140P2d, and the side surface 140S3d of the third horizontal portion 140P3d may each extend to be inclined relative to the upper surface of the semiconductor substrate 110. In some embodiments, the side surface 140S1d of the first horizontal portion 140P1d, the side surface 140S2d of the second horizontal portion 140P2d, and the side surface 140S3d of the third horizontal portion 140P3d may be inclined surfaces extending to have a slope of the same angle having a value in the range of 90 to 180 degrees relative to the upper surface of the semiconductor substrate 110. In some other embodiments, the side surface 140S1d of the first horizontal portion 140P1d, the side surface 140S2d of the second horizontal portion 140P2d, and the side surface 140S3d of the third horizontal portion 140P3d may be an inclined surface extending to have a slope having an angle with a value in the range of 90 degrees to 180 degrees relative to the upper surface of the semiconductor substrate 110, in which case at least one inclined surface may extend to have a slope of another angle. In some other embodiments, the side surface 140S1d of the first horizontal portion 140P1d, the side surface 140S2d of the second horizontal portion 140P2d, and the side surface 140S3d of the third horizontal portion 140P3d may extend in a direction perpendicular to the upper surface of the semiconductor substrate 110.

[0096] The side surface 140S1d of the first horizontal portion 140P1d and the side surface 130Sb of the passivation layer 130b may be aligned in a direction corresponding to the same angle with respect to the upper surface of the semiconductor substrate 110. In some embodiments, the side surface 140S1d of the first horizontal portion 140P1d and the side surface 130Sb of the passivation layer 130b may be aligned in a direction corresponding to the same angle in a range of 90 to 180 degrees with respect to the upper surface of the semiconductor substrate 110. In some other embodiments, the side surface 140S1d of the first horizontal portion 140P1d and the side surface 130Sb of the passivation layer 130b may be aligned in a direction perpendicular to the upper surface of the semiconductor substrate 110.

[0097] The side surface 140S2d of the second horizontal portion 140P2d may connect the upper surface 140H2d of the second horizontal portion 140P2d to the upper surface 140H1d of the first horizontal portion 140P1d, and the side surface 140S3d of the third horizontal portion 140P3d may connect the upper surface 140H3d of the third horizontal portion 140P3d to the upper surface 140H2d of the second horizontal portion 140P2d. The upper surface of the conductive pillar 156 may be located at a level higher than the uppermost surface of the insulating layer 140d (i.e., the upper surface 140H3d of the third horizontal portion 140P3d) in a direction perpendicular to the upper surface of the semiconductor substrate 110.

[0098] Each of the side surfaces 140S1d of the first horizontal portion 140P1d, 140S2d of the second horizontal portion 140P2d, and 140S3d of the third horizontal portion 140P3d may be an inclined surface extending to become farther away from the connection bump 160 as the distance from the upper surface of the semiconductor substrate 110 increases.

[0099] The side surface 140S3d of the third horizontal portion 140P3d may be farther from the connection bump 160 than the side surface 140S2d of the second horizontal portion 140P2d, and the side surface 140S2d of the second horizontal portion 140P2d may be farther from the connection bump 160 than the side surface 140S1d of the first horizontal portion 140P1d. Therefore, the width between the side surfaces 140S3d of the two third horizontal portions 140P3d facing each other and having the connection bump 160 therebetween may be greater than the width between the side surfaces 140S2d of the two second horizontal portions 140P2d facing each other and having the connection bump 160 therebetween, and the width between the side surfaces 140S2d of the two second horizontal portions 140P2d facing each other and having the connection bump 160 therebetween may be greater than the width between the side surfaces 140S1d of the two first horizontal portions 140P1d facing each other and having the connection bump 160 therebetween.

[0100] Reference Figure 2J , the connection bump 160 may be attached to the connection pad 120 disposed on the effective surface as the upper surface of the semiconductor substrate 110. The insulating layer 140d may be disposed on the upper surface of the semiconductor substrate 110. The insulating layer 140d may expose the connection pad 120 and may cover a portion of the upper surface of the semiconductor substrate 110. The insulating layer 140d may be spaced apart from the connection bump 160 and may surround the connection bump 160.

[0101] exist Figure 2J In, replace Fig.2I 140a. The passivation layer 130a may be disposed between the upper surface of the semiconductor substrate 110 and the insulating layer 140d. The passivation layer 130a may extend from the space between the upper surface of the semiconductor substrate 110 and the insulating layer 140d to the space between the connection pad 120 and the conductive pillar 156. The passivation layer 130a may cover all of the upper surface of the semiconductor substrate 110 except a portion of the upper surface of the connection pad 120.

[0102] The conductive pillar 156 may be in contact with a portion of the upper surface of the connection pad 120 that is not covered by the passivation layer 130 a .

[0103] The passivation layer 130 a may cover portions of the upper surface of the semiconductor substrate 110 not covered by the insulating layer 140 d and the conductive pillars 156 and portions of the upper surface of the connection pad 120 not covered by the insulating layer 140 d and the conductive pillars 156 .

[0104] The above describes Figure 1 The connection bump in the part A corresponds to the case, but the inventive concept is not limited thereto. In some other embodiments, Figure 1 The connecting bumps adjacent to the connecting bumps in the portion A may have the same structure. In this case, the portion of the insulating layer 140 located between the two adjacent connecting bumps may have a first side wall and a second side wall opposite to each other. Each of the first side wall and the second side wall may have a FIG. 2A to FIG. 2J The structure described in .

[0105] FIG. 3A to FIG. 3D is an enlarged plan view showing connection bumps of a semiconductor chip according to an embodiment.

[0106] Reference FIG. 3A to FIG. 3D , the passivation layer 130 and the insulating layer 140 may be separated from the connection bump 160 attached to the connection pad 120 and may surround the connection bump 160. FIG. 3A to FIG. 3D , a conductive cover 158 disposed on the uppermost end of the connection bump 160 is shown.

[0107] The side surface 140S1 of the first horizontal portion 140P1 and the side surface 140S2 of the second horizontal portion 140P2 may be formed on the semiconductor substrate ( Figure 1 and Figure 2A 110) extends as a straight line in the horizontal direction of the upper surface and may surround the connecting bump 160.

[0108] exist FIG. 3A to FIG. 3D In the figure, it is shown that each of the side surfaces 140S1 of the first horizontal portion 140P1 and the side surfaces 140S2 of the second horizontal portion 140P2 is configured to have a quadrilateral shape, a pentagonal shape, a hexagonal shape or an octagonal shape in the horizontal direction of the upper surface of the semiconductor substrate 110 and surrounds the connecting bump 160, but the present embodiment is not limited to this.

[0109] For example, each of the side surface 140S1 of the first horizontal portion 140P1 and the side surface 140S2 of the second horizontal portion 140P2 may have an n-gonal shape (n≧4) and may surround the connection bump 160 .

[0110] Figure 4 is a cross-sectional view showing a semiconductor package 1000 including a semiconductor chip according to an embodiment.

[0111] Reference Figure 4The semiconductor package 1000 may include a plurality of semiconductor chips. The plurality of semiconductor chips may include a first semiconductor chip 100 a and a plurality of second semiconductor chips 200 .

[0112] In some embodiments, the first semiconductor chip 100 a may be a buffer chip including a serial-to-parallel conversion circuit, and the plurality of second semiconductor chips 200 may all be high bandwidth memory dynamic random access memory (HBM DRAM) semiconductor chips.

[0113] The first semiconductor chip 100 a may generally have Figure 1 The first semiconductor chip 100a may include a first semiconductor substrate 110, a first connection pad 120, a first insulating layer 140, and a first connection bump 160 including a first conductive column 156 and a first conductive cover 158. The first semiconductor substrate 110, the first connection pad 120, the first insulating layer 140, and the first connection bump 160 including the first conductive column 156 and the first conductive cover 158 are similar to the structure of the semiconductor chip 100 of FIG. Figure 1 The semiconductor substrate 110, the connection pad 120, the insulating layer 140, and the connection bump 160 including the conductive pillar 156 and the conductive cap 158 shown in FIG. 1 are substantially the same elements, and thus, their detailed description is omitted.

[0114] The first semiconductor chip 100a may further include a first through electrode 170 and a second connection pad 180. The first through electrode 170 may connect the first connection pad 120 to the second connection pad 180. The first connection pad 120 and the second connection pad 180 may be disposed on an active surface and an inactive surface of the first semiconductor substrate 110, respectively.

[0115] The first through electrode 170 may include a conductive plug passing through the first semiconductor substrate 110 and a conductive barrier layer surrounding the conductive plug. The conductive plug may have a cylindrical shape, and the conductive barrier layer may have a cylindrical shape surrounding the sidewall of the conductive plug. The conductive plug may include Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W or W alloy, but is not limited thereto. The conductive plug may include, for example, Al, Au, beryllium (Be), Bi, cobalt (Co), Cu, hafnium (Hf), In, manganese (Mn), molybdenum (Mo), Ni, Pb, Pd, Pt, rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Ta), tellurium (Te), titanium (Ti), W, Zn and zirconium (Zr) One or more, and may include one or more stacked structures. The conductive barrier layer may include, for example, at least one material selected from the group consisting of W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB, but is not limited thereto.

[0116] The via insulating layer may be disposed between the first semiconductor substrate 110 and the first through electrode 170 and may surround the sidewall of the first through electrode 170. The via insulating layer may include oxide, nitride, carbide, polymer, or a combination thereof. The via insulating layer may include, for example, ozone / tetraethylorthosilicate (O 3 / TEOS)-type high aspect ratio process (HARP) oxides.

[0117] exist Figure 4 , an example is shown in which the first through electrode 170 directly connects the first connection pad 120 to the second connection pad 180, but the present embodiment is not limited thereto. In other embodiments, the first through electrode 170 may be configured to have one of a via-first structure, a via-intermediate structure, and a via-final structure.

[0118] A plurality of second semiconductor chips 200 may be stacked on the first semiconductor chip 100 a .

[0119] The plurality of second semiconductor chips 200 may each include a second semiconductor substrate 210 , a second top connection pad 220 , a second insulating layer 240 , and a second connection bump 260 including a second conductive pillar 256 and a second conductive cap 258 .

[0120] Each of the plurality of second semiconductor chips 200 may further include a second through electrode 270 and a second connection pad 280 . In some embodiments, an uppermost second semiconductor chip 200 of the plurality of second semiconductor chips 200 may not include the second through electrode 270 and the second connection pad 280 .

[0121] The second semiconductor substrate 210, the second top connection pad 220, the second insulating layer 240, the second connection bump 260 including the second conductive pillar 256 and the second conductive cap 258, the second through electrode 270, and the second connection pad 280 are substantially similar to the first semiconductor substrate 110, the first connection pad 120, the first insulating layer 140, the first connection bump 160 including the first conductive pillar 156 and the first conductive cap 158, the first through electrode 170, and the second connection pad 180. Therefore, repeated descriptions are omitted hereinafter, and the differences will be mainly described.

[0122] The second semiconductor chip 200 disposed in the upper portion among the plurality of second semiconductor chips 200 may be electrically connected to the first semiconductor chip 100 a through the second through electrode 270 included in the lower second semiconductor chip 200 .

[0123] The insulating adhesive layer 350 may be disposed between the first semiconductor chip 100a and one second semiconductor chip 200 and between two adjacent second semiconductor chips 200. The insulating adhesive layer 350 may include a non-conductive film (NCF) or a non-conductive paste (NCP). Alternatively, the insulating adhesive layer 350 may include an underfill material such as an insulating polymer or epoxy resin.

[0124] The semiconductor package 1000 may include a mold layer 300 disposed on the first semiconductor chip 100a to surround a side surface of each of the plurality of second semiconductor chips 200 and a side surface of the insulating adhesive layer 350. The mold layer 300 may include, for example, epoxy mold compound (EMC).

[0125] The plurality of first connection bumps 160 included in the first semiconductor chip 100a may be arranged at a first pitch, and the plurality of second connection bumps 260 included in each of the plurality of second semiconductor chips 200 may be arranged at a second pitch. In some embodiments, the first pitch and the second pitch may have the same value.

[0126] Figure 5A and Figure 5B is an enlarged cross-sectional view showing a connection bump of a semiconductor chip included in a semiconductor package according to an embodiment. In detail, Figure 5A and Figure 5B It is shown Figure 4 An enlarged cross-sectional view of part B and part C.

[0127] Reference Figure 5A , Figure 5B and Figure 4 , the first semiconductor chip 100a may include a first passivation layer 130, a first insulating layer 140, and a first connection bump 160 including a first conductive pillar 156 and a first conductive cover 158. The first semiconductor chip 100a may include a first semiconductor substrate 110, a first connection pad 120, a first insulating layer 140, and a first connection bump 160 including a first conductive pillar 156 and a first conductive cover 158. The second semiconductor chip 200 may include a second passivation layer 230, a second insulating layer 240, and a second connection bump 260 including a second conductive pillar 256 and a second conductive cover 258. The first passivation layer 130 is connected to Figure 1 The second passivation layer 230 is substantially similar to the first passivation layer 130 .

[0128] The first conductive pillar 156 may include a first base pillar 152 and a first cover pillar 154 covering an upper surface of the first base pillar 152. The second conductive pillar 256 may include a second base pillar 252 and a second cover pillar 254 covering an upper surface of the second base pillar 252. Figure 1 The first cover column 154 is substantially the same as the first base column 152. The second base column 252 is substantially similar to the first base column 152. Figure 1 The second covering pillars 254 are substantially similar to the first covering pillars 154. Therefore, repeated descriptions are omitted hereinafter, and the differences will be mainly described.

[0129] The first insulating layer 140 may include a first horizontal portion 140P1 adjacent to the first semiconductor substrate 110 and a second horizontal portion 140P2 located on the first horizontal portion 140P1. The first horizontal portion 140P1 and the second horizontal portion 140P2 may be a portion of the first insulating layer 140 provided as a whole. The first horizontal portion 140P1 and the second horizontal portion 140P2 may have a step height located therebetween. That is, the first insulating layer 140 may include a first horizontal portion 140P1 and a second horizontal portion 140P2 having a step height located therebetween and constituting different layers. In other words, the first insulating layer 140 may include two or more horizontal portions constituting two or more layers having a step height located therebetween.

[0130] The second insulating layer 240 may be composed of only one layer. That is, the second insulating layer 240 may have a single-layer structure composed of one layer so as not to have a step height.

[0131] The first conductive pillar 156 may have a first width W1 and a first height H1, and the second conductive pillar 256 may have a second width W2 and a second height H2.

[0132] The first width W1 may have a value greater than the second width W2, and the first height H1 may have a value greater than the second height H2. For example, the first width W1 may be 15 μm to 40 μm, and the second width W2 may be 10 μm to 30 μm in a range smaller than the first width W1. For example, the first height H1 may be 10 μm to 30 μm, and the second height H2 may be 2 μm to 15 μm in a range smaller than the first height H1.

[0133] The ratio of the first height H1 to the first width W1 (i.e., the aspect ratio of the first conductive pillar 156) may have a higher value than the ratio of the second height H2 to the second width W2 (i.e., the aspect ratio of the second conductive pillar 256). For example, the aspect ratio of the first conductive pillar 156 may be 0.5 to 1.5, and the aspect ratio of the second conductive pillar 256 may be 0.1 to 1 in a range smaller than the aspect ratio of the first conductive pillar 156.

[0134] The process of manufacturing the first semiconductor chip 100a, the process of manufacturing the second semiconductor chip 200, and the process of manufacturing the semiconductor package 1000 including the first semiconductor chip 100a and the second semiconductor chip 200 may include fixing the first semiconductor chip 100a and / or the second semiconductor chip 200 to a carrier substrate by using an adhesive layer, and then removing the carrier substrate and the adhesive layer from the first semiconductor chip 100a and / or the second semiconductor chip 200.

[0135] In such a process, when the aspect ratio of the first conductive pillar 156 is greater than the aspect ratio of the second conductive pillar 256, there is a high possibility that a portion of the adhesive layer remains between the first insulating layer 140 of the first semiconductor chip 100a and the first conductive pillar 156. However, the semiconductor package 1000 according to the present embodiment may have a single-layer structure in which the first insulating layer 140 of the first semiconductor chip 100a has a step height, and thus, a space between the first connection bump 160 and the first insulating layer 140 may be ensured, thereby preventing a portion of the adhesive layer from remaining between the first connection bump 160 and the first insulating layer 140.

[0136] FIG. 6A to FIG. 6C is an enlarged cross-sectional view showing a connection bump of a semiconductor chip according to an embodiment. In detail, FIG. 6A to FIG. 6C is with Figure 4 Part C is an enlarged cross-sectional view of the portion corresponding to the part.

[0137] Reference Fig. 6A , the second passivation layer 230a may be disposed between the upper surface of the second semiconductor substrate 210 and the second insulating layer 240. Fig. 6A In, replace Figure 5B The second passivation layer 230 of FIG. 2 is a second passivation layer 230a. The second passivation layer 230a may extend from the space between the upper surface of the second semiconductor substrate 210 and the second insulating layer 240 to the space between the second connection pad 220 and the second conductive pillar 256. The second passivation layer 230a may cover all of the upper surface of the second semiconductor substrate 210 except a portion of the upper surface of the second connection pad 220.

[0138] The second conductive pillar 256 may contact a portion of the upper surface of the second connection pad 220 that is not covered by the second passivation layer 230a. The second passivation layer 230a may cover a portion of the upper surface of the second semiconductor substrate 210 that is not covered by the second insulating layer 240 and the second conductive pillar 256 and a portion of the upper surface of the second connection pad 220 that is not covered by the second insulating layer 240 and the second conductive pillar 256.

[0139] Reference Figure 6B, the second insulating layer 240b may be disposed on the upper surface of the second semiconductor substrate 210. The second insulating layer 240b may expose the second connection pad 220 and may cover a portion of the upper surface of the second semiconductor substrate 210. The second passivation layer 230b may be disposed between the upper surface of the second semiconductor substrate 210 and the second insulating layer 240b.

[0140] exist Figure 6B In, replace Figure 5B The second passivation layer 230 and the second insulating layer 240 are shown, and the second passivation layer 230b and the second insulating layer 240b are shown.

[0141] A side surface of each of the second passivation layer 230 b and the second insulating layer 240 b may extend to be inclined with respect to the upper surface of the second semiconductor substrate 210 .

[0142] Reference Figure 6C , the second passivation layer 230a may be disposed between the upper surface of the second semiconductor substrate 210 and the second insulating layer 240b. Figure 6C In, replace Figure 6B The second passivation layer 230b is shown as the second passivation layer 230a. The second passivation layer 230a may extend from the space between the upper surface of the second semiconductor substrate 210 and the second insulating layer 240b to the space between the second connection pad 220 and the second conductive pillar 256. The second passivation layer 230a may cover all of the upper surface of the second semiconductor substrate 210 except a portion of the upper surface of the second connection pad 220.

[0143] The second conductive pillar 256 may contact a portion of the upper surface of the second connection pad 220 that is not covered by the second passivation layer 230a. The second passivation layer 230a may cover a portion of the upper surface of the second semiconductor substrate 210 that is not covered by the second insulating layer 240b and the second conductive pillar 256 and a portion of the upper surface of the second connection pad 220 that is not covered by the second insulating layer 240b and the second conductive pillar 256.

[0144] Furthermore, although not shown, it is obvious to those skilled in the art that Figure 4 and Figure 5A The first passivation layer 130 and the first insulating layer 140 included in the first semiconductor chip 100a are FIG. 2B to FIG. 2J The first passivation layer 130a or 130b and the first insulating layer 140a, 140b, 140c or 140d shown in FIG.

[0145] 7A to 7C 1 is a cross-sectional view sequentially showing a method of manufacturing a semiconductor chip according to an embodiment. In detail, 7A to 7C is shown in order to manufacture Figure 2AA cross-sectional view of a semiconductor chip 100 is shown in the method.

[0146] Reference Fig. 7A , a preliminary passivation layer 130PL and a preliminary insulating layer 140PL may be sequentially formed on the semiconductor substrate 110 including the connection pad 120. The preliminary passivation layer 130PL may include, for example, an inorganic material such as oxide or nitride. The preliminary insulating layer 140PL may include, for example, PSPI.

[0147] Next, a mask MK1 including a light-transmitting portion RE, a light-blocking portion RD, and a strip pattern portion RH may be disposed on the semiconductor substrate 110. The light-transmitting portion RE may transmit most of the light radiated from the exposure device applied to the photolithography process, and the light-blocking portion RD may block most of the radiated light. The strip pattern portion RH may include a plurality of scattering strip patterns arranged repeatedly. The strip pattern portion RH may transmit only a portion of the light radiated from the exposure device applied to the photolithography process and may block other light.

[0148] The plurality of scattering stripe patterns provided in the stripe pattern part RH may have a one-dimensional shape and be surrounded by a plurality of n (n≥4) angles in sequence. In the plurality of scattering stripe patterns, each portion may extend in a straight line shape, and a portion extending in a curved shape may not be provided.

[0149] Reference Figure 7B The preliminary insulating layer ( Fig. 7A A portion of the 140PL) is exposed.

[0150] The portion of the preliminary insulating layer 140PL corresponding to the light transmitting portion RE of the mask MK1 may be completely exposed, and all portions corresponding to the light blocking portion RD may not be exposed. In addition, only a portion of the upper portion of the portion of the preliminary insulating layer 140PL corresponding to the strip pattern portion RH may be exposed.

[0151] therefore, Fig. 7A The preliminary insulating layer 140PL shown in FIG. 1 may include a first portion 140EX exposed by a photolithography process using a mask MK1 and a second portion 140DK not exposed.

[0152] Reference Figure 7C , the insulating layer 140 including the first horizontal portion 140P1 and the second horizontal portion 140P2 integrally formed can be formed by removing the first portion 140EX so that the insulating layer 140 is retained. Figure 7B In the process of removing the first portion 140EX, the preliminary passivation layer ( Fig. 7A130PL), and thus, a passivation layer 130 can be formed between the semiconductor substrate 110 and the insulating layer 140.

[0153] FIG. 8A to FIG. 8C 1 is a cross-sectional view sequentially showing a method for manufacturing a semiconductor chip according to an embodiment. In detail, FIG. 8A to FIG. 8C is shown in order to manufacture Figure 2B A cross-sectional view of a semiconductor chip is shown in the method.

[0154] Reference Fig. 8A , a passivation layer 130a that does not cover a portion of the connection pad 120 may be formed on the semiconductor substrate 110 including the connection pad 120. Fig. 7A ) After that, a portion of the preliminary passivation layer 130PL disposed on the connection pad 120 is removed to form the passivation layer 130a. Next, a preliminary insulating layer 140PL covering the semiconductor substrate 110 on which the passivation layer 130a is formed may be formed.

[0155] Reference Figure 8B and Figure 8C ,and Figure 7B and Figure 7C Similar to the example of, the prepared insulating layer ( Fig. 8A 140PL) is divided into an exposed first portion 140EX and an unexposed second portion 140DK. Next, the insulating layer 140 including the first horizontal portion 140P1 and the second horizontal portion 140P2 set as one body may be formed by removing the first portion 140EX so that the second portion 140DK remains. When the passivation layer 130a has etching resistance relative to the process of removing the first portion 140EX, a portion of the passivation layer 130a may not be removed in the process of removing the first portion 140EX.

[0156] FIG. 9A to FIG. 9G are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment.

[0157] Reference Fig. 9A , a first preliminary semiconductor substrate 110 p on which the first connection pad 120 and the first through electrode 170 are formed may be provided.

[0158] Reference Fig. 9B , a first insulating layer 140 exposing the first connection pad 120 but not covering the first connection pad 120 may be formed on the upper surface of the first preliminary semiconductor substrate 110p. Although not shown, a first passivation layer ( Figure 7C 130 or Figure 8C130a). 7A to 7C or FIG. 8A to FIG. 8C The method is described to form the first passivation layer 130 or 130 a and the first insulating layer 140 .

[0159] Next, a first connection bump 160 including a first conductive pillar 156 and a first conductive cap 158 may be formed on the first connection pad 120 .

[0160] Reference Fig. 9C In order to make the first connection bumps 160 face the carrier substrate 10, the first preliminary semiconductor substrate 110p may be attached to the carrier substrate 10 with the adhesive layer 20 located between the first preliminary semiconductor substrate 110p and the carrier substrate 10. The adhesive layer 20 may fill the space between the first insulating layer 140 and the first connection bumps 160 and may surround the first connection bumps 160.

[0161] Reference Fig.9D , by removing the first prepared semiconductor substrate ( Fig. 9B The first semiconductor chip 100a is formed by exposing a portion of the lower surface of the first semiconductor substrate 110p to expose the first through electrode 170 at the lower surface of the first semiconductor substrate 110. Next, a second connection pad 180 connected to the first through electrode 170 may be formed on the lower surface of the first semiconductor substrate 110, thereby completing the first semiconductor chip 100a.

[0162] Reference Fig.9E , a plurality of second semiconductor chips 200 may be stacked on the first semiconductor chip 100 a. Each of the plurality of second semiconductor chips 200 may be stacked on the first semiconductor chip 100 a through an insulating adhesive layer 350 .

[0163] Reference Fig.9F , a mold layer 300 surrounding a side surface of each of the plurality of second semiconductor chips 200 and a side surface of the insulating adhesive layer 350 may be formed on the first semiconductor chip 100 a .

[0164] Reference Figure 9G , the semiconductor package 1000 may be formed by removing the carrier substrate 10 and the adhesive layer 20 from the first semiconductor chip 100 a .

[0165] As described above, the first insulating layer 140 of the first semiconductor chip 100a can have a multilayer structure with a step height, so that the space between the first connecting bump 160 and the first insulating layer 140 can be fully ensured, thereby preventing a portion of the adhesive layer 20 from remaining between the first connecting bump 160 and the first insulating layer 140.

[0166] Fig.10 is a cross-sectional view showing a system 1 including a semiconductor package according to an embodiment.

[0167] Reference Fig.10 , the system 1 may include a semiconductor package 1000 including a first semiconductor chip 100 a and a plurality of second semiconductor chips 200 , an interposer 500 having a third semiconductor chip 400 attached thereto, and a main board 600 having the interposer 500 mounted thereon.

[0168] The third semiconductor chip 400 may include a third semiconductor substrate 410, a third connection pad 420, a third insulating layer 440, and a third connection bump 460 including a third conductive column 456 and a third conductive cap 458. The third semiconductor substrate 410 and the third connection pad 420 are connected to Figure 1 The semiconductor substrate 110 and the connection pad 120 shown in FIG. 1 are substantially similar elements, and the third insulating layer 440 is Figure 4 The second insulating layer 240 is substantially similar to the element shown in FIG. Figure 4 1 and 2. Therefore, hereinafter, their detailed description is omitted.

[0169] The third semiconductor chip 400 may be, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0170] The interposer 500 may include a base layer 510 , a first top pad 520 disposed on an upper surface of the base layer 510 , and a first bottom pad 530 disposed on a lower surface of the base layer 510 .

[0171] The base layer 510 may include semiconductor, glass, ceramic or plastic. For example, the base layer 510 may include silicon. A wiring layer connected to the first top pad 520 and / or the first bottom pad 530 may be disposed on the upper surface and / or the lower surface of the base layer 510, and an internal through electrode that electrically connects the first top pad 520 to the first bottom pad 530 may be disposed in the base layer 510. The first connection bump 160 of the semiconductor package 1000 and the third connection bump 460 of the third semiconductor chip 400 may be connected to the first top pad 520.

[0172] The first underfill layer 380 may be disposed between the semiconductor package 1000 and the interposer 500, and the second underfill layer 480 may be disposed between the third semiconductor chip 400 and the interposer 500. The first underfill layer 380 and the second underfill layer 480 may surround the first and third connecting bumps 160 and 460, respectively.

[0173] The first connection terminal 550 may be attached to the first bottom pad 530. The first connection terminal 550 may electrically connect the interposer 500 to the main board 600.

[0174] The main board 600 may include a base board layer 610 , a second top pad 620 disposed on an upper surface of the base board layer 610 , and a second bottom pad 630 disposed on a lower surface of the base board layer 610 .

[0175] In some embodiments, the main board 600 may be a printed circuit board (PCB). For example, the main board 600 may be a multilayer PCB. The base board layer 610 may include at least one material selected from phenolic resin, epoxy resin, and polyimide. The base board layer 610 may include, for example, at least one material selected from frame flame retardant 4 (FR4), tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, bismaleimide triazine (BT), heat, cyanate ester, polyimide, and liquid crystal polymer.

[0176] A solder resist layer exposing the second top pad 620 may be formed on the upper surface of the base plate layer 610, and a solder resist layer (not shown) exposing the second bottom pad 630 may be formed on the lower surface of the base plate layer 610. The first connection terminal 550 may be connected to the second top pad 620, and the second connection terminal 650 may be connected to the second bottom pad 630. The first connection terminal 550 may electrically connect the second bottom pad 630 to the second top pad 620. The second connection terminal 650 connected to the second bottom pad 630 may perform the function of an external connection terminal.

[0177] In some embodiments, the system 1 may not include the main board 600 , and the first connection terminal 550 of the interposer 500 may perform the function of an external connection terminal.

[0178] The semiconductor chip according to the embodiment may include an insulating layer, the insulating layer is separated from the connection bump to surround the connection bump and has a multilayer structure in which at least two horizontal portions are arranged to have a step height disposed therebetween. The insulating layer may cover a relatively large portion of the upper surface of the semiconductor substrate, greatly ensuring a space between the conductive pillars of the connection bump and the insulating layer.

[0179] Therefore, defects caused by a portion of the adhesive layer remaining between the conductive pillar and the insulating layer are prevented in the process of manufacturing the semiconductor chip and the process of manufacturing the semiconductor package including the semiconductor chip, thereby ensuring the reliability of the semiconductor chip and thus ensuring the reliability of the semiconductor package including the semiconductor chip.

[0180] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor device, the semiconductor device include: Semiconductor substrate; A connection base column is located on the semiconductor substrate; as well as an insulating layer disposed on the semiconductor substrate, the insulating layer comprising an opening disposed in the insulating layer, the connecting base pillar extending through the opening, wherein a sidewall of the insulating layer defining the opening comprises a horizontal step at a level lower than an uppermost surface of the connecting base pillar, The side wall of the insulating layer includes a lower side wall located below the horizontal step and an upper side wall located above the horizontal step. When viewed from a top view, the lower side wall and the upper side wall of the insulating layer are separated from the outermost side wall of the connecting base column. wherein the upper side wall is further away from the connection base column than the lower side wall, and The lower side wall is inclined downward toward the connection base column, and the upper side wall is inclined downward toward the connection base column.

2. The semiconductor device according to claim 1, in, The lower side wall is formed by a lower horizontal portion of the insulating layer, and the upper side wall is formed by an upper horizontal portion of the insulating layer located on the lower horizontal portion of the insulating layer.

3. The semiconductor device according to claim 1, further comprising: include: The passivation layer is located between the insulating layer and the semiconductor substrate, and comprises a side wall extending from the lower side wall of the insulating layer toward the semiconductor substrate.

4. The semiconductor device according to claim 3, in, The sidewalls of the passivation layer slope downward toward the connection base pillar.

5. The semiconductor device according to claim 3, wherein the semiconductor device further comprises: include: A connection pad is located in the semiconductor substrate below the connection base column, wherein both the lower sidewall of the insulating layer and the passivation layer overlap a portion of the connection pad.

6. The semiconductor device according to claim 1, in, The inclination degree of the lower side wall relative to the semiconductor substrate is greater than or equal to the inclination degree of the upper side wall relative to the semiconductor substrate.

7. The semiconductor device according to claim 1, in, The inclination degree of the lower side wall relative to the semiconductor substrate is smaller than the inclination degree of the upper side wall relative to the semiconductor substrate.

8. The semiconductor device according to claim 1, in, The transition from the upper sidewall of the insulating layer to the horizontal step is gradual.

9. The semiconductor device according to claim 1, further comprising: include: The passivation layer is located between the insulating layer and the semiconductor substrate, wherein the passivation layer extends on the semiconductor substrate to below the connection base column.

10. The semiconductor device according to claim 1, in, The sidewalls of the insulating layer define a pentagonal shape surrounding the connection base post.

11. The semiconductor device according to claim 1, in, The sidewalls of the insulating layer define an octagonal shape surrounding the connection base post.

12. The semiconductor device according to claim 1, in, The horizontal step includes a first horizontal step, and the semiconductor device further includes a second horizontal step located in the upper sidewall.

13. The semiconductor device according to claim 2, in, The lower horizontal portion and the upper horizontal portion include an integrally formed insulating layer.

14. The semiconductor device according to claim 1, in, The widest space between the upper side wall of the insulating layer and the connection base pillar is twice as wide as the widest space between the lower side wall of the insulating layer and the connection base pillar.

15. A semiconductor device, the semiconductor device include: Semiconductor substrate; A micro-bump structure is located on a semiconductor substrate; connecting substrate pillars, included in microbump structures; as well as An insulating layer is located on a semiconductor substrate, the insulating layer includes an opening located in the insulating layer, and the connecting base pillar extends through the opening, wherein a sidewall of the insulating layer located on a first side of the opening includes a lower sidewall and an upper sidewall, wherein the lower sidewall is inclined downward toward the connecting base pillar at a first angle relative to the semiconductor substrate, and the upper sidewall is located above the lower sidewall and is inclined downward toward the connecting base pillar at a second angle different from the first angle relative to the semiconductor substrate, When viewed from a top view, the lower side wall and the upper side wall of the insulating layer are separated from the outermost side wall of the connecting base column, and The upper side wall is farther away from the connection base column than the lower side wall.

16. The semiconductor device according to claim 15, wherein the semiconductor device further comprises: include: A horizontal step is located in the side wall of the insulating layer and between the lower side wall and the upper side wall.

17. The semiconductor device according to claim 15, in, The first angle is greater than the second angle.

18. The semiconductor device according to claim 15, in, The connecting base column includes a first connecting base column, the opening includes a first opening, the sidewall of the insulating layer includes a first sidewall, and the semiconductor device further includes: A second connection base column is separated from the first connection base column on the semiconductor substrate, wherein the insulating layer includes a second opening, the second connection base column extends through the second opening, and the second opening is formed by a second sidewall of the insulating layer opposite to the first sidewall of the insulating layer.

19. The semiconductor device according to claim 18, in, The second sidewall includes a lower sidewall and an upper sidewall, wherein the lower sidewall of the second sidewall is inclined downward toward the second connection base column at a first angle relative to the semiconductor substrate, and the upper sidewall of the second sidewall is located on the lower sidewall and is inclined downward toward the second connection base column at a second angle relative to the semiconductor substrate, and the semiconductor device further includes: The horizontal step is located in the second side wall of the insulating layer and between the upper side wall and the lower side wall of the second side wall.

20. The semiconductor device according to claim 19, in, The transition from the upper side wall of the second side wall to the second horizontal step is gradual.

21. A semiconductor device, the semiconductor device include: Semiconductor packaging motherboard; Processor chip, located on the semiconductor package motherboard; An interposer is located between the processor chip and the semiconductor package motherboard, and the processor chip is directly mounted on the interposer; a buffer chip mounted directly on the interposer and spaced apart from the processor chip, the buffer chip comprising: a first connection base post located on the buffer chip, the first connection base post having a first aspect ratio; and an insulating layer located on the buffer chip, the insulating layer comprising an opening located in the insulating layer, the first connection base post extending through the opening, wherein a sidewall of the insulating layer defining the opening comprises a horizontal step located at a level recessed relative to a portion of the insulating layer protruding at a maximum distance from the buffer chip; and A high bandwidth dynamic random access memory chip is mounted on the buffer chip, the high bandwidth dynamic random access memory chip comprising a second connection matrix pillar having a second aspect ratio lower than the first aspect ratio, The sidewall of the insulating layer includes a first sidewall located above the horizontal step and close to the high bandwidth dynamic random access memory chip and a second sidewall located below the horizontal step and away from the high bandwidth dynamic random access memory chip. When viewed from a top view, the first side wall and the second side wall of the insulating layer are both separated from the outermost side wall of the first connecting base column. The second side wall is further away from the first connection base column than the first side wall, and The first side wall is inclined toward the first connection base column, and the second side wall is inclined toward the first connection base column.

22. The semiconductor device according to claim 21, in, The widest space between the second sidewall of the insulating layer and the first connection base pillar is twice as wide as the widest space between the first sidewall of the insulating layer and the first connection base pillar.

23. The semiconductor device according to claim 21, in, The height of the first connecting base column is higher than that of the second connecting base column, and the width of the first connecting base column is greater than that of the second connecting base column.

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