Semiconductor device with negative capacitance using ferroelectric material

Abstract

A semiconductor device includes: a substrate, the substrate includes a first region and a second region; a first interface layer, the first interface layer is arranged on the substrate in the first region and has a first thickness; a second interface layer, the second interface layer is arranged on the substrate in the second region, wherein the second interface layer includes a second thickness less than the first thickness; a first gate insulating layer, the first gate insulating layer is arranged on the first interface layer and includes a first ferroelectric material layer; a second gate insulating layer, the second gate insulating layer is arranged on the second interface layer; a first gate electrode, the first gate electrode is arranged on the first gate insulating layer; and a second gate electrode, the second gate electrode is arranged on the second gate insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0078743 filed on Jul. 6, 2018, and Korean Patent Application No. 10-2019-0001700 filed on Jan. 7, 2019, both of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a transistor having a negative capacitance (NC) using a ferroelectric material. Background Art

[0004] After the development of the metal oxide semiconductor field effect transistor (MOSFET), the integration density of integrated circuits has continued to increase. For example, the integration density of integrated circuits (e.g., the total number of transistors per unit chip area) doubles every two years. To increase the integration density of integrated circuits, the size of individual transistors has continued to decrease. In addition, semiconductor technology has emerged to improve the performance of miniaturized transistors.

[0005] Such semiconductor technologies may include high-k metal gate (HKMG) technology that improves gate capacitance and reduces leakage current, and short channel effect (SCE) fin field effect transistor (FET) technology that can reduce the effect of drain voltage on the potential of the channel region.

[0006] However, the low drive voltage of transistors has not increased much compared to the miniaturization of transistor size. Therefore, the power density of complementary metal oxide semiconductor (CMOS) transistors has increased exponentially. To reduce the power density, the drive voltage can be reduced. However, because the physical operating characteristics of silicon-based MOSFETs are based on heat dissipation, it may be difficult to achieve very low supply voltages. Summary of the invention

[0007] According to an exemplary embodiment conceived in the present invention, a semiconductor device includes: a substrate, the substrate including a first region and a second region; a first interface layer, the first interface layer is arranged on the substrate in the first region and has a first thickness; a second interface layer, the second interface layer is arranged on the substrate in the second region, wherein the second interface layer includes a second thickness less than the first thickness; a first gate insulation layer, the first gate insulation layer is arranged on the first interface layer and includes a first ferroelectric material layer; a second gate insulation layer, the second gate insulation layer is arranged on the second interface layer; a first gate electrode, the first gate electrode is arranged on the first gate insulation layer; and a second gate electrode, the second gate electrode is arranged on the second gate insulation layer.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate, which includes a first region and a second region; a first gate structure, which is arranged on the substrate in the first region, wherein the first gate structure includes a first gate stack having a first width and a first gate spacer arranged on the sidewall of the first gate stack, wherein the first gate stack includes a first gate insulation layer, and the first gate insulation layer includes a first ferroelectric material layer; and a second gate structure, which is arranged on the substrate in the second region, wherein the second gate structure includes a second gate stack having a second width smaller than the first width and a second gate spacer arranged on the sidewall of the second gate stack.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including an input / output (I / O) region and a logic region; a first negative capacitance field effect transistor (NCFET) formed in the I / O region and including a first ferroelectric material layer; and a first transistor formed in the logic region and including a first gate insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure and its many attendant aspects will be more fully appreciated and more readily understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a layout diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0012] Figure 2 An exemplary embodiment according to the present inventive concept is shown. Figure 1 Cross-sectional views taken along lines AA, BB and CC;

[0013] Figure 3 An exemplary embodiment according to the present inventive concept is shown. Figure 1 A cross-sectional view taken along lines DD, EE and FF;

[0014] Figure 4 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0015] Figure 5 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0016] Figure 6 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0017] Figure 7 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0018] Figure 8 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0019] Fig. 9 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0020] Fig.10 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0021] Fig.11 is a layout diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept; and

[0022] Fig.12 is an exemplary embodiment according to the inventive concept. Fig.11 A cross-sectional view taken along line DD. DETAILED DESCRIPTION

[0023] Although the drawings related to the semiconductor device according to the exemplary embodiment of the present invention illustrate a fin transistor (FinFET) or a planar transistor including a channel region having a fin-shaped pattern, the present invention is not limited thereto. The semiconductor device according to the exemplary embodiment of the present invention may be applied to a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor. In addition, the semiconductor device according to the exemplary embodiment of the present invention may be applied to a planar transistor.

[0024] Figure 1 is a layout diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 2 An exemplary embodiment according to the present inventive concept is shown. Figure 1 Cross-sectional views taken along lines AA, BB and CC. Figure 3 An exemplary embodiment according to the present inventive concept is shown. Figure 1 Cross-sectional view taken along lines DD, EE and FF.

[0025] refer to Figures 1 to 3 , a semiconductor device according to an exemplary embodiment of the inventive concept includes a first transistor 101 , a second transistor 201 , and a third transistor 301 formed on a substrate 100 .

[0026] The substrate 100 may include a first region I, a second region II, and a third region III.

[0027] For example, the first region I of the substrate 100 may be an input / output (I / O) region, the second region II of the substrate 100 may be a logic region, and the third region III of the substrate 100 may be a memory region, such as a static random access memory (SRAM) region.

[0028] In one example, the first region I of the substrate 100 is an I / O region, and the second and third regions II and III of the substrate 100 may be logic regions. The second and third regions II and III of the substrate 100 may be regions in which transistors of different conductivity types are formed.

[0029] For example, the substrate 100 may be bulk silicon or silicon on insulator (SOI). In addition, the substrate 100 may be a silicon substrate, or may include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide and / or gallium antimonide, but the inventive concept is not limited thereto.

[0030] The first transistor 101 may be formed in a first region I of the substrate 100, the second transistor 201 may be formed in a second region II of the substrate 100, and the third transistor 301 may be formed in a third region III of the substrate 100. Each of the first transistor 101, the second transistor 201, and the third transistor 301 may be a fin transistor (finFET) using a three-dimensional channel.

[0031] The first transistor 101 may be formed in a region where a first fin pattern 110 extending in the first direction X1 and a first gate electrode 120 extending in the second direction Y1 intersect each other. The second transistor 201 may be formed in a region where a second fin pattern 210 extending in the third direction X2 and a second gate electrode 220 extending in the fourth direction Y2 intersect each other. The third transistor 301 may be formed in a region where a third fin pattern 310 extending in the fifth direction X3 and a third gate electrode 320 extending in the sixth direction Y3 intersect each other.

[0032] In the semiconductor device according to the exemplary embodiment of the inventive concept, the first transistor 101 may be a negative capacitance (NC) FET using a negative capacitor. Each of the second transistor 201 and the third transistor 301 may not be a NCFET.

[0033] Here, the negative capacitor is a capacitor having negative capacitance, and capacitance can be increased by connecting the negative capacitor in series with the positive capacitor.

[0034] The first transistor 101 as a NCFET may include an insulating layer having ferroelectric characteristics. The first transistor 101 may have a subthreshold swing (SS) of less than about 60 mV / dec at about room temperature.

[0035] The first transistor 101 may include a first fin pattern 110, a first gate structure 116, and a first source / drain region 150. The first gate structure 116 may include a first gate spacer 140 and a first gate stack 115. The first gate stack 115 may include a first interface layer 130, a first ferroelectric material layer 125, and a first gate electrode 120.

[0036] The second transistor 201 may include a second fin pattern 210, a second gate structure 216, and a second source / drain region 250. The second gate structure 216 may include a second gate spacer 240 and a second gate stack 215. The second gate stack 215 may include a second interface layer 230, a second high dielectric constant (high-k) insulating layer 235, and a second gate electrode 220. For example, the high dielectric constant may be a dielectric constant at least as high as that of silicon oxide.

[0037] The third transistor 301 may include a third fin pattern 310, a third gate structure 316, and a third source / drain region 350. The third gate structure 316 may include a third gate spacer 340 and a third gate stack 315. The third gate stack 315 may include a third interface layer 330, a third high-k insulating layer 335, and a third gate electrode 320.

[0038] The first fin pattern 110, the second fin pattern 210, and the third fin pattern 310 may be formed on the substrate 100. For example, the first fin pattern 110, the second fin pattern 210, and the third fin pattern 310 may protrude from the substrate 100.

[0039] The first fin pattern 110, the second fin pattern 210, and the third fin pattern 310 may be part of the substrate 100, or may include an epitaxial layer grown from the substrate 100. Each of the first fin pattern 110, the second fin pattern 210, and the third fin pattern 310 may include silicon and / or germanium, which are semiconductor materials. Each of the first fin pattern 110, the second fin pattern 210, and the third fin pattern 310 may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0040] For example, the IV-IV compound semiconductor may be a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), and / or a compound obtained by doping the above compounds with a group IV element. For example, the III-V compound semiconductor may be a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements.

[0041] A field insulating layer 105 may be formed on the substrate 100 . The field insulating layer 105 may be disposed on at least a portion of sidewalls of the first fin pattern 110 , the second fin pattern 210 , and the third fin pattern 310 .

[0042] Upper surfaces of the first fin pattern 110, the second fin pattern 210, and the third fin pattern 310 may protrude upward from an upper surface of the field insulation layer 105. The field insulation layer 105 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0043] An interlayer insulating layer 190 may be disposed on the substrate 100 . A first gate trench 140 t , a second gate trench 240 t , and a third gate trench 340 t may be formed in the interlayer insulating layer 190 .

[0044] The first gate trench 140t may be formed by the first gate spacer 140. For example, the first gate spacer 140 may be a side surface of the first gate trench 140t. The second gate trench 240t may be formed by the second gate spacer 240. The third gate trench 340t may be formed by the third gate spacer 340.

[0045] For example, each of the first gate spacer 140 , the second gate spacer 240 , and the third gate spacer 340 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), and silicon oxycarbonitride (SiOCN).

[0046] For example, the interlayer insulating layer 190 may include silicon oxide, silicon nitride, silicon oxynitride, flowable oxide (FOX), Tosz (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material or a combination thereof. However, the inventive concept is not limited thereto.

[0047] The first gate stack 115 may be formed in the first gate trench 140t. The second gate stack 215 may be formed in the second gate trench 240t. The third gate stack 315 may be formed in the third gate trench 340t. The first gate spacer 140, the second gate spacer 240, and the third gate spacer 340 may be formed on the sidewalls of the first gate stack 115, the second gate stack 215, and the third gate stack 315, respectively.

[0048] The first gate stack 115, the second gate stack 215, and the third gate stack 315 may fill the first gate trench 140t, the second gate trench 240t, and the third gate trench 340t, respectively. For example, the first gate stack 115, the second gate stack 215, and the third gate stack 315 may completely fill the first gate trench 140t, the second gate trench 240t, and the third gate trench 340t, respectively. Although the upper surfaces of the first gate stack 115, the second gate stack 215, and the third gate stack 315 are shown as being flush with the upper surface of the interlayer insulating layer 190, the inventive concept is not limited thereto. For example, the upper surfaces of the first gate stack 115, the second gate stack 215, and the third gate stack 315 may be located below the upper surface of the interlayer insulating layer 190, or may protrude beyond the upper surface of the interlayer insulating layer 190.

[0049] In addition, a capping pattern may be formed on the first gate stack 115, the second gate stack 215, and the third gate stack 315 to fill a portion of the first gate trench 140t, the second gate trench 240t, and the third gate trench 340t, respectively. In this case, the upper surface of the capping pattern may be flush with the upper surface of the interlayer insulating layer 190. However, the inventive concept is not limited thereto.

[0050] In a semiconductor device according to an exemplary embodiment of the inventive concept, a width W11 of the first gate stack 115 in the first direction X1, a width W12 of the second gate stack 215 in the third direction X2, and a width W13 of the third gate stack 315 in the fifth direction X3 may be substantially the same.

[0051] The first interface layer 130 may be formed on the substrate 100 . For example, the first interface layer 130 may be formed on the first fin pattern 110 .

[0052] The first interface layer 130 may be formed in the first gate trench 140t. For example, the first interface layer 130 may be formed along a bottom surface of the first gate trench 140t.

[0053] The first ferroelectric material layer 125 may be formed on the first interface layer 130. For example, the first ferroelectric material layer 125 may contact the first interface layer 130.

[0054] The first ferroelectric material layer 125 may be formed along the inner wall of the first gate trench 140t. For example, the first ferroelectric material layer 125 may be formed along the sidewall and bottom surface of the first gate trench 140t. For example, the first ferroelectric material layer 125 may contact the first gate spacer 140.

[0055] The first ferroelectric material layer 125 may have ferroelectric properties. The first ferroelectric material layer 125 may be thick enough to have ferroelectric properties. The first ferroelectric material layer 125 may have a thickness of, for example, about 3 nm to about 10 nm, but the inventive concept is not limited thereto. Since the thickness at which each ferroelectric material exhibits ferroelectric properties may be different, the thickness of the first ferroelectric material layer 125 may vary depending on the ferroelectric material.

[0056] At least one of the first interface layer 130 or the first ferroelectric material layer 125 may be a gate insulating layer of the first transistor 101. The gate insulating layer of the first transistor 101 may have ferroelectric characteristics.

[0057] The second interface layer 230 may be formed on the substrate 100 . For example, the second interface layer 230 may be formed on the second fin pattern 210 .

[0058] The second interface layer 230 may be formed in the second gate trench 240t. For example, the second interface layer 230 may be formed along a bottom surface of the second gate trench 240t.

[0059] The second high-k insulating layer 235 may be formed on the second interface layer 230. For example, the second high-k insulating layer 235 may contact the second interface layer 230.

[0060] The second high-k insulating layer 235 may be formed along the inner wall of the second gate trench 240t. For example, the second high-k insulating layer 235 may be formed along the sidewall and bottom surface of the second gate trench 240t. For example, the second high-k insulating layer 235 may contact the second gate partition wall 240. The second high-k insulating layer 235 may not have ferroelectric properties.

[0061] At least one of the second interface layer 230 or the second high-k insulating layer 235 may be a gate insulating layer of the second transistor 201. The gate insulating layer of the second transistor 201 may not have ferroelectric characteristics.

[0062] The third interface layer 330 may be formed on the substrate 100 . For example, the third interface layer 330 may be formed on the third fin pattern 310 .

[0063] The third interface layer 330 may be formed in the third gate trench 340t. The third interface layer 330 may be formed along a bottom surface of the third gate trench 340t.

[0064] The third high-k insulating layer 335 may be formed on the third interface layer 330. The third high-k insulating layer 335 may make contact with the third interface layer 330.

[0065] The third high-k insulating layer 335 may be formed along the inner wall of the third gate trench 340t. For example, the third high-k insulating layer 335 may be formed along the sidewall and bottom surface of the third gate trench 340t. For example, the third high-k insulating layer 335 may contact the third gate partition wall 340. The third high-k insulating layer 335 may not have ferroelectric properties.

[0066] Each of the third interface layer 330 and the third high-k insulating layer 335 may be a gate insulating layer of the third transistor 301. The gate insulating layer of the third transistor 301 may not have a ferroelectric property.

[0067] In the semiconductor device according to an exemplary embodiment of the inventive concept, the thickness t11 of the first interface layer 130 is greater than the thickness t12 of the second interface layer 230 and the thickness t13 of the third interface layer 330 .

[0068] Although the first interface layer 130, the second interface layer 230, and the third interface layer 330 are illustrated as being formed only on the bottom surfaces of the first gate trench 140t, the second gate trench 240t, and the third gate trench 340t, respectively, the inventive concept is not limited thereto. According to the manufacturing method, the first interface layer 130, the second interface layer 230, and the third interface layer 330 may be formed on the sidewalls of the first gate trench 140t, the second gate trench 240t, and the third gate trench 340t, respectively. According to the manufacturing method, each of the first interface layer 130, the second interface layer 230, and the third interface layer 330 may be disposed on the upper surface of the field insulation layer 105. For example, each of the first interface layer 130, the second interface layer 230, and the third interface layer 330 may extend along the upper surface of the field insulation layer 105.

[0069] For example, each of the first interface layer 130 , the second interface layer 230 , and the third interface layer 330 may include a silicon oxide layer.

[0070] For example, the first ferroelectric material layer 125 may include at least one of hafnium oxide, hafnium zirconium oxide, zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead titanium zirconium oxide. Here, hafnium zirconium oxide may be obtained by doping hafnium oxide with zirconium (Zr), or may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0071] The first ferroelectric material layer 125 may further include doping elements doped with the above materials. The doping element may be at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and / or tin (Sn).

[0072] For example, each of the second high-k insulating layer 235 and the third high-k insulating layer 335 may include at least one of the following: hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and / or lead zinc niobate.

[0073] In an exemplary embodiment of the present inventive concept, each of the second high-k insulating layer 235 and the third high-k insulating layer 335 may include the same material as the first ferroelectric material layer 125. Even if each of the second high-k insulating layer 235 and the third high-k insulating layer 335 includes the same material as the first ferroelectric material layer 125, the second high-k insulating layer 235 and the third high-k insulating layer 335 may not have ferroelectric properties. In this case, the thickness of each of the second high-k insulating layer 235 and the third high-k insulating layer 335 may be less than the thickness of the first ferroelectric material layer 125.

[0074] The first gate electrode 120 may be formed on the first ferroelectric material layer 125. The first gate electrode 120 may be disposed in the first gate trench 140t.

[0075] The second gate electrode 220 may be formed on the second high-k insulating layer 235. The second gate electrode 220 may be disposed in the second gate trench 240t.

[0076] The third gate electrode 320 may be formed on the third high-k insulating layer 335. The third gate electrode 320 may be disposed in the third gate trench 340t.

[0077] For example, the first gate electrode 120, the second gate electrode 220, and the third gate electrode 320 may include at least one of the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), titanium aluminum nitride (TiAlN ... (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and / or combinations thereof.

[0078] The first source / drain region 150 may be formed on at least one side of the first gate structure 116. The second source / drain region 250 may be formed on at least one side of the second gate structure 216. The third source / drain region 350 may be formed on at least one side of the third gate structure 316.

[0079] For example, the first, second, and third source / drain regions 150 , 250 , and 350 may include epitaxial patterns formed on the first, second, and third fin patterns 110 , 210 , and 310 , respectively.

[0080] Figure 4 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figures 1 to 3 The descriptions are different, so any redundant descriptions will be omitted.

[0081] refer to Figure 4 In the semiconductor device according to the exemplary embodiment of the inventive concept, the second gate stack 215 may include a second ferroelectric material layer 225 .

[0082] The second gate stack 215 may include a second ferroelectric material layer 225 instead of the second high-k insulating layer 235. The second transistor 201 including the second gate stack 215 including the second ferroelectric material layer 225 may be a NCFET.

[0083] The second ferroelectric material layer 225 may be formed on the second interface layer 230. For example, the second ferroelectric material layer 225 may contact the second interface layer 230.

[0084] The second ferroelectric material layer 225 may be formed along the inner wall of the second gate trench 240t. For example, the second ferroelectric material layer 225 may be formed along the sidewall and bottom surface of the second gate trench 240t. For example, the second ferroelectric material layer 225 may contact the second gate partition wall 240.

[0085] The second ferroelectric material layer 225 may have ferroelectric properties. The second ferroelectric material layer 225 may be thick enough to have ferroelectric properties.

[0086] Each of the second interface layer 230 and the second ferroelectric material layer 225 may be a gate insulating layer of the second transistor 201. The gate insulating layer of the second transistor 201 may have ferroelectric characteristics.

[0087] The first transistor 101 of the first region I and the second transistor 201 of the second region II may perform different functions. For example, the first transistor 101 may be formed in an I / O region, and the second transistor 201 may be formed in a logic region.

[0088] For example, the first ferroelectric material layer 125 included in the first transistor 101 formed in the I / O region may include a ferroelectric material having suitable on-current characteristics. The second ferroelectric material layer 225 included in the second transistor 201 formed in the logic region may include a ferroelectric material having appropriate subthreshold swing characteristics.

[0089] For example, when NCFETs are respectively formed in regions having different functions, the ferroelectric material layers included in the respective NCFETs may include materials different from each other. For example, the first ferroelectric material layer 125 may include a material different from that of the second ferroelectric material layer 225 .

[0090] Figure 5 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 4 The descriptions are different, so any redundant descriptions will be omitted.

[0091] refer to Figure 5 In the semiconductor device according to the exemplary embodiment of the inventive concept, the third gate stack 315 may include a third ferroelectric material layer 325 .

[0092] The third gate stack 315 may include a third ferroelectric material layer 325 instead of the third high-k insulating layer 335. The third transistor 301 including the third gate stack 315 including the third ferroelectric material layer 325 may be a NCFET.

[0093] The third ferroelectric material layer 325 may be formed on the third interface layer 330. For example, the third ferroelectric material layer 325 may contact the third interface layer 330.

[0094] The third ferroelectric material layer 325 may be formed along the inner wall of the third gate trench 340t. For example, the third ferroelectric material layer 325 may be formed along the sidewall and bottom surface of the third gate trench 340t. For example, the third ferroelectric material layer 325 may contact the third gate partition wall 340.

[0095] The third ferroelectric material layer 325 may have ferroelectric properties. The third ferroelectric material layer 325 may be thick enough to have ferroelectric properties.

[0096] Each of the third interface layer 330 and the third ferroelectric material layer 325 may be a gate insulating layer of the third transistor 301. The gate insulating layer of the third transistor 301 may have ferroelectric characteristics.

[0097] Figure 6 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figures 1 to 3 The descriptions are different, so any redundant descriptions will be omitted.

[0098] refer to Figure 6 In the semiconductor device according to an exemplary embodiment of the inventive concept, the first gate stack 115 may further include a first insertion conductive layer 121 .

[0099] The first gate stack 115 may include a first interface layer 130 , a first insertion conductive layer 121 , a first ferroelectric material layer 125 , and a first gate electrode 120 .

[0100] The first insertion conductive layer 121 may be formed on the first interface layer 130. The first insertion conductive layer 121 may be formed along the sidewall and bottom surface of the first gate trench 140t. For example, the first insertion conductive layer 121 may be disposed between the first gate spacer 140 and the first ferroelectric material layer 125.

[0101] The first ferroelectric material layer 125 may be formed on the first insertion conductive layer 121. For example, the first ferroelectric material layer 125 may be formed along the contour of the first inserted conductive layer 121. For example, the first ferroelectric material layer 125 may be formed on the inner sidewall and the inner lower surface of the first insertion conductive layer 121.

[0102] For example, the first insertion conductive layer 121 may include at least one of metal, at least two metal alloys, metal nitride, metal silicide, metal carbide, metal carbonitride, nitride of metal alloy, carbonitride of metal alloy, and / or doped polysilicon.

[0103] Figure 7 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figures 1 to 3 The descriptions are different, so any redundant descriptions will be omitted.

[0104] refer to Figure 7 In the semiconductor device according to the exemplary embodiment of the inventive concept, the first gate stack 115 may further include a first high-k insulating layer 135 and a first insertion conductive layer 121 .

[0105] The first high-k insulating layer 135 and the first insertion conductive layer 121 may be formed between the first interface layer 130 and the first ferroelectric material layer 125 .

[0106] The first high-k insulating layer 135 may be formed on the first interface layer 130. The first high-k insulating layer 135 may be formed along sidewalls and a bottom surface of the first gate trench 140t.

[0107] The first insertion conductive layer 121 may be formed on the first high-k insulating layer 135. The first insertion conductive layer 121 may be formed along the sidewall and bottom surface of the first gate trench 140t.

[0108] The first ferroelectric material layer 125 may be formed on the first insertion conductive layer 121 .

[0109] Figure 8 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 4 The descriptions are different, so any redundant descriptions will be omitted.

[0110] refer to Figure 8 In the semiconductor device according to the exemplary embodiment of the inventive concept, the first gate stack 115 may further include a first insertion conductive layer 121 . The second gate stack 215 may further include a second insertion conductive layer 221 .

[0111] The first insertion conductive layer 121 may be formed between the first interface layer 130 and the first ferroelectric material layer 125 .

[0112] The first insertion conductive layer 121 may be formed on the first interface layer 130. The first insertion conductive layer 121 may be formed along sidewalls and a bottom surface of the first gate trench 140t.

[0113] The first ferroelectric material layer 125 may be formed on the first insertion conductive layer 121 .

[0114] The second penetration conductive layer 221 may be formed between the second interface layer 230 and the second ferroelectric material layer 225 .

[0115] The second insertion conductive layer 221 may be formed on the second interface layer 230. The second insertion conductive layer 221 may be formed along the sidewall and bottom surface of the second gate trench 240t. For example, the second insertion conductive layer 221 may be disposed between the second gate spacer 240 and the second ferroelectric material layer 225.

[0116] The second ferroelectric material layer 225 may be formed on the second insertion conductive layer 221 .

[0117] Fig. 9 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 8 The descriptions are different, so any redundant descriptions will be omitted.

[0118] refer to Fig. 9 In the semiconductor device according to the exemplary embodiment of the inventive concept, the first gate stack 115 may further include a first high-k insulating layer 135 . The second gate stack 215 may further include a second high-k insulating layer 235 .

[0119] The first high-k insulating layer 135 may be formed between the first interface layer 130 and the first insertion conductive layer 121. For example, the first high-k insulating layer 135 is formed between the first insertion conductive layer 121 and the first gate spacer 140. The first high-k insulating layer 135 may be formed along the sidewall and bottom surface of the first gate trench 140t.

[0120] The second high-k insulating layer 235 may be formed between the second interface layer 230 and the second insertion conductive layer 221. For example, the second high-k insulating layer 235 is formed between the second insertion conductive layer 221 and the second gate spacer 240. The second high-k insulating layer 235 may be formed along the sidewalls and bottom surface of the second gate trench 240t.

[0121] Fig.10 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figures 1 to 3 The descriptions are different, so any redundant descriptions will be omitted.

[0122] refer to Fig.10 In the semiconductor device according to an exemplary embodiment of the inventive concept, a width W11 of the first gate stack 115 in the first direction X1 is different from a width W12 of the second gate stack 215 in the third direction X2 and a width W13 of the third gate stack 315 in the fifth direction X3.

[0123] The width W11 of the first gate stack 115 in the first direction X1 is greater than the width W12 of the second gate stack 215 in the third direction X2. The width W11 of the first gate stack 115 in the first direction X1 is greater than the width W13 of the third gate stack 315 in the fifth direction X3.

[0124] Fig.11 is a layout diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig.12 is an exemplary embodiment according to the inventive concept. Fig.11 A cross-sectional view taken along line DD.

[0125] refer to Fig.11 and Fig.12 , in the semiconductor device according to an exemplary embodiment of the inventive concept, the first transistor 101 may be a planar transistor.

[0126] The active region 111 may be a field insulating layer 105 .

[0127] A first gate electrode 120 may be formed on the substrate 100 across the active region 111 .

[0128] According to an exemplary embodiment of the inventive concept, a semiconductor device may include a negative capacitance field effect transistor (NCFET) using a gate insulating layer having ferroelectric characteristics to improve performance of the device.

[0129] Although the present inventive concept has been described with reference to exemplary embodiments thereof, persons skilled in the art will recognize that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept.

Claims

1. A semiconductor device, comprising: a substrate comprising a first region and a second region; a first interface layer, the first interface layer being disposed on the substrate in the first region and having a first thickness; a second interface layer disposed on the substrate in the second region, wherein the second interface layer has a second thickness less than the first thickness; a first gate insulating layer, the first gate insulating layer being disposed on the first interface layer and comprising a first ferroelectric material layer; a second gate insulating layer, wherein the second gate insulating layer is disposed on the second interface layer; a first gate electrode, the first gate electrode being disposed on the first gate insulating layer; as well as a second gate electrode, the second gate electrode being disposed on the second gate insulating layer; The first area is an input / output area, and the second area is a logic area or a memory area.

2. The semiconductor device according to claim 1, wherein The first interface layer contacts the first gate insulating layer.

3. The semiconductor device according to claim 1, further comprising: An inserted conductive layer is disposed between the first interface layer and the first gate insulating layer.

4. The semiconductor device according to claim 1, wherein: The second gate insulating layer includes a second ferroelectric material layer.

5. The semiconductor device according to claim 4, wherein: The first interface layer contacts the first gate insulating layer, and Wherein, the second interface layer is in contact with the second gate insulating layer.

6. The semiconductor device according to claim 4, further comprising: a first insertion conductive layer, the first insertion conductive layer being disposed between the first interface layer and the first gate insulating layer; as well as A second insertion conductive layer is disposed between the second interface layer and the second gate insulating layer.

7. The semiconductor device according to claim 4, wherein: The first ferroelectric material layer is different from the second ferroelectric material layer.

8. The semiconductor device according to claim 1, wherein The first gate insulating layer and the second gate insulating layer include the same material.

9. A semiconductor device comprising: a substrate comprising a first region and a second region; a first gate structure, the first gate structure being disposed on the substrate in the first region, wherein the first gate structure comprises a first gate stack having a first width and a first gate spacer disposed on a sidewall of the first gate stack, wherein the first gate stack comprises a first gate insulating layer, and the first gate insulating layer comprises a first ferroelectric material layer; as well as A second gate structure is disposed on the substrate in the second region, wherein the second gate structure includes a second gate stack having a second width smaller than the first width and a second gate spacer disposed on a sidewall of the second gate stack.

10. The semiconductor device according to claim 9, wherein The second gate stack includes a second gate insulating layer, and The second gate insulating layer includes a material different from that of the first gate insulating layer.

11. The semiconductor device according to claim 10, wherein: The first gate stack includes a first interface layer disposed between the first gate insulating layer and the substrate, The second gate stack includes a second interface layer disposed between the second gate insulating layer and the substrate. Wherein, the first gate insulating layer is in contact with the first interface layer, and Wherein, the second gate insulating layer is in contact with the second interface layer.

12. The semiconductor device according to claim 10, wherein: The first gate stack further includes an intervening conductive layer disposed between the first gate insulating layer and the substrate.

13. The semiconductor device according to claim 9, wherein: The second gate stack includes a second gate insulating layer, and Wherein, the second gate insulating layer includes a second ferroelectric material layer.

14. The semiconductor device according to claim 13, wherein: The first gate stack includes a first interface layer disposed between the first gate insulating layer and the substrate, The second gate stack includes a second interface layer disposed between the second gate insulating layer and the substrate. Wherein, the first gate insulating layer is in contact with the first interface layer, and Wherein, the second gate insulating layer is in contact with the second interface layer.

15. The semiconductor device according to claim 13, wherein: The first gate stack further includes a first insertion conductive layer disposed between the first gate insulating layer and the substrate, and The second gate stack further includes a second inserted conductive layer disposed between the second gate insulating layer and the substrate.

16. A semiconductor device comprising: A substrate, the substrate comprising an input / output I / O area and a logic area; a first negative capacitance field effect transistor NCFET, which is formed in the I / O region and includes a first ferroelectric material layer and a first interface layer; as well as a first transistor, the first transistor being formed in the logic region and comprising a first gate insulating layer and a second interface layer, wherein the first interface layer is disposed on the substrate and has a first thickness, and the first ferroelectric material layer is disposed on the first interface layer, and The second interface layer is disposed on the substrate and has a second thickness that is smaller than the first thickness, and the first gate insulating layer is disposed on the second interface layer.

17. The semiconductor device according to claim 16, wherein: The first transistor is a second NCFET, and Wherein, the first gate insulating layer includes a second ferroelectric material layer.

18. The semiconductor device according to claim 17, wherein: The substrate includes a memory region, wherein a second transistor including a second gate insulating layer is formed in the memory region, and Wherein, the second gate insulating layer includes a first high dielectric constant insulating layer.

19. The semiconductor device according to claim 16, wherein: The first gate insulating layer includes a second high dielectric constant insulating layer.

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