LED display screen blanking method, circuit and chip

Abstract

The LED display screen blanking method provided by the present invention comprises a blanking enable module generating a blanking enable signal according to an external display clock signal and a command signal, and transmitting the blanking enable signal to a combinational logic circuit; the combinational logic circuit receives output data of each channel in an LED chip, processes the output data and the blanking enable signal, obtains a blanking pulse signal of each channel in the LED chip, and transmits the blanking pulse signal to an output drive circuit module; when a channel in an LED chip is closed, the output drive circuit module uses the blanking pulse signal to pre-charge the parasitic between the column and the row in the channel. The method improves the display effect and meets the high image quality requirements.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a method, circuit and chip for blanking an LED display screen. Background Art

[0002] LED scanning screen has many advantages such as high grayscale, wide viewing angle, low operating voltage, low power consumption, long life and customizable shape. Therefore, it is widely used in commercial advertising, information release and other fields. However, in the commonly used LED display screen, there are two defects in the following situations (see Figure 1 , taking ROW1 and ROW2 as examples):

[0003] ① When the LEDs of the two rows of display screens ROW1 and ROW2 need to be turned on, after ROW1 is turned on, the row voltage drops slowly. When the row scan signal of ROW2 arrives, the column signal is pulled down, so ROW1 will appear dark and produce an upper ghost.

[0004] ② When ROW1 of the upper and lower rows of display LEDs needs to be turned on and ROW2 needs to be turned off, after ROW1 is turned on, ROW2 rises slowly due to the slow rise of the column voltage. When the row scan signal of ROW1 arrives, ROW2 is found to be dim and a lower ghosting situation occurs.

[0005] In the current mainstream LED display control system, the LED grayscale brightness is usually dispersed into different subframes, and the accumulated lighting time of the LED lamp in each frame cycle is used to express the grayscale and display the image. In the entire frame cycle, the accumulated effective lighting time of the LED lamp corresponds to the grayscale data of the corresponding pixel.

[0006] In traditional blanking technology, at the end of each line display scan, a fixed pulse blanking is performed on the scanning array to achieve the purpose of removing ghost images. Figure 2 However, in each row scan display, the column scan driver chip is not fully turned on. There is a certain delay when the column scan driver chip is pulled up and turned off, which leads to a certain error between the LED display brightness and the actual grayscale data. The greater the display array parasitic, the greater the error. With the increasing requirements for the quality of LED display images, this error can no longer be ignored. Summary of the invention

[0007] In view of the defects in the prior art, the LED display screen blanking method, circuit and chip provided by the present invention improve the display effect and meet the high image quality requirements.

[0008] In a first aspect, a method for blanking an LED display screen comprises the following steps:

[0009] The blanking enable module generates a blanking enable signal according to an external display clock signal and an instruction signal, and transmits the blanking enable signal to a combinational logic circuit;

[0010] The combinational logic circuit receives the output data of each channel in the LED chip, processes the output data and the blanking enable signal, obtains the blanking pulse signal of each channel in the LED chip, and transmits the blanking pulse signal to the output drive circuit module;

[0011] When a channel in the LED chip is closed, the output drive circuit module uses the blanking pulse signal to pre-charge the parasitic between the columns and rows in the channel.

[0012] Preferably, the blanking enable module generates a blanking enable signal according to an external display clock signal and an external command signal, specifically comprising:

[0013] The blanking enable module synchronizes the row counter inside the LED chip according to the command signal, and then counts the external display clock signal to obtain the row display on period and off period in the LED chip to form the blanking enable signal.

[0014] Preferably, the combinational logic circuit includes a shift register, an instruction decoding circuit, a memory and a PWM data segmentation processing module;

[0015] The combinational logic circuit receives output data of each channel in the LED chip, processes the output data and the blanking enable signal, obtains a blanking pulse signal of each channel in the LED chip, and transmits the blanking pulse signal to the output drive circuit module, specifically comprising:

[0016] The shift register stores the written register configuration information and each row of LED grayscale data. The instruction decoding circuit writes the data in the shift register into the configuration register or the memory according to the external input signal. The instruction decoding circuit generates the instruction signal. The PWM data segmentation processing module reads the next row of LED grayscale data stored in the memory, and breaks up the next row of LED grayscale data into different grouped subframes to obtain the blanking pulse signal, which is transmitted to the output drive circuit module.

[0017] In a second aspect, a LED display screen blanking circuit includes a configuration register, a blanking enable module, a combinational logic circuit and an output drive circuit module;

[0018] Among them, the output end of the configuration register is connected to the first input end of the blanking enable module, the second input end of the blanking enable module is connected to the external display clock signal, the third input end of the blanking enable module is connected to the external command signal, the output end of the blanking enable module is connected to the first input end of the combinational logic circuit, the second input end of the combinational logic circuit is connected to the channel of the LED chip, and the output end of the combinational logic circuit is connected to the output drive circuit module.

[0019] Preferably, the output drive circuit module includes an operational amplifier OP1, an operational amplifier OP2, a field effect transistor PM1, a field effect transistor NM1 and a current source Isink;

[0020] The source of the field effect transistor PM1 is connected to a high level, the gate of the field effect transistor PM1 is connected to a line control signal, and the drain of the field effect transistor PM1 is connected to the drain of the field effect transistor NM1 through the positive light emitting diode L1;

[0021] The positive input terminal of the operational amplifier OP2 is connected to the reference voltage, the enable terminal of the operational amplifier OP2 is connected to the channel of the LED chip, the output terminal of the operational amplifier OP2 is connected to the gate of the field effect tube NM1, the source of the field effect tube NM1 is connected to the reverse input terminal of the operational amplifier OP2, the source of the field effect tube NM1 is grounded by being connected in series with the current source Isink, the node between the drain of the field effect tube NM1 and the cathode of the light emitting diode L1 is connected to the output terminal of the operational amplifier OP1, the positive input terminal of the operational amplifier OP1 is connected to the blanking voltage, the reverse input terminal of the operational amplifier OP1 is connected to its output terminal, and the enable terminal of the operational amplifier OP1 is connected to the output terminal of the combinational logic circuit.

[0022] Preferably, the combinational logic circuit includes a shift register, an instruction decoding circuit, a memory and a PWM data segmentation processing module;

[0023] Wherein, the first input terminal of the shift register is connected to an external control signal, the second input terminal of the shift register and the first input terminal of the instruction decoding circuit are connected to an external data clock signal, and the second input terminal of the instruction decoding circuit is connected to an external input signal;

[0024] The first output terminal of the shift register is connected to the instruction decoding circuit, the second output terminal of the shift register is connected to the memory, and the third output terminal of the shift register serves as the data output terminal of the circuit;

[0025] A first output terminal of the instruction decoding circuit is connected to the memory, and a second output terminal of the instruction decoding circuit is connected to the configuration register;

[0026] The multiple output terminals of the memory are respectively connected to the multiple first input terminals of the PWM data segmentation processing module;

[0027] The first output end of the configuration register is connected to the second input end of the PWM data segmentation processing module, the second output end of the configuration register and multiple output ends of the PWM data segmentation processing module are connected to the output drive circuit module, and the third input end of the PWM data segmentation processing module is connected to the external display clock signal.

[0028] Preferably, the memory includes SRAM and a cache;

[0029] The second output end of the shift register and the first output end of the instruction decoding circuit are connected to the SRAM, the output end of the SRAM is connected to the buffer, and the multiple output ends of the buffer are respectively connected to the multiple first input ends of the PWM data segmentation processing module.

[0030] In the third aspect, a LED display screen blanking chip,

[0031] It includes the LED display screen blanking circuit described in the first aspect.

[0032] It can be seen from the above technical solutions that the LED display screen blanking method, circuit and chip provided by the present invention improve the display effect and meet the high image quality requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0034] Figure 1 This is a schematic diagram of the principle of an LED display screen provided in the background technology.

[0035] Figure 2 This is a timing diagram of the traditional blanking method provided in the background technology.

[0036] Figure 3 This is a flow chart of a method for blanking an LED display screen provided in Embodiment 1 of the present invention.

[0037] Figure 4 This is a timing diagram of data blanking in combination with LED grayscale display provided in the first embodiment of the present invention.

[0038] Figure 5 This is a structural diagram of the LED display screen blanking circuit provided in the second embodiment of the present invention.

[0039] Figure 6 for Figure 5 Circuit diagram of the output drive circuit module. DETAILED DESCRIPTION

[0040] The embodiments of the technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and the protection scope of the present invention cannot be limited thereto. It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should be the common meanings understood by those skilled in the art to which the present invention belongs.

[0041] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0042] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0043] As used in this specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0044] Embodiment 1:

[0045] A method for blanking an LED display screen, see Figure 3 , including the following steps:

[0046] S1: The blanking enable module generates a blanking enable signal BK Enable according to the external display clock signal GCLK and the command signal Vsync, and transmits the blanking enable signal BK Enable to the combinational logic circuit;

[0047] Specifically, the blanking enable signal BK Enable generated by the external display clock signal GCLK in step S1 can be applied to all channels in the LED chip.

[0048] S2: The combinational logic circuit receives the output data SPWMn of each channel in the LED chip, processes the output data SPWMn and the blanking enable signal BK Enable, obtains the blanking pulse signal BKn of each channel in the LED chip, and transmits the blanking pulse signal BKn to the output drive circuit module;

[0049] Specifically, step S2 combines the output data SPWMn of the LED chip channel and performs a logic operation on it and the blanking enable signal BKEnable, thereby obtaining the blanking pulse signal BKn of the channel in the LED chip.

[0050] S3: When the channel in the LED chip is closed, the output drive circuit module uses the blanking pulse signal to perform pre-charging on the parasitic between the columns and rows in the channel.

[0051] Specifically, since the blanking pulse BKn of each channel in the LED chip is associated with its output data SPWMn, when the channel in the LED chip is closed, the parasitic between the row and the column is quickly precharged in step S3, thereby eliminating the LED brightness display error and ghosting phenomenon caused by it. This method is combined with the LED grayscale display data blanking timing diagram. Figure 4 .

[0052] The LED display screen blanking method combines LED grayscale display data to perform real-time blanking control on different channels of the LED chip, thereby improving the display effect, meeting high-quality image requirements, and solving the ghosting phenomenon of LED display screens in the prior art.

[0053] Preferably, the blanking enable module generates a blanking enable signal according to an external display clock signal and an external command signal, specifically comprising:

[0054] The blanking enable module synchronizes the row counter inside the LED chip according to the command signal Vsync, and then counts the external display clock signal GCLK to obtain the row display on period and off period in the LED chip to form the blanking enable signal BK Enable.

[0055] Specifically, the method synchronizes the internal row counter of the LED chip, counts GCLK, obtains the row display on and off periods, and generates a blanking enable signal BK Enable. After the combinational logic circuit obtains the blanking enable signal BK Enable, it performs blanking processing in combination with the output data SPWMn of each channel in the LED chip.

[0056] Preferably, the combinational logic circuit includes a shift register, an instruction decoding circuit, a memory and a PWM data segmentation processing module;

[0057] The combinational logic circuit receives output data of each channel in the LED chip, processes the output data and the blanking enable signal, obtains a blanking pulse signal of each channel in the LED chip, and transmits the blanking pulse signal to the output drive circuit module, specifically comprising:

[0058] The shift register stores the written register configuration information and each row of LED grayscale data. The instruction decoding circuit writes the data in the shift register into the configuration register or the memory according to the external input signal. The instruction decoding circuit generates the instruction signal. The PWM data segmentation processing module reads the next row of LED grayscale data stored in the memory, and breaks up the next row of LED grayscale data into different grouped subframes to obtain the blanking pulse signal, which is transmitted to the output drive circuit module.

[0059] Specifically, the method writes register configuration information and LED grayscale data into the shift register by serial shifting of an external control signal SDI and an external data clock signal DCLK. The instruction decoding circuit uses N (N is an arbitrary integer) DCLK edges contained in the high level of the external input signal LA as instructions to write the shift register data into the configuration register or the memory, and the instruction decoding circuit also generates an instruction signal Vsync signal. The PWM data segmentation processing module breaks up the LED grayscale data into different group subframes. The blanking enable module generates a blanking enable signal. The output drive circuit module realizes the blanking function and provides a drive current.

[0060] Embodiment 2:

[0061] A LED display blanking circuit, see Figure 5 , including a configuration register, a blanking enable module, a combinational logic circuit and an output drive circuit module;

[0062] Among them, the output end of the configuration register is connected to the first input end of the blanking enable module, the second input end of the blanking enable module is connected to the external display clock signal, the third input end of the blanking enable module is connected to the external command signal, the output end of the blanking enable module is connected to the first input end of the combinational logic circuit, the second input end of the combinational logic circuit is connected to the channel of the LED chip, and the output end of the combinational logic circuit is connected to the output drive circuit module.

[0063] Specifically, the blanking enable module generates a blanking enable signal BK Enable according to the external display clock signal GCLK and the command signal Vsync, and transmits it to the combinational logic circuit. The blanking enable signal BK Enable can be applied to all channels in the LED chip. The combinational logic circuit obtains the blanking pulse signal BKn of each channel in the LED chip according to the output data SPWMn of the LED chip, and transmits the blanking pulse signal BKn to the output drive circuit module; when the channel in the LED chip is closed, the output drive circuit module uses the blanking pulse signal to pre-charge the parasitic between the column and the row in the channel.

[0064] The circuit combines the LED grayscale display data to perform real-time blanking control on different channels of the LED chip, thereby improving the display effect, meeting high-quality image requirements, and solving the ghosting phenomenon of LED display screens in the prior art.

[0065] See also Figure 6 , the output drive circuit module includes an operational amplifier OP1, an operational amplifier OP2, a field effect transistor PM1, a field effect transistor NM1 and a current source Isink;

[0066] The source of the field effect transistor PM1 is connected to a high level, the gate of the field effect transistor PM1 is connected to a line control signal, and the drain of the field effect transistor PM1 is connected to the drain of the field effect transistor NM1 through the positive light emitting diode L1;

[0067] The positive input terminal of the operational amplifier OP2 is connected to the reference voltage, the enable terminal of the operational amplifier OP2 is connected to the channel of the LED chip, the output terminal of the operational amplifier OP2 is connected to the gate of the field effect tube NM1, the source of the field effect tube NM1 is connected to the reverse input terminal of the operational amplifier OP2, the source of the field effect tube NM1 is grounded by being connected in series with the current source Isink, the node between the drain of the field effect tube NM1 and the cathode of the light emitting diode L1 is connected to the output terminal of the operational amplifier OP1, the positive input terminal of the operational amplifier OP1 is connected to the blanking voltage, the reverse input terminal of the operational amplifier OP1 is connected to its output terminal, and the enable terminal of the operational amplifier OP1 is connected to the output terminal of the combinational logic circuit.

[0068] Specifically, Figure 6 In the figure, Vsync is the command signal, and a pulse appears in each frame of the image to refresh the display data. GCLK is the external display clock signal; Vghost is the blanking voltage; ROW is the row control signal, and ROW is set to 0 to scan the current row; SPWMn is the output data of the nth channel of the LED chip; Vds is the reference voltage, which is used to determine the Vds voltage of the constant current NMOS tube; Isink is the channel output constant current source; BKn is the blanking pulse signal of the nth channel; OUTn is the output port of the nth channel.

[0069] When a channel in an LED chip is closed, the output drive circuit module uses the blanking pulse signal to pre-charge the parasitic between columns and rows in the channel, thereby eliminating LED brightness display errors and ghosting phenomena caused by the blanking pulse signal.

[0070] Preferably, the combinational logic circuit includes a shift register, an instruction decoding circuit, a memory and a PWM data segmentation processing module;

[0071] Wherein, the first input terminal of the shift register is connected to an external control signal, the second input terminal of the shift register and the first input terminal of the instruction decoding circuit are connected to an external data clock signal, and the second input terminal of the instruction decoding circuit is connected to an external input signal;

[0072] The first output terminal of the shift register is connected to the instruction decoding circuit, the second output terminal of the shift register is connected to the memory, and the third output terminal of the shift register serves as the data output terminal of the circuit;

[0073] A first output terminal of the instruction decoding circuit is connected to the memory, and a second output terminal of the instruction decoding circuit is connected to the configuration register;

[0074] The multiple output terminals of the memory are respectively connected to the multiple first input terminals of the PWM data segmentation processing module;

[0075] The first output end of the configuration register is connected to the second input end of the PWM data segmentation processing module, the second output end of the configuration register and multiple output ends of the PWM data segmentation processing module are connected to the output drive circuit module, and the third input end of the PWM data segmentation processing module is connected to the external display clock signal.

[0076] Specifically, the circuit writes register configuration information and LED grayscale data into the shift register by serial shifting of an external control signal SDI and an external data clock signal DCLK. The instruction decoding circuit uses N (N is an arbitrary integer) DCLK edges contained in the high level of the external input signal LA as instructions to write the shift register data into the configuration register or memory, and the instruction decoding circuit also generates an instruction signal Vsync signal. The PWM data segmentation processing module breaks up the LED grayscale data into different group subframes. The blanking enable module generates a blanking enable signal. The output drive circuit module realizes the blanking function and provides a drive current.

[0077] Preferably, the memory includes SRAM and a cache;

[0078] The second output end of the shift register and the first output end of the instruction decoding circuit are connected to the SRAM, the output end of the SRAM is connected to the buffer, and the multiple output ends of the buffer are respectively connected to the multiple first input ends of the PWM data segmentation processing module.

[0079] Specifically, the SRAM capacity can store two frames of LED grayscale data. While storing the LED grayscale data, the LED grayscale data written in the previous frame is displayed, thereby forming a "ping-pong" operation. The buffer BUFFER is used to pre-fetch the next line of LED grayscale data from the SRAM for caching when a line is wrapped or a line display ends.

[0080] The circuit provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference may be made to the corresponding contents in the aforementioned embodiment.

[0081] Embodiment three:

[0082] A LED display screen blanking chip,

[0083] Including the above-mentioned LED display screen blanking circuit.

[0084] The chip combines LED grayscale display data to perform real-time blanking control on different channels of the LED chip, improving the display effect, meeting high-quality image requirements, and solving the ghosting problem of LED display screens in the prior art.

[0085] The chip provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference may be made to the corresponding contents in the aforementioned embodiment.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

Claims

1. A method for blanking an LED display screen, characterized in that: The following steps are involved: The blanking enable module generates a blanking enable signal according to an external display clock signal and an instruction signal, and transmits the blanking enable signal to a combinational logic circuit; The combinational logic circuit receives the output data of each channel in the LED chip, processes the output data and the blanking enable signal, obtains the blanking pulse signal of each channel in the LED chip, and transmits the blanking pulse signal to the output drive circuit module; When the channel in the LED chip is closed, the output drive circuit module uses the blanking pulse signal to pre-charge the parasitic between the column and the row in the channel; The combinational logic circuit includes a shift register, an instruction decoding circuit, a memory and a PWM data segmentation processing module; The combinational logic circuit receives output data of each channel in the LED chip, processes the output data and the blanking enable signal, obtains a blanking pulse signal of each channel in the LED chip, and transmits the blanking pulse signal to the output drive circuit module, specifically comprising: The shift register stores the written register configuration information and each row of LED grayscale data. The instruction decoding circuit writes the data in the shift register into the configuration register or the memory according to the external input signal. The instruction decoding circuit generates the instruction signal. The PWM data segmentation processing module reads the next row of LED grayscale data stored in the memory, and breaks up the next row of LED grayscale data into different grouped subframes to obtain the blanking pulse signal, which is transmitted to the output drive circuit module.

2. The LED display screen blanking method according to claim 1, characterized in that: The blanking enable module generates a blanking enable signal according to an external display clock signal and an external command signal, specifically comprising: The blanking enable module synchronizes the row counter inside the LED chip according to the command signal, and then counts the external display clock signal to obtain the row display on period and off period in the LED chip to form the blanking enable signal.

3. A LED display screen blanking circuit, characterized in that: Execute the LED display screen blanking method according to claim 1; including a configuration register, a blanking enable module, a combinational logic circuit and an output drive circuit module; Among them, the output end of the configuration register is connected to the first input end of the blanking enable module, the second input end of the blanking enable module is connected to the external display clock signal, the third input end of the blanking enable module is connected to the external command signal, the output end of the blanking enable module is connected to the first input end of the combinational logic circuit, the second input end of the combinational logic circuit is connected to the channel of the LED chip, and the output end of the combinational logic circuit is connected to the output drive circuit module.

4. The LED display screen blanking circuit according to claim 3, characterized in that: The output drive circuit module includes an operational amplifier OP1, an operational amplifier OP2, a field effect transistor PM1, a field effect transistor NM1 and a current source Isink; The source of the field effect transistor PM1 is connected to a high level, the gate of the field effect transistor PM1 is connected to a line control signal, and the drain of the field effect transistor PM1 is connected to the drain of the field effect transistor NM1 through the positive light emitting diode L1; The positive input terminal of the operational amplifier OP2 is connected to the reference voltage, the enable terminal of the operational amplifier OP2 is connected to the channel of the LED chip, the output terminal of the operational amplifier OP2 is connected to the gate of the field effect tube NM1, the source of the field effect tube NM1 is connected to the reverse input terminal of the operational amplifier OP2, the source of the field effect tube NM1 is grounded by being connected in series with the current source Isink, the node between the drain of the field effect tube NM1 and the cathode of the light emitting diode L1 is connected to the output terminal of the operational amplifier OP1, the positive input terminal of the operational amplifier OP1 is connected to the blanking voltage, the reverse input terminal of the operational amplifier OP1 is connected to its output terminal, and the enable terminal of the operational amplifier OP1 is connected to the output terminal of the combinational logic circuit.

5. The LED display screen blanking circuit according to claim 3, characterized in that: Wherein, the first input terminal of the shift register is connected to an external control signal, the second input terminal of the shift register and the first input terminal of the instruction decoding circuit are connected to an external data clock signal, and the second input terminal of the instruction decoding circuit is connected to an external input signal; The first output terminal of the shift register is connected to the instruction decoding circuit, the second output terminal of the shift register is connected to the memory, and the third output terminal of the shift register serves as the data output terminal of the circuit; A first output terminal of the instruction decoding circuit is connected to the memory, and a second output terminal of the instruction decoding circuit is connected to the configuration register; The multiple output terminals of the memory are respectively connected to the multiple first input terminals of the PWM data segmentation processing module; The first output end of the configuration register is connected to the second input end of the PWM data segmentation processing module, the second output end of the configuration register and multiple output ends of the PWM data segmentation processing module are connected to the output drive circuit module, and the third input end of the PWM data segmentation processing module is connected to the external display clock signal.

6. The LED display screen blanking circuit according to claim 5, characterized in that: The memory includes an SRAM and a buffer; The second output end of the shift register and the first output end of the instruction decoding circuit are connected to the SRAM, the output end of the SRAM is connected to the buffer, and the multiple output ends of the buffer are respectively connected to the multiple first input ends of the PWM data segmentation processing module.

7. A LED display screen blanking chip, characterized in that: The invention comprises the LED display screen blanking circuit as described in any one of claims 3 to 6.

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