Leakage Compensation Dynamic Register, Data Arithmetic Unit, Chip, Computing Power Board and Computing Device

Abstract

The present invention provides a leakage compensation dynamic register, a data operation unit, a chip, a computing power board and a computing device. The leakage compensation dynamic register includes an input end, an output end, a clock signal end, and an analog switch unit; a data latch unit that latches data under the control of the clock signal; an output driving unit for inverting and outputting the data received from the data latch unit; the analog switch unit, the data latch unit, and the output driving unit are sequentially connected in series between the input end and the output end, and there is a node between the analog switch unit and the data latch unit; wherein, it further includes a leakage compensation unit, and the leakage compensation unit is electrically connected between the node and the output end. It can effectively compensate the dynamic leakage current of the node and improve the security and accuracy of data.

Description

Technical Field

[0001] The present invention relates to a clock-controlled storage device, and in particular to a leakage compensation dynamic register, a data operation unit, a chip, a computing board and a computing device used in large-scale data computing equipment. Background Art

[0002] Dynamic registers are widely used and can be used to store digital signals. Figure 1 FIG. 1 is a circuit diagram of an existing dynamic register. Figure 1 As shown, the dynamic register includes a transmission gate 101, a tri-state inverter 102, and an inverter 103 connected in series between an input terminal D and an output terminal Q. A node S0 is formed between the transmission gate 101 and the tri-state inverter 102, and a node S1 is formed between the tri-state inverter 102 and the inverter 103. Data is temporarily stored in the node S0 and / or the node S1 through the parasitic capacitance of the transistors in the tri-state inverter 102 and the inverter 103. However, the node S0 is prone to dynamic leakage, resulting in the loss of the temporarily stored data.

[0003] Therefore, how to effectively reduce the dynamic leakage of the dynamic register is a problem that needs to be solved. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a leakage compensation dynamic register, which can effectively compensate for the dynamic leakage current of the node and improve the security and accuracy of data.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a leakage compensation dynamic register, including an input end for inputting data; an output end for outputting the data; a clock signal end for providing a clock signal; an analog switch unit for transmitting the data under the control of the clock signal; a data latch unit for latching the data under the control of the clock signal; an output drive unit for inverting and outputting the data received from the data latch unit; the analog switch unit, the data latch unit, and the output drive unit are connected in series between the input end and the output end in sequence, and there is a node between the analog switch unit and the data latch unit; wherein, it also includes a leakage compensation unit, and the leakage compensation unit is electrically connected between the node and the output end.

[0006] In the above leakage compensation dynamic register, the leakage compensation unit has a first end, a second end and a control end, the first end is electrically connected to the output end, and the second end is electrically connected to the node.

[0007] The above-mentioned leakage compensation dynamic register, wherein the leakage compensation unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the output terminal and the node.

[0008] The above-mentioned leakage compensation dynamic register, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the node.

[0009] The above-mentioned leakage compensation dynamic register, wherein the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a power supply.

[0010] The above-mentioned leakage compensation dynamic register, wherein the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the node.

[0011] The above-mentioned leakage compensation dynamic register, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the NMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the PMOS transistor, and the source terminal of the PMOS transistor is electrically connected to the node.

[0012] The above-mentioned leakage compensation dynamic register, wherein the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a ground.

[0013] The above-mentioned leakage compensation dynamic register, wherein the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the node.

[0014] The above-mentioned leakage compensation dynamic register, wherein the leakage compensation unit includes a PMOS transistor, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the node, and the gate terminal is electrically connected to a power supply.

[0015] The above-mentioned leakage compensation dynamic register, wherein the leakage compensation unit includes an NMOS transistor, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the drain terminal of the NMOS transistor is electrically connected to the output terminal, the source terminal is electrically connected to the node, and the gate terminal is electrically connected to a ground.

[0016] The above-mentioned leakage compensation dynamic register, wherein the clock signal includes a first clock signal and a second clock signal, and the first clock signal is inverted with respect to the second clock signal.

[0017] The above-mentioned leakage compensation dynamic register, wherein the analog switch unit is a transmission gate.

[0018] The above-mentioned leakage compensation dynamic register, wherein the data latch unit is a tri-state inverter.

[0019] The above-mentioned leakage compensation dynamic register, wherein the output driver unit is an inverter.

[0020] By using the leakage compensation dynamic register of the present invention, the leakage current can be fed back from the output terminal to the node, compensating for the dynamic leakage current of the node, improving the stability of data storage, and further enhancing the security and accuracy of data.

[0021] To better achieve the above object, the present invention also provides a data operation unit, including a control circuit, an operation circuit, and a plurality of leakage compensation dynamic registers connected in an interconnected manner, the plurality of leakage compensation dynamic registers being connected in series and / or in parallel; wherein, the plurality of leakage compensation dynamic registers are any one of the above-mentioned leakage compensation dynamic registers.

[0022] To better achieve the above object, the present invention also provides a chip, which includes at least one of the above-mentioned data operation units.

[0023] To better achieve the above object, the present invention also provides a computing power board for a computing device, which includes at least one of the above-mentioned chips.

[0024] To better achieve the above object, the present invention also provides a computing device, including a power supply board, a control board, a connection board, a radiator, and a plurality of computing power boards, the control board is connected to the computing power boards through the connection board, the radiator is arranged around the computing power boards, and the power supply board is used to supply power to the connection board, the control board, the radiator, and the computing power boards, wherein, the computing power board is the above-mentioned computing power board.

[0025] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not a limitation to the present invention. Description of the Drawings

[0026] Figure 1 Schematic diagram of the circuit structure of an existing dynamic register;

[0027] Figure 2 Schematic diagram of the circuit structure of a leakage compensation dynamic register according to an embodiment of the present invention;

[0028] Figure 3 Schematic diagram of the circuit structure of a leakage compensation dynamic register according to another embodiment of the present invention;

[0029] Figure 4 Schematic diagram of the circuit structure of a leakage compensation dynamic register according to another embodiment of the present invention;

[0030] Figure 5 Schematic diagram of the circuit structure of a leakage compensation dynamic register according to still another embodiment of the present invention;

[0031] Figure 6 Schematic diagram of the circuit structure of a leakage compensation dynamic register according to an extended embodiment of the present invention;

[0032] Figure 7 Schematic diagram of the circuit structure of a leakage compensation dynamic register according to another extended embodiment of the present invention;

[0033] Figure 8 Schematic diagram of the structure of a data operation unit of the present invention;

[0034] Figure 9 Schematic diagram of the structure of a chip of the present invention;

[0035] Figure 10 Schematic diagram of the structure of a computing power board of the present invention;

[0036] Figure 11 Schematic diagram of the structure of a computing device of the present invention.

[0037] Among them, reference numerals:

[0038] 100: Dynamic register

[0039] 101: Transmission gate

[0040] 102: Tri-state inverter

[0041] 103: Inverter

[0042] 200: Leakage compensation dynamic register

[0043] 201: Analog switch unit

[0044] 202: Data latch unit

[0045] 203: Output driver unit

[0046] 204: Leakage compensation unit

[0047] 201P, 202P1, 202P2, 204P: PMOS transistors

[0048] 201N, 202N1, 202N2, 204N: NMOS transistors

[0049] 800: Data operation unit

[0050] 801: Control circuit

[0051] 802: Operation circuit

[0052] 900: Chip

[0053] 901: Control unit

[0054] 1000: Computing power board

[0055] 1100: Computing device

[0056] 1101: Connection board

[0057] 1102: Control board

[0058] 1103: Radiator

[0059] 1104: Power supply board

[0060] D: Input terminal

[0061] Q: Output terminal

[0062] CKP, CKN: Clock signals

[0063] S0, S1: Nodes Detailed implementation manners

[0064] The following specifically describes the structural principle and working principle of the present invention with reference to the accompanying drawings:

[0065] In the specification and subsequent claims, certain terms are used to refer to specific components. Those of ordinary skill in the art should understand that manufacturers may use different names to refer to the same component. The specification and subsequent claims do not use the difference in names as a way to distinguish components, but use the difference in functions of components as the criterion for distinction.

[0066] The terms "comprising" and "including" mentioned throughout the specification and subsequent claims are open-ended terms, and should therefore be interpreted as "including but not limited to". In addition, the term "connected" herein includes any direct and indirect electrical connection means. Indirect electrical connection means include connection through other devices.

[0067] Embodiment 1:

[0068] Figure 2 This is a schematic diagram of the circuit structure of a leakage compensation dynamic register according to an embodiment of the present invention. As Figure 2 shown, the leakage compensation dynamic register 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, an analog switch unit 201, a data latch unit 202, an output driver unit 203, and a leakage compensation unit 204. The analog switch unit 201, the data latch unit 202, and the output driver unit 203 are connected in series between the input terminal D and the output terminal Q in sequence, and a node S0 is formed between the analog switch unit 201 and the data latch unit 202. The leakage compensation unit 204 is electrically connected between the node S0 and the output terminal Q. Among them, the input terminal D is used to input data, the output terminal is used to output data, the clock signal terminals CKN and CKP are used to provide the clock signal CKN and the clock signal CKP, and the clock signal CKN and the clock signal CKP are inverted clock signals.

[0069] Specifically, as Figure 2 shown, the analog switch unit 201 of the leakage compensation dynamic register 200 has a transmission gate structure. The analog switch unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel. Among them, the source terminal of the PMOS transistor 201P is connected in parallel with the source terminal of the NMOS transistor 201N and is electrically connected to the input terminal D. The drain terminal of the PMOS transistor 201P is connected in parallel with the drain terminal of the NMOS transistor 201N and is electrically connected to the node S0. The gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate terminal of the PMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is at a low level and CKN is at a high level, both the PMOS transistor 201P and the NMOS transistor 201N are in a conducting state, and the data at the input terminal D is transmitted to the node S0 through the analog switch unit 201. When CKP is at a high level and CKN is at a low level, both the PMOS transistor 201P and the NMOS transistor 201N are in a non-conducting state, and the data at the input terminal D cannot be transmitted to the node S0 through the analog switch unit 201. In this embodiment, the analog switch unit 201 is exemplified by a transmission gate structure. Of course, it can also be other forms of analog switch units as long as they can achieve the switching function under the control of the clock signal. The present invention is not limited thereto.

[0070] Continue to refer to Figure 2As shown, the data latch unit 202 of the leakage compensation dynamic register 200 has a tri-state inverter structure. The data latch unit 202 includes PMOS transistors 202P1 and 202P2 and NMOS transistors 202N1 and 202N2 connected in series between the power supply VDD and the ground VSS. The gate terminals of PMOS transistor 202P1 and NMOS transistor 202N2 are connected together to form the input terminal of the data latch unit 202. The drain terminals of PMOS transistor 202P2 and NMOS transistor 202N1 are connected together to form the output terminal of the data latch unit 202. The source terminal of PMOS transistor 202P1 is connected to the power supply VDD, and the source terminal of NMOS transistor 202N2 is connected to the ground VSS. The source terminal of PMOS transistor 202P2 is connected to the drain terminal of PMOS transistor 202P1, and the source terminal of NMOS transistor 202N1 is connected to the drain terminal of NMOS transistor 202N2.

[0071] In this embodiment, the gate terminal of PMOS transistor 202P2 is controlled by the clock signal CKN, and the gate terminal of NMOS transistor 202N1 is controlled by the clock signal CKP, serving as the clock control terminals of the data latch unit 202. Of course, it can also be that the gate terminal of PMOS transistor 20212 is controlled by the clock signal CKN, and the gate terminal of NMOS transistor 202N2 is controlled by the clock signal CKP. The present invention is not limited thereto.

[0072] When CKP is at a low level and CKN is at a high level, both PMOS transistor 202P2 and NMOS transistor 202N1 are in a non-conducting state, and the data latch unit 202 is in a high-impedance state. The data at node S0 cannot pass through the data latch unit 202, and the data at node S0 is latched and maintains its original state, playing the role of data storage.

[0073] When CKP is at a high level and CKN is at a low level, both PMOS transistor 202P2 and NMOS transistor 202N1 are in a conducting state, and the data latch unit 202 serves to invert the data at node S0, that is, the input data of the data latch unit. At this time, the data at node S0 is inverted and output to the output driving unit 203 to rewrite the data at the output terminal Q.

[0074] As Figure 2 As shown, the output driving unit 203 of the leakage compensation dynamic register 200 has an inverter structure, which inverts the data received from the data latch unit 202 again to form data with the same phase as the data at the input terminal D, and outputs the data through the output terminal Q. At the same time, the output driving unit can also improve the driving ability of the data.

[0075] As Figure 2As shown, the leakage compensation dynamic register 200 further includes a leakage compensation unit 204. In this embodiment, the leakage compensation unit 204 includes a PMOS transistor 204P and an NMOS transistor 204N. The PMOS transistor 204P and the NMOS transistor 204N are connected in series between the output terminal Q and the node S0. The source terminal of the PMOS transistor 204P is electrically connected to the output terminal Q, the drain terminal of the PMOS transistor 204P is electrically connected to the drain terminal of the NMOS transistor 204N, the source terminal of the NMOS transistor 204N is electrically connected to the node S0, and the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the power supply VDD.

[0076] Since the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are also electrically connected to the power supply VDD, driven by the high-level signal of the power supply VDD, the PMOS transistor 204P is in the cut-off state and the NMOS transistor 204N is in the on state. At this time, the leakage compensation unit 204 can feedback the leakage current of the output terminal Q to the node S0 to compensate for the dynamic leakage current at the node S0, improve the stability of data storage, and further enhance the security and accuracy of the data.

[0077] Embodiment 2:

[0078] Figure 3 It is a schematic circuit diagram of a leakage compensation dynamic register according to an embodiment of the present invention. As Figure 3 shown, the leakage compensation dynamic register 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, an analog switch unit 201, a data latch unit 202, an output driving unit 203, and a leakage compensation unit 204. The analog switch unit 201, the data latch unit 202, and the output driving unit 203 are sequentially connected in series between the input terminal D and the output terminal Q, and a node S0 is formed between the analog switch unit 201 and the data latch unit 202. The leakage compensation unit 204 is electrically connected between the node S0 and the output terminal Q. Among them, the input terminal D is used to input data, the output terminal is used to output data, the clock signal terminals CKN and CKP are used to provide the clock signal CKN and the clock signal CKP, and the clock signal CKN and the clock signal CKP are inverted clock signals.

[0079] Specifically, as Figure 3As shown in the figure, the analog switch unit 201 of the leakage compensation dynamic register 200 is a transmission gate structure. The analog switch unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel. Among them, the source terminals of the PMOS transistor 201P and the NMOS transistor 201N are connected in parallel and electrically connected to the input terminal D. The drain terminals of the PMOS transistor 201P and the NMOS transistor 201N are connected in parallel and electrically connected to the node S0. The gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate terminal of the PMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is at a low level and CKN is at a high level, both the PMOS transistor 201P and the NMOS transistor 201N are in the conducting state, and the data at the input terminal D is transmitted to the node S0 through the analog switch unit 201. When CKP is at a high level and CKN is at a low level, both the PMOS transistor 201P and the NMOS transistor 201N are in the non-conducting state, and the data at the input terminal D cannot be transmitted to the node S0 through the analog switch unit 201. In this embodiment, the analog switch unit 201 is exemplified by a transmission gate structure. Of course, it can also be other forms of analog switch units, as long as it can implement the switching function under the control of the clock signal. The present invention is not limited thereto.

[0080] Continue to refer to Figure 3 As shown in the figure, the data latch unit 202 of the leakage compensation dynamic register 200 is a three-state inverter structure. The data latch unit 202 includes PMOS transistors 202P1, 202P2 and NMOS transistors 202N1, 202N2 connected in series between the power supply VDD and the ground VSS. The gate terminals of the PMOS transistor 202P1 and the NMOS transistor 202N2 are connected together to form the input terminal of the data latch unit 202. The drain terminals of the PMOS transistor 202P2 and the NMOS transistor 201N1 are connected together to form the output terminal of the data latch unit 202. The source terminal of the PMOS transistor 202P1 is connected to the power supply VDD, and the source terminal of the NMOS transistor 202N2 is connected to the ground VSS. The source terminal of the PMOS transistor 202P2 is connected to the drain terminal of the PMOS transistor 202P1, and the source terminal of the NMOS transistor 202N1 is connected to the drain terminal of the NMOS transistor 202N2.

[0081] In this embodiment, the gate terminal of PMOS transistor 202P2 is controlled by clock signal CKN, and the gate terminal of NMOS transistor 202N1 is controlled by clock signal CKP, serving as the clock control terminals of data latch unit 202. Of course, it can also be that the gate terminal of PMOS transistor 20212 is controlled by clock signal CKN, and the gate terminal of NMOS transistor 202N2 is controlled by clock signal CKP. The present invention is not limited thereto.

[0082] When CKP is at a low level and CKN is at a high level, both PMOS transistor 202P2 and NMOS transistor 202N1 are in a non-conducting state, and data latch unit 202 is in a high-impedance state. The data at node S0 cannot pass through data latch unit 202, and the data at node S0 is latched and maintains its original state, serving the function of data storage.

[0083] When CKP is at a high level and CKN is at a low level, both PMOS transistor 202P2 and NMOS transistor 202N1 are in a conducting state, and data latch unit 202 serves to invert the data at node S0, which is the input terminal of the data latch unit. At this time, the data at node S0 is inverted and output to output driving unit 203 to rewrite the data at output terminal Q.

[0084] As Figure 3 shown, the output driving unit 203 of leakage compensation dynamic register 200 has an inverter structure, which inverts the data received from data latch unit 202 again to form data with the same phase as the data at input terminal D, and outputs the data through output terminal Q. At the same time, the output driving unit can also improve the driving ability of the data.

[0085] As Figure 3 shown, leakage compensation dynamic register 200 further includes a leakage compensation unit 204. Different from the embodiment Figure 2 shown, in this embodiment, leakage compensation unit 204 includes PMOS transistor 204P and NMOS transistor 204N. PMOS transistor 204P and NMOS transistor 204N are connected in series between output terminal Q and node S0. The source terminal of PMOS transistor 204P is electrically connected to node S0, the drain terminal of PMOS transistor 204P is electrically connected to the drain terminal of NMOS transistor 204N, the source terminal of NMOS transistor 204N is electrically connected to output terminal Q, and the gate terminals of PMOS transistor 204P and NMOS transistor 204N are connected in parallel and electrically connected to ground VSS.

[0086] Since the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are both electrically connected to the ground VSS, driven by the low-level signal of the ground VSS, the PMOS transistor 204P is in the conducting state and the NMOS transistor 204N is in the cutoff state. Therefore, the leakage compensation unit 204 can feedback the leakage current at the output terminal Q to the node S0, compensate for the leakage current at the node S0, improve the stability of data storage, and further enhance the security and accuracy of the data.

[0087] Variant:

[0088] Figure 4 This is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As Figure 2 and Figure 4 shown, the difference from the embodiment shown in Figure 2 is that in this embodiment, in the leakage compensation unit 204, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the node S0.

[0089] Since the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are both electrically connected to the node S0, driven by signals of the same level, the PMOS transistor 205P and the NMOS transistor 205N will not conduct simultaneously, and only one can be in the conducting state while the other is in the cutoff state. For example, when the potential at the node S0 is high, the PMOS transistor 205P is in the cutoff state and the NMOS transistor 205N is in the conducting state; when the potential at the node S0 is low, the PMOS transistor 205P is in the conducting state and the NMOS transistor 205N is in the cutoff state. Therefore, the leakage feedback unit 205 can feedback the leakage current at the output terminal Q to the node S0, compensate for the leakage current at the node S0, improve the stability of data storage, and further enhance the security and accuracy of the data.

[0090] Figure 5 This is a schematic circuit diagram of a leakage compensation dynamic register according to still another embodiment of the present invention. As Figure 3 and Figure 5 shown, the difference from the embodiment shown in Figure 3 is that in this embodiment, in the leakage compensation unit 204, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the node S0.

[0091] Since the gate terminals of PMOS transistor 205P and NMOS transistor 205N are both electrically connected to node S0, under the drive of signals at the same level, PMOS transistor 205P and NMOS transistor 205N will not conduct simultaneously. Only one of them can be in the conducting state while the other is in the cut-off state. For example, when the potential at node S0 is high, PMOS transistor 205P is in the cut-off state while NMOS transistor 205N is in the conducting state; when the potential at node S0 is low, PMOS transistor 205P is in the conducting state while NMOS transistor 205N is in the cut-off state. Therefore, the leakage feedback unit 205 can feedback the leakage current at the output terminal Q to node S0, compensate for the leakage current at node S0, improve the stability of data storage, and further enhance the security and accuracy of data.

[0092] Figure 6 This is a schematic circuit diagram of the leakage compensation dynamic register according to an extended embodiment of the present invention. As Figure 6 shown, the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes a PMOS transistor 204P. The source terminal of the PMOS transistor 204P is electrically connected to the output terminal, the drain terminal of the PMOS transistor 204P is electrically connected to node S0, and the gate terminal of the PMOS transistor 204P is electrically connected to the power supply VDD.

[0093] Since the gate terminal of the PMOS transistor 204P is electrically connected to the power supply VDD, under the drive of the high-level signal of the power supply VDD, the PMOS transistor 204P is in the cut-off state. Therefore, the leakage compensation unit 204 can feedback the leakage current at the output terminal Q to node S0, compensate for the leakage current at node S0, improve the stability of data storage, and further enhance the security and accuracy of data.

[0094] Figure 7 This is a schematic circuit diagram of the leakage compensation dynamic register according to another extended embodiment of the present invention. As Figure 7 shown, the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes an NMOS transistor 204N. The source terminal of the NMOS transistor 204N is electrically connected to node S0, the drain terminal of the NMOS transistor 204N is electrically connected to the output terminal Q, and the gate terminal of the NMOS transistor 204N is electrically connected to the ground VSS.

[0095] Since the gate terminal of the NMOS transistor 204N is electrically connected to the ground VSS, under the drive of the low-level signal of the ground VSS, the NMOS transistor 204N is in the cut-off state. Therefore, the leakage compensation unit 204 can feedback the leakage current at the output terminal Q to node S0, compensate for the leakage current at node S0, improve the stability of data storage, and further enhance the security and accuracy of data.

[0096] The present invention also provides a data operation unit, Figure 8 which is a schematic structural diagram of the data operation unit of the present invention. As Figure 8 shown, the data operation unit 800 includes a control circuit 801, an operation circuit 802, and a plurality of leakage compensation dynamic registers 200. The control circuit 801 refreshes the data in the leakage compensation dynamic registers 200 and reads the data from the leakage compensation dynamic registers 200. The operation circuit 802 operates on the read data, and then the control circuit 801 outputs the operation result.

[0097] The present invention also provides a chip, Figure 9 which is a schematic structural diagram of the chip of the present invention. As Figure 9 shown, the chip 900 includes a control unit 901 and one or more data operation units 800. The control unit 901 inputs data to the data operation unit 800 and processes the data output by the data operation unit 800.

[0098] The present invention also provides a computing power board, Figure 10 which is a schematic structural diagram of the computing power board of the present invention. As Figure 10 shown, each computing power board 1000 includes one or more chips 900, which perform large-scale operations on the working data issued by the computing device.

[0099] The present invention also provides a computing device, Figure 11 which is a schematic structural diagram of the computing device of the present invention. As Figure 11 shown, each computing device 1100 includes a connection board 1101, a control board 1102, a radiator 1103, a power supply board 1104, and one or more computing power boards 1000. The control board 1102 is connected to the computing power board 1000 through the connection board 1101, and the radiator 1103 is arranged around the computing power board 1000. The power supply board 1104 is used to supply power to the connection board 1101, the control board 1102, the radiator 1103, and the computing power board 1000.

[0100] It should be noted that in the description of the present invention, the orientation or positional relationship indicated by the terms "horizontal", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0101] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention. However, these corresponding changes and modifications should all fall within the protection scope of the appended claims of the present invention.

Claims

1. A leakage compensation dynamic register, characterized in that, Comprising: An input terminal for inputting a piece of data; An output terminal for outputting the data; A clock signal terminal for providing a clock signal; An analog switch unit for transmitting the data under the control of the clock signal; A data latch unit for latching the data under the control of the clock signal; An output driving unit for inverting and outputting the data received from the data latch unit; The analog switch unit, the data latch unit, and the output driving unit are connected in series between the input terminal and the output terminal in sequence, and there is a node between the analog switch unit and the data latch unit; Wherein, a leakage current compensation unit is further included, and the leakage current compensation unit at least includes a PMOS transistor and an NMOS transistor. The PMOS transistor and the NMOS transistor are connected in series between the output terminal and the node, and the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected, for feeding back the leakage current of the output terminal to the node to compensate the dynamic leakage current at the node.

2. The leakage compensation dynamic register according to claim 1, wherein: The PMOS transistor has a source terminal, a drain terminal, and a gate terminal. The NMOS transistor has a source terminal, a drain terminal, and a gate terminal. The source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the node.

3. The leakage compensation dynamic register according to claim 2, characterized in that: The gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a power supply.

4. The leakage current compensation dynamic register according to claim 2, characterized in that: The gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the node.

5. The leakage compensation dynamic register according to claim 1, wherein: The PMOS transistor has a source terminal, a drain terminal, and a gate terminal. The NMOS transistor has a source terminal, a drain terminal, and a gate terminal. The source terminal of the NMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the PMOS transistor, and the source terminal of the PMOS transistor is electrically connected to the node.

6. The leakage compensation dynamic register as claimed in claim 5, wherein: The gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a ground.

7. The leakage compensation dynamic register as claimed in claim 5, wherein: The gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the node.

8. The leakage compensation dynamic register according to claim 1, wherein: The clock signal includes a first clock signal and a second clock signal, and the first clock signal is inverted with respect to the second clock signal.

9. The leakage compensation dynamic register according to claim 1, wherein: The analog switch unit is a transmission gate.

10. The leakage compensation dynamic register according to claim 1, wherein: The data latch unit is a tri-state inverter.

11. The leakage compensation dynamic register according to claim 1, wherein: The output driving unit is an inverter.

12. A data operation unit includes a control circuit, an operation circuit, and a plurality of leakage compensation dynamic registers that are interconnected. The plurality of leakage compensation dynamic registers are connected in series and / or in parallel; it is characterized in that: The plurality of leakage current compensation dynamic registers are the leakage current compensation dynamic registers as described in any one of claims 1 - 11.

13. A chip, characterized in that, Including at least one data operation unit as described in claim 12.

14. A computing power board for a computing device, characterized in that, Including at least one chip as described in claim 13.

15. A computing device, comprising a power supply board, a control board, a connection board, a radiator, and a plurality of computing power boards, wherein the control board is connected to the computing power boards through the connection board, the radiator is disposed around the computing power boards, and the power supply board is configured to supply power to the connection board, the control board, the radiator, and the computing power boards, and is characterized in that: The computing power board is the computing power board as described in claim 14.

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