Quasi-five-level inverter

Abstract

The present disclosure relates to, but is not limited to, a quasi-five-level inverter. According to one aspect, an embodiment of the present invention provides an inverter, which includes an input terminal, an output terminal, a plurality of DC buses, a midpoint bus, an LC filter, a common point coupled to the LC filter, a plurality of switches coupled to the plurality of DC buses and the common point, a bidirectional switch coupled between the midpoint bus and the common point, and a controller, wherein the controller is configured to operate the plurality of switches and the bidirectional switch in a first operating mode to generate a voltage at a first positive DC voltage level at the common point, to operate the plurality of switches and the bidirectional switch in a second operating mode to generate a voltage at a second positive DC voltage level, to operate the plurality of switches and the bidirectional switch in a third operating mode to generate a voltage at a first negative DC voltage level, and to operate the plurality of switches and the bidirectional switch in a fourth operating mode to generate a voltage at a second negative DC voltage level.

Description

background

[0001] 1. Field of the Invention

[0002] The present invention generally relates to systems and methods for controlling an uninterruptible power supply (UPS).

[0003] 2. Discussion of related technologies

[0004] It is well known to use power equipment, such as an uninterruptible power supply (UPS), to provide regulated, uninterruptible power to sensitive and / or critical loads, such as computer systems and other data processing systems. Known uninterruptible power supplies include online UPS, offline UPS, line-interactive UPS, and others. An online UPS provides regulated AC power and provides backup AC power when the main source of AC power is interrupted. An offline UPS typically does not provide regulation of the input AC power, but does provide backup AC power when the main AC power is interrupted. A line-interactive UPS is similar to an offline UPS in that they both switch to battery power when a power outage occurs, but a line-interactive UPS typically also includes a multi-tap transformer for stabilizing the output voltage provided by the UPS.

[0005] Overview

[0006] At least one aspect of the present invention is directed to an inverter, comprising: an input terminal, the input terminal being configured to be coupled to a DC source and to receive input DC power from the DC source; an output terminal, the input terminal being configured to be coupled to a load and to provide output AC power to the load; a plurality of DC buses, the plurality of DC buses being coupled to the input terminal and being configured to receive input DC power from the DC source; a midpoint bus, the midpoint bus being coupled to the input terminal and coupled to the plurality of DC buses; an LC filter, the LC filter being coupled to the output terminal; a common point, the common point being coupled to the LC filter; a plurality of switches, the plurality of switches being coupled to the plurality of DC A bus and a common point; a bidirectional switch coupled between the midpoint bus and the common point; and a controller configured to operate the plurality of switches and the bidirectional switch in a first operating mode to generate a voltage at a first positive DC voltage level at the common point, operate the plurality of switches and the bidirectional switch in a second operating mode to generate a voltage at a second positive DC voltage level at the common point, operate the plurality of switches and the bidirectional switch in a third operating mode to generate a voltage at a first negative DC voltage level at the common point, and operate the plurality of switches and the bidirectional switch in a fourth operating mode to generate a voltage at a second negative DC voltage level at the common point. In one embodiment, the LC filter is configured to provide an output AC voltage waveform derived from the voltage at the common point to the output terminal during the first operating mode, the second operating mode, the third operating mode, and the fourth operating mode.

[0007] According to one embodiment, in a first operating mode, the controller is further configured to operate multiple switches and bidirectional switches to generate voltage pulses alternating between zero and a first positive DC voltage level at a common point, in a second operating mode, the controller is further configured to operate multiple switches and bidirectional switches to generate voltage pulses alternating between a first positive DC voltage level and a second positive DC voltage level at a common point, in a third operating mode, the controller is further configured to operate multiple switches and bidirectional switches to generate voltage pulses alternating between zero and a first negative DC voltage level at a common point, and in a fourth operating mode, the controller is further configured to operate multiple switches and bidirectional switches to generate voltage pulses alternating between a first negative DC voltage level and a second negative DC voltage level at a common point.

[0008] According to another embodiment, the plurality of DC buses include a first positive DC bus coupled to the input terminal, a second positive DC bus coupled to the input terminal, a first negative DC bus coupled to the input terminal, and a second negative DC bus coupled to the input terminal, and the plurality of switches include a first switch coupled to the first positive DC bus, a second switch coupled between the first switch and a common point, a third switch coupled to the first negative DC bus, and a fourth switch coupled between the third switch and the common point. In one embodiment, the inverter further includes a first diode coupled between the second positive DC bus and the second switch, and a second diode coupled between the second negative DC bus and the fourth switch. In another embodiment, the inverter further includes a first capacitor coupled between the first positive DC bus and the second positive DC bus, a second capacitor coupled between the second positive DC bus and the midpoint bus, a third capacitor coupled between the first negative DC bus and the second negative DC bus, and a fourth capacitor coupled between the second negative DC bus and the midpoint bus.

[0009] According to one embodiment, the controller is further configured to operate the plurality of switches in a first phase of the first operating mode to provide current from the second capacitor to the common point via the second positive DC bus, the first diode, and the second switch, and to operate the bidirectional switches in a second phase of the first operating mode to provide current from the midpoint bus to the common point via the bidirectional switches. In one embodiment, the controller is further configured to operate the plurality of switches in a first phase of the second operating mode to provide current from the first capacitor to the common point via the first positive DC bus, the first switch, and the second switch, and to operate the plurality of switches in a second phase of the second operating mode to provide current from the second capacitor to the common point via the second positive DC bus, the first diode, and the second switch.

[0010] According to another embodiment, the controller is further configured to operate the plurality of switches in a first phase of the third operating mode to provide current from the common point to the third capacitor via the second negative DC bus, the second diode, and the fourth switch, and to operate the bidirectional switch in a second phase of the third operating mode to provide current from the common point to the midpoint bus via the bidirectional switch. In one embodiment, the controller is further configured to operate the plurality of switches in a first phase of the fourth operating mode to provide current from the common point to the fourth capacitor via the first negative DC bus, the third switch, and the fourth switch, and to operate the plurality of switches in a second phase of the fourth operating mode to provide current from the common point to the third capacitor via the second negative DC bus, the second diode, and the fourth switch.

[0011] According to one embodiment, the controller is further configured to operate the plurality of switches in a first phase of a fifth operating mode occurring during a transition from the second operating mode to the third operating mode to provide current from the common point to the first capacitor via the first positive DC bus, the first switch, and the second switch, and to operate the bidirectional switch in a second phase of the fifth operating mode to provide current from the common point to the midpoint bus via the bidirectional switch. In one embodiment, the controller is further configured to operate the plurality of switches in a first phase of a sixth operating mode occurring during a transition from the third operating mode to the second operating mode to provide current from the fourth capacitor to the common point via the first negative DC bus, the third switch, and the fourth switch, and to operate the bidirectional switch in a second phase of the sixth operating mode to provide current from the midpoint bus to the common point via the bidirectional switch.

[0012] According to another embodiment, the bidirectional switch includes a third diode coupled to the midpoint bus, a fifth switch coupled between the third diode and a common point, a fourth diode coupled to the common point, and a sixth switch coupled between the fourth diode and the midpoint bus.

[0013] Another aspect of the present invention is directed to a method for operating an inverter, the inverter comprising an input terminal configured to be coupled to a DC source, an output terminal, a plurality of DC buses, a midpoint bus coupled to the input terminal and the plurality of DC buses, an LC filter coupled to the output terminal, a common point coupled to the LC filter, a plurality of switches coupled to the plurality of DC buses and the common point, and a bidirectional switch coupled between the midpoint bus and the common point, the method comprising receiving an input DC power from the DC source at the input terminal, operating the plurality of switches and the bidirectional switches in a first operating mode to generate a voltage at a first positive DC voltage level at the common point, operating the plurality of switches and the bidirectional switches in a second operating mode to generate a voltage at a second positive DC voltage level at the common point, operating the plurality of switches and the bidirectional switches in a third operating mode to generate a voltage at a first negative DC voltage level at the common point, operating the plurality of switches and the bidirectional switches in a fourth operating mode to generate a voltage at a second negative DC voltage level at the common point, and generating an output AC voltage waveform derived from the voltage at the common point at the output terminal using the LC filter during the first operating mode, the second operating mode, the third operating mode, and the fourth operating mode.

[0014] According to one embodiment, operating multiple switches and bidirectional switches in a first operating mode includes operating the multiple switches and bidirectional switches to generate voltage pulses alternating between zero and a first positive DC voltage level at a common point, operating the multiple switches and bidirectional switches in a second operating mode includes operating the multiple switches and bidirectional switches to generate voltage pulses alternating between a first positive DC voltage level and a second positive DC voltage level at a common point, operating the multiple switches and bidirectional switches in a third operating mode includes operating the multiple switches and bidirectional switches to generate voltage pulses alternating between zero and a first negative DC voltage level at a common point, and operating the multiple switches and bidirectional switches in a fourth operating mode includes operating the multiple switches and bidirectional switches to generate voltage pulses alternating between a first negative DC voltage level and a second negative DC voltage level at a common point.

[0015] According to another embodiment, the plurality of DC buses include a first positive DC bus, a second positive DC bus, a first negative DC bus, and a second negative DC bus, wherein the plurality of switches include a first switch coupled to the first positive DC bus, a second switch coupled between the first switch and a common point, a third switch coupled to the first negative DC bus, and a fourth switch coupled between the third switch and the common point, and operating the plurality of switches and the bidirectional switch to generate voltage pulses alternating between zero and a first positive DC voltage level at the common point includes operating the plurality of switches to provide current from the midpoint bus to the common point via the second positive DC bus and the second switch in a first phase of a first operating mode, and operating the bidirectional switch to provide current from the midpoint bus to the common point via the bidirectional switch in a second phase of the first operating mode.

[0016] According to one embodiment, operating the plurality of switches and the bidirectional switches to generate voltage pulses alternating between a first positive DC voltage level and a second positive DC voltage level at the common point includes operating the plurality of switches to provide current from the midpoint bus to the common point via the first positive DC bus, the first switch, and the second switch in a first phase of the second operating mode, and operating the plurality of switches to provide current from the midpoint bus to the common point via the second positive DC bus and the second switch in a second phase of the second operating mode. In another embodiment, operating the plurality of switches and the bidirectional switches to generate voltage pulses alternating between zero and a first negative DC voltage level at the common point includes operating the plurality of switches to provide current from the common point to the midpoint bus via the second negative DC bus and the fourth switch in a first phase of the third operating mode, and operating the bidirectional switches to provide current from the common point to the midpoint bus via the bidirectional switches in a second phase of the third operating mode.

[0017] According to another embodiment, operating a plurality of switches and a bidirectional switch to generate voltage pulses alternating between a first negative DC voltage level and a second negative DC voltage level at a common point includes operating the plurality of switches to provide current from the common point to a midpoint bus via the first negative DC bus, the third switch, and the fourth switch in a first phase of a fourth operating mode, and operating the plurality of switches to provide current from the common point to the midpoint bus via the second negative DC bus and the fourth switch in a second phase of the fourth operating mode.

[0018] At least one aspect of the present invention is directed to an inverter, comprising: an input terminal, the input terminal being configured to be coupled to a DC source and to receive input DC power from the DC source; an output terminal, the output terminal being configured to be coupled to a load and to provide output AC power to the load; a plurality of DC buses, the plurality of DC buses being coupled to the input terminal and being configured to receive input DC power from the DC source; a midpoint bus, the midpoint bus being coupled to the input terminal and being coupled to the plurality of DC buses; an LC filter, the LC filter being coupled to the output terminal; a common point, the common point being coupled to the LC filter; a plurality of switches, the plurality of switches being coupled to the plurality of DC buses and the common point; and a device for coupling the midpoint bus to the common point to switch a voltage between five different voltage levels at the common point and for providing an output AC voltage waveform derived from the five different voltage levels to the output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Various aspects of at least one embodiment are discussed below with reference to the accompanying drawings, which are not intended to be drawn to scale. The accompanying drawings are included to provide illustration and further understanding of various aspects and embodiments, and are incorporated into and constitute a part of the specification, but are not intended to be used as a definition of limitations of the present invention. In the accompanying drawings, each identical or nearly identical component shown in different figures is represented by a like number. For the purpose of clarity, not every component is labeled in every figure. In the drawings:

[0020] Figure 1 is a block diagram of an online UPS according to aspects described herein;

[0021] Figure 2 is a schematic diagram of an inverter according to aspects described herein;

[0022] Figure 3 is a graph illustrating operation of an inverter according to aspects described herein;

[0023] Figure 4 is a schematic diagram of an inverter operating in a first phase of a first operating mode according to aspects described herein;

[0024] Figure 5 is a schematic diagram of an inverter operating in a second phase of a first operating mode according to aspects described herein;

[0025] Figure 6 is a schematic diagram of an inverter operating in a first phase of a second operating mode according to aspects described herein;

[0026] Figure 7 is a schematic diagram of an inverter operating in a second phase of a second operating mode according to aspects described herein;

[0027] Figure 8 is a schematic diagram of an inverter operating in a first phase of a third operating mode according to aspects described herein;

[0028] Fig. 9 is a schematic diagram of an inverter operating in a second phase of a third operating mode according to aspects described herein;

[0029] Fig.10 is a schematic diagram of an inverter operating in a first phase of a fourth operating mode according to aspects described herein;

[0030] Fig.11 is a schematic diagram of an inverter operating in a second phase of a fourth operating mode according to aspects described herein;

[0031] Fig.12is a schematic diagram of an inverter operating in a first phase of a fifth operating mode according to aspects described herein;

[0032] Fig.13 is a schematic diagram of an inverter operating in a second phase of a fifth operating mode according to aspects described herein;

[0033] Fig.14 is a schematic diagram of an inverter operating in a first phase of a sixth operating mode according to aspects described herein;

[0034] Fig.15 is a schematic diagram of an inverter operating in a second phase of a sixth operating mode according to aspects described herein; and

[0035] Fig.16 is a block diagram of a system upon which various embodiments of the invention may be implemented. Detailed Description

[0036] The examples of the methods and systems discussed herein are not intended to limit their application to the details of the structure and arrangement of the components set forth in the following description or shown in the accompanying drawings. The methods and systems can be implemented in other embodiments and can be practiced or executed in various ways. The examples of specific implementations provided herein are for illustrative purposes only and are not intended to be limiting. Specifically, the actions, components, elements, and features discussed in conjunction with any one or more examples are not intended to exclude similar effects in any other examples.

[0037] In addition, the words and terms used herein are for descriptive purposes and should not be considered restrictive. Any reference to the examples, embodiments, parts, elements or actions of the systems and methods mentioned in the singular herein may also include embodiments including the plural, and any reference to any embodiments, parts, elements or actions plural herein may also include embodiments including only the singular. References in singular or plural form are not intended to limit the currently disclosed systems or methods, their parts, actions or elements. The use of "including", "comprising", "having", "containing" and "involving" and their variations herein is intended to include the items listed thereafter and their equivalents and additional items. The reference of "or" may be interpreted as inclusive, so that any term described using "or" may indicate any of the single, more than one and all of the terms described. In addition, in the case of inconsistent usage of terms between this document and the documents incorporated by reference, the term usage in the incorporated document is used as a supplement to the term usage in this document; for irreconcilable inconsistencies, the term usage in this document shall prevail.

[0038] As mentioned above, power equipment such as uninterruptible power supplies (UPS) are often used to provide conditioned, uninterruptible power to sensitive and / or critical loads.

[0039] Conventional online UPS uses a power factor correction circuit (PFC) to rectify the input AC power provided by the power company to provide DC power to the DC bus. The rectified DC power on the DC bus is usually used to charge the battery when the mains power is available. In the absence of mains power, the battery discharges and provides DC power to the DC bus.

[0040] The inverter generates an AC output voltage from the DC power on the DC bus that is provided to the load. Since the DC bus is powered by a power source or a battery, the output power of the UPS is uninterrupted when the mains fails and the battery is fully charged. Generally, an online UPS can also operate in a bypass mode, where unregulated power with basic protection is provided directly from the AC power source to the load via a bypass line.

[0041] A common method of improving UPS efficiency is to utilize a multi-level power converter within the UPS. One type of multi-level power converter commonly used in UPS is a five-level inverter capable of switching between five voltage levels: a first positive DC voltage level, a second positive DC voltage level, a midpoint zero voltage level, a first negative DC voltage level, and a second negative DC voltage level. However, such a 5-level inverter is typically complex, includes a large number of power switches, and is relatively expensive. Thus, the use of a five-level inverter is typically limited.

[0042] In at least one embodiment, a quasi-five-level inverter system and method are provided, which can reduce the disadvantages of the above-mentioned traditional five-level inverter while providing relatively high efficiency and low harmonic distortion.

[0043] Figure 1 1 is a block diagram of an online UPS 100 according to one aspect of the present invention. The UPS 100 includes an input terminal 102, a converter 104, a DC bus 106, an inverter 108, an output terminal 110, a battery 112, and a controller 114. The input terminal 102 is coupled to the converter 104. The DC bus 106 is coupled between the converter 104 and the inverter 108. The output terminal 110 is coupled to the inverter 108. The controller 114 is coupled to the input terminal 102, the output terminal 110, the converter 104, the DC bus 106, and the inverter 108. The battery is coupled to the converter 104.

[0044] The input terminal 102 is configured to be coupled to an AC main power source and receive input AC power having an input voltage level. The controller 114 monitors the input AC power received by the input terminal 102 and is configured to operate the UPS 100 in different operating modes based on the state of the input AC power received by the input terminal 102. When the AC power provided to the input terminal 102 is acceptable (i.e., above the input power threshold), the controller 114 operates the UPS 100 in a normal operating mode. In the normal operating mode, the AC power from the input terminal 102 is provided to the converter 104. According to one embodiment, the converter 104 is a power factor correction converter 104; however, in other embodiments, other types of converters may also be utilized.

[0045] The controller 114 operates the converter 104 to convert the AC power into DC power and provide the DC power to the DC bus 106. In one embodiment, the DC power is also provided from the converter 104 to the battery 112 to charge the battery 112. In another embodiment, the DC power from the DC bus 106 is provided to the battery 112 via a DC / DC converter to charge the battery 112. In a normal operating mode, the inverter 108 receives DC power from the DC bus 106, and the controller 114 operates the inverter 108 to convert the DC power into regulated AC power and provide the regulated AC power to a load coupled to the output terminal 110.

[0046] When the AC power provided to the input 102 is unacceptable (i.e., below an input power threshold), the controller 114 operates the UPS 100 in a backup operating mode. In the backup operating mode, DC power from the battery 112 (e.g., by the converter 104 or a DC / DC converter coupled to the battery 112) is conditioned and provided to the DC bus 106. The inverter 108 receives the DC power from the DC bus 106, and the controller 114 operates the inverter 108 to convert the DC power into conditioned AC power and provide the conditioned AC power to the output 110.

[0047] Figure 2 1 is a schematic diagram of an inverter 108 according to at least one embodiment described herein. The inverter 108 is a quasi-five-level inverter. Figure 2As shown, the inverter 108 includes an input terminal 201 and a plurality of switches, the plurality of switches including a first switch (S1) 202, a second switch (S2) 204, a third switch (S3) 206, and a fourth switch (S4) 208. The inverter 108 also includes a bidirectional switch 233, an LC filter 211, a first positive bus 214, a second positive bus 231, a midpoint bus 216, a first negative bus 218, a second negative bus 235, a neutral line 220, a first capacitor (C1) 217, a second capacitor (C2) 228, a third capacitor (C3) 219, a fourth capacitor (C4) 230, a first diode (D1) 232, and a fourth diode (D4) 238. In one embodiment, the bidirectional switch 233 includes a fifth switch (S5) 224, a sixth switch (S6) 226, a second diode (D2) 234, and a third diode (D3) 236. In other embodiments, the bidirectional switch 233 may be another type of bidirectional switch.

[0048] LC filter 211 includes an output inductor 210 and an output capacitor 222. In one embodiment, each of switches 202, 204, 206, 208, 224, 226 is an insulated gate bipolar transistor (IGBT); however, in other embodiments, each switch 202, 204, 206, 208, 224, 226 may be another suitable type of switch and / or transistor (e.g., a metal oxide semiconductor field effect transistor (MOSFET)). According to at least one embodiment, each switch 202, 204, 206, 208, 224, 226 includes a diode connected in anti-parallel with the switch. In at least one embodiment, the diode is an intrinsic body diode of a MOSFET or a co-pack diode of an IGBT.

[0049] According to Figure 2 In at least one embodiment shown, the collector of the first switch (S1) 202 is coupled to the first positive bus 214, and the emitter of the first switch (S1) 202 is coupled to the collector of the second switch (S2) 204. The emitter of the second switch (S2) 204 is coupled to the common point 215. The first terminal of the first capacitor (C1) 217 ​​is coupled to the first positive bus 214, and the second terminal of the first capacitor (C1) 217 ​​is coupled to the second positive bus 231. The second positive bus 231 is coupled to the emitter of the first switch (S1) 202 via the first diode (D1) 232. The first terminal of the second capacitor (C2) 228 is coupled to the second positive bus 231, and the second terminal of the second capacitor (C2) 228 is coupled to the midpoint bus 216.

[0050] The collector of the third switch (S3) 206 is coupled to the common point 215, and the emitter of the third switch (S3) 206 is coupled to the collector of the fourth switch (S4) 208. The emitter of the fourth switch (S4) 208 is coupled to the first negative bus 218. The first terminal of the third capacitor (C3) 219 is coupled to the midpoint bus 216, and the second terminal of the third capacitor (C3) 219 is coupled to the second negative bus 235. The second negative bus 235 is coupled to the emitter of the third switch (S3) 206 via a fourth diode (D4) 238. The first terminal of the fourth capacitor (C4) 230 is coupled to the second negative bus 235, and the second terminal of the fourth capacitor (C4) 230 is coupled to the first negative bus 218.

[0051] The emitter of the fifth switch (S5) 224 is coupled to the midpoint bus 216 via a second diode (D2) 234. The collector of the fifth switch (S5) 224 is coupled to the common point 215. The collector of the sixth switch (S6) 226 is coupled to the midpoint bus 216. The emitter of the sixth switch (S6) 226 is coupled to the common point 215 via a third diode (D3) 236. The common point 215 is coupled to a first terminal of the inductor 210. A second terminal of the inductor 210 is coupled to the output 110 of the UPS 100. According to at least one embodiment, the output 110 is also coupled to the neutral line 220 via an output capacitor 222. The neutral line is also coupled to the midpoint bus 216. The controller 114 is coupled to the gate of each switch 202 , 204 , 206 , 208 , 224 , 226 and is configured to provide a control signal to the gate of each switch 202 , 204 , 206 , 208 , 224 , 226 .

[0052] In the following about Figure 3-15 The operation of the inverter is discussed in more detail. Figure 3 is a graph 300 including a first trace 302 showing the voltage of the inverter 108 at the common point 215 under different operating modes (AF) of the inverter 108, a second trace 304 showing the filtered output voltage of the inverter 108 at the output terminal 110 under different operating modes (AF) of the inverter 108, and a third trace 306 showing the load current of the inverter 108 under different operating modes (AF) of the inverter 108.

[0053] Figure 4-15 is a schematic diagram of the inverter 108 operating in different operation modes (AF). For example, Figure 4 is a schematic diagram of the inverter 108 operating in the first stage of mode A, Figure 5 is a schematic diagram of the inverter 108 operating in the second phase of mode A, Figure 6 is a schematic diagram of the inverter 108 operating in the first stage of mode B, Figure 7 is a schematic diagram of the inverter 108 operating in the second phase of mode B, Figure 8 is a schematic diagram of the inverter 108 operating in the first stage of mode C, Fig. 9 is a schematic diagram of the inverter 108 operating in the second phase of mode C, Fig.10 is a schematic diagram of the inverter 108 operating in the first stage of mode D, Fig.11 is a schematic diagram of the inverter 108 operating in the second phase of mode D, Fig.12 is a schematic diagram of the inverter 108 operating in the first stage of Mode E, Fig.13 is a schematic diagram of the inverter 108 operating in the second phase of Mode E, Fig.14 is a schematic diagram of the inverter 108 operating in the first stage of mode F, Fig.15 is a schematic diagram of the inverter 108 operating in the second phase of Mode F.

[0054] As similarly discussed above, in normal and backup operating modes, the inverter 108 is configured to receive DC power from a DC source (e.g., the converter 104 and / or the battery 112) via the input terminal 201, and the controller 114 operates the inverter 108 in modes A–F to convert the DC power received by the buses 214, 218, 231, 235 from the converter 104 and / or the battery 112 into regulated AC power and provide the regulated AC power to the output terminal 110.

[0055] In mode A, the controller 114 operates the first switch (S1) 202, the third switch (S3) 206, the fourth switch (S4) 208, and the fifth switch (S5) 224 to be turned off (i.e., opened), and operates the sixth switch (S6) 226 to be turned on (i.e., closed). In mode A, the controller 114 also operates the second switch (S2) 204 to alternate (i.e., switch) between the open and closed states. Figure 4 2 is a schematic diagram of the inverter 108 operating in the first stage of mode A, wherein the second switch (S2) 204 is closed. When the second switch (S2) 204 is closed, a current 402 from the second capacitor (C2) 228 to the output terminal 110 passes through the second positive bus 231, the first diode (D1) 232, the second switch (S2) 204, and the LC filter 211. During the first stage of mode A, the load 236 coupled to the output terminal 110 draws energy from the second capacitor (C2) 228, and a voltage (at Figure 3 2 (shown as first trace 302 in FIG. 1 ) has a first positive level 308 that is equal to approximately half of a second positive voltage level 312 generated at common point 215 during mode B (described below).

[0056] Figure 5 is a schematic diagram of the inverter 108 operating in the second phase of mode A, wherein the second switch (S2) 204 is open. When the second switch (S2) 204 is open, the current 502 from the midpoint bus 216 to the output terminal 110 passes through the sixth switch (S6) 226, the third diode (D3) 236, the common point 215, and the LC filter 211. During the second phase of mode A, the voltage 302 at the common point 215 becomes zero 308. In mode A, the controller operates the second switch (S2) 204 to alternate between the first phase and the second phase to generate pulses alternating between zero 308 and a first positive level 310 at the common point 215. The output current (at Figure 3 , shown as the third trace 306, is positive.

[0057] After mode A, the inverter 108 transitions to mode B. In mode B, the controller 114 operates the third switch (S3) 206, the fourth switch (S4) 208, the fifth switch (S5) 224, and the sixth switch (S6) 226 to turn off, and operates the second switch (S2) 204 to turn on. In mode B, the controller 114 also operates the first switch (S1) 202 to alternate (i.e., switch) between open and closed states. Figure 6 is a schematic diagram of the inverter 108 operating in the first phase of Mode B, wherein the first switch (S1) 202 is closed. When the first switch (S1) 202 is closed, a current 602 from the second capacitor (C2) 228 to the output terminal 110 passes through the first capacitor (C1) 217, the first positive bus 214, the first switch (S1) 202, the second switch (S2) 204, the common point 215, and the LC filter 211. During the first phase of Mode B, the load 236 coupled to the output terminal 110 draws energy from the first capacitor (C1) 217 ​​and the second capacitor (C2) 228, and the voltage 302 generated at the common point 215 has a second positive level 312 that is equal to approximately twice the first positive level 310 generated at the common point 215 during Mode A (described above).

[0058] Figure 7is a schematic diagram of the inverter 108 operating in the second phase of mode B, wherein the first switch (S1) 202 is open. When the first switch (S1) 202 is open, the current 702 from the second capacitor (C2) 228 to the output terminal 110 passes through the second positive bus 231, the first diode (D1) 232, the second switch (S2) 204, and the LC filter 211. During the second phase of mode B, the load 236 coupled to the output terminal 110 draws energy from the second capacitor (C2) 228, and the voltage 302 generated at the common point 215 is at the first positive level 310 (i.e., the same level as generated during the first phase of mode A). In mode B, the controller operates the first switch (S1) 202 to alternate between the first phase and the second phase to generate pulses alternating between the first positive level 310 and the second positive level 312 at the common point 215. The output current 306 at the output terminal 110 during mode B is positive.

[0059] After mode B, the inverter 108 transitions back to mode A. After transitioning back to mode A, the inverter 108 transitions to mode C. In mode C, the controller 114 operates the first switch (S1) 202, the third switch (S3) 206, the fourth switch (S4) 208, and the sixth switch (S6) 226 to turn off. In mode B, the controller 114 also operates the second switch (S2) 204 and the fifth switch (S5) 224 in a complementary switching mode (i.e., one switch is closed and the other switch is open). Figure 8 2 is a schematic diagram of operating the inverter 108 in the first stage of mode C, wherein the second switch (S2) 204 is closed and the fifth switch (S5) 224 is open. When the second switch (S2) 204 is closed and the fifth switch (S5) 224 is open, a current 802 from the output terminal 110 to the first capacitor (C1) 217 ​​and the second capacitor (C2) 218 ​​passes through the LC filter 211, the common point 215, the second switch (S2) 204 (which may include the diode (Ds2) of the second switch (S2) 204) and the diode (Ds1) of the first switch (S1) 202. During the first stage of mode C, the load 236 coupled to the output terminal 110 provides back power to the first capacitor (C1) 217 ​​and the second capacitor (C2) 228, and the voltage 302 generated at the common point 215 is at a second positive level 312.

[0060] Fig. 92 is a schematic diagram of the inverter 108 operating in the second phase of mode C, wherein the second switch (S2) 204 is open and the fifth switch (S5) 224 is closed. When the second switch (S2) 204 is open and the fifth switch (S5) 224 is closed, the current 902 from the output terminal 110 to the midpoint bus 216 passes through the LC filter 211, the common point 215, the switch (S5) 224 and the second diode (D2) 234. During the second phase of mode C, the voltage at the common point 215 becomes zero. In mode C, the controller operates the second switch (S2) 204 and the fifth switch (S5) 224 to alternate between the first phase and the second phase to generate pulses alternating between the second positive level 312 and zero 308 at the common point 215. The output current 306 at the common point 215 during mode C is negative. The controller 114 adjusts the width of the common point pulses in modes A, B, and C to produce the desired positive half cycle of the output voltage waveform 304 at the output terminal 110 in conjunction with the LC filter 211 .

[0061] After mode C, the inverter 108 transitions to mode D. In mode D, the controller 114 operates the first switch (S1) 202, the second switch (S2) 204, the fourth switch (S4) 208, and the sixth switch (S6) 226 to turn off (i.e., open), and operates the fifth switch (S5) 224 to turn on (i.e., close). In mode D, the controller 114 also operates the third switch (S3) 206 to alternate (i.e., switch) between open and closed states. Fig.10 is a schematic diagram of the inverter 108 operating in the first stage of mode D, wherein the third switch (S3) 206 is closed. When the third switch (S3) 206 is closed, a current 1002 from the output terminal 110 to the third capacitor (C3) 219 passes through the LC filter 211, the common point 215, the third switch (S3) 206, the fourth diode (D4) 238, and the second negative bus 235. During the first stage of mode D, the load 236 coupled to the output terminal 110 draws energy from the third capacitor (C3) 219, and the voltage 302 generated at the common point 215 has a first negative level 314 that is equal to approximately half of the second negative voltage level 316 generated at the common point 215 during mode E (described below).

[0062] Fig.112 is a schematic diagram of the inverter 108 operating in the second phase of mode D, wherein the third switch (S3) 206 is open. When the third switch (S3) 206 is open, the current 1102 from the output terminal 110 to the midpoint bus 216 passes through the LC filter 211, the common point 215, the fifth switch (S5) 224, and the second diode (D2) 234. During the second phase of mode D, the voltage 302 at the common point 215 becomes zero 308. In mode D, the controller operates the third switch (S3) 206 to alternate between the first phase and the second phase to generate pulses alternating between zero 308 and a first negative level 314 at the common point 215. The output current 306 at the output terminal 110 during mode D is negative.

[0063] After mode D, the inverter 108 transitions to mode E. In mode E, the controller 114 operates the first switch (S1) 202, the second switch (S2) 204, the fifth switch (S5) 224, and the sixth switch (S6) 226 to turn off (i.e., open), and operates the third switch (S3) 224 to turn on (i.e., close). In mode E, the controller 114 also operates the fourth switch (S4) 208 to alternate (i.e., switch) between open and closed states. Fig.12 2 is a schematic diagram of the inverter 108 operating during the first stage of Mode E, wherein the fourth switch (S4) 208 is closed. When the fourth switch (S4) 208 is closed, a current 1202 from the output terminal 110 to the third capacitor (C3) 219 passes through the LC filter 211, the third switch (S3) 206, the fourth switch (S4) 208, the first negative bus 218, and the fourth capacitor (C4) 230. During the first stage of Mode E, the load 236 coupled to the output terminal 110 draws energy from the third capacitor (C3) 219 and the fourth capacitor (C4) 230, and the voltage 302 generated at the common point 215 has a second negative level 316 that is equal to approximately twice the first negative level 314 generated at the common point 215 during Mode D (described above).

[0064] Fig.13is a schematic diagram of the inverter 108 operating during the second phase of mode E, wherein the fourth switch (S4) 208 is open. When the fourth switch (S4) 208 is open, the current 1302 from the output terminal 110 to the third capacitor (C3) 219 passes through the LC filter 211, the common point 215, the third switch (S3) 206, the fourth diode (D4) 238, and the second negative bus 235. During the second phase of mode E, the load 236 coupled to the output terminal 110 draws energy from the third capacitor (C3) 219, and the voltage 302 generated at the common point 215 has a first negative level 314. In mode E, the controller operates the fourth switch (S4) 208 to alternate between the first phase and the second phase to generate pulses alternating between the first negative level 314 and the second negative level 316 at the common point 215. The output current 306 at the output terminal 110 during mode E is negative.

[0065] After mode E, the inverter 108 transitions back to mode D. After transitioning back to mode D, the inverter 108 transitions to mode F. In mode F, the controller 114 operates the first switch (S1) 202, the second switch (S2) 204, the fourth switch (S4) 208, and the fifth switch (S5) 224 to turn off. In mode F, the controller 114 also operates the third switch (S3) 206 and the sixth switch (S6) 226 in a complementary switching mode (i.e., one switch is closed and the other switch is open). Fig.14 206 is a schematic diagram of the inverter 108 operating in the first stage of mode F, wherein the third switch (S3) 206 is closed and the sixth switch (S6) 226 is open. When the third switch (S3) 206 is closed and the sixth switch (S6) 226 is open, a current 1402 from the third capacitor (C3) 219 and the fourth capacitor (C4) 230 to the output terminal 110 passes through the first negative bus 218, the diode (Ds4) of the fourth switch (S4) 208, the third switch (S3) 206 (possibly including the diode (Ds3) of the third switch (S3) 206), the common point 215, and the LC filter 211. During the first stage of mode F, the load 236 coupled to the output terminal 110 provides back power to the third capacitor (C3) 219 and the fourth capacitor (C4) 230, and the voltage 302 generated at the common point 215 is at a second negative level 316.

[0066] Fig.152 is a schematic diagram of the inverter 108 operating during the second phase of mode F, wherein the third switch (S3) 206 is open and the sixth switch (S6) 226 is closed. When the third switch (S3) 206 is open and the sixth switch (S6) 226 is closed, the current 1502 from the midpoint bus 216 to the output terminal 110 passes through the sixth switch (S6) 226, the third diode (D3) 236, the common point 215 and the LC filter 211. During the second phase of mode F, the voltage at the common point 215 becomes zero. In mode F, the controller operates the third switch (S3) 206 and the sixth switch (S6) 226 to alternate between the first phase and the second phase to generate pulses alternating between the second negative level 316 and zero 308 at the common point 215. The output current 306 at the common point 215 during mode F is positive. The controller 114 adjusts the width of the common point pulses in modes D, E, and F to produce the desired negative half cycle of the output voltage waveform 304 at the output terminal 110 in conjunction with the LC filter 211 .

[0067] Fig.16 An example block diagram of computing components forming a system 1600 that may be configured to implement one or more aspects disclosed herein is shown. For example, the system 1600 may be communicatively coupled to or included within the controller 114. The system 1600 may also be configured to operate an inverter as discussed above.

[0068] System 1600 may include, for example, a computing platform such as those based on an Intel Pentium-type processor, Motorola's PowerPC, Sun's UltraSPARC, a Texas Instruments DSP, a Hewlett-Packard PA-RISC processor, or any other type of processor. System 1600 may include specially programmed, dedicated hardware, such as an application specific integrated circuit (ASIC). System 1600 may also include a field programmable gate array (FPGA). Various aspects of the present disclosure may be implemented as a processor in system 1600 (e.g., in Fig.16 Dedicated software executed on the system shown in .

[0069] The system 1600 may include a processor / ASIC 1606 connected to one or more memory devices 1610 such as a disk drive, memory, flash memory, or other device for storing data. The memory 1610 may be used to store programs and data during the operation of the system 1600. The components of the computer system 1600 may be coupled by an interconnection mechanism 1608, which may include one or more buses (e.g., between components integrated in the same machine) and / or networks (e.g., between components present on separate machines). The interconnection mechanism 1608 enables the exchange of communications (e.g., data, instructions) between the components of the system 1600. The system 1600 also includes one or more input devices 1604, which may include, for example, a keyboard or a touch screen. The system 1600 includes one or more output devices 1602, which may include, for example, a display. In addition, the computer system 1600 may include one or more interfaces (not shown) that may connect the computer system 1600 to a communication network (in addition to or as an alternative to the interconnection mechanism 1608).

[0070] The system 1600 may include a storage system 1612, which may include a computer-readable and / or writable non-volatile medium, where signals may be stored to provide a program executed by a processor or to provide information processed by a program on or stored in the medium. The medium may be, for example, a disk or flash memory, and in some examples may include RAM or other non-volatile memory, such as EEPROM. In some embodiments, the processor may cause data to be read from the non-volatile medium to another memory 1610 that allows the processor / ASIC to access information faster than the medium. This memory 1610 may be a volatile random access memory, such as a dynamic random access memory (DRAM) or a static memory (SRAM). It may be located in the storage system 1612 or in the memory system 1610. The processor 1606 may manipulate the data within the integrated circuit memory 1610 and then copy the data to the storage 1612 after completing the processing. Various mechanisms for managing the movement of data between the storage 1612 and the integrated circuit memory element 1610 are known, and the present disclosure is not limited thereto. The present disclosure is not limited to a particular memory system 1610 or storage system 1612 .

[0071] System 1600 may include a computer platform that can be programmed using a high-level computer programming language. System 1600 may also be implemented using specialized hardware (e.g., ASIC) that is professionally programmed. System 1600 may include processor 1606, which may be a commercially available processor, such as a known Pentium class processor available from Intel Corporation. Many other processors are also available. Processor 1606 may execute an operating system, which may be, for example, a Windows operating system available from Microsoft Corporation, a MAC OS system X available from Apple Computer, a Solaris operating system available from Sun Microsystems, or UNIX and / or LINUX available from various sources. Many other operating systems may be used.

[0072] The processor and the operating system can together form a computer platform, and applications on the computer platform can be written in a high-level programming language. It should be understood that the present disclosure is not limited to a specific computer system platform, processor, operating system, or network. In addition, it should be apparent to those skilled in the art that the present disclosure is not limited to a specific programming language or computer system. In addition, it should be appreciated that other suitable programming languages ​​and other suitable computer systems may also be used.

[0073] As described above, the inverter 108 may be utilized with an online UPS; however, in other embodiments, the inverter 108 may be utilized with another type of UPS and / or another type of power system requiring DC to AC conversion.

[0074] As discussed herein, a quasi-five-level inverter system and method are provided that can reduce the disadvantages of the above-mentioned conventional five-level inverter while providing relatively high efficiency and low harmonic distortion. By utilizing a bidirectional switch 233 in conjunction with diodes D1 and D4 as discussed above, the quasi-five-level inverter system described herein can switch between five voltage levels and generate a desired output voltage waveform while having a simpler structure than a conventional five-level inverter, utilizing fewer power switches and having a lower cost.

[0075] Having thus described several aspects of at least one embodiment of the present invention, it will be appreciated that various changes, modifications and improvements will readily occur to those skilled in the art. Such changes, modifications and improvements are considered part of this disclosure and are considered to be within the spirit and scope of the present invention. Therefore, the foregoing description and drawings are merely exemplary.

Claims

1. An inverter, comprising: an input terminal configured to be coupled to a DC source and receive input DC power from the DC source; an output terminal configured to be coupled to a load and provide output AC power to the load; a plurality of DC buses coupled to the input and configured to receive the input DC power from the DC source; a midpoint bus coupled to the input terminal and to the plurality of DC busses; an LC filter coupled to the output terminal; a common point coupled to the LC filter; a plurality of switches coupled to the plurality of DC buses and the common point; a bidirectional switch coupled between the midpoint bus and the common point; as well as a controller configured to operate the plurality of switches and the bidirectional switch in a first operating mode to generate a voltage at a first positive DC voltage level at the common point, to operate the plurality of switches and the bidirectional switch in a second operating mode to generate a voltage at a second positive DC voltage level at the common point, to operate the plurality of switches and the bidirectional switch in a third operating mode to generate a voltage at a first negative DC voltage level at the common point, to operate the plurality of switches and the bidirectional switch in a fourth operating mode to generate a voltage at a second negative DC voltage level at the common point, and to operate the plurality of switches and the bidirectional switch in a fifth operating mode occurring during a transition from the second operating mode to the third operating mode, wherein during the first operation mode, the second operation mode, the third operation mode and the fourth operation mode, the controller is further configured to operate only at least one switch of the plurality of switches without operating the bidirectional switch, and During the fifth operation mode, the controller is further configured to complementarily operate the bidirectional switch and at least one of the plurality of switches.

2. The inverter according to claim 1, wherein: The LC filter is configured to provide an output AC voltage waveform derived from a voltage at the common point to the output terminal during the first, second, third, and fourth operation modes.

3. The inverter according to claim 1, wherein: In the first operating mode, the controller is further configured to operate the plurality of switches and the bidirectional switches to generate voltage pulses alternating between zero and the first positive DC voltage level at the common point, in the second operating mode, the controller is further configured to operate the plurality of switches and the bidirectional switches to generate voltage pulses alternating between the first positive DC voltage level and the second positive DC voltage level at the common point, in the third operating mode, the controller is further configured to operate the plurality of switches and the bidirectional switches to generate voltage pulses alternating between zero and the first negative DC voltage level at the common point, and in the fourth operating mode, the controller is further configured to operate the plurality of switches and the bidirectional switches to generate voltage pulses alternating between the first negative DC voltage level and the second negative DC voltage level at the common point.

4. The inverter according to claim 1, in, The plurality of DC buses include: a first positive DC bus coupled to the input; a second positive DC bus coupled to the input; a first negative DC bus coupled to the input; and a second negative DC bus coupled to the input terminal, and wherein the plurality of switches comprises: a first switch coupled to the first positive DC bus; a second switch coupled between the first switch and the common point; a third switch coupled to the first negative DC bus; and A fourth switch is coupled between the third switch and the common point.

5. The inverter according to claim 4, further comprising: a first diode coupled between the second positive DC bus and the second switch; as well as A second diode is coupled between the second negative DC bus and the fourth switch.

6. The inverter according to claim 5, further comprising: a first capacitor coupled between the first positive DC bus and the second positive DC bus; a second capacitor coupled between the second positive DC bus and the midpoint bus; a third capacitor coupled between the first negative DC bus and the second negative DC bus; as well as A fourth capacitor is coupled between the second negative DC bus and the midpoint bus.

7. The inverter according to claim 6, wherein: The controller is also configured to operate the plurality of switches to provide current from the second capacitor to the common point via the second positive DC bus, the first diode, and the second switch in a first phase of the first operating mode, and to operate the bidirectional switches to provide current from the midpoint bus to the common point via the bidirectional switches in a second phase of the first operating mode.

8. The inverter according to claim 7, wherein: The controller is also configured to operate the plurality of switches to provide current from the first capacitor to the common point via the first positive DC bus, the first switch, and the second switch in a first phase of the second operating mode, and to operate the plurality of switches to provide current from the second capacitor to the common point via the second positive DC bus, the first diode, and the second switch in a second phase of the second operating mode.

9. The inverter according to claim 8, wherein: The controller is also configured to operate the plurality of switches to provide current from the common point to the third capacitor via the second negative DC bus, the second diode, and the fourth switch in a first phase of the third operating mode, and to operate the bidirectional switches to provide current from the common point to the midpoint bus via the bidirectional switches in a second phase of the third operating mode.

10. The inverter according to claim 9, wherein: The controller is also configured to operate the plurality of switches to provide current from the common point to the fourth capacitor via the first negative DC bus, the third switch, and the fourth switch in a first stage of the fourth operating mode, and to operate the plurality of switches to provide current from the common point to the third capacitor via the second negative DC bus, the second diode, and the fourth switch in a second stage of the fourth operating mode.

11. The inverter according to claim 6, wherein: The controller is also configured to operate the plurality of switches to provide current from the common point to the first capacitor via the first positive DC bus, the first switch, and the second switch in a first stage of the fifth operating mode, and to operate the bidirectional switches to provide current from the common point to the midpoint bus via the bidirectional switches in a second stage of the fifth operating mode.

12. The inverter according to claim 6, wherein: The controller is also configured to operate the plurality of switches to provide current from the fourth capacitor to the common point via the first negative DC bus, the third switch, and the fourth switch in a first stage of a sixth operating mode occurring during a transition from the third operating mode to the second operating mode, and to operate the bidirectional switches to provide current from the midpoint bus to the common point via the bidirectional switches in a second stage of the sixth operating mode.

13. The inverter according to claim 12, wherein: The bidirectional switch comprises: a third diode coupled to the midpoint bus; a fifth switch coupled between the third diode and the common point; a fourth diode coupled to the common point; and A sixth switch is coupled between the fourth diode and the midpoint bus.

14. A method for operating an inverter, the inverter comprising an input terminal configured to be coupled to a DC source, an output terminal, a plurality of DC buses, a midpoint bus coupled to the input terminal and the plurality of DC buses, an LC filter coupled to the output terminal, a common point coupled to the LC filter, a plurality of switches coupled to the plurality of DC buses and the common point, and a bidirectional switch coupled between the midpoint bus and the common point, the method comprising: receiving input DC power from the DC source at the input; in a first operating mode, operating the plurality of switches and the bidirectional switch to generate a voltage at the common point at a first positive DC voltage level by operating only at least one switch of the plurality of switches without operating the bidirectional switch; in a second operating mode, operating the plurality of switches and the bidirectional switch to generate a voltage at the common point at a second positive DC voltage level by operating only at least one switch of the plurality of switches without operating the bidirectional switch; in a third operating mode, operating the plurality of switches and the bidirectional switch to generate a voltage at the common point at a first negative DC voltage level by operating only at least one switch of the plurality of switches without operating the bidirectional switch; in a fourth operating mode, operating the plurality of switches and the bidirectional switch to generate a voltage at the common point at a second negative DC voltage level by operating only at least one switch of the plurality of switches without operating the bidirectional switch; complementarily operating at least one switch of the plurality of switches and the bidirectional switch in a fifth operation mode between transitions of the second operation mode and the third operation mode; as well as An output AC voltage waveform derived from the voltage at the common point is generated at the output terminal using the LC filter during the first, second, third, fourth, and fifth operating modes.

15. The method according to claim 14, wherein: operating the plurality of switches and the bidirectional switch in the first operating mode comprises operating the plurality of switches and the bidirectional switch to generate voltage pulses alternating between zero and the first positive DC voltage level at the common point, wherein operating the plurality of switches and the bidirectional switch in the second operating mode comprises operating the plurality of switches and the bidirectional switch to generate voltage pulses alternating between the first positive DC voltage level and the second positive DC voltage level at the common point, wherein operating the plurality of switches and the bidirectional switch in the third operating mode comprises operating the plurality of switches and the bidirectional switch to generate voltage pulses alternating between zero and the first negative DC voltage level at the common point, and Wherein, operating the plurality of switches and the bidirectional switch in the fourth operating mode includes operating the plurality of switches and the bidirectional switch to generate voltage pulses alternating between the first negative DC voltage level and the second negative DC voltage level at the common point.

16. The method according to claim 15, wherein: The plurality of DC buses include a first positive DC bus, a second positive DC bus, a first negative DC bus, and a second negative DC bus, wherein the plurality of switches include a first switch coupled to the first positive DC bus, a second switch coupled between the first switch and the common point, a third switch coupled to the first negative DC bus, and a fourth switch coupled between the third switch and the common point, and wherein operating the plurality of switches and the bidirectional switch to generate voltage pulses alternating between zero and the first positive DC voltage level at the common point includes: in a first phase of the first operating mode, operating the plurality of switches to provide current from the midpoint bus to the common point via the second positive DC bus and the second switches; and In a second phase of the first operating mode, the bidirectional switch is operated to provide current from the midpoint bus to the common point via the bidirectional switch.

17. The method according to claim 16, wherein: Operating the plurality of switches and the bidirectional switch to generate voltage pulses alternating between the first positive DC voltage level and the second positive DC voltage level at the common point comprises: in a first phase of the second operating mode, operating the plurality of switches to provide current from the midpoint bus to the common point via the first positive DC bus, the first switch, and the second switch; and In a second phase of the second operating mode, the plurality of switches are operated to provide current from the midpoint bus to the common point via the second positive DC bus and the second switches.

18. The method according to claim 17, wherein: Operating the plurality of switches and the bidirectional switch to generate voltage pulses at the common point alternating between zero and the first negative DC voltage level comprises: In a first phase of the third operating mode, operating the plurality of switches to provide current from the common point to the midpoint bus via the second negative DC bus and the fourth switch; and In a second phase of the third operation mode, the bidirectional switch is operated to provide current from the common point to the midpoint bus via the bidirectional switch.

19. The method according to claim 18, wherein: Operating the plurality of switches and the bidirectional switch to generate voltage pulses alternating between the first negative DC voltage level and the second negative DC voltage level at the common point comprises: In a first phase of the fourth operating mode, operating the plurality of switches to provide current from the common point to the midpoint bus via the first negative DC bus, the third switch, and the fourth switch; and In a second phase of the fourth operating mode, the plurality of switches are operated to provide current from the common point to the midpoint bus via the second negative DC bus and the fourth switch.

20. An inverter, comprising: an input terminal configured to be coupled to a DC source and to receive input DC power from the DC source; an output terminal configured to be coupled to a load and to provide output AC power to the load; a plurality of DC buses coupled to the input and configured to receive the input DC power from the DC source; a midpoint bus coupled to the input terminal and to the plurality of DC busses; an LC filter coupled to the output terminal; a common point coupled to the LC filter; a plurality of switches coupled to the plurality of DC buses and the common point; as well as means for coupling the midpoint bus to the common point and operating at least one of the plurality of switches to switch the voltage at the common point to a first positive DC voltage level during a first operating mode, to a second positive DC voltage level during a second operating mode, to the first positive DC voltage level during a third operating mode, to the second positive DC voltage level during a fourth operating mode, and to the second positive DC voltage level during a fifth operating mode, and for providing an output AC voltage waveform derived from different voltage levels to the output terminal.

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